1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
16 Permission is granted to copy, distribute and/or modify this document
17 under the terms of the GNU Free Documentation License, Version 1.2 or
18 any later version published by the Free Software Foundation; with no
19 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
20 Texts. A copy of the license is included in the section entitled ``GNU
21 Free Documentation License''.
26 @title Open On-Chip Debugger (OpenOCD)
27 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
28 @subtitle @value{UPDATED}
30 @vskip 0pt plus 1filll
36 @node Top, About, , (dir)
39 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
40 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
45 * About:: About OpenOCD.
46 * Developers:: OpenOCD developers
47 * Building:: Building OpenOCD
48 * Running:: Running OpenOCD
49 * Configuration:: OpenOCD Configuration.
50 * Target library:: Target library
51 * Commands:: OpenOCD Commands
52 * Sample Scripts:: Sample Target Scripts
53 * GDB and OpenOCD:: Using GDB and OpenOCD
54 * TCL and OpenOCD:: Using TCL and OpenOCD
55 * TCL scripting API:: Tcl scripting API
56 * Upgrading:: Deprecated/Removed Commands
57 * FAQ:: Frequently Asked Questions
58 * License:: GNU Free Documentation License
66 The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming
67 and boundary-scan testing for embedded target devices. The targets are interfaced
68 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
69 connection types in the future.
71 OpenOCD currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
72 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
73 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
74 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
76 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
77 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
78 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
84 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
85 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
86 Others interested in improving the state of free and open debug and testing technology
87 are welcome to participate.
89 Other developers have contributed support for additional targets and flashes as well
90 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
92 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
96 @cindex building OpenOCD
98 You can download the current SVN version with SVN client of your choice from the
99 following repositories:
101 (@uref{svn://svn.berlios.de/openocd/trunk})
105 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
107 Using the SVN command line client, you can use the following command to fetch the
108 latest version (make sure there is no (non-svn) directory called "openocd" in the
112 svn checkout svn://svn.berlios.de/openocd/trunk openocd
115 Building OpenOCD requires a recent version of the GNU autotools.
116 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
117 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
118 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
119 paths, resulting in obscure dependency errors (This is an observation I've gathered
120 from the logs of one user - correct me if I'm wrong).
122 You further need the appropriate driver files, if you want to build support for
123 a FTDI FT2232 based interface:
125 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
126 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
127 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
128 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
131 libftdi is supported under windows. Versions earlier than 0.13 will require patching.
132 see contrib/libftdi for more details.
134 In general, the D2XX driver provides superior performance (several times as fast),
135 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
136 a kernel module, only a user space library.
138 To build OpenOCD (on both Linux and Cygwin), use the following commands:
142 Bootstrap generates the configure script, and prepares building on your system.
146 Configure generates the Makefiles used to build OpenOCD.
150 Make builds OpenOCD, and places the final executable in ./src/.
152 The configure script takes several options, specifying which JTAG interfaces
157 @option{--enable-parport}
159 @option{--enable-parport_ppdev}
161 @option{--enable-parport_giveio}
163 @option{--enable-amtjtagaccel}
165 @option{--enable-ft2232_ftd2xx}
166 @footnote{Using the latest D2XX drivers from FTDI and following their installation
167 instructions, I had to use @option{--enable-ft2232_libftd2xx} for OpenOCD to
170 @option{--enable-ft2232_libftdi}
172 @option{--with-ftd2xx=/path/to/d2xx/}
174 @option{--enable-gw16012}
176 @option{--enable-usbprog}
178 @option{--enable-presto_libftdi}
180 @option{--enable-presto_ftd2xx}
182 @option{--enable-jlink}
185 If you want to access the parallel port using the PPDEV interface you have to specify
186 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
187 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
188 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
190 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
191 absolute path containing no spaces.
193 Linux users should copy the various parts of the D2XX package to the appropriate
194 locations, i.e. /usr/include, /usr/lib.
196 Miscellaneous configure options
200 @option{--enable-gccwarnings} - enable extra gcc warnings during build
205 @cindex running OpenOCD
207 @cindex --debug_level
210 OpenOCD runs as a daemon, waiting for connections from clients (Telnet, GDB, Other).
211 Run with @option{--help} or @option{-h} to view the available command line switches.
213 It reads its configuration by default from the file openocd.cfg located in the current
214 working directory. This may be overwritten with the @option{-f <configfile>} command line
215 switch. The @option{-f} command line switch can be specified multiple times, in which case the config files
216 are executed in order.
218 Also it is possible to interleave commands w/config scripts using the @option{-c} command line switch.
220 To enable debug output (when reporting problems or working on OpenOCD itself), use
221 the @option{-d} command line switch. This sets the debug_level to "3", outputting
222 the most information, including debug messages. The default setting is "2", outputting
223 only informational messages, warnings and errors. You can also change this setting
224 from within a telnet or gdb session (@option{debug_level <n>}).
226 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
228 Search paths for config/script files can be added to OpenOCD by using
229 the @option{-s <search>} switch. The current directory and the OpenOCD target library
230 is in the search path by default.
232 Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
233 with the target. In general, it is possible for the JTAG controller to be unresponsive until
234 the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
237 @chapter Configuration
238 @cindex configuration
239 OpenOCD runs as a daemon, and reads it current configuration
240 by default from the file openocd.cfg in the current directory. A different configuration
241 file can be specified with the @option{-f <conf.file>} command line switch specified when starting OpenOCD.
243 The configuration file is used to specify on which ports the daemon listens for new
244 connections, the JTAG interface used to connect to the target, the layout of the JTAG
245 chain, the targets that should be debugged, and connected flashes.
247 @section Daemon configuration
250 @item @b{init} This command terminates the configuration stage and enters the normal
251 command mode. This can be useful to add commands to the startup scripts and commands
252 such as resetting the target, programming flash, etc. To reset the CPU upon startup,
253 add "init" and "reset" at the end of the config script or at the end of the
254 OpenOCD command line using the @option{-c} command line switch.
256 @item @b{telnet_port} <@var{number}>
258 Port on which to listen for incoming telnet connections
259 @item @b{gdb_port} <@var{number}>
261 First port on which to listen for incoming GDB connections. The GDB port for the
262 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
263 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
265 Configures what OpenOCD will do when gdb detaches from the daeman.
266 Default behaviour is <@var{resume}>
267 @item @b{gdb_memory_map} <@var{enable|disable}>
268 @cindex gdb_memory_map
269 Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
270 requested. gdb will then know when to set hardware breakpoints, and program flash
271 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
272 for flash programming to work.
273 Default behaviour is <@var{enable}>
274 @item @b{gdb_flash_program} <@var{enable|disable}>
275 @cindex gdb_flash_program
276 Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
277 vFlash packet is received.
278 Default behaviour is <@var{enable}>
279 at item @b{tcl_port} <@var{number}>
281 Port on which to listen for incoming TCL syntax. This port is intended as
282 a simplified RPC connection that can be used by clients to issue commands
283 and get the output from the TCL engine.
286 @section JTAG interface configuration
289 @item @b{interface} <@var{name}>
291 Use the interface driver <@var{name}> to connect to the target. Currently supported
295 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
298 @item @b{amt_jtagaccel}
299 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
304 FTDI FT2232 based devices using either the open-source libftdi or the binary only
305 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
306 platform. The libftdi uses libusb, and should be portable to all systems that provide
311 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
315 ASIX PRESTO USB JTAG programmer.
319 usbprog is a freely programmable USB adapter.
323 Gateworks GW16012 JTAG programmer.
327 Segger jlink usb adapter
332 @item @b{jtag_speed} <@var{reset speed}>
334 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
335 speed. The actual effect of this option depends on the JTAG interface used.
337 The speed used during reset can be adjusted using setting jtag_speed during
338 pre_reset and post_reset events.
341 @item wiggler: maximum speed / @var{number}
342 @item ft2232: 6MHz / (@var{number}+1)
343 @item amt jtagaccel: 8 / 2**@var{number}
344 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
347 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
348 especially true for synthesized cores (-S).
350 @item @b{jtag_khz} <@var{reset speed kHz}>
352 Same as jtag_speed, except that the speed is specified in maximum kHz. If
353 the device can not support the rate asked for, or can not translate from
354 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
355 is not supported, then an error is reported.
357 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
359 The configuration of the reset signals available on the JTAG interface AND the target.
360 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
361 then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
362 @option{srst_only} or @option{trst_and_srst}.
364 [@var{combination}] is an optional value specifying broken reset signal implementations.
365 @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
366 the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
367 that the system is reset together with the test logic (only hypothetical, I haven't
368 seen hardware with such a bug, and can be worked around).
369 @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
370 The default behaviour if no option given is @option{separate}.
372 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
373 reset lines to be specified. Possible values are @option{trst_push_pull} (default)
374 and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
375 (default) and @option{srst_push_pull} for the system reset. These values only affect
376 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
378 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
380 Describes the devices that form the JTAG daisy chain, with the first device being
381 the one closest to TDO. The parameters are the length of the instruction register
382 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
383 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
384 The IDCODE instruction will in future be used to query devices for their JTAG
385 identification code. This line is the same for all ARM7 and ARM9 devices.
386 Other devices, like CPLDs, require different parameters. An example configuration
387 line for a Xilinx XC9500 CPLD would look like this:
389 jtag_device 8 0x01 0x0e3 0xfe
391 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
392 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
393 The IDCODE instruction is 0xfe.
395 @item @b{jtag_nsrst_delay} <@var{ms}>
396 @cindex jtag_nsrst_delay
397 How long (in milliseconds) OpenOCD should wait after deasserting nSRST before
398 starting new JTAG operations.
399 @item @b{jtag_ntrst_delay} <@var{ms}>
400 @cindex jtag_ntrst_delay
401 How long (in milliseconds) OpenOCD should wait after deasserting nTRST before
402 starting new JTAG operations.
404 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
405 or on-chip features) keep a reset line asserted for some time after the external reset
409 @section parport options
412 @item @b{parport_port} <@var{number}>
414 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
415 the @file{/dev/parport} device
417 When using PPDEV to access the parallel port, use the number of the parallel port:
418 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
419 you may encounter a problem.
420 @item @b{parport_cable} <@var{name}>
421 @cindex parport_cable
422 The layout of the parallel port cable used to connect to the target.
423 Currently supported cables are
427 The original Wiggler layout, also supported by several clones, such
428 as the Olimex ARM-JTAG
429 @item @b{old_amt_wiggler}
430 @cindex old_amt_wiggler
431 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
432 version available from the website uses the original Wiggler layout ('@var{wiggler}')
435 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to program the Chameleon itself, not a connected target.
438 The Xilinx Parallel cable III.
441 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
442 This is also the layout used by the HollyGates design
443 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
446 The ST Parallel cable.
448 @item @b{parport_write_on_exit} <@var{on|off}>
449 @cindex parport_write_on_exit
450 This will configure the parallel driver to write a known value to the parallel
451 interface on exiting OpenOCD
454 @section amt_jtagaccel options
456 @item @b{parport_port} <@var{number}>
458 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
459 @file{/dev/parport} device
461 @section ft2232 options
464 @item @b{ft2232_device_desc} <@var{description}>
465 @cindex ft2232_device_desc
466 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
467 default value is used. This setting is only valid if compiled with FTD2XX support.
468 @item @b{ft2232_layout} <@var{name}>
469 @cindex ft2232_layout
470 The layout of the FT2232 GPIO signals used to control output-enables and reset
471 signals. Valid layouts are
474 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
476 Amontec JTAGkey and JTAGkey-tiny
479 @item @b{olimex-jtag}
482 American Microsystems M5960
483 @item @b{evb_lm3s811}
484 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
485 SRST signals on external connector
489 Hitex STM32 Performance Stick
491 Tin Can Tools Flyswatter
492 @item @b{turtelizer2}
493 egnite Software turtelizer2
498 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
499 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
500 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
502 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
504 @item @b{ft2232_latency} <@var{ms}>
505 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
506 ft2232_read() fails to return the expected number of bytes. This can be caused by
507 USB communication delays and has proved hard to reproduce and debug. Setting the
508 FT2232 latency timer to a larger value increases delays for short USB packages but it
509 also reduces the risk of timeouts before receiving the expected number of bytes.
510 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
513 @section ep93xx options
514 @cindex ep93xx options
515 Currently, there are no options available for the ep93xx interface.
518 @section Target configuration
521 @item @b{target} <@var{type}> <@var{endianess}> <@var{JTAG pos}>
524 Defines a target that should be debugged. Currently supported types are:
538 If you want to use a target board that is not on this list, see Adding a new
541 Endianess may be @option{little} or @option{big}.
543 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
544 @cindex target_script
545 Event is one of the following:
546 @option{pre_reset}, @option{reset}, @option{post_reset}, @option{post_halt},
547 @option{pre_resume} or @option{gdb_program_config}.
548 @option{post_reset} and @option{reset} will produce the same results.
550 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
551 <@var{backup}|@var{nobackup}>
553 Specifies a working area for the debugger to use. This may be used to speed-up
554 downloads to target memory and flash operations, or to perform otherwise unavailable
555 operations (some coprocessor operations on ARM7/9 systems, for example). The last
556 parameter decides whether the memory should be preserved (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If possible, use
557 a working_area that doesn't need to be backed up, as performing a backup slows down operation.
560 @subsection arm7tdmi options
561 @cindex arm7tdmi options
562 target arm7tdmi <@var{endianess}> <@var{jtag#}>
563 The arm7tdmi target definition requires at least one additional argument, specifying
564 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
565 The optional [@var{variant}] parameter has been removed in recent versions.
566 The correct feature set is determined at runtime.
568 @subsection arm720t options
569 @cindex arm720t options
570 ARM720t options are similar to ARM7TDMI options.
572 @subsection arm9tdmi options
573 @cindex arm9tdmi options
574 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
575 @option{arm920t}, @option{arm922t} and @option{arm940t}.
576 This enables the hardware single-stepping support found on these cores.
578 @subsection arm920t options
579 @cindex arm920t options
580 ARM920t options are similar to ARM9TDMI options.
582 @subsection arm966e options
583 @cindex arm966e options
584 ARM966e options are similar to ARM9TDMI options.
586 @subsection cortex_m3 options
587 @cindex cortex_m3 options
588 use variant <@var{variant}> @option{lm3s} when debugging luminary lm3s targets. This will cause
589 openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
590 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
591 be detected and the normal reset behaviour used.
593 @subsection xscale options
594 @cindex xscale options
595 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
596 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
598 @section Flash configuration
599 @cindex Flash configuration
602 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
603 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
605 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
606 and <@var{bus_width}> bytes using the selected flash <driver>.
609 @subsection lpc2000 options
610 @cindex lpc2000 options
612 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
613 <@var{clock}> [@var{calc_checksum}]
614 LPC flashes don't require the chip and bus width to be specified. Additional
615 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
616 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
617 of the target this flash belongs to (first is 0), the frequency at which the core
618 is currently running (in kHz - must be an integral number), and the optional keyword
619 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
622 @subsection cfi options
625 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
626 <@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
627 CFI flashes require the number of the target they're connected to as an additional
628 argument. The CFI driver makes use of a working area (specified for the target)
629 to significantly speed up operation.
631 @var{chip_width} and @var{bus_width} are specified in bytes.
633 The @var{jedec_probe} option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
637 @subsection at91sam7 options
638 @cindex at91sam7 options
640 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
641 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
642 reading the chip-id and type.
644 @subsection str7 options
647 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
648 variant can be either STR71x, STR73x or STR75x.
650 @subsection str9 options
653 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
654 The str9 needs the flash controller to be configured prior to Flash programming, eg.
656 str9x flash_config 0 4 2 0 0x80000
658 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
660 @subsection str9 options (str9xpec driver)
662 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
663 Before using the flash commands the turbo mode will need enabling using str9xpec
664 @option{enable_turbo} <@var{num>.}
666 Only use this driver for locking/unlocking the device or configuring the option bytes.
667 Use the standard str9 driver for programming.
669 @subsection stellaris (LM3Sxxx) options
670 @cindex stellaris (LM3Sxxx) options
672 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
673 stellaris flash plugin only require the @var{target#}.
675 @subsection stm32x options
676 @cindex stm32x options
678 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
679 stm32x flash plugin only require the @var{target#}.
682 @chapter Target library
683 @cindex Target library
685 OpenOCD comes with a target configuration script library. These scripts can be
686 used as-is or serve as a starting point.
688 The target library is published together with the openocd executable and
689 the path to the target library is in the OpenOCD script search path.
690 Similarly there are example scripts for configuring the JTAG interface.
692 The command line below uses the example parport configuration scripts
693 that ship with OpenOCD, then configures the str710.cfg target and
694 finally issues the init and reset command. The communication speed
695 is set to 10kHz for reset and 8MHz for post reset.
699 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
703 To list the target scripts available:
706 $ ls /usr/local/lib/openocd/target
708 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
709 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
710 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
711 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
719 OpenOCD allows user interaction through a GDB server (default: port 3333),
720 a telnet interface (default: port 4444), and a TCL interface (default: port 5555). The command line interpreter
721 is available from both the telnet interface and a GDB session. To issue commands to the
722 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
723 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
726 The TCL interface is used as a simplified RPC mechanism that feeds all the
727 input into the TCL interpreter and returns the output from the evaluation of
733 @item @b{sleep} <@var{msec}>
735 Wait for n milliseconds before resuming. Useful in connection with script files
736 (@var{script} command and @var{target_script} configuration).
740 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
742 @item @b{debug_level} [@var{n}]
744 Display or adjust debug level to n<0-3>
746 @item @b{fast} [@var{enable/disable}]
748 Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
749 downloads and fast memory access will work if the JTAG interface isn't too fast and
750 the core doesn't run at a too low frequency. Note that this option only changes the default
751 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
754 The target specific "dangerous" optimisation tweaking options may come and go
755 as more robust and user friendly ways are found to ensure maximum throughput
756 and robustness with a minimum of configuration.
758 Typically the "fast enable" is specified first on the command line:
761 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
764 @item @b{log_output} <@var{file}>
766 Redirect logging to <file> (default: stderr)
768 @item @b{script} <@var{file}>
770 Execute commands from <file>
774 @subsection Target state handling
776 @item @b{poll} [@option{on}|@option{off}]
778 Poll the target for its current state. If the target is in debug mode, architecture
779 specific information about the current state is printed. An optional parameter
780 allows continuous polling to be enabled and disabled.
782 @item @b{halt} [@option{ms}]
784 Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
785 Default [@option{ms}] is 5 seconds if no arg given.
786 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
787 will stop OpenOCD from waiting.
789 @item @b{wait_halt} [@option{ms}]
791 Wait for the target to enter debug mode. Optional [@option{ms}] is
792 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
795 @item @b{resume} [@var{address}]
797 Resume the target at its current code position, or at an optional address.
798 OpenOCD will wait 5 seconds for the target to resume.
800 @item @b{step} [@var{address}]
802 Single-step the target at its current code position, or at an optional address.
804 @item @b{reset} [@option{run}|@option{halt}|@option{init}]
806 Perform a hard-reset. The optional parameter specifies what should happen after the reset.
808 With no arguments a "reset run" is executed
815 Immediately halt the target (works only with certain configurations).
818 Immediately halt the target, and execute the reset script (works only with certain
823 @subsection Memory access commands
824 These commands allow accesses of a specific size to the memory system:
826 @item @b{mdw} <@var{addr}> [@var{count}]
829 @item @b{mdh} <@var{addr}> [@var{count}]
831 display memory half-words
832 @item @b{mdb} <@var{addr}> [@var{count}]
835 @item @b{mww} <@var{addr}> <@var{value}>
838 @item @b{mwh} <@var{addr}> <@var{value}>
840 write memory half-word
841 @item @b{mwb} <@var{addr}> <@var{value}>
845 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
847 Load image <@var{file}> to target memory at <@var{address}>
848 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
850 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
851 (binary) <@var{file}>.
852 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
854 Verify <@var{file}> against target memory starting at <@var{address}>.
855 This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
858 @subsection Flash commands
859 @cindex Flash commands
861 @item @b{flash banks}
863 List configured flash banks
864 @item @b{flash info} <@var{num}>
866 Print info about flash bank <@option{num}>
867 @item @b{flash probe} <@var{num}>
869 Identify the flash, or validate the parameters of the configured flash. Operation
870 depends on the flash type.
871 @item @b{flash erase_check} <@var{num}>
872 @cindex flash erase_check
873 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
874 updates the erase state information displayed by @option{flash info}. That means you have
875 to issue an @option{erase_check} command after erasing or programming the device to get
877 @item @b{flash protect_check} <@var{num}>
878 @cindex flash protect_check
879 Check protection state of sectors in flash bank <num>.
880 @option{flash erase_sector} using the same syntax.
881 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
882 @cindex flash erase_sector
883 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
884 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
885 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
887 @item @b{flash erase_address} <@var{address}> <@var{length}>
888 @cindex flash erase_address
889 Erase sectors starting at <@var{address}> for <@var{length}> bytes
890 @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
891 @cindex flash write_bank
892 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
893 <@option{offset}> bytes from the beginning of the bank.
894 @item @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
895 @cindex flash write_image
896 Write the image <@var{file}> to the current target's flash bank(s). A relocation
897 [@var{offset}] can be specified and the file [@var{type}] can be specified
898 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
899 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
900 if the @option{erase} parameter is given.
901 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
902 @cindex flash protect
903 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
904 <@var{last}> of @option{flash bank} <@var{num}>.
908 @section Target Specific Commands
909 @cindex Target Specific Commands
911 @subsection AT91SAM7 specific commands
912 @cindex AT91SAM7 specific commands
913 The flash configuration is deduced from the chip identification register. The flash
914 controller handles erases automatically on a page (128/265 byte) basis so erase is
915 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
916 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
917 that can be erased separatly. Only an EraseAll command is supported by the controller
918 for each flash plane and this is called with
920 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
921 bulk erase flash planes first_plane to last_plane.
922 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
923 @cindex at91sam7 gpnvm
924 set or clear a gpnvm bit for the processor
927 @subsection STR9 specific commands
928 @cindex STR9 specific commands
929 These are flash specific commands when using the str9xpec driver.
931 @item @b{str9xpec enable_turbo} <@var{num}>
932 @cindex str9xpec enable_turbo
933 enable turbo mode, simply this will remove the str9 from the chain and talk
934 directly to the embedded flash controller.
935 @item @b{str9xpec disable_turbo} <@var{num}>
936 @cindex str9xpec disable_turbo
937 restore the str9 into jtag chain.
938 @item @b{str9xpec lock} <@var{num}>
939 @cindex str9xpec lock
940 lock str9 device. The str9 will only respond to an unlock command that will
942 @item @b{str9xpec unlock} <@var{num}>
943 @cindex str9xpec unlock
945 @item @b{str9xpec options_read} <@var{num}>
946 @cindex str9xpec options_read
947 read str9 option bytes.
948 @item @b{str9xpec options_write} <@var{num}>
949 @cindex str9xpec options_write
950 write str9 option bytes.
953 @subsection STR9 configuration
954 @cindex STR9 configuration
956 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
957 <@var{BBADR}> <@var{NBBADR}>
958 @cindex str9x flash_config
959 Configure str9 flash controller.
961 eg. str9x flash_config 0 4 2 0 0x80000
963 BBSR - Boot Bank Size register
964 NBBSR - Non Boot Bank Size register
965 BBADR - Boot Bank Start Address register
966 NBBADR - Boot Bank Start Address register
970 @subsection STR9 option byte configuration
971 @cindex STR9 option byte configuration
973 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
974 @cindex str9xpec options_cmap
975 configure str9 boot bank.
976 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
977 @cindex str9xpec options_lvdthd
978 configure str9 lvd threshold.
979 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
980 @cindex str9xpec options_lvdsel
981 configure str9 lvd source.
982 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
983 @cindex str9xpec options_lvdwarn
984 configure str9 lvd reset warning source.
987 @subsection STM32x specific commands
988 @cindex STM32x specific commands
990 These are flash specific commands when using the stm32x driver.
992 @item @b{stm32x lock} <@var{num}>
995 @item @b{stm32x unlock} <@var{num}>
996 @cindex stm32x unlock
998 @item @b{stm32x options_read} <@var{num}>
999 @cindex stm32x options_read
1000 read stm32 option bytes.
1001 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
1002 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
1003 @cindex stm32x options_write
1004 write stm32 option bytes.
1005 @item @b{stm32x mass_erase} <@var{num}>
1006 @cindex stm32x mass_erase
1007 mass erase flash memory.
1010 @subsection Stellaris specific commands
1011 @cindex Stellaris specific commands
1013 These are flash specific commands when using the Stellaris driver.
1015 @item @b{stellaris mass_erase} <@var{num}>
1016 @cindex stellaris mass_erase
1017 mass erase flash memory.
1021 @section Architecture Specific Commands
1022 @cindex Architecture Specific Commands
1024 @subsection ARMV4/5 specific commands
1025 @cindex ARMV4/5 specific commands
1027 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
1028 or Intel XScale (XScale isn't supported yet).
1030 @item @b{armv4_5 reg}
1032 Display a list of all banked core registers, fetching the current value from every
1033 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
1035 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
1036 @cindex armv4_5 core_mode
1037 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
1038 The target is resumed in the currently set @option{core_mode}.
1041 @subsection ARM7/9 specific commands
1042 @cindex ARM7/9 specific commands
1044 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
1045 ARM920t or ARM926EJ-S.
1047 @item @b{arm7_9 sw_bkpts} <@var{enable}|@var{disable}>
1048 @cindex arm7_9 sw_bkpts
1049 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
1050 one of the watchpoint registers to implement software breakpoints. Disabling
1051 SW Bkpts frees that register again.
1052 @item @b{arm7_9 force_hw_bkpts} <@var{enable}|@var{disable}>
1053 @cindex arm7_9 force_hw_bkpts
1054 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
1055 breakpoints are turned into hardware breakpoints.
1056 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
1057 @cindex arm7_9 dbgrq
1058 Enable use of the DBGRQ bit to force entry into debug mode. This should be
1059 safe for all but ARM7TDMI--S cores (like Philips LPC).
1060 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
1061 @cindex arm7_9 fast_memory_access
1062 Allow OpenOCD to read and write memory without checking completion of
1063 the operation. This provides a huge speed increase, especially with USB JTAG
1064 cables (FT2232), but might be unsafe if used with targets running at a very low
1065 speed, like the 32kHz startup clock of an AT91RM9200.
1066 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
1067 @cindex arm7_9 dcc_downloads
1068 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1069 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1070 unsafe, especially with targets running at a very low speed. This command was introduced
1071 with OpenOCD rev. 60.
1074 @subsection ARM720T specific commands
1075 @cindex ARM720T specific commands
1078 @item @b{arm720t cp15} <@var{num}> [@var{value}]
1079 @cindex arm720t cp15
1080 display/modify cp15 register <@option{num}> [@option{value}].
1081 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
1082 @cindex arm720t md<bhw>_phys
1083 Display memory at physical address addr.
1084 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
1085 @cindex arm720t mw<bhw>_phys
1086 Write memory at physical address addr.
1087 @item @b{arm720t virt2phys} <@var{va}>
1088 @cindex arm720t virt2phys
1089 Translate a virtual address to a physical address.
1092 @subsection ARM9TDMI specific commands
1093 @cindex ARM9TDMI specific commands
1096 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
1097 @cindex arm9tdmi vector_catch
1098 Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
1099 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
1100 @option{irq} @option{fiq}.
1102 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
1105 @subsection ARM966E specific commands
1106 @cindex ARM966E specific commands
1109 @item @b{arm966e cp15} <@var{num}> [@var{value}]
1110 @cindex arm966e cp15
1111 display/modify cp15 register <@option{num}> [@option{value}].
1114 @subsection ARM920T specific commands
1115 @cindex ARM920T specific commands
1118 @item @b{arm920t cp15} <@var{num}> [@var{value}]
1119 @cindex arm920t cp15
1120 display/modify cp15 register <@option{num}> [@option{value}].
1121 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
1122 @cindex arm920t cp15i
1123 display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
1124 @item @b{arm920t cache_info}
1125 @cindex arm920t cache_info
1126 Print information about the caches found. This allows you to see if your target
1127 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1128 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1129 @cindex arm920t md<bhw>_phys
1130 Display memory at physical address addr.
1131 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1132 @cindex arm920t mw<bhw>_phys
1133 Write memory at physical address addr.
1134 @item @b{arm920t read_cache} <@var{filename}>
1135 @cindex arm920t read_cache
1136 Dump the content of ICache and DCache to a file.
1137 @item @b{arm920t read_mmu} <@var{filename}>
1138 @cindex arm920t read_mmu
1139 Dump the content of the ITLB and DTLB to a file.
1140 @item @b{arm920t virt2phys} <@var{va}>
1141 @cindex arm920t virt2phys
1142 Translate a virtual address to a physical address.
1145 @subsection ARM926EJS specific commands
1146 @cindex ARM926EJS specific commands
1149 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
1150 @cindex arm926ejs cp15
1151 display/modify cp15 register <@option{num}> [@option{value}].
1152 @item @b{arm926ejs cache_info}
1153 @cindex arm926ejs cache_info
1154 Print information about the caches found.
1155 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
1156 @cindex arm926ejs md<bhw>_phys
1157 Display memory at physical address addr.
1158 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
1159 @cindex arm926ejs mw<bhw>_phys
1160 Write memory at physical address addr.
1161 @item @b{arm926ejs virt2phys} <@var{va}>
1162 @cindex arm926ejs virt2phys
1163 Translate a virtual address to a physical address.
1167 @section Debug commands
1168 @cindex Debug commands
1169 The following commands give direct access to the core, and are most likely
1170 only useful while debugging OpenOCD.
1172 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1173 @cindex arm7_9 write_xpsr
1174 Immediately write either the current program status register (CPSR) or the saved
1175 program status register (SPSR), without changing the register cache (as displayed
1176 by the @option{reg} and @option{armv4_5 reg} commands).
1177 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1178 <@var{0=cpsr},@var{1=spsr}>
1179 @cindex arm7_9 write_xpsr_im8
1180 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1181 operation (similar to @option{write_xpsr}).
1182 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1183 @cindex arm7_9 write_core_reg
1184 Write a core register, without changing the register cache (as displayed by the
1185 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1186 encoding of the [M4:M0] bits of the PSR.
1190 @section JTAG commands
1191 @cindex JTAG commands
1193 @item @b{scan_chain}
1195 Print current scan chain configuration.
1196 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
1199 @item @b{endstate} <@var{tap_state}>
1201 Finish JTAG operations in <@var{tap_state}>.
1202 @item @b{runtest} <@var{num_cycles}>
1204 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1205 @item @b{statemove} [@var{tap_state}]
1207 Move to current endstate or [@var{tap_state}]
1208 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1210 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1211 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
1213 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1214 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
1215 @cindex verify_ircapture
1216 Verify value captured during Capture-IR. Default is enabled.
1217 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1219 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1220 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1222 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
1226 @section Target Requests
1227 @cindex Target Requests
1228 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
1229 See libdcc in the contrib dir for more details.
1231 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
1232 @cindex target_request debugmsgs
1233 Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
1236 @node Sample Scripts
1237 @chapter Sample Scripts
1240 This page shows how to use the target library.
1242 The configuration script can be divided in the following section:
1244 @item daemon configuration
1246 @item jtag scan chain
1247 @item target configuration
1248 @item flash configuration
1251 Detailed information about each section can be found at OpenOCD configuration.
1253 @section AT91R40008 example
1254 @cindex AT91R40008 example
1255 To start OpenOCD with a target script for the AT91R40008 CPU and reset
1256 the CPU upon startup of the OpenOCD daemon.
1258 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
1262 @node GDB and OpenOCD
1263 @chapter GDB and OpenOCD
1264 @cindex GDB and OpenOCD
1265 OpenOCD complies with the remote gdbserver protocol, and as such can be used
1266 to debug remote targets.
1268 @section Connecting to gdb
1269 @cindex Connecting to gdb
1270 A connection is typically started as follows:
1272 target remote localhost:3333
1274 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1276 To see a list of available OpenOCD commands type @option{monitor help} on the
1279 OpenOCD supports the gdb @option{qSupported} packet, this enables information
1280 to be sent by the gdb server (openocd) to gdb. Typical information includes
1281 packet size and device memory map.
1283 Previous versions of OpenOCD required the following gdb options to increase
1284 the packet size and speed up gdb communication.
1286 set remote memory-write-packet-size 1024
1287 set remote memory-write-packet-size fixed
1288 set remote memory-read-packet-size 1024
1289 set remote memory-read-packet-size fixed
1291 This is now handled in the @option{qSupported} PacketSize.
1293 @section Programming using gdb
1294 @cindex Programming using gdb
1296 By default the target memory map is sent to gdb, this can be disabled by
1297 the following OpenOCD config option:
1299 gdb_memory_map disable
1301 For this to function correctly a valid flash config must also be configured
1302 in OpenOCD. For faster performance you should also configure a valid
1305 Informing gdb of the memory map of the target will enable gdb to protect any
1306 flash area of the target and use hardware breakpoints by default. This means
1307 that the OpenOCD option @option{arm7_9 force_hw_bkpts} is not required when
1310 To view the configured memory map in gdb, use the gdb command @option{info mem}
1311 All other unasigned addresses within gdb are treated as RAM.
1313 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
1314 this can be changed to the old behaviour by using the following gdb command.
1316 set mem inaccessible-by-default off
1319 If @option{gdb_flash_program enable} is also used, gdb will be able to
1320 program any flash memory using the vFlash interface.
1322 gdb will look at the target memory map when a load command is given, if any
1323 areas to be programmed lie within the target flash area the vFlash packets
1326 If the target needs configuring before gdb programming, a script can be executed.
1328 target_script 0 gdb_program_config config.script
1331 To verify any flash programming the gdb command @option{compare-sections}
1334 @node TCL and OpenOCD
1335 @chapter TCL and OpenOCD
1336 @cindex TCL and OpenOCD
1337 OpenOCD embeds a TCL interpreter (see JIM) for command parsing and scripting
1340 The TCL interpreter can be invoked from the interactive command line, files, and a network port.
1342 The command and file interfaces are fairly straightforward, while the network
1343 port is geared toward intergration with external clients. A small example
1344 of an external TCL script that can connect to openocd is shown below.
1347 # Simple tcl client to connect to openocd
1348 puts "Use empty line to exit"
1349 set fo [socket 127.0.0.1 6666]
1350 puts -nonewline stdout "> "
1352 while {[gets stdin line] >= 0} {
1353 if {$line eq {}} break
1358 puts -nonewline stdout "> "
1364 This script can easily be modified to front various GUIs or be a sub
1365 component of a larger framework for control and interaction.
1368 @node TCL scripting API
1369 @chapter TCL scripting API
1370 @cindex TCL scripting API
1373 The commands are stateless. E.g. the telnet command line has a concept
1374 of currently active target, the Tcl API proc's take this sort of state
1375 information as an argument to each proc.
1377 There are three main types of return values: single value, name value
1378 pair list and lists.
1380 Name value pair. The proc 'foo' below returns a name/value pair
1386 > set foo(you) Oyvind
1387 > set foo(mouse) Micky
1388 > set foo(duck) Donald
1396 me Duane you Oyvind mouse Micky duck Donald
1398 Thus, to get the names of the associative array is easy:
1400 foreach { name value } [set foo] {
1401 puts "Name: $name, Value: $value"
1405 Lists returned must be relatively small. Otherwise a range
1406 should be passed in to the proc in question.
1408 Low level commands are prefixed with "openocd_", e.g. openocd_flash_banks
1409 is the low level API upon which "flash banks" is implemented.
1411 OpenOCD commands can consist of two words, e.g. "flash banks". The
1412 startup.tcl "unknown" proc will translate this into a tcl proc
1413 called "flash_banks".
1417 @chapter Deprecated/Removed Commands
1418 @cindex Deprecated/Removed Commands
1419 Certain OpenOCD commands have been deprecated/removed during the various revisions.
1422 @item @b{load_binary}
1424 use @option{load_image} command with same args
1425 @item @b{dump_binary}
1427 use @option{dump_image} command with same args
1428 @item @b{flash erase}
1430 use @option{flash erase_sector} command with same args
1431 @item @b{flash write}
1433 use @option{flash write_bank} command with same args
1434 @item @b{flash write_binary}
1435 @cindex flash write_binary
1436 use @option{flash write_bank} command with same args
1437 @item @b{arm7_9 fast_writes}
1438 @cindex arm7_9 fast_writes
1439 use @option{arm7_9 fast_memory_access} command with same args
1440 @item @b{flash auto_erase}
1441 @cindex flash auto_erase
1442 use @option{flash write_image} command passing @option{erase} as the first parameter.
1443 @item @b{daemon_startup}
1444 @cindex daemon_startup
1445 this config option has been removed, simply adding @option{init} and @option{reset halt} to
1446 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
1447 and @option{target cortex_m3 little reset_halt 0}.
1448 @item @b{run_and_halt_time}
1449 @cindex run_and_halt_time
1450 This command has been removed for simpler reset behaviour, it can be simulated with the
1463 @item OpenOCD complains about a missing cygwin1.dll.
1465 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1466 claims to come with all the necessary dlls. When using Cygwin, try launching
1467 OpenOCD from the Cygwin shell.
1469 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1470 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1471 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1473 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1474 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1475 software breakpoints consume one of the two available hardware breakpoints,
1476 and are therefore disabled by default. If your code is running from RAM, you
1477 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1478 your code resides in Flash, you can't use software breakpoints, but you can force
1479 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1481 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1482 and works sometimes fine.
1484 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1485 clock at the time you're programming the flash. If you've specified the crystal's
1486 frequency, make sure the PLL is disabled, if you've specified the full core speed
1487 (e.g. 60MHz), make sure the PLL is enabled.
1489 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1490 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1491 out while waiting for end of scan, rtck was disabled".
1493 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1494 settings in your PC BIOS (ECP, EPP, and different versions of those).
1496 @item When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1497 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1498 memory read caused data abort".
1500 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1501 beyond the last valid frame. It might be possible to prevent this by setting up
1502 a proper "initial" stack frame, if you happen to know what exactly has to
1503 be done, feel free to add this here.
1505 @item I get the following message in the OpenOCD console (or log file):
1506 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1508 This warning doesn't indicate any serious problem, as long as you don't want to
1509 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1510 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
1511 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1512 independently. With this setup, it's not possible to halt the core right out of
1513 reset, everything else should work fine.
1515 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1516 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1517 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1518 quit with an error message. Is there a stability issue with OpenOCD?
1520 No, this is not a stability issue concerning OpenOCD. Most users have solved
1521 this issue by simply using a self-powered USB hub, which they connect their
1522 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1523 supply stable enough for the Amontec JTAGkey to be operated.
1525 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1526 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1527 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1528 What does that mean and what might be the reason for this?
1530 First of all, the reason might be the USB power supply. Try using a self-powered
1531 hub instead of a direct connection to your computer. Secondly, the error code 4
1532 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1533 chip ran into some sort of error - this points us to a USB problem.
1535 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1536 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1537 What does that mean and what might be the reason for this?
1539 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1540 has closed the connection to OpenOCD. This might be a GDB issue.
1542 @item In the configuration file in the section where flash device configurations
1543 are described, there is a parameter for specifying the clock frequency for
1544 LPC2000 internal flash devices (e.g.
1545 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
1546 which must be specified in kilohertz. However, I do have a quartz crystal of a
1547 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1548 Is it possible to specify real numbers for the clock frequency?
1550 No. The clock frequency specified here must be given as an integral number.
1551 However, this clock frequency is used by the In-Application-Programming (IAP)
1552 routines of the LPC2000 family only, which seems to be very tolerant concerning
1553 the given clock frequency, so a slight difference between the specified clock
1554 frequency and the actual clock frequency will not cause any trouble.
1556 @item Do I have to keep a specific order for the commands in the configuration file?
1558 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1559 listed for the JTAG scan chain must be given in the right order (jtag_device),
1560 with the device closest to the TDO-Pin being listed first. In general,
1561 whenever objects of the same type exist which require an index number, then
1562 these objects must be given in the right order (jtag_devices, targets and flash
1563 banks - a target references a jtag_device and a flash bank references a target).
1565 @item Sometimes my debugging session terminates with an error. When I look into the
1566 log file, I can see these error messages: Error: arm7_9_common.c:561
1567 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP