1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
100 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
101 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
106 @section What is OpenOCD?
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board can be directly connected to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD only supports
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
153 based, parallel port based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
158 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
159 debugged via the GDB protocol.
161 @b{Flash Programing:} Flash writing is supported for external CFI
162 compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
164 STM32x). Preliminary support for various NAND flash controllers
165 (LPC3180, Orion, S3C24xx, more) controller is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{http://openocd.sourceforge.net/}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published irregularly at:
179 @uref{http://openocd.sourceforge.net/doc/html/index.html}
181 PDF form is likewise published at:
183 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
197 @chapter OpenOCD Developer Resources
200 If you are interested in improving the state of OpenOCD's debugging and
201 testing support, new contributions will be welcome. Motivated developers
202 can produce new target, flash or interface drivers, improve the
203 documentation, as well as more conventional bug fixes and enhancements.
205 The resources in this chapter are available for developers wishing to explore
206 or expand the OpenOCD source code.
208 @section OpenOCD GIT Repository
210 During the 0.3.x release cycle, OpenOCD switched from Subversion to
211 a GIT repository hosted at SourceForge. The repository URL is:
213 @uref{git://openocd.git.sourceforge.net/gitroot/openocd/openocd}
215 You may prefer to use a mirror and the HTTP protocol:
217 @uref{http://repo.or.cz/r/openocd.git}
219 With standard GIT tools, use @command{git clone} to initialize
220 a local repository, and @command{git pull} to update it.
221 There are also gitweb pages letting you browse the repository
222 with a web browser, or download arbitrary snapshots without
223 needing a GIT client:
225 @uref{http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd}
227 @uref{http://repo.or.cz/w/openocd.git}
229 The @file{README} file contains the instructions for building the project
230 from the repository or a snapshot.
232 Developers that want to contribute patches to the OpenOCD system are
233 @b{strongly} encouraged to work against mainline.
234 Patches created against older versions may require additional
235 work from their submitter in order to be updated for newer releases.
237 @section Doxygen Developer Manual
239 During the 0.2.x release cycle, the OpenOCD project began
240 providing a Doxygen reference manual. This document contains more
241 technical information about the software internals, development
242 processes, and similar documentation:
244 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
246 This document is a work-in-progress, but contributions would be welcome
247 to fill in the gaps. All of the source files are provided in-tree,
248 listed in the Doxyfile configuration in the top of the source tree.
250 @section OpenOCD Developer Mailing List
252 The OpenOCD Developer Mailing List provides the primary means of
253 communication between developers:
255 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
257 Discuss and submit patches to this list.
258 The @file{HACKING} file contains basic information about how
261 @section OpenOCD Bug Database
263 During the 0.4.x release cycle the OpenOCD project team began
264 using Trac for its bug database:
266 @uref{https://sourceforge.net/apps/trac/openocd}
269 @node Debug Adapter Hardware
270 @chapter Debug Adapter Hardware
279 Defined: @b{dongle}: A small device that plugins into a computer and serves as
280 an adapter .... [snip]
282 In the OpenOCD case, this generally refers to @b{a small adapter} that
283 attaches to your computer via USB or the Parallel Printer Port. One
284 exception is the Zylin ZY1000, packaged as a small box you attach via
285 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
286 require any drivers to be installed on the developer PC. It also has
287 a built in web interface. It supports RTCK/RCLK or adaptive clocking
288 and has a built in relay to power cycle targets remotely.
291 @section Choosing a Dongle
293 There are several things you should keep in mind when choosing a dongle.
296 @item @b{Transport} Does it support the kind of communication that you need?
297 OpenOCD focusses mostly on JTAG. Your version may also support
298 other ways to communicate with target devices.
299 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
300 Does your dongle support it? You might need a level converter.
301 @item @b{Pinout} What pinout does your target board use?
302 Does your dongle support it? You may be able to use jumper
303 wires, or an "octopus" connector, to convert pinouts.
304 @item @b{Connection} Does your computer have the USB, printer, or
305 Ethernet port needed?
306 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
307 RTCK support? Also known as ``adaptive clocking''
310 @section Stand alone Systems
312 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe} Technically, not a
313 dongle, but a standalone box. The ZY1000 has the advantage that it does
314 not require any drivers installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built in relay to power cycle targets remotely.
318 @section USB FT2232 Based
320 There are many USB JTAG dongles on the market, many of them are based
321 on a chip from ``Future Technology Devices International'' (FTDI)
322 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
323 See: @url{http://www.ftdichip.com} for more information.
324 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
325 chips are starting to become available in JTAG adapters. (Adapters
326 using those high speed FT2232H chips may support adaptive clocking.)
328 The FT2232 chips are flexible enough to support some other
329 transport options, such as SWD or the SPI variants used to
330 program some chips. They have two communications channels,
331 and one can be used for a UART adapter at the same time the
332 other one is used to provide a debug adapter.
334 Also, some development boards integrate an FT2232 chip to serve as
335 a built-in low cost debug adapter and usb-to-serial solution.
339 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
341 @* See: @url{http://www.amontec.com/jtagkey.shtml}
343 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
345 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
347 @* See: @url{http://www.signalyzer.com}
348 @item @b{Stellaris Eval Boards}
349 @* See: @url{http://www.luminarymicro.com} - The Stellaris eval boards
350 bundle FT2232-based JTAG and SWD support, which can be used to debug
351 the Stellaris chips. Using separate JTAG adapters is optional.
352 These boards can also be used in a "pass through" mode as JTAG adapters
353 to other target boards, disabling the Stellaris chip.
354 @item @b{Luminary ICDI}
355 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug
356 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
357 Evaluation Kits. Like the non-detachable FT2232 support on the other
358 Stellaris eval boards, they can be used to debug other target boards.
359 @item @b{olimex-jtag}
360 @* See: @url{http://www.olimex.com}
361 @item @b{Flyswatter/Flyswatter2}
362 @* See: @url{http://www.tincantools.com}
363 @item @b{turtelizer2}
365 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
366 @url{http://www.ethernut.de}
368 @* Link: @url{http://www.hitex.com/index.php?id=383}
370 @* Link @url{http://www.hitex.com/stm32-stick}
371 @item @b{axm0432_jtag}
372 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
373 to be available anymore as of April 2012.
375 @* Link @url{http://www.hitex.com/index.php?id=cortino}
376 @item @b{dlp-usb1232h}
377 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
378 @item @b{digilent-hs1}
379 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
382 @section USB-JTAG / Altera USB-Blaster compatibles
384 These devices also show up as FTDI devices, but are not
385 protocol-compatible with the FT2232 devices. They are, however,
386 protocol-compatible among themselves. USB-JTAG devices typically consist
387 of a FT245 followed by a CPLD that understands a particular protocol,
388 or emulate this protocol using some other hardware.
390 They may appear under different USB VID/PID depending on the particular
391 product. The driver can be configured to search for any VID/PID pair
392 (see the section on driver commands).
395 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
396 @* Link: @url{http://ixo-jtag.sourceforge.net/}
397 @item @b{Altera USB-Blaster}
398 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
401 @section USB JLINK based
402 There are several OEM versions of the Segger @b{JLINK} adapter. It is
403 an example of a micro controller based JTAG adapter, it uses an
404 AT91SAM764 internally.
407 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
408 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
409 @item @b{SEGGER JLINK}
410 @* Link: @url{http://www.segger.com/jlink.html}
412 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
415 @section USB RLINK based
416 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
419 @item @b{Raisonance RLink}
420 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
421 @item @b{STM32 Primer}
422 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
423 @item @b{STM32 Primer2}
424 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
427 @section USB ST-LINK based
428 ST Micro has an adapter called @b{ST-LINK}.
429 They only work with ST Micro chips, notably STM32 and STM8.
433 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
434 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
436 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
437 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
440 For info the original ST-LINK enumerates using the mass storage usb class, however
441 it's implementation is completely broken. The result is this causes issues under linux.
442 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
444 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
445 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
451 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
453 @item @b{USB - Presto}
454 @* Link: @url{http://tools.asix.net/prg_presto.htm}
456 @item @b{Versaloon-Link}
457 @* Link: @url{http://www.versaloon.com}
459 @item @b{ARM-JTAG-EW}
460 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
463 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
466 @* Link: @url{http://code.google.com/p/opendous-jtag/}
469 @* Link: @url{http://code.google.com/p/estick-jtag/}
472 @section IBM PC Parallel Printer Port Based
474 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
475 and the Macraigor Wiggler. There are many clones and variations of
478 Note that parallel ports are becoming much less common, so if you
479 have the choice you should probably avoid these adapters in favor
484 @item @b{Wiggler} - There are many clones of this.
485 @* Link: @url{http://www.macraigor.com/wiggler.htm}
487 @item @b{DLC5} - From XILINX - There are many clones of this
488 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
489 produced, PDF schematics are easily found and it is easy to make.
491 @item @b{Amontec - JTAG Accelerator}
492 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
495 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
498 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
500 @item @b{Wiggler_ntrst_inverted}
501 @* Yet another variation - See the source code, src/jtag/parport.c
503 @item @b{old_amt_wiggler}
504 @* Unknown - probably not on the market today
507 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
510 @* Link: @url{http://www.amontec.com/chameleon.shtml}
516 @* ispDownload from Lattice Semiconductor
517 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
520 @* From ST Microsystems;
521 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
529 @* An EP93xx based Linux machine using the GPIO pins directly.
532 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
537 @chapter About Jim-Tcl
541 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
542 This programming language provides a simple and extensible
545 All commands presented in this Guide are extensions to Jim-Tcl.
546 You can use them as simple commands, without needing to learn
547 much of anything about Tcl.
548 Alternatively, can write Tcl programs with them.
550 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
551 There is an active and responsive community, get on the mailing list
552 if you have any questions. Jim-Tcl maintainers also lurk on the
553 OpenOCD mailing list.
556 @item @b{Jim vs. Tcl}
557 @* Jim-Tcl is a stripped down version of the well known Tcl language,
558 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
559 fewer features. Jim-Tcl is several dozens of .C files and .H files and
560 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
561 4.2 MB .zip file containing 1540 files.
563 @item @b{Missing Features}
564 @* Our practice has been: Add/clone the real Tcl feature if/when
565 needed. We welcome Jim-Tcl improvements, not bloat. Also there
566 are a large number of optional Jim-Tcl features that are not
570 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
571 command interpreter today is a mixture of (newer)
572 Jim-Tcl commands, and (older) the orginal command interpreter.
575 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
576 can type a Tcl for() loop, set variables, etc.
577 Some of the commands documented in this guide are implemented
578 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
580 @item @b{Historical Note}
581 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
582 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
583 as a git submodule, which greatly simplified upgrading Jim Tcl
584 to benefit from new features and bugfixes in Jim Tcl.
586 @item @b{Need a crash course in Tcl?}
587 @*@xref{Tcl Crash Course}.
592 @cindex command line options
594 @cindex directory search
596 Properly installing OpenOCD sets up your operating system to grant it access
597 to the debug adapters. On Linux, this usually involves installing a file
598 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
599 complex and confusing driver configuration for every peripheral. Such issues
600 are unique to each operating system, and are not detailed in this User's Guide.
602 Then later you will invoke the OpenOCD server, with various options to
603 tell it how each debug session should work.
604 The @option{--help} option shows:
608 --help | -h display this help
609 --version | -v display OpenOCD version
610 --file | -f use configuration file <name>
611 --search | -s dir to search for config files and scripts
612 --debug | -d set debug level <0-3>
613 --log_output | -l redirect log output to file <name>
614 --command | -c run <command>
617 If you don't give any @option{-f} or @option{-c} options,
618 OpenOCD tries to read the configuration file @file{openocd.cfg}.
619 To specify one or more different
620 configuration files, use @option{-f} options. For example:
623 openocd -f config1.cfg -f config2.cfg -f config3.cfg
626 Configuration files and scripts are searched for in
628 @item the current directory,
629 @item any search dir specified on the command line using the @option{-s} option,
630 @item any search dir specified using the @command{add_script_search_dir} command,
631 @item @file{$HOME/.openocd} (not on Windows),
632 @item the site wide script library @file{$pkgdatadir/site} and
633 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
635 The first found file with a matching file name will be used.
638 Don't try to use configuration script names or paths which
639 include the "#" character. That character begins Tcl comments.
642 @section Simple setup, no customization
644 In the best case, you can use two scripts from one of the script
645 libraries, hook up your JTAG adapter, and start the server ... and
646 your JTAG setup will just work "out of the box". Always try to
647 start by reusing those scripts, but assume you'll need more
648 customization even if this works. @xref{OpenOCD Project Setup}.
650 If you find a script for your JTAG adapter, and for your board or
651 target, you may be able to hook up your JTAG adapter then start
655 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
658 You might also need to configure which reset signals are present,
659 using @option{-c 'reset_config trst_and_srst'} or something similar.
660 If all goes well you'll see output something like
663 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
664 For bug reports, read
665 http://openocd.sourceforge.net/doc/doxygen/bugs.html
666 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
667 (mfg: 0x23b, part: 0xba00, ver: 0x3)
670 Seeing that "tap/device found" message, and no warnings, means
671 the JTAG communication is working. That's a key milestone, but
672 you'll probably need more project-specific setup.
674 @section What OpenOCD does as it starts
676 OpenOCD starts by processing the configuration commands provided
677 on the command line or, if there were no @option{-c command} or
678 @option{-f file.cfg} options given, in @file{openocd.cfg}.
679 @xref{Configuration Stage}.
680 At the end of the configuration stage it verifies the JTAG scan
681 chain defined using those commands; your configuration should
682 ensure that this always succeeds.
683 Normally, OpenOCD then starts running as a daemon.
684 Alternatively, commands may be used to terminate the configuration
685 stage early, perform work (such as updating some flash memory),
686 and then shut down without acting as a daemon.
688 Once OpenOCD starts running as a daemon, it waits for connections from
689 clients (Telnet, GDB, Other) and processes the commands issued through
692 If you are having problems, you can enable internal debug messages via
693 the @option{-d} option.
695 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
696 @option{-c} command line switch.
698 To enable debug output (when reporting problems or working on OpenOCD
699 itself), use the @option{-d} command line switch. This sets the
700 @option{debug_level} to "3", outputting the most information,
701 including debug messages. The default setting is "2", outputting only
702 informational messages, warnings and errors. You can also change this
703 setting from within a telnet or gdb session using @command{debug_level
704 <n>} (@pxref{debug_level}).
706 You can redirect all output from the daemon to a file using the
707 @option{-l <logfile>} switch.
709 Note! OpenOCD will launch the GDB & telnet server even if it can not
710 establish a connection with the target. In general, it is possible for
711 the JTAG controller to be unresponsive until the target is set up
712 correctly via e.g. GDB monitor commands in a GDB init script.
714 @node OpenOCD Project Setup
715 @chapter OpenOCD Project Setup
717 To use OpenOCD with your development projects, you need to do more than
718 just connecting the JTAG adapter hardware (dongle) to your development board
719 and then starting the OpenOCD server.
720 You also need to configure that server so that it knows
721 about that adapter and board, and helps your work.
722 You may also want to connect OpenOCD to GDB, possibly
723 using Eclipse or some other GUI.
725 @section Hooking up the JTAG Adapter
727 Today's most common case is a dongle with a JTAG cable on one side
728 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
729 and a USB cable on the other.
730 Instead of USB, some cables use Ethernet;
731 older ones may use a PC parallel port, or even a serial port.
734 @item @emph{Start with power to your target board turned off},
735 and nothing connected to your JTAG adapter.
736 If you're particularly paranoid, unplug power to the board.
737 It's important to have the ground signal properly set up,
738 unless you are using a JTAG adapter which provides
739 galvanic isolation between the target board and the
742 @item @emph{Be sure it's the right kind of JTAG connector.}
743 If your dongle has a 20-pin ARM connector, you need some kind
744 of adapter (or octopus, see below) to hook it up to
745 boards using 14-pin or 10-pin connectors ... or to 20-pin
746 connectors which don't use ARM's pinout.
748 In the same vein, make sure the voltage levels are compatible.
749 Not all JTAG adapters have the level shifters needed to work
750 with 1.2 Volt boards.
752 @item @emph{Be certain the cable is properly oriented} or you might
753 damage your board. In most cases there are only two possible
754 ways to connect the cable.
755 Connect the JTAG cable from your adapter to the board.
756 Be sure it's firmly connected.
758 In the best case, the connector is keyed to physically
759 prevent you from inserting it wrong.
760 This is most often done using a slot on the board's male connector
761 housing, which must match a key on the JTAG cable's female connector.
762 If there's no housing, then you must look carefully and
763 make sure pin 1 on the cable hooks up to pin 1 on the board.
764 Ribbon cables are frequently all grey except for a wire on one
765 edge, which is red. The red wire is pin 1.
767 Sometimes dongles provide cables where one end is an ``octopus'' of
768 color coded single-wire connectors, instead of a connector block.
769 These are great when converting from one JTAG pinout to another,
770 but are tedious to set up.
771 Use these with connector pinout diagrams to help you match up the
772 adapter signals to the right board pins.
774 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
775 A USB, parallel, or serial port connector will go to the host which
776 you are using to run OpenOCD.
777 For Ethernet, consult the documentation and your network administrator.
779 For USB based JTAG adapters you have an easy sanity check at this point:
780 does the host operating system see the JTAG adapter? If that host is an
781 MS-Windows host, you'll need to install a driver before OpenOCD works.
783 @item @emph{Connect the adapter's power supply, if needed.}
784 This step is primarily for non-USB adapters,
785 but sometimes USB adapters need extra power.
787 @item @emph{Power up the target board.}
788 Unless you just let the magic smoke escape,
789 you're now ready to set up the OpenOCD server
790 so you can use JTAG to work with that board.
794 Talk with the OpenOCD server using
795 telnet (@code{telnet localhost 4444} on many systems) or GDB.
796 @xref{GDB and OpenOCD}.
798 @section Project Directory
800 There are many ways you can configure OpenOCD and start it up.
802 A simple way to organize them all involves keeping a
803 single directory for your work with a given board.
804 When you start OpenOCD from that directory,
805 it searches there first for configuration files, scripts,
806 files accessed through semihosting,
807 and for code you upload to the target board.
808 It is also the natural place to write files,
809 such as log files and data you download from the board.
811 @section Configuration Basics
813 There are two basic ways of configuring OpenOCD, and
814 a variety of ways you can mix them.
815 Think of the difference as just being how you start the server:
818 @item Many @option{-f file} or @option{-c command} options on the command line
819 @item No options, but a @dfn{user config file}
820 in the current directory named @file{openocd.cfg}
823 Here is an example @file{openocd.cfg} file for a setup
824 using a Signalyzer FT2232-based JTAG adapter to talk to
825 a board with an Atmel AT91SAM7X256 microcontroller:
828 source [find interface/signalyzer.cfg]
830 # GDB can also flash my flash!
831 gdb_memory_map enable
832 gdb_flash_program enable
834 source [find target/sam7x256.cfg]
837 Here is the command line equivalent of that configuration:
840 openocd -f interface/signalyzer.cfg \
841 -c "gdb_memory_map enable" \
842 -c "gdb_flash_program enable" \
843 -f target/sam7x256.cfg
846 You could wrap such long command lines in shell scripts,
847 each supporting a different development task.
848 One might re-flash the board with a specific firmware version.
849 Another might set up a particular debugging or run-time environment.
852 At this writing (October 2009) the command line method has
853 problems with how it treats variables.
854 For example, after @option{-c "set VAR value"}, or doing the
855 same in a script, the variable @var{VAR} will have no value
856 that can be tested in a later script.
859 Here we will focus on the simpler solution: one user config
860 file, including basic configuration plus any TCL procedures
861 to simplify your work.
863 @section User Config Files
864 @cindex config file, user
865 @cindex user config file
866 @cindex config file, overview
868 A user configuration file ties together all the parts of a project
870 One of the following will match your situation best:
873 @item Ideally almost everything comes from configuration files
874 provided by someone else.
875 For example, OpenOCD distributes a @file{scripts} directory
876 (probably in @file{/usr/share/openocd/scripts} on Linux).
877 Board and tool vendors can provide these too, as can individual
878 user sites; the @option{-s} command line option lets you say
879 where to find these files. (@xref{Running}.)
880 The AT91SAM7X256 example above works this way.
882 Three main types of non-user configuration file each have their
883 own subdirectory in the @file{scripts} directory:
886 @item @b{interface} -- one for each different debug adapter;
887 @item @b{board} -- one for each different board
888 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
891 Best case: include just two files, and they handle everything else.
892 The first is an interface config file.
893 The second is board-specific, and it sets up the JTAG TAPs and
894 their GDB targets (by deferring to some @file{target.cfg} file),
895 declares all flash memory, and leaves you nothing to do except
899 source [find interface/olimex-jtag-tiny.cfg]
900 source [find board/csb337.cfg]
903 Boards with a single microcontroller often won't need more
904 than the target config file, as in the AT91SAM7X256 example.
905 That's because there is no external memory (flash, DDR RAM), and
906 the board differences are encapsulated by application code.
908 @item Maybe you don't know yet what your board looks like to JTAG.
909 Once you know the @file{interface.cfg} file to use, you may
910 need help from OpenOCD to discover what's on the board.
911 Once you find the JTAG TAPs, you can just search for appropriate
913 configuration files ... or write your own, from the bottom up.
916 @item You can often reuse some standard config files but
917 need to write a few new ones, probably a @file{board.cfg} file.
918 You will be using commands described later in this User's Guide,
919 and working with the guidelines in the next chapter.
921 For example, there may be configuration files for your JTAG adapter
922 and target chip, but you need a new board-specific config file
923 giving access to your particular flash chips.
924 Or you might need to write another target chip configuration file
925 for a new chip built around the Cortex M3 core.
928 When you write new configuration files, please submit
929 them for inclusion in the next OpenOCD release.
930 For example, a @file{board/newboard.cfg} file will help the
931 next users of that board, and a @file{target/newcpu.cfg}
932 will help support users of any board using that chip.
936 You may may need to write some C code.
937 It may be as simple as a supporting a new ft2232 or parport
938 based adapter; a bit more involved, like a NAND or NOR flash
939 controller driver; or a big piece of work like supporting
940 a new chip architecture.
943 Reuse the existing config files when you can.
944 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
945 You may find a board configuration that's a good example to follow.
947 When you write config files, separate the reusable parts
948 (things every user of that interface, chip, or board needs)
949 from ones specific to your environment and debugging approach.
953 For example, a @code{gdb-attach} event handler that invokes
954 the @command{reset init} command will interfere with debugging
955 early boot code, which performs some of the same actions
956 that the @code{reset-init} event handler does.
959 Likewise, the @command{arm9 vector_catch} command (or
961 its siblings @command{xscale vector_catch}
962 and @command{cortex_m3 vector_catch}) can be a timesaver
963 during some debug sessions, but don't make everyone use that either.
964 Keep those kinds of debugging aids in your user config file,
965 along with messaging and tracing setup.
966 (@xref{Software Debug Messages and Tracing}.)
969 You might need to override some defaults.
970 For example, you might need to move, shrink, or back up the target's
971 work area if your application needs much SRAM.
974 TCP/IP port configuration is another example of something which
975 is environment-specific, and should only appear in
976 a user config file. @xref{TCP/IP Ports}.
979 @section Project-Specific Utilities
981 A few project-specific utility
982 routines may well speed up your work.
983 Write them, and keep them in your project's user config file.
985 For example, if you are making a boot loader work on a
986 board, it's nice to be able to debug the ``after it's
987 loaded to RAM'' parts separately from the finicky early
988 code which sets up the DDR RAM controller and clocks.
989 A script like this one, or a more GDB-aware sibling,
993 proc ramboot @{ @} @{
994 # Reset, running the target's "reset-init" scripts
995 # to initialize clocks and the DDR RAM controller.
996 # Leave the CPU halted.
999 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1000 load_image u-boot.bin 0x20000000
1007 Then once that code is working you will need to make it
1008 boot from NOR flash; a different utility would help.
1009 Alternatively, some developers write to flash using GDB.
1010 (You might use a similar script if you're working with a flash
1011 based microcontroller application instead of a boot loader.)
1014 proc newboot @{ @} @{
1015 # Reset, leaving the CPU halted. The "reset-init" event
1016 # proc gives faster access to the CPU and to NOR flash;
1017 # "reset halt" would be slower.
1020 # Write standard version of U-Boot into the first two
1021 # sectors of NOR flash ... the standard version should
1022 # do the same lowlevel init as "reset-init".
1023 flash protect 0 0 1 off
1024 flash erase_sector 0 0 1
1025 flash write_bank 0 u-boot.bin 0x0
1026 flash protect 0 0 1 on
1028 # Reboot from scratch using that new boot loader.
1033 You may need more complicated utility procedures when booting
1035 That often involves an extra bootloader stage,
1036 running from on-chip SRAM to perform DDR RAM setup so it can load
1037 the main bootloader code (which won't fit into that SRAM).
1039 Other helper scripts might be used to write production system images,
1040 involving considerably more than just a three stage bootloader.
1042 @section Target Software Changes
1044 Sometimes you may want to make some small changes to the software
1045 you're developing, to help make JTAG debugging work better.
1046 For example, in C or assembly language code you might
1047 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1048 handling issues like:
1052 @item @b{Watchdog Timers}...
1053 Watchog timers are typically used to automatically reset systems if
1054 some application task doesn't periodically reset the timer. (The
1055 assumption is that the system has locked up if the task can't run.)
1056 When a JTAG debugger halts the system, that task won't be able to run
1057 and reset the timer ... potentially causing resets in the middle of
1058 your debug sessions.
1060 It's rarely a good idea to disable such watchdogs, since their usage
1061 needs to be debugged just like all other parts of your firmware.
1062 That might however be your only option.
1064 Look instead for chip-specific ways to stop the watchdog from counting
1065 while the system is in a debug halt state. It may be simplest to set
1066 that non-counting mode in your debugger startup scripts. You may however
1067 need a different approach when, for example, a motor could be physically
1068 damaged by firmware remaining inactive in a debug halt state. That might
1069 involve a type of firmware mode where that "non-counting" mode is disabled
1070 at the beginning then re-enabled at the end; a watchdog reset might fire
1071 and complicate the debug session, but hardware (or people) would be
1072 protected.@footnote{Note that many systems support a "monitor mode" debug
1073 that is a somewhat cleaner way to address such issues. You can think of
1074 it as only halting part of the system, maybe just one task,
1075 instead of the whole thing.
1076 At this writing, January 2010, OpenOCD based debugging does not support
1077 monitor mode debug, only "halt mode" debug.}
1079 @item @b{ARM Semihosting}...
1080 @cindex ARM semihosting
1081 When linked with a special runtime library provided with many
1082 toolchains@footnote{See chapter 8 "Semihosting" in
1083 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1084 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1085 The CodeSourcery EABI toolchain also includes a semihosting library.},
1086 your target code can use I/O facilities on the debug host. That library
1087 provides a small set of system calls which are handled by OpenOCD.
1088 It can let the debugger provide your system console and a file system,
1089 helping with early debugging or providing a more capable environment
1090 for sometimes-complex tasks like installing system firmware onto
1093 @item @b{ARM Wait-For-Interrupt}...
1094 Many ARM chips synchronize the JTAG clock using the core clock.
1095 Low power states which stop that core clock thus prevent JTAG access.
1096 Idle loops in tasking environments often enter those low power states
1097 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1099 You may want to @emph{disable that instruction} in source code,
1100 or otherwise prevent using that state,
1101 to ensure you can get JTAG access at any time.@footnote{As a more
1102 polite alternative, some processors have special debug-oriented
1103 registers which can be used to change various features including
1104 how the low power states are clocked while debugging.
1105 The STM32 DBGMCU_CR register is an example; at the cost of extra
1106 power consumption, JTAG can be used during low power states.}
1107 For example, the OpenOCD @command{halt} command may not
1108 work for an idle processor otherwise.
1110 @item @b{Delay after reset}...
1111 Not all chips have good support for debugger access
1112 right after reset; many LPC2xxx chips have issues here.
1113 Similarly, applications that reconfigure pins used for
1114 JTAG access as they start will also block debugger access.
1116 To work with boards like this, @emph{enable a short delay loop}
1117 the first thing after reset, before "real" startup activities.
1118 For example, one second's delay is usually more than enough
1119 time for a JTAG debugger to attach, so that
1120 early code execution can be debugged
1121 or firmware can be replaced.
1123 @item @b{Debug Communications Channel (DCC)}...
1124 Some processors include mechanisms to send messages over JTAG.
1125 Many ARM cores support these, as do some cores from other vendors.
1126 (OpenOCD may be able to use this DCC internally, speeding up some
1127 operations like writing to memory.)
1129 Your application may want to deliver various debugging messages
1130 over JTAG, by @emph{linking with a small library of code}
1131 provided with OpenOCD and using the utilities there to send
1132 various kinds of message.
1133 @xref{Software Debug Messages and Tracing}.
1137 @section Target Hardware Setup
1139 Chip vendors often provide software development boards which
1140 are highly configurable, so that they can support all options
1141 that product boards may require. @emph{Make sure that any
1142 jumpers or switches match the system configuration you are
1145 Common issues include:
1149 @item @b{JTAG setup} ...
1150 Boards may support more than one JTAG configuration.
1151 Examples include jumpers controlling pullups versus pulldowns
1152 on the nTRST and/or nSRST signals, and choice of connectors
1153 (e.g. which of two headers on the base board,
1154 or one from a daughtercard).
1155 For some Texas Instruments boards, you may need to jumper the
1156 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1158 @item @b{Boot Modes} ...
1159 Complex chips often support multiple boot modes, controlled
1160 by external jumpers. Make sure this is set up correctly.
1161 For example many i.MX boards from NXP need to be jumpered
1162 to "ATX mode" to start booting using the on-chip ROM, when
1163 using second stage bootloader code stored in a NAND flash chip.
1165 Such explicit configuration is common, and not limited to
1166 booting from NAND. You might also need to set jumpers to
1167 start booting using code loaded from an MMC/SD card; external
1168 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1169 flash; some external host; or various other sources.
1172 @item @b{Memory Addressing} ...
1173 Boards which support multiple boot modes may also have jumpers
1174 to configure memory addressing. One board, for example, jumpers
1175 external chipselect 0 (used for booting) to address either
1176 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1177 or NAND flash. When it's jumpered to address NAND flash, that
1178 board must also be told to start booting from on-chip ROM.
1180 Your @file{board.cfg} file may also need to be told this jumper
1181 configuration, so that it can know whether to declare NOR flash
1182 using @command{flash bank} or instead declare NAND flash with
1183 @command{nand device}; and likewise which probe to perform in
1184 its @code{reset-init} handler.
1186 A closely related issue is bus width. Jumpers might need to
1187 distinguish between 8 bit or 16 bit bus access for the flash
1188 used to start booting.
1190 @item @b{Peripheral Access} ...
1191 Development boards generally provide access to every peripheral
1192 on the chip, sometimes in multiple modes (such as by providing
1193 multiple audio codec chips).
1194 This interacts with software
1195 configuration of pin multiplexing, where for example a
1196 given pin may be routed either to the MMC/SD controller
1197 or the GPIO controller. It also often interacts with
1198 configuration jumpers. One jumper may be used to route
1199 signals to an MMC/SD card slot or an expansion bus (which
1200 might in turn affect booting); others might control which
1201 audio or video codecs are used.
1205 Plus you should of course have @code{reset-init} event handlers
1206 which set up the hardware to match that jumper configuration.
1207 That includes in particular any oscillator or PLL used to clock
1208 the CPU, and any memory controllers needed to access external
1209 memory and peripherals. Without such handlers, you won't be
1210 able to access those resources without working target firmware
1211 which can do that setup ... this can be awkward when you're
1212 trying to debug that target firmware. Even if there's a ROM
1213 bootloader which handles a few issues, it rarely provides full
1214 access to all board-specific capabilities.
1217 @node Config File Guidelines
1218 @chapter Config File Guidelines
1220 This chapter is aimed at any user who needs to write a config file,
1221 including developers and integrators of OpenOCD and any user who
1222 needs to get a new board working smoothly.
1223 It provides guidelines for creating those files.
1225 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1226 with files including the ones listed here.
1227 Use them as-is where you can; or as models for new files.
1229 @item @file{interface} ...
1230 These are for debug adapters.
1231 Files that configure JTAG adapters go here.
1234 altera-usb-blaster.cfg hilscher_nxhx50_etm.cfg openrd.cfg
1235 arm-jtag-ew.cfg hilscher_nxhx50_re.cfg osbdm.cfg
1236 arm-usb-ocd.cfg hitex_str9-comstick.cfg parport.cfg
1237 at91rm9200.cfg icebear.cfg parport_dlc5.cfg
1238 axm0432.cfg jlink.cfg redbee-econotag.cfg
1239 busblaster.cfg jtagkey2.cfg redbee-usb.cfg
1240 buspirate.cfg jtagkey2p.cfg rlink.cfg
1241 calao-usb-a9260-c01.cfg jtagkey.cfg sheevaplug.cfg
1242 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg signalyzer.cfg
1243 calao-usb-a9260.cfg kt-link.cfg signalyzer-h2.cfg
1244 chameleon.cfg lisa-l.cfg signalyzer-h4.cfg
1245 cortino.cfg luminary.cfg signalyzer-lite.cfg
1246 digilent-hs1.cfg luminary-icdi.cfg stlink-v1.cfg
1247 dlp-usb1232h.cfg luminary-lm3s811.cfg stlink-v2.cfg
1248 dummy.cfg minimodule.cfg stm32-stick.cfg
1249 estick.cfg neodb.cfg turtelizer2.cfg
1250 flashlink.cfg ngxtech.cfg ulink.cfg
1251 flossjtag.cfg olimex-arm-usb-ocd.cfg usb-jtag.cfg
1252 flossjtag-noeeprom.cfg olimex-arm-usb-ocd-h.cfg usbprog.cfg
1253 flyswatter2.cfg olimex-arm-usb-tiny-h.cfg vpaclink.cfg
1254 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
1255 hilscher_nxhx10_etm.cfg oocdlink.cfg xds100v2.cfg
1256 hilscher_nxhx500_etm.cfg opendous.cfg
1257 hilscher_nxhx500_re.cfg openocd-usb.cfg
1260 @item @file{board} ...
1261 think Circuit Board, PWA, PCB, they go by many names. Board files
1262 contain initialization items that are specific to a board.
1263 They reuse target configuration files, since the same
1264 microprocessor chips are used on many boards,
1265 but support for external parts varies widely. For
1266 example, the SDRAM initialization sequence for the board, or the type
1267 of external flash and what address it uses. Any initialization
1268 sequence to enable that external flash or SDRAM should be found in the
1269 board file. Boards may also contain multiple targets: two CPUs; or
1273 actux3.cfg logicpd_imx27.cfg
1274 am3517evm.cfg lubbock.cfg
1275 arm_evaluator7t.cfg mcb1700.cfg
1276 at91cap7a-stk-sdram.cfg microchip_explorer16.cfg
1277 at91eb40a.cfg mini2440.cfg
1278 at91rm9200-dk.cfg mini6410.cfg
1279 at91rm9200-ek.cfg olimex_LPC2378STK.cfg
1280 at91sam9261-ek.cfg olimex_lpc_h2148.cfg
1281 at91sam9263-ek.cfg olimex_sam7_ex256.cfg
1282 at91sam9g20-ek.cfg olimex_sam9_l9260.cfg
1283 atmel_at91sam7s-ek.cfg olimex_stm32_h103.cfg
1284 atmel_at91sam9260-ek.cfg olimex_stm32_h107.cfg
1285 atmel_at91sam9rl-ek.cfg olimex_stm32_p107.cfg
1286 atmel_sam3n_ek.cfg omap2420_h4.cfg
1287 atmel_sam3s_ek.cfg open-bldc.cfg
1288 atmel_sam3u_ek.cfg openrd.cfg
1289 atmel_sam3x_ek.cfg osk5912.cfg
1290 atmel_sam4s_ek.cfg phytec_lpc3250.cfg
1291 balloon3-cpu.cfg pic-p32mx.cfg
1292 colibri.cfg propox_mmnet1001.cfg
1293 crossbow_tech_imote2.cfg pxa255_sst.cfg
1294 csb337.cfg redbee.cfg
1295 csb732.cfg rsc-w910.cfg
1296 da850evm.cfg sheevaplug.cfg
1297 digi_connectcore_wi-9c.cfg smdk6410.cfg
1298 diolan_lpc4350-db1.cfg spear300evb.cfg
1299 dm355evm.cfg spear300evb_mod.cfg
1300 dm365evm.cfg spear310evb20.cfg
1301 dm6446evm.cfg spear310evb20_mod.cfg
1302 efikamx.cfg spear320cpu.cfg
1303 eir.cfg spear320cpu_mod.cfg
1304 ek-lm3s1968.cfg steval_pcc010.cfg
1305 ek-lm3s3748.cfg stm320518_eval_stlink.cfg
1306 ek-lm3s6965.cfg stm32100b_eval.cfg
1307 ek-lm3s811.cfg stm3210b_eval.cfg
1308 ek-lm3s811-revb.cfg stm3210c_eval.cfg
1309 ek-lm3s9b9x.cfg stm3210e_eval.cfg
1310 ek-lm4f232.cfg stm3220g_eval.cfg
1311 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1312 ethernut3.cfg stm3241g_eval.cfg
1313 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1314 hammer.cfg stm32f0discovery.cfg
1315 hilscher_nxdb500sys.cfg stm32f4discovery.cfg
1316 hilscher_nxeb500hmi.cfg stm32ldiscovery.cfg
1317 hilscher_nxhx10.cfg stm32vldiscovery.cfg
1318 hilscher_nxhx500.cfg str910-eval.cfg
1319 hilscher_nxhx50.cfg telo.cfg
1320 hilscher_nxsb100.cfg ti_beagleboard.cfg
1321 hitex_lpc2929.cfg ti_beagleboard_xm.cfg
1322 hitex_stm32-performancestick.cfg ti_beaglebone.cfg
1323 hitex_str9-comstick.cfg ti_blaze.cfg
1324 iar_lpc1768.cfg ti_pandaboard.cfg
1325 iar_str912_sk.cfg ti_pandaboard_es.cfg
1326 icnova_imx53_sodimm.cfg topas910.cfg
1327 icnova_sam9g45_sodimm.cfg topasa900.cfg
1328 imx27ads.cfg twr-k60n512.cfg
1329 imx27lnst.cfg tx25_stk5.cfg
1330 imx28evk.cfg tx27_stk5.cfg
1331 imx31pdk.cfg unknown_at91sam9260.cfg
1332 imx35pdk.cfg uptech_2410.cfg
1333 imx53loco.cfg verdex.cfg
1334 keil_mcb1700.cfg voipac.cfg
1335 keil_mcb2140.cfg voltcraft_dso-3062c.cfg
1336 kwikstik.cfg x300t.cfg
1337 linksys_nslu2.cfg zy1000.cfg
1341 @item @file{target} ...
1342 think chip. The ``target'' directory represents the JTAG TAPs
1344 which OpenOCD should control, not a board. Two common types of targets
1345 are ARM chips and FPGA or CPLD chips.
1346 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1347 the target config file defines all of them.
1350 $duc702x.cfg ixp42x.cfg
1353 ar71xx.cfg lpc1768.cfg
1354 at32ap7000.cfg lpc2103.cfg
1355 at91r40008.cfg lpc2124.cfg
1356 at91rm9200.cfg lpc2129.cfg
1357 at91sam3ax_4x.cfg lpc2148.cfg
1358 at91sam3ax_8x.cfg lpc2294.cfg
1359 at91sam3ax_xx.cfg lpc2378.cfg
1360 at91sam3nXX.cfg lpc2460.cfg
1361 at91sam3sXX.cfg lpc2478.cfg
1362 at91sam3u1c.cfg lpc2900.cfg
1363 at91sam3u1e.cfg lpc2xxx.cfg
1364 at91sam3u2c.cfg lpc3131.cfg
1365 at91sam3u2e.cfg lpc3250.cfg
1366 at91sam3u4c.cfg lpc4350.cfg
1367 at91sam3u4e.cfg mc13224v.cfg
1368 at91sam3uxx.cfg nuc910.cfg
1369 at91sam3XXX.cfg omap2420.cfg
1370 at91sam4sXX.cfg omap3530.cfg
1371 at91sam4XXX.cfg omap4430.cfg
1372 at91sam7se512.cfg omap4460.cfg
1373 at91sam7sx.cfg omap5912.cfg
1374 at91sam7x256.cfg omapl138.cfg
1375 at91sam7x512.cfg pic32mx.cfg
1376 at91sam9260.cfg pxa255.cfg
1377 at91sam9260_ext_RAM_ext_flash.cfg pxa270.cfg
1378 at91sam9261.cfg pxa3xx.cfg
1379 at91sam9263.cfg readme.txt
1380 at91sam9.cfg samsung_s3c2410.cfg
1381 at91sam9g10.cfg samsung_s3c2440.cfg
1382 at91sam9g20.cfg samsung_s3c2450.cfg
1383 at91sam9g45.cfg samsung_s3c4510.cfg
1384 at91sam9rl.cfg samsung_s3c6410.cfg
1385 atmega128.cfg sharp_lh79532.cfg
1386 avr32.cfg smp8634.cfg
1387 c100.cfg spear3xx.cfg
1388 c100config.tcl stellaris.cfg
1389 c100helper.tcl stm32.cfg
1390 c100regs.tcl stm32f0x_stlink.cfg
1391 cs351x.cfg stm32f1x.cfg
1392 davinci.cfg stm32f1x_stlink.cfg
1393 dragonite.cfg stm32f2x.cfg
1394 dsp56321.cfg stm32f2x_stlink.cfg
1395 dsp568013.cfg stm32f2xxx.cfg
1396 dsp568037.cfg stm32f4x.cfg
1397 epc9301.cfg stm32f4x_stlink.cfg
1399 feroceon.cfg stm32lx_stlink.cfg
1400 fm3.cfg stm32_stlink.cfg
1401 hilscher_netx10.cfg stm32xl.cfg
1402 hilscher_netx500.cfg str710.cfg
1403 hilscher_netx50.cfg str730.cfg
1404 icepick.cfg str750.cfg
1405 imx21.cfg str912.cfg
1406 imx25.cfg swj-dp.tcl
1407 imx27.cfg test_reset_syntax_error.cfg
1408 imx28.cfg test_syntax_error.cfg
1409 imx31.cfg ti_dm355.cfg
1410 imx35.cfg ti_dm365.cfg
1411 imx51.cfg ti_dm6446.cfg
1412 imx53.cfg tmpa900.cfg
1414 is5114.cfg u8500.cfg
1416 @item @emph{more} ... browse for other library files which may be useful.
1417 For example, there are various generic and CPU-specific utilities.
1420 The @file{openocd.cfg} user config
1421 file may override features in any of the above files by
1422 setting variables before sourcing the target file, or by adding
1423 commands specific to their situation.
1425 @section Interface Config Files
1427 The user config file
1428 should be able to source one of these files with a command like this:
1431 source [find interface/FOOBAR.cfg]
1434 A preconfigured interface file should exist for every debug adapter
1435 in use today with OpenOCD.
1436 That said, perhaps some of these config files
1437 have only been used by the developer who created it.
1439 A separate chapter gives information about how to set these up.
1440 @xref{Debug Adapter Configuration}.
1441 Read the OpenOCD source code (and Developer's Guide)
1442 if you have a new kind of hardware interface
1443 and need to provide a driver for it.
1445 @section Board Config Files
1446 @cindex config file, board
1447 @cindex board config file
1449 The user config file
1450 should be able to source one of these files with a command like this:
1453 source [find board/FOOBAR.cfg]
1456 The point of a board config file is to package everything
1457 about a given board that user config files need to know.
1458 In summary the board files should contain (if present)
1461 @item One or more @command{source [target/...cfg]} statements
1462 @item NOR flash configuration (@pxref{NOR Configuration})
1463 @item NAND flash configuration (@pxref{NAND Configuration})
1464 @item Target @code{reset} handlers for SDRAM and I/O configuration
1465 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1466 @item All things that are not ``inside a chip''
1469 Generic things inside target chips belong in target config files,
1470 not board config files. So for example a @code{reset-init} event
1471 handler should know board-specific oscillator and PLL parameters,
1472 which it passes to target-specific utility code.
1474 The most complex task of a board config file is creating such a
1475 @code{reset-init} event handler.
1476 Define those handlers last, after you verify the rest of the board
1477 configuration works.
1479 @subsection Communication Between Config files
1481 In addition to target-specific utility code, another way that
1482 board and target config files communicate is by following a
1483 convention on how to use certain variables.
1485 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1486 Thus the rule we follow in OpenOCD is this: Variables that begin with
1487 a leading underscore are temporary in nature, and can be modified and
1488 used at will within a target configuration file.
1490 Complex board config files can do the things like this,
1491 for a board with three chips:
1494 # Chip #1: PXA270 for network side, big endian
1495 set CHIPNAME network
1497 source [find target/pxa270.cfg]
1498 # on return: _TARGETNAME = network.cpu
1499 # other commands can refer to the "network.cpu" target.
1500 $_TARGETNAME configure .... events for this CPU..
1502 # Chip #2: PXA270 for video side, little endian
1505 source [find target/pxa270.cfg]
1506 # on return: _TARGETNAME = video.cpu
1507 # other commands can refer to the "video.cpu" target.
1508 $_TARGETNAME configure .... events for this CPU..
1510 # Chip #3: Xilinx FPGA for glue logic
1513 source [find target/spartan3.cfg]
1516 That example is oversimplified because it doesn't show any flash memory,
1517 or the @code{reset-init} event handlers to initialize external DRAM
1518 or (assuming it needs it) load a configuration into the FPGA.
1519 Such features are usually needed for low-level work with many boards,
1520 where ``low level'' implies that the board initialization software may
1521 not be working. (That's a common reason to need JTAG tools. Another
1522 is to enable working with microcontroller-based systems, which often
1523 have no debugging support except a JTAG connector.)
1525 Target config files may also export utility functions to board and user
1526 config files. Such functions should use name prefixes, to help avoid
1529 Board files could also accept input variables from user config files.
1530 For example, there might be a @code{J4_JUMPER} setting used to identify
1531 what kind of flash memory a development board is using, or how to set
1532 up other clocks and peripherals.
1534 @subsection Variable Naming Convention
1535 @cindex variable names
1537 Most boards have only one instance of a chip.
1538 However, it should be easy to create a board with more than
1539 one such chip (as shown above).
1540 Accordingly, we encourage these conventions for naming
1541 variables associated with different @file{target.cfg} files,
1542 to promote consistency and
1543 so that board files can override target defaults.
1545 Inputs to target config files include:
1548 @item @code{CHIPNAME} ...
1549 This gives a name to the overall chip, and is used as part of
1550 tap identifier dotted names.
1551 While the default is normally provided by the chip manufacturer,
1552 board files may need to distinguish between instances of a chip.
1553 @item @code{ENDIAN} ...
1554 By default @option{little} - although chips may hard-wire @option{big}.
1555 Chips that can't change endianness don't need to use this variable.
1556 @item @code{CPUTAPID} ...
1557 When OpenOCD examines the JTAG chain, it can be told verify the
1558 chips against the JTAG IDCODE register.
1559 The target file will hold one or more defaults, but sometimes the
1560 chip in a board will use a different ID (perhaps a newer revision).
1563 Outputs from target config files include:
1566 @item @code{_TARGETNAME} ...
1567 By convention, this variable is created by the target configuration
1568 script. The board configuration file may make use of this variable to
1569 configure things like a ``reset init'' script, or other things
1570 specific to that board and that target.
1571 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1572 @code{_TARGETNAME1}, ... etc.
1575 @subsection The reset-init Event Handler
1576 @cindex event, reset-init
1577 @cindex reset-init handler
1579 Board config files run in the OpenOCD configuration stage;
1580 they can't use TAPs or targets, since they haven't been
1582 This means you can't write memory or access chip registers;
1583 you can't even verify that a flash chip is present.
1584 That's done later in event handlers, of which the target @code{reset-init}
1585 handler is one of the most important.
1587 Except on microcontrollers, the basic job of @code{reset-init} event
1588 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1589 Microcontrollers rarely use boot loaders; they run right out of their
1590 on-chip flash and SRAM memory. But they may want to use one of these
1591 handlers too, if just for developer convenience.
1594 Because this is so very board-specific, and chip-specific, no examples
1596 Instead, look at the board config files distributed with OpenOCD.
1597 If you have a boot loader, its source code will help; so will
1598 configuration files for other JTAG tools
1599 (@pxref{Translating Configuration Files}).
1602 Some of this code could probably be shared between different boards.
1603 For example, setting up a DRAM controller often doesn't differ by
1604 much except the bus width (16 bits or 32?) and memory timings, so a
1605 reusable TCL procedure loaded by the @file{target.cfg} file might take
1606 those as parameters.
1607 Similarly with oscillator, PLL, and clock setup;
1608 and disabling the watchdog.
1609 Structure the code cleanly, and provide comments to help
1610 the next developer doing such work.
1611 (@emph{You might be that next person} trying to reuse init code!)
1613 The last thing normally done in a @code{reset-init} handler is probing
1614 whatever flash memory was configured. For most chips that needs to be
1615 done while the associated target is halted, either because JTAG memory
1616 access uses the CPU or to prevent conflicting CPU access.
1618 @subsection JTAG Clock Rate
1620 Before your @code{reset-init} handler has set up
1621 the PLLs and clocking, you may need to run with
1622 a low JTAG clock rate.
1624 Then you'd increase that rate after your handler has
1625 made it possible to use the faster JTAG clock.
1626 When the initial low speed is board-specific, for example
1627 because it depends on a board-specific oscillator speed, then
1628 you should probably set it up in the board config file;
1629 if it's target-specific, it belongs in the target config file.
1631 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1632 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1633 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1634 Consult chip documentation to determine the peak JTAG clock rate,
1635 which might be less than that.
1638 On most ARMs, JTAG clock detection is coupled to the core clock, so
1639 software using a @option{wait for interrupt} operation blocks JTAG access.
1640 Adaptive clocking provides a partial workaround, but a more complete
1641 solution just avoids using that instruction with JTAG debuggers.
1644 If both the chip and the board support adaptive clocking,
1645 use the @command{jtag_rclk}
1646 command, in case your board is used with JTAG adapter which
1647 also supports it. Otherwise use @command{adapter_khz}.
1648 Set the slow rate at the beginning of the reset sequence,
1649 and the faster rate as soon as the clocks are at full speed.
1651 @anchor{The init_board procedure}
1652 @subsection The init_board procedure
1653 @cindex init_board procedure
1655 The concept of @code{init_board} procedure is very similar to @code{init_targets} (@xref{The init_targets procedure}.)
1656 - it's a replacement of ``linear'' configuration scripts. This procedure is meant to be executed when OpenOCD enters run
1657 stage (@xref{Entering the Run Stage},) after @code{init_targets}. The idea to have spearate @code{init_targets} and
1658 @code{init_board} procedures is to allow the first one to configure everything target specific (internal flash,
1659 internal RAM, etc.) and the second one to configure everything board specific (reset signals, chip frequency,
1660 reset-init event handler, external memory, etc.). Additionally ``linear'' board config file will most likely fail when
1661 target config file uses @code{init_targets} scheme (``linear'' script is executed before @code{init} and
1662 @code{init_targets} - after), so separating these two configuration stages is very convenient, as the easiest way to
1663 overcome this problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1664 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1666 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1667 the original), allowing greater code reuse.
1670 ### board_file.cfg ###
1672 # source target file that does most of the config in init_targets
1673 source [find target/target.cfg]
1675 proc enable_fast_clock @{@} @{
1676 # enables fast on-board clock source
1677 # configures the chip to use it
1680 # initialize only board specifics - reset, clock, adapter frequency
1681 proc init_board @{@} @{
1682 reset_config trst_and_srst trst_pulls_srst
1684 $_TARGETNAME configure -event reset-init @{
1692 @section Target Config Files
1693 @cindex config file, target
1694 @cindex target config file
1696 Board config files communicate with target config files using
1697 naming conventions as described above, and may source one or
1698 more target config files like this:
1701 source [find target/FOOBAR.cfg]
1704 The point of a target config file is to package everything
1705 about a given chip that board config files need to know.
1706 In summary the target files should contain
1710 @item Add TAPs to the scan chain
1711 @item Add CPU targets (includes GDB support)
1712 @item CPU/Chip/CPU-Core specific features
1716 As a rule of thumb, a target file sets up only one chip.
1717 For a microcontroller, that will often include a single TAP,
1718 which is a CPU needing a GDB target, and its on-chip flash.
1720 More complex chips may include multiple TAPs, and the target
1721 config file may need to define them all before OpenOCD
1722 can talk to the chip.
1723 For example, some phone chips have JTAG scan chains that include
1724 an ARM core for operating system use, a DSP,
1725 another ARM core embedded in an image processing engine,
1726 and other processing engines.
1728 @subsection Default Value Boiler Plate Code
1730 All target configuration files should start with code like this,
1731 letting board config files express environment-specific
1732 differences in how things should be set up.
1735 # Boards may override chip names, perhaps based on role,
1736 # but the default should match what the vendor uses
1737 if @{ [info exists CHIPNAME] @} @{
1738 set _CHIPNAME $CHIPNAME
1740 set _CHIPNAME sam7x256
1743 # ONLY use ENDIAN with targets that can change it.
1744 if @{ [info exists ENDIAN] @} @{
1750 # TAP identifiers may change as chips mature, for example with
1751 # new revision fields (the "3" here). Pick a good default; you
1752 # can pass several such identifiers to the "jtag newtap" command.
1753 if @{ [info exists CPUTAPID ] @} @{
1754 set _CPUTAPID $CPUTAPID
1756 set _CPUTAPID 0x3f0f0f0f
1759 @c but 0x3f0f0f0f is for an str73x part ...
1761 @emph{Remember:} Board config files may include multiple target
1762 config files, or the same target file multiple times
1763 (changing at least @code{CHIPNAME}).
1765 Likewise, the target configuration file should define
1766 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1767 use it later on when defining debug targets:
1770 set _TARGETNAME $_CHIPNAME.cpu
1771 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1774 @subsection Adding TAPs to the Scan Chain
1775 After the ``defaults'' are set up,
1776 add the TAPs on each chip to the JTAG scan chain.
1777 @xref{TAP Declaration}, and the naming convention
1780 In the simplest case the chip has only one TAP,
1781 probably for a CPU or FPGA.
1782 The config file for the Atmel AT91SAM7X256
1783 looks (in part) like this:
1786 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1789 A board with two such at91sam7 chips would be able
1790 to source such a config file twice, with different
1791 values for @code{CHIPNAME}, so
1792 it adds a different TAP each time.
1794 If there are nonzero @option{-expected-id} values,
1795 OpenOCD attempts to verify the actual tap id against those values.
1796 It will issue error messages if there is mismatch, which
1797 can help to pinpoint problems in OpenOCD configurations.
1800 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1801 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1802 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1803 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1804 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1807 There are more complex examples too, with chips that have
1808 multiple TAPs. Ones worth looking at include:
1811 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1812 plus a JRC to enable them
1813 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1814 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1815 is not currently used)
1818 @subsection Add CPU targets
1820 After adding a TAP for a CPU, you should set it up so that
1821 GDB and other commands can use it.
1822 @xref{CPU Configuration}.
1823 For the at91sam7 example above, the command can look like this;
1824 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1825 to little endian, and this chip doesn't support changing that.
1828 set _TARGETNAME $_CHIPNAME.cpu
1829 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1832 Work areas are small RAM areas associated with CPU targets.
1833 They are used by OpenOCD to speed up downloads,
1834 and to download small snippets of code to program flash chips.
1835 If the chip includes a form of ``on-chip-ram'' - and many do - define
1836 a work area if you can.
1837 Again using the at91sam7 as an example, this can look like:
1840 $_TARGETNAME configure -work-area-phys 0x00200000 \
1841 -work-area-size 0x4000 -work-area-backup 0
1844 @anchor{Define CPU targets working in SMP}
1845 @subsection Define CPU targets working in SMP
1847 After setting targets, you can define a list of targets working in SMP.
1850 set _TARGETNAME_1 $_CHIPNAME.cpu1
1851 set _TARGETNAME_2 $_CHIPNAME.cpu2
1852 target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
1853 -coreid 0 -dbgbase $_DAP_DBG1
1854 target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
1855 -coreid 1 -dbgbase $_DAP_DBG2
1856 #define 2 targets working in smp.
1857 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1859 In the above example on cortex_a8, 2 cpus are working in SMP.
1860 In SMP only one GDB instance is created and :
1862 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1863 @item halt command triggers the halt of all targets in the list.
1864 @item resume command triggers the write context and the restart of all targets in the list.
1865 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1866 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1867 displayed by the GDB session @pxref{Using openocd SMP with GDB}.
1870 The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
1871 command have been implemented.
1873 @item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
1874 @item cortex_a8 smp_off : disable SMP mode, the current target is the one
1875 displayed in the GDB session, only this target is now controlled by GDB
1876 session. This behaviour is useful during system boot up.
1877 @item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
1884 #0 : coreid 0 is displayed to GDB ,
1885 #-> -1 : next resume triggers a real resume
1886 > cortex_a8 smp_gdb 1
1888 #0 :coreid 0 is displayed to GDB ,
1889 #->1 : next resume displays coreid 1 to GDB
1893 #1 :coreid 1 is displayed to GDB ,
1894 #->1 : next resume displays coreid 1 to GDB
1895 > cortex_a8 smp_gdb -1
1897 #1 :coreid 1 is displayed to GDB,
1898 #->-1 : next resume triggers a real resume
1902 @subsection Chip Reset Setup
1904 As a rule, you should put the @command{reset_config} command
1905 into the board file. Most things you think you know about a
1906 chip can be tweaked by the board.
1908 Some chips have specific ways the TRST and SRST signals are
1909 managed. In the unusual case that these are @emph{chip specific}
1910 and can never be changed by board wiring, they could go here.
1911 For example, some chips can't support JTAG debugging without
1914 Provide a @code{reset-assert} event handler if you can.
1915 Such a handler uses JTAG operations to reset the target,
1916 letting this target config be used in systems which don't
1917 provide the optional SRST signal, or on systems where you
1918 don't want to reset all targets at once.
1919 Such a handler might write to chip registers to force a reset,
1920 use a JRC to do that (preferable -- the target may be wedged!),
1921 or force a watchdog timer to trigger.
1922 (For Cortex-M3 targets, this is not necessary. The target
1923 driver knows how to use trigger an NVIC reset when SRST is
1926 Some chips need special attention during reset handling if
1927 they're going to be used with JTAG.
1928 An example might be needing to send some commands right
1929 after the target's TAP has been reset, providing a
1930 @code{reset-deassert-post} event handler that writes a chip
1931 register to report that JTAG debugging is being done.
1932 Another would be reconfiguring the watchdog so that it stops
1933 counting while the core is halted in the debugger.
1935 JTAG clocking constraints often change during reset, and in
1936 some cases target config files (rather than board config files)
1937 are the right places to handle some of those issues.
1938 For example, immediately after reset most chips run using a
1939 slower clock than they will use later.
1940 That means that after reset (and potentially, as OpenOCD
1941 first starts up) they must use a slower JTAG clock rate
1942 than they will use later.
1945 @quotation Important
1946 When you are debugging code that runs right after chip
1947 reset, getting these issues right is critical.
1948 In particular, if you see intermittent failures when
1949 OpenOCD verifies the scan chain after reset,
1950 look at how you are setting up JTAG clocking.
1953 @anchor{The init_targets procedure}
1954 @subsection The init_targets procedure
1955 @cindex init_targets procedure
1957 Target config files can either be ``linear'' (script executed line-by-line when parsed in configuration stage,
1958 @xref{Configuration Stage},) or they can contain a special procedure called @code{init_targets}, which will be executed
1959 when entering run stage (after parsing all config files or after @code{init} command, @xref{Entering the Run Stage}.)
1960 Such procedure can be overriden by ``next level'' script (which sources the original). This concept faciliates code
1961 reuse when basic target config files provide generic configuration procedures and @code{init_targets} procedure, which
1962 can then be sourced and enchanced or changed in a ``more specific'' target config file. This is not possible with
1963 ``linear'' config scripts, because sourcing them executes every initialization commands they provide.
1966 ### generic_file.cfg ###
1968 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1969 # basic initialization procedure ...
1972 proc init_targets @{@} @{
1973 # initializes generic chip with 4kB of flash and 1kB of RAM
1974 setup_my_chip MY_GENERIC_CHIP 4096 1024
1977 ### specific_file.cfg ###
1979 source [find target/generic_file.cfg]
1981 proc init_targets @{@} @{
1982 # initializes specific chip with 128kB of flash and 64kB of RAM
1983 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1987 The easiest way to convert ``linear'' config files to @code{init_targets} version is to enclose every line of ``code''
1988 (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1990 For an example of this scheme see LPC2000 target config files.
1992 The @code{init_boards} procedure is a similar concept concerning board config files (@xref{The init_board procedure}.)
1994 @subsection ARM Core Specific Hacks
1996 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1997 special high speed download features - enable it.
1999 If present, the MMU, the MPU and the CACHE should be disabled.
2001 Some ARM cores are equipped with trace support, which permits
2002 examination of the instruction and data bus activity. Trace
2003 activity is controlled through an ``Embedded Trace Module'' (ETM)
2004 on one of the core's scan chains. The ETM emits voluminous data
2005 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
2006 If you are using an external trace port,
2007 configure it in your board config file.
2008 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2009 configure it in your target config file.
2012 etm config $_TARGETNAME 16 normal full etb
2013 etb config $_TARGETNAME $_CHIPNAME.etb
2016 @subsection Internal Flash Configuration
2018 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2020 @b{Never ever} in the ``target configuration file'' define any type of
2021 flash that is external to the chip. (For example a BOOT flash on
2022 Chip Select 0.) Such flash information goes in a board file - not
2023 the TARGET (chip) file.
2027 @item at91sam7x256 - has 256K flash YES enable it.
2028 @item str912 - has flash internal YES enable it.
2029 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2030 @item pxa270 - again - CS0 flash - it goes in the board file.
2033 @anchor{Translating Configuration Files}
2034 @section Translating Configuration Files
2036 If you have a configuration file for another hardware debugger
2037 or toolset (Abatron, BDI2000, BDI3000, CCS,
2038 Lauterbach, Segger, Macraigor, etc.), translating
2039 it into OpenOCD syntax is often quite straightforward. The most tricky
2040 part of creating a configuration script is oftentimes the reset init
2041 sequence where e.g. PLLs, DRAM and the like is set up.
2043 One trick that you can use when translating is to write small
2044 Tcl procedures to translate the syntax into OpenOCD syntax. This
2045 can avoid manual translation errors and make it easier to
2046 convert other scripts later on.
2048 Example of transforming quirky arguments to a simple search and
2052 # Lauterbach syntax(?)
2054 # Data.Set c15:0x042f %long 0x40000015
2056 # OpenOCD syntax when using procedure below.
2058 # setc15 0x01 0x00050078
2060 proc setc15 @{regs value@} @{
2063 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2065 arm mcr 15 [expr ($regs>>12)&0x7] \
2066 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2067 [expr ($regs>>8)&0x7] $value
2073 @node Daemon Configuration
2074 @chapter Daemon Configuration
2075 @cindex initialization
2076 The commands here are commonly found in the openocd.cfg file and are
2077 used to specify what TCP/IP ports are used, and how GDB should be
2080 @anchor{Configuration Stage}
2081 @section Configuration Stage
2082 @cindex configuration stage
2083 @cindex config command
2085 When the OpenOCD server process starts up, it enters a
2086 @emph{configuration stage} which is the only time that
2087 certain commands, @emph{configuration commands}, may be issued.
2088 Normally, configuration commands are only available
2089 inside startup scripts.
2091 In this manual, the definition of a configuration command is
2092 presented as a @emph{Config Command}, not as a @emph{Command}
2093 which may be issued interactively.
2094 The runtime @command{help} command also highlights configuration
2095 commands, and those which may be issued at any time.
2097 Those configuration commands include declaration of TAPs,
2099 the interface used for JTAG communication,
2100 and other basic setup.
2101 The server must leave the configuration stage before it
2102 may access or activate TAPs.
2103 After it leaves this stage, configuration commands may no
2106 @anchor{Entering the Run Stage}
2107 @section Entering the Run Stage
2109 The first thing OpenOCD does after leaving the configuration
2110 stage is to verify that it can talk to the scan chain
2111 (list of TAPs) which has been configured.
2112 It will warn if it doesn't find TAPs it expects to find,
2113 or finds TAPs that aren't supposed to be there.
2114 You should see no errors at this point.
2115 If you see errors, resolve them by correcting the
2116 commands you used to configure the server.
2117 Common errors include using an initial JTAG speed that's too
2118 fast, and not providing the right IDCODE values for the TAPs
2121 Once OpenOCD has entered the run stage, a number of commands
2123 A number of these relate to the debug targets you may have declared.
2124 For example, the @command{mww} command will not be available until
2125 a target has been successfuly instantiated.
2126 If you want to use those commands, you may need to force
2127 entry to the run stage.
2129 @deffn {Config Command} init
2130 This command terminates the configuration stage and
2131 enters the run stage. This helps when you need to have
2132 the startup scripts manage tasks such as resetting the target,
2133 programming flash, etc. To reset the CPU upon startup, add "init" and
2134 "reset" at the end of the config script or at the end of the OpenOCD
2135 command line using the @option{-c} command line switch.
2137 If this command does not appear in any startup/configuration file
2138 OpenOCD executes the command for you after processing all
2139 configuration files and/or command line options.
2141 @b{NOTE:} This command normally occurs at or near the end of your
2142 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2143 targets ready. For example: If your openocd.cfg file needs to
2144 read/write memory on your target, @command{init} must occur before
2145 the memory read/write commands. This includes @command{nand probe}.
2148 @deffn {Overridable Procedure} jtag_init
2149 This is invoked at server startup to verify that it can talk
2150 to the scan chain (list of TAPs) which has been configured.
2152 The default implementation first tries @command{jtag arp_init},
2153 which uses only a lightweight JTAG reset before examining the
2155 If that fails, it tries again, using a harder reset
2156 from the overridable procedure @command{init_reset}.
2158 Implementations must have verified the JTAG scan chain before
2160 This is done by calling @command{jtag arp_init}
2161 (or @command{jtag arp_init-reset}).
2164 @anchor{TCP/IP Ports}
2165 @section TCP/IP Ports
2170 The OpenOCD server accepts remote commands in several syntaxes.
2171 Each syntax uses a different TCP/IP port, which you may specify
2172 only during configuration (before those ports are opened).
2174 For reasons including security, you may wish to prevent remote
2175 access using one or more of these ports.
2176 In such cases, just specify the relevant port number as zero.
2177 If you disable all access through TCP/IP, you will need to
2178 use the command line @option{-pipe} option.
2180 @deffn {Command} gdb_port [number]
2182 Normally gdb listens to a TCP/IP port, but GDB can also
2183 communicate via pipes(stdin/out or named pipes). The name
2184 "gdb_port" stuck because it covers probably more than 90% of
2185 the normal use cases.
2187 No arguments reports GDB port. "pipe" means listen to stdin
2188 output to stdout, an integer is base port number, "disable"
2189 disables the gdb server.
2191 When using "pipe", also use log_output to redirect the log
2192 output to a file so as not to flood the stdin/out pipes.
2194 The -p/--pipe option is deprecated and a warning is printed
2195 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2197 Any other string is interpreted as named pipe to listen to.
2198 Output pipe is the same name as input pipe, but with 'o' appended,
2199 e.g. /var/gdb, /var/gdbo.
2201 The GDB port for the first target will be the base port, the
2202 second target will listen on gdb_port + 1, and so on.
2203 When not specified during the configuration stage,
2204 the port @var{number} defaults to 3333.
2207 @deffn {Command} tcl_port [number]
2208 Specify or query the port used for a simplified RPC
2209 connection that can be used by clients to issue TCL commands and get the
2210 output from the Tcl engine.
2211 Intended as a machine interface.
2212 When not specified during the configuration stage,
2213 the port @var{number} defaults to 6666.
2217 @deffn {Command} telnet_port [number]
2218 Specify or query the
2219 port on which to listen for incoming telnet connections.
2220 This port is intended for interaction with one human through TCL commands.
2221 When not specified during the configuration stage,
2222 the port @var{number} defaults to 4444.
2223 When specified as zero, this port is not activated.
2226 @anchor{GDB Configuration}
2227 @section GDB Configuration
2229 @cindex GDB configuration
2230 You can reconfigure some GDB behaviors if needed.
2231 The ones listed here are static and global.
2232 @xref{Target Configuration}, about configuring individual targets.
2233 @xref{Target Events}, about configuring target-specific event handling.
2235 @anchor{gdb_breakpoint_override}
2236 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2237 Force breakpoint type for gdb @command{break} commands.
2238 This option supports GDB GUIs which don't
2239 distinguish hard versus soft breakpoints, if the default OpenOCD and
2240 GDB behaviour is not sufficient. GDB normally uses hardware
2241 breakpoints if the memory map has been set up for flash regions.
2244 @anchor{gdb_flash_program}
2245 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2246 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2247 vFlash packet is received.
2248 The default behaviour is @option{enable}.
2251 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2252 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2253 requested. GDB will then know when to set hardware breakpoints, and program flash
2254 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2255 for flash programming to work.
2256 Default behaviour is @option{enable}.
2257 @xref{gdb_flash_program}.
2260 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2261 Specifies whether data aborts cause an error to be reported
2262 by GDB memory read packets.
2263 The default behaviour is @option{disable};
2264 use @option{enable} see these errors reported.
2267 @anchor{Event Polling}
2268 @section Event Polling
2270 Hardware debuggers are parts of asynchronous systems,
2271 where significant events can happen at any time.
2272 The OpenOCD server needs to detect some of these events,
2273 so it can report them to through TCL command line
2276 Examples of such events include:
2279 @item One of the targets can stop running ... maybe it triggers
2280 a code breakpoint or data watchpoint, or halts itself.
2281 @item Messages may be sent over ``debug message'' channels ... many
2282 targets support such messages sent over JTAG,
2283 for receipt by the person debugging or tools.
2284 @item Loss of power ... some adapters can detect these events.
2285 @item Resets not issued through JTAG ... such reset sources
2286 can include button presses or other system hardware, sometimes
2287 including the target itself (perhaps through a watchdog).
2288 @item Debug instrumentation sometimes supports event triggering
2289 such as ``trace buffer full'' (so it can quickly be emptied)
2290 or other signals (to correlate with code behavior).
2293 None of those events are signaled through standard JTAG signals.
2294 However, most conventions for JTAG connectors include voltage
2295 level and system reset (SRST) signal detection.
2296 Some connectors also include instrumentation signals, which
2297 can imply events when those signals are inputs.
2299 In general, OpenOCD needs to periodically check for those events,
2300 either by looking at the status of signals on the JTAG connector
2301 or by sending synchronous ``tell me your status'' JTAG requests
2302 to the various active targets.
2303 There is a command to manage and monitor that polling,
2304 which is normally done in the background.
2306 @deffn Command poll [@option{on}|@option{off}]
2307 Poll the current target for its current state.
2308 (Also, @pxref{target curstate}.)
2309 If that target is in debug mode, architecture
2310 specific information about the current state is printed.
2311 An optional parameter
2312 allows background polling to be enabled and disabled.
2314 You could use this from the TCL command shell, or
2315 from GDB using @command{monitor poll} command.
2316 Leave background polling enabled while you're using GDB.
2319 background polling: on
2320 target state: halted
2321 target halted in ARM state due to debug-request, \
2322 current mode: Supervisor
2323 cpsr: 0x800000d3 pc: 0x11081bfc
2324 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2329 @node Debug Adapter Configuration
2330 @chapter Debug Adapter Configuration
2331 @cindex config file, interface
2332 @cindex interface config file
2334 Correctly installing OpenOCD includes making your operating system give
2335 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2336 are used to select which one is used, and to configure how it is used.
2339 Because OpenOCD started out with a focus purely on JTAG, you may find
2340 places where it wrongly presumes JTAG is the only transport protocol
2341 in use. Be aware that recent versions of OpenOCD are removing that
2342 limitation. JTAG remains more functional than most other transports.
2343 Other transports do not support boundary scan operations, or may be
2344 specific to a given chip vendor. Some might be usable only for
2345 programming flash memory, instead of also for debugging.
2348 Debug Adapters/Interfaces/Dongles are normally configured
2349 through commands in an interface configuration
2350 file which is sourced by your @file{openocd.cfg} file, or
2351 through a command line @option{-f interface/....cfg} option.
2354 source [find interface/olimex-jtag-tiny.cfg]
2358 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2359 A few cases are so simple that you only need to say what driver to use:
2366 Most adapters need a bit more configuration than that.
2369 @section Interface Configuration
2371 The interface command tells OpenOCD what type of debug adapter you are
2372 using. Depending on the type of adapter, you may need to use one or
2373 more additional commands to further identify or configure the adapter.
2375 @deffn {Config Command} {interface} name
2376 Use the interface driver @var{name} to connect to the
2380 @deffn Command {interface_list}
2381 List the debug adapter drivers that have been built into
2382 the running copy of OpenOCD.
2384 @deffn Command {interface transports} transport_name+
2385 Specifies the transports supported by this debug adapter.
2386 The adapter driver builds-in similar knowledge; use this only
2387 when external configuration (such as jumpering) changes what
2388 the hardware can support.
2393 @deffn Command {adapter_name}
2394 Returns the name of the debug adapter driver being used.
2397 @section Interface Drivers
2399 Each of the interface drivers listed here must be explicitly
2400 enabled when OpenOCD is configured, in order to be made
2401 available at run time.
2403 @deffn {Interface Driver} {amt_jtagaccel}
2404 Amontec Chameleon in its JTAG Accelerator configuration,
2405 connected to a PC's EPP mode parallel port.
2406 This defines some driver-specific commands:
2408 @deffn {Config Command} {parport_port} number
2409 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2410 the number of the @file{/dev/parport} device.
2413 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2414 Displays status of RTCK option.
2415 Optionally sets that option first.
2419 @deffn {Interface Driver} {arm-jtag-ew}
2420 Olimex ARM-JTAG-EW USB adapter
2421 This has one driver-specific command:
2423 @deffn Command {armjtagew_info}
2428 @deffn {Interface Driver} {at91rm9200}
2429 Supports bitbanged JTAG from the local system,
2430 presuming that system is an Atmel AT91rm9200
2431 and a specific set of GPIOs is used.
2432 @c command: at91rm9200_device NAME
2433 @c chooses among list of bit configs ... only one option
2436 @deffn {Interface Driver} {dummy}
2437 A dummy software-only driver for debugging.
2440 @deffn {Interface Driver} {ep93xx}
2441 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2444 @deffn {Interface Driver} {ft2232}
2445 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2446 These interfaces have several commands, used to configure the driver
2447 before initializing the JTAG scan chain:
2449 @deffn {Config Command} {ft2232_device_desc} description
2450 Provides the USB device description (the @emph{iProduct string})
2451 of the FTDI FT2232 device. If not
2452 specified, the FTDI default value is used. This setting is only valid
2453 if compiled with FTD2XX support.
2456 @deffn {Config Command} {ft2232_serial} serial-number
2457 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2458 in case the vendor provides unique IDs and more than one FT2232 device
2459 is connected to the host.
2460 If not specified, serial numbers are not considered.
2461 (Note that USB serial numbers can be arbitrary Unicode strings,
2462 and are not restricted to containing only decimal digits.)
2465 @deffn {Config Command} {ft2232_layout} name
2466 Each vendor's FT2232 device can use different GPIO signals
2467 to control output-enables, reset signals, and LEDs.
2468 Currently valid layout @var{name} values include:
2470 @item @b{axm0432_jtag} Axiom AXM-0432
2471 @item @b{comstick} Hitex STR9 comstick
2472 @item @b{cortino} Hitex Cortino JTAG interface
2473 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
2474 either for the local Cortex-M3 (SRST only)
2475 or in a passthrough mode (neither SRST nor TRST)
2476 This layout can not support the SWO trace mechanism, and should be
2477 used only for older boards (before rev C).
2478 @item @b{luminary_icdi} This layout should be used with most Luminary
2479 eval boards, including Rev C LM3S811 eval boards and the eponymous
2480 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2481 to debug some other target. It can support the SWO trace mechanism.
2482 @item @b{flyswatter} Tin Can Tools Flyswatter
2483 @item @b{icebear} ICEbear JTAG adapter from Section 5
2484 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2485 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2486 @item @b{m5960} American Microsystems M5960
2487 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2488 @item @b{oocdlink} OOCDLink
2489 @c oocdlink ~= jtagkey_prototype_v1
2490 @item @b{redbee-econotag} Integrated with a Redbee development board.
2491 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2492 @item @b{sheevaplug} Marvell Sheevaplug development kit
2493 @item @b{signalyzer} Xverve Signalyzer
2494 @item @b{stm32stick} Hitex STM32 Performance Stick
2495 @item @b{turtelizer2} egnite Software turtelizer2
2496 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2500 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2501 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2502 default values are used.
2503 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2505 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2509 @deffn {Config Command} {ft2232_latency} ms
2510 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2511 ft2232_read() fails to return the expected number of bytes. This can be caused by
2512 USB communication delays and has proved hard to reproduce and debug. Setting the
2513 FT2232 latency timer to a larger value increases delays for short USB packets but it
2514 also reduces the risk of timeouts before receiving the expected number of bytes.
2515 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2518 For example, the interface config file for a
2519 Turtelizer JTAG Adapter looks something like this:
2523 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2524 ft2232_layout turtelizer2
2525 ft2232_vid_pid 0x0403 0xbdc8
2529 @deffn {Interface Driver} {remote_bitbang}
2530 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2531 with a remote process and sends ASCII encoded bitbang requests to that process
2532 instead of directly driving JTAG.
2534 The remote_bitbang driver is useful for debugging software running on
2535 processors which are being simulated.
2537 @deffn {Config Command} {remote_bitbang_port} number
2538 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2539 sockets instead of TCP.
2542 @deffn {Config Command} {remote_bitbang_host} hostname
2543 Specifies the hostname of the remote process to connect to using TCP, or the
2544 name of the UNIX socket to use if remote_bitbang_port is 0.
2547 For example, to connect remotely via TCP to the host foobar you might have
2551 interface remote_bitbang
2552 remote_bitbang_port 3335
2553 remote_bitbang_host foobar
2556 To connect to another process running locally via UNIX sockets with socket
2560 interface remote_bitbang
2561 remote_bitbang_port 0
2562 remote_bitbang_host mysocket
2566 @deffn {Interface Driver} {usb_blaster}
2567 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2568 for FTDI chips. These interfaces have several commands, used to
2569 configure the driver before initializing the JTAG scan chain:
2571 @deffn {Config Command} {usb_blaster_device_desc} description
2572 Provides the USB device description (the @emph{iProduct string})
2573 of the FTDI FT245 device. If not
2574 specified, the FTDI default value is used. This setting is only valid
2575 if compiled with FTD2XX support.
2578 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2579 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2580 default values are used.
2581 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2582 Altera USB-Blaster (default):
2584 usb_blaster_vid_pid 0x09FB 0x6001
2586 The following VID/PID is for Kolja Waschk's USB JTAG:
2588 usb_blaster_vid_pid 0x16C0 0x06AD
2592 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2593 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2594 female JTAG header). These pins can be used as SRST and/or TRST provided the
2595 appropriate connections are made on the target board.
2597 For example, to use pin 6 as SRST (as with an AVR board):
2599 $_TARGETNAME configure -event reset-assert \
2600 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2606 @deffn {Interface Driver} {gw16012}
2607 Gateworks GW16012 JTAG programmer.
2608 This has one driver-specific command:
2610 @deffn {Config Command} {parport_port} [port_number]
2611 Display either the address of the I/O port
2612 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2613 If a parameter is provided, first switch to use that port.
2614 This is a write-once setting.
2618 @deffn {Interface Driver} {jlink}
2619 Segger jlink USB adapter
2620 @c command: jlink caps
2621 @c dumps jlink capabilities
2622 @c command: jlink config
2623 @c access J-Link configurationif no argument this will dump the config
2624 @c command: jlink config kickstart [val]
2625 @c set Kickstart power on JTAG-pin 19.
2626 @c command: jlink config mac_address [ff:ff:ff:ff:ff:ff]
2627 @c set the MAC Address
2628 @c command: jlink config ip [A.B.C.D[/E] [F.G.H.I]]
2629 @c set the ip address of the J-Link Pro, "
2630 @c where A.B.C.D is the ip,
2631 @c E the bit of the subnet mask
2632 @c F.G.H.I the subnet mask
2633 @c command: jlink config reset
2634 @c reset the current config
2635 @c command: jlink config save
2636 @c save the current config
2637 @c command: jlink config usb_address [0x00 to 0x03 or 0xff]
2638 @c set the USB-Address,
2639 @c This will change the product id
2640 @c command: jlink info
2642 @c command: jlink hw_jtag (2|3)
2643 @c sets version 2 or 3
2644 @c command: jlink pid
2645 @c set the pid of the interface we want to use
2648 @deffn {Interface Driver} {parport}
2649 Supports PC parallel port bit-banging cables:
2650 Wigglers, PLD download cable, and more.
2651 These interfaces have several commands, used to configure the driver
2652 before initializing the JTAG scan chain:
2654 @deffn {Config Command} {parport_cable} name
2655 Set the layout of the parallel port cable used to connect to the target.
2656 This is a write-once setting.
2657 Currently valid cable @var{name} values include:
2660 @item @b{altium} Altium Universal JTAG cable.
2661 @item @b{arm-jtag} Same as original wiggler except SRST and
2662 TRST connections reversed and TRST is also inverted.
2663 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2664 in configuration mode. This is only used to
2665 program the Chameleon itself, not a connected target.
2666 @item @b{dlc5} The Xilinx Parallel cable III.
2667 @item @b{flashlink} The ST Parallel cable.
2668 @item @b{lattice} Lattice ispDOWNLOAD Cable
2669 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2671 Amontec's Chameleon Programmer. The new version available from
2672 the website uses the original Wiggler layout ('@var{wiggler}')
2673 @item @b{triton} The parallel port adapter found on the
2674 ``Karo Triton 1 Development Board''.
2675 This is also the layout used by the HollyGates design
2676 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2677 @item @b{wiggler} The original Wiggler layout, also supported by
2678 several clones, such as the Olimex ARM-JTAG
2679 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2680 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2684 @deffn {Config Command} {parport_port} [port_number]
2685 Display either the address of the I/O port
2686 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2687 If a parameter is provided, first switch to use that port.
2688 This is a write-once setting.
2690 When using PPDEV to access the parallel port, use the number of the parallel port:
2691 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2692 you may encounter a problem.
2695 @deffn Command {parport_toggling_time} [nanoseconds]
2696 Displays how many nanoseconds the hardware needs to toggle TCK;
2697 the parport driver uses this value to obey the
2698 @command{adapter_khz} configuration.
2699 When the optional @var{nanoseconds} parameter is given,
2700 that setting is changed before displaying the current value.
2702 The default setting should work reasonably well on commodity PC hardware.
2703 However, you may want to calibrate for your specific hardware.
2705 To measure the toggling time with a logic analyzer or a digital storage
2706 oscilloscope, follow the procedure below:
2708 > parport_toggling_time 1000
2711 This sets the maximum JTAG clock speed of the hardware, but
2712 the actual speed probably deviates from the requested 500 kHz.
2713 Now, measure the time between the two closest spaced TCK transitions.
2714 You can use @command{runtest 1000} or something similar to generate a
2715 large set of samples.
2716 Update the setting to match your measurement:
2718 > parport_toggling_time <measured nanoseconds>
2720 Now the clock speed will be a better match for @command{adapter_khz rate}
2721 commands given in OpenOCD scripts and event handlers.
2723 You can do something similar with many digital multimeters, but note
2724 that you'll probably need to run the clock continuously for several
2725 seconds before it decides what clock rate to show. Adjust the
2726 toggling time up or down until the measured clock rate is a good
2727 match for the adapter_khz rate you specified; be conservative.
2731 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2732 This will configure the parallel driver to write a known
2733 cable-specific value to the parallel interface on exiting OpenOCD.
2736 For example, the interface configuration file for a
2737 classic ``Wiggler'' cable on LPT2 might look something like this:
2742 parport_cable wiggler
2746 @deffn {Interface Driver} {presto}
2747 ASIX PRESTO USB JTAG programmer.
2748 @deffn {Config Command} {presto_serial} serial_string
2749 Configures the USB serial number of the Presto device to use.
2753 @deffn {Interface Driver} {rlink}
2754 Raisonance RLink USB adapter
2757 @deffn {Interface Driver} {usbprog}
2758 usbprog is a freely programmable USB adapter.
2761 @deffn {Interface Driver} {vsllink}
2762 vsllink is part of Versaloon which is a versatile USB programmer.
2765 This defines quite a few driver-specific commands,
2766 which are not currently documented here.
2770 @deffn {Interface Driver} {stlink}
2771 ST Micro ST-LINK adapter.
2773 @deffn {Config Command} {stlink_device_desc} description
2774 Currently Not Supported.
2777 @deffn {Config Command} {stlink_serial} serial
2778 Currently Not Supported.
2781 @deffn {Config Command} {stlink_layout} (@option{sg}|@option{usb})
2782 Specifies the stlink layout to use.
2785 @deffn {Config Command} {stlink_vid_pid} vid pid
2786 The vendor ID and product ID of the STLINK device.
2789 @deffn {Config Command} {stlink_api} api_level
2790 Manually sets the stlink api used, valid options are 1 or 2.
2794 @deffn {Interface Driver} {opendous}
2795 opendous-jtag is a freely programmable USB adapter.
2798 @deffn {Interface Driver} {ZY1000}
2799 This is the Zylin ZY1000 JTAG debugger.
2803 This defines some driver-specific commands,
2804 which are not currently documented here.
2807 @deffn Command power [@option{on}|@option{off}]
2808 Turn power switch to target on/off.
2809 No arguments: print status.
2812 @section Transport Configuration
2814 As noted earlier, depending on the version of OpenOCD you use,
2815 and the debug adapter you are using,
2816 several transports may be available to
2817 communicate with debug targets (or perhaps to program flash memory).
2818 @deffn Command {transport list}
2819 displays the names of the transports supported by this
2823 @deffn Command {transport select} transport_name
2824 Select which of the supported transports to use in this OpenOCD session.
2825 The transport must be supported by the debug adapter hardware and by the
2826 version of OPenOCD you are using (including the adapter's driver).
2827 No arguments: returns name of session's selected transport.
2830 @subsection JTAG Transport
2832 JTAG is the original transport supported by OpenOCD, and most
2833 of the OpenOCD commands support it.
2834 JTAG transports expose a chain of one or more Test Access Points (TAPs),
2835 each of which must be explicitly declared.
2836 JTAG supports both debugging and boundary scan testing.
2837 Flash programming support is built on top of debug support.
2838 @subsection SWD Transport
2840 @cindex Serial Wire Debug
2841 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
2842 Debug Access Point (DAP, which must be explicitly declared.
2843 (SWD uses fewer signal wires than JTAG.)
2844 SWD is debug-oriented, and does not support boundary scan testing.
2845 Flash programming support is built on top of debug support.
2846 (Some processors support both JTAG and SWD.)
2847 @deffn Command {swd newdap} ...
2848 Declares a single DAP which uses SWD transport.
2849 Parameters are currently the same as "jtag newtap" but this is
2852 @deffn Command {swd wcr trn prescale}
2853 Updates TRN (turnaraound delay) and prescaling.fields of the
2854 Wire Control Register (WCR).
2855 No parameters: displays current settings.
2858 @subsection SPI Transport
2860 @cindex Serial Peripheral Interface
2861 The Serial Peripheral Interface (SPI) is a general purpose transport
2862 which uses four wire signaling. Some processors use it as part of a
2863 solution for flash programming.
2867 JTAG clock setup is part of system setup.
2868 It @emph{does not belong with interface setup} since any interface
2869 only knows a few of the constraints for the JTAG clock speed.
2870 Sometimes the JTAG speed is
2871 changed during the target initialization process: (1) slow at
2872 reset, (2) program the CPU clocks, (3) run fast.
2873 Both the "slow" and "fast" clock rates are functions of the
2874 oscillators used, the chip, the board design, and sometimes
2875 power management software that may be active.
2877 The speed used during reset, and the scan chain verification which
2878 follows reset, can be adjusted using a @code{reset-start}
2879 target event handler.
2880 It can then be reconfigured to a faster speed by a
2881 @code{reset-init} target event handler after it reprograms those
2882 CPU clocks, or manually (if something else, such as a boot loader,
2883 sets up those clocks).
2884 @xref{Target Events}.
2885 When the initial low JTAG speed is a chip characteristic, perhaps
2886 because of a required oscillator speed, provide such a handler
2887 in the target config file.
2888 When that speed is a function of a board-specific characteristic
2889 such as which speed oscillator is used, it belongs in the board
2890 config file instead.
2891 In both cases it's safest to also set the initial JTAG clock rate
2892 to that same slow speed, so that OpenOCD never starts up using a
2893 clock speed that's faster than the scan chain can support.
2897 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2900 If your system supports adaptive clocking (RTCK), configuring
2901 JTAG to use that is probably the most robust approach.
2902 However, it introduces delays to synchronize clocks; so it
2903 may not be the fastest solution.
2905 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2906 instead of @command{adapter_khz}, but only for (ARM) cores and boards
2907 which support adaptive clocking.
2909 @deffn {Command} adapter_khz max_speed_kHz
2910 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2911 JTAG interfaces usually support a limited number of
2912 speeds. The speed actually used won't be faster
2913 than the speed specified.
2915 Chip data sheets generally include a top JTAG clock rate.
2916 The actual rate is often a function of a CPU core clock,
2917 and is normally less than that peak rate.
2918 For example, most ARM cores accept at most one sixth of the CPU clock.
2920 Speed 0 (khz) selects RTCK method.
2922 If your system uses RTCK, you won't need to change the
2923 JTAG clocking after setup.
2924 Not all interfaces, boards, or targets support ``rtck''.
2925 If the interface device can not
2926 support it, an error is returned when you try to use RTCK.
2929 @defun jtag_rclk fallback_speed_kHz
2930 @cindex adaptive clocking
2932 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2933 If that fails (maybe the interface, board, or target doesn't
2934 support it), falls back to the specified frequency.
2936 # Fall back to 3mhz if RTCK is not supported
2941 @node Reset Configuration
2942 @chapter Reset Configuration
2943 @cindex Reset Configuration
2945 Every system configuration may require a different reset
2946 configuration. This can also be quite confusing.
2947 Resets also interact with @var{reset-init} event handlers,
2948 which do things like setting up clocks and DRAM, and
2949 JTAG clock rates. (@xref{JTAG Speed}.)
2950 They can also interact with JTAG routers.
2951 Please see the various board files for examples.
2954 To maintainers and integrators:
2955 Reset configuration touches several things at once.
2956 Normally the board configuration file
2957 should define it and assume that the JTAG adapter supports
2958 everything that's wired up to the board's JTAG connector.
2960 However, the target configuration file could also make note
2961 of something the silicon vendor has done inside the chip,
2962 which will be true for most (or all) boards using that chip.
2963 And when the JTAG adapter doesn't support everything, the
2964 user configuration file will need to override parts of
2965 the reset configuration provided by other files.
2968 @section Types of Reset
2970 There are many kinds of reset possible through JTAG, but
2971 they may not all work with a given board and adapter.
2972 That's part of why reset configuration can be error prone.
2976 @emph{System Reset} ... the @emph{SRST} hardware signal
2977 resets all chips connected to the JTAG adapter, such as processors,
2978 power management chips, and I/O controllers. Normally resets triggered
2979 with this signal behave exactly like pressing a RESET button.
2981 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2982 just the TAP controllers connected to the JTAG adapter.
2983 Such resets should not be visible to the rest of the system; resetting a
2984 device's TAP controller just puts that controller into a known state.
2986 @emph{Emulation Reset} ... many devices can be reset through JTAG
2987 commands. These resets are often distinguishable from system
2988 resets, either explicitly (a "reset reason" register says so)
2989 or implicitly (not all parts of the chip get reset).
2991 @emph{Other Resets} ... system-on-chip devices often support
2992 several other types of reset.
2993 You may need to arrange that a watchdog timer stops
2994 while debugging, preventing a watchdog reset.
2995 There may be individual module resets.
2998 In the best case, OpenOCD can hold SRST, then reset
2999 the TAPs via TRST and send commands through JTAG to halt the
3000 CPU at the reset vector before the 1st instruction is executed.
3001 Then when it finally releases the SRST signal, the system is
3002 halted under debugger control before any code has executed.
3003 This is the behavior required to support the @command{reset halt}
3004 and @command{reset init} commands; after @command{reset init} a
3005 board-specific script might do things like setting up DRAM.
3006 (@xref{Reset Command}.)
3008 @anchor{SRST and TRST Issues}
3009 @section SRST and TRST Issues
3011 Because SRST and TRST are hardware signals, they can have a
3012 variety of system-specific constraints. Some of the most
3017 @item @emph{Signal not available} ... Some boards don't wire
3018 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3019 support such signals even if they are wired up.
3020 Use the @command{reset_config} @var{signals} options to say
3021 when either of those signals is not connected.
3022 When SRST is not available, your code might not be able to rely
3023 on controllers having been fully reset during code startup.
3024 Missing TRST is not a problem, since JTAG-level resets can
3025 be triggered using with TMS signaling.
3027 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3028 adapter will connect SRST to TRST, instead of keeping them separate.
3029 Use the @command{reset_config} @var{combination} options to say
3030 when those signals aren't properly independent.
3032 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3033 delay circuit, reset supervisor, or on-chip features can extend
3034 the effect of a JTAG adapter's reset for some time after the adapter
3035 stops issuing the reset. For example, there may be chip or board
3036 requirements that all reset pulses last for at least a
3037 certain amount of time; and reset buttons commonly have
3038 hardware debouncing.
3039 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3040 commands to say when extra delays are needed.
3042 @item @emph{Drive type} ... Reset lines often have a pullup
3043 resistor, letting the JTAG interface treat them as open-drain
3044 signals. But that's not a requirement, so the adapter may need
3045 to use push/pull output drivers.
3046 Also, with weak pullups it may be advisable to drive
3047 signals to both levels (push/pull) to minimize rise times.
3048 Use the @command{reset_config} @var{trst_type} and
3049 @var{srst_type} parameters to say how to drive reset signals.
3051 @item @emph{Special initialization} ... Targets sometimes need
3052 special JTAG initialization sequences to handle chip-specific
3053 issues (not limited to errata).
3054 For example, certain JTAG commands might need to be issued while
3055 the system as a whole is in a reset state (SRST active)
3056 but the JTAG scan chain is usable (TRST inactive).
3057 Many systems treat combined assertion of SRST and TRST as a
3058 trigger for a harder reset than SRST alone.
3059 Such custom reset handling is discussed later in this chapter.
3062 There can also be other issues.
3063 Some devices don't fully conform to the JTAG specifications.
3064 Trivial system-specific differences are common, such as
3065 SRST and TRST using slightly different names.
3066 There are also vendors who distribute key JTAG documentation for
3067 their chips only to developers who have signed a Non-Disclosure
3070 Sometimes there are chip-specific extensions like a requirement to use
3071 the normally-optional TRST signal (precluding use of JTAG adapters which
3072 don't pass TRST through), or needing extra steps to complete a TAP reset.
3074 In short, SRST and especially TRST handling may be very finicky,
3075 needing to cope with both architecture and board specific constraints.
3077 @section Commands for Handling Resets
3079 @deffn {Command} adapter_nsrst_assert_width milliseconds
3080 Minimum amount of time (in milliseconds) OpenOCD should wait
3081 after asserting nSRST (active-low system reset) before
3082 allowing it to be deasserted.
3085 @deffn {Command} adapter_nsrst_delay milliseconds
3086 How long (in milliseconds) OpenOCD should wait after deasserting
3087 nSRST (active-low system reset) before starting new JTAG operations.
3088 When a board has a reset button connected to SRST line it will
3089 probably have hardware debouncing, implying you should use this.
3092 @deffn {Command} jtag_ntrst_assert_width milliseconds
3093 Minimum amount of time (in milliseconds) OpenOCD should wait
3094 after asserting nTRST (active-low JTAG TAP reset) before
3095 allowing it to be deasserted.
3098 @deffn {Command} jtag_ntrst_delay milliseconds
3099 How long (in milliseconds) OpenOCD should wait after deasserting
3100 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3103 @deffn {Command} reset_config mode_flag ...
3104 This command displays or modifies the reset configuration
3105 of your combination of JTAG board and target in target
3106 configuration scripts.
3108 Information earlier in this section describes the kind of problems
3109 the command is intended to address (@pxref{SRST and TRST Issues}).
3110 As a rule this command belongs only in board config files,
3111 describing issues like @emph{board doesn't connect TRST};
3112 or in user config files, addressing limitations derived
3113 from a particular combination of interface and board.
3114 (An unlikely example would be using a TRST-only adapter
3115 with a board that only wires up SRST.)
3117 The @var{mode_flag} options can be specified in any order, but only one
3118 of each type -- @var{signals}, @var{combination},
3121 and @var{srst_type} -- may be specified at a time.
3122 If you don't provide a new value for a given type, its previous
3123 value (perhaps the default) is unchanged.
3124 For example, this means that you don't need to say anything at all about
3125 TRST just to declare that if the JTAG adapter should want to drive SRST,
3126 it must explicitly be driven high (@option{srst_push_pull}).
3130 @var{signals} can specify which of the reset signals are connected.
3131 For example, If the JTAG interface provides SRST, but the board doesn't
3132 connect that signal properly, then OpenOCD can't use it.
3133 Possible values are @option{none} (the default), @option{trst_only},
3134 @option{srst_only} and @option{trst_and_srst}.
3137 If your board provides SRST and/or TRST through the JTAG connector,
3138 you must declare that so those signals can be used.
3142 The @var{combination} is an optional value specifying broken reset
3143 signal implementations.
3144 The default behaviour if no option given is @option{separate},
3145 indicating everything behaves normally.
3146 @option{srst_pulls_trst} states that the
3147 test logic is reset together with the reset of the system (e.g. NXP
3148 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3149 the system is reset together with the test logic (only hypothetical, I
3150 haven't seen hardware with such a bug, and can be worked around).
3151 @option{combined} implies both @option{srst_pulls_trst} and
3152 @option{trst_pulls_srst}.
3155 The @var{gates} tokens control flags that describe some cases where
3156 JTAG may be unvailable during reset.
3157 @option{srst_gates_jtag} (default)
3158 indicates that asserting SRST gates the
3159 JTAG clock. This means that no communication can happen on JTAG
3160 while SRST is asserted.
3161 Its converse is @option{srst_nogate}, indicating that JTAG commands
3162 can safely be issued while SRST is active.
3165 The optional @var{trst_type} and @var{srst_type} parameters allow the
3166 driver mode of each reset line to be specified. These values only affect
3167 JTAG interfaces with support for different driver modes, like the Amontec
3168 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3169 relevant signal (TRST or SRST) is not connected.
3173 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3174 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3175 Most boards connect this signal to a pulldown, so the JTAG TAPs
3176 never leave reset unless they are hooked up to a JTAG adapter.
3179 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3180 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3181 Most boards connect this signal to a pullup, and allow the
3182 signal to be pulled low by various events including system
3183 powerup and pressing a reset button.
3187 @section Custom Reset Handling
3190 OpenOCD has several ways to help support the various reset
3191 mechanisms provided by chip and board vendors.
3192 The commands shown in the previous section give standard parameters.
3193 There are also @emph{event handlers} associated with TAPs or Targets.
3194 Those handlers are Tcl procedures you can provide, which are invoked
3195 at particular points in the reset sequence.
3197 @emph{When SRST is not an option} you must set
3198 up a @code{reset-assert} event handler for your target.
3199 For example, some JTAG adapters don't include the SRST signal;
3200 and some boards have multiple targets, and you won't always
3201 want to reset everything at once.
3203 After configuring those mechanisms, you might still
3204 find your board doesn't start up or reset correctly.
3205 For example, maybe it needs a slightly different sequence
3206 of SRST and/or TRST manipulations, because of quirks that
3207 the @command{reset_config} mechanism doesn't address;
3208 or asserting both might trigger a stronger reset, which
3209 needs special attention.
3211 Experiment with lower level operations, such as @command{jtag_reset}
3212 and the @command{jtag arp_*} operations shown here,
3213 to find a sequence of operations that works.
3214 @xref{JTAG Commands}.
3215 When you find a working sequence, it can be used to override
3216 @command{jtag_init}, which fires during OpenOCD startup
3217 (@pxref{Configuration Stage});
3218 or @command{init_reset}, which fires during reset processing.
3220 You might also want to provide some project-specific reset
3221 schemes. For example, on a multi-target board the standard
3222 @command{reset} command would reset all targets, but you
3223 may need the ability to reset only one target at time and
3224 thus want to avoid using the board-wide SRST signal.
3226 @deffn {Overridable Procedure} init_reset mode
3227 This is invoked near the beginning of the @command{reset} command,
3228 usually to provide as much of a cold (power-up) reset as practical.
3229 By default it is also invoked from @command{jtag_init} if
3230 the scan chain does not respond to pure JTAG operations.
3231 The @var{mode} parameter is the parameter given to the
3232 low level reset command (@option{halt},
3233 @option{init}, or @option{run}), @option{setup},
3234 or potentially some other value.
3236 The default implementation just invokes @command{jtag arp_init-reset}.
3237 Replacements will normally build on low level JTAG
3238 operations such as @command{jtag_reset}.
3239 Operations here must not address individual TAPs
3240 (or their associated targets)
3241 until the JTAG scan chain has first been verified to work.
3243 Implementations must have verified the JTAG scan chain before
3245 This is done by calling @command{jtag arp_init}
3246 (or @command{jtag arp_init-reset}).
3249 @deffn Command {jtag arp_init}
3250 This validates the scan chain using just the four
3251 standard JTAG signals (TMS, TCK, TDI, TDO).
3252 It starts by issuing a JTAG-only reset.
3253 Then it performs checks to verify that the scan chain configuration
3254 matches the TAPs it can observe.
3255 Those checks include checking IDCODE values for each active TAP,
3256 and verifying the length of their instruction registers using
3257 TAP @code{-ircapture} and @code{-irmask} values.
3258 If these tests all pass, TAP @code{setup} events are
3259 issued to all TAPs with handlers for that event.
3262 @deffn Command {jtag arp_init-reset}
3263 This uses TRST and SRST to try resetting
3264 everything on the JTAG scan chain
3265 (and anything else connected to SRST).
3266 It then invokes the logic of @command{jtag arp_init}.
3270 @node TAP Declaration
3271 @chapter TAP Declaration
3272 @cindex TAP declaration
3273 @cindex TAP configuration
3275 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3276 TAPs serve many roles, including:
3279 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3280 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3281 Others do it indirectly, making a CPU do it.
3282 @item @b{Program Download} Using the same CPU support GDB uses,
3283 you can initialize a DRAM controller, download code to DRAM, and then
3284 start running that code.
3285 @item @b{Boundary Scan} Most chips support boundary scan, which
3286 helps test for board assembly problems like solder bridges
3287 and missing connections
3290 OpenOCD must know about the active TAPs on your board(s).
3291 Setting up the TAPs is the core task of your configuration files.
3292 Once those TAPs are set up, you can pass their names to code
3293 which sets up CPUs and exports them as GDB targets,
3294 probes flash memory, performs low-level JTAG operations, and more.
3296 @section Scan Chains
3299 TAPs are part of a hardware @dfn{scan chain},
3300 which is daisy chain of TAPs.
3301 They also need to be added to
3302 OpenOCD's software mirror of that hardware list,
3303 giving each member a name and associating other data with it.
3304 Simple scan chains, with a single TAP, are common in
3305 systems with a single microcontroller or microprocessor.
3306 More complex chips may have several TAPs internally.
3307 Very complex scan chains might have a dozen or more TAPs:
3308 several in one chip, more in the next, and connecting
3309 to other boards with their own chips and TAPs.
3311 You can display the list with the @command{scan_chain} command.
3312 (Don't confuse this with the list displayed by the @command{targets}
3313 command, presented in the next chapter.
3314 That only displays TAPs for CPUs which are configured as
3316 Here's what the scan chain might look like for a chip more than one TAP:
3319 TapName Enabled IdCode Expected IrLen IrCap IrMask
3320 -- ------------------ ------- ---------- ---------- ----- ----- ------
3321 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3322 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3323 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3326 OpenOCD can detect some of that information, but not all
3327 of it. @xref{Autoprobing}.
3328 Unfortunately those TAPs can't always be autoconfigured,
3329 because not all devices provide good support for that.
3330 JTAG doesn't require supporting IDCODE instructions, and
3331 chips with JTAG routers may not link TAPs into the chain
3332 until they are told to do so.
3334 The configuration mechanism currently supported by OpenOCD
3335 requires explicit configuration of all TAP devices using
3336 @command{jtag newtap} commands, as detailed later in this chapter.
3337 A command like this would declare one tap and name it @code{chip1.cpu}:
3340 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3343 Each target configuration file lists the TAPs provided
3345 Board configuration files combine all the targets on a board,
3347 Note that @emph{the order in which TAPs are declared is very important.}
3348 It must match the order in the JTAG scan chain, both inside
3349 a single chip and between them.
3350 @xref{FAQ TAP Order}.
3352 For example, the ST Microsystems STR912 chip has
3353 three separate TAPs@footnote{See the ST
3354 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3355 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3356 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3357 To configure those taps, @file{target/str912.cfg}
3358 includes commands something like this:
3361 jtag newtap str912 flash ... params ...
3362 jtag newtap str912 cpu ... params ...
3363 jtag newtap str912 bs ... params ...
3366 Actual config files use a variable instead of literals like
3367 @option{str912}, to support more than one chip of each type.
3368 @xref{Config File Guidelines}.
3370 @deffn Command {jtag names}
3371 Returns the names of all current TAPs in the scan chain.
3372 Use @command{jtag cget} or @command{jtag tapisenabled}
3373 to examine attributes and state of each TAP.
3375 foreach t [jtag names] @{
3376 puts [format "TAP: %s\n" $t]
3381 @deffn Command {scan_chain}
3382 Displays the TAPs in the scan chain configuration,
3384 The set of TAPs listed by this command is fixed by
3385 exiting the OpenOCD configuration stage,
3386 but systems with a JTAG router can
3387 enable or disable TAPs dynamically.
3390 @c FIXME! "jtag cget" should be able to return all TAP
3391 @c attributes, like "$target_name cget" does for targets.
3393 @c Probably want "jtag eventlist", and a "tap-reset" event
3394 @c (on entry to RESET state).
3399 When TAP objects are declared with @command{jtag newtap},
3400 a @dfn{dotted.name} is created for the TAP, combining the
3401 name of a module (usually a chip) and a label for the TAP.
3402 For example: @code{xilinx.tap}, @code{str912.flash},
3403 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3404 Many other commands use that dotted.name to manipulate or
3405 refer to the TAP. For example, CPU configuration uses the
3406 name, as does declaration of NAND or NOR flash banks.
3408 The components of a dotted name should follow ``C'' symbol
3409 name rules: start with an alphabetic character, then numbers
3410 and underscores are OK; while others (including dots!) are not.
3413 In older code, JTAG TAPs were numbered from 0..N.
3414 This feature is still present.
3415 However its use is highly discouraged, and
3416 should not be relied on; it will be removed by mid-2010.
3417 Update all of your scripts to use TAP names rather than numbers,
3418 by paying attention to the runtime warnings they trigger.
3419 Using TAP numbers in target configuration scripts prevents
3420 reusing those scripts on boards with multiple targets.
3423 @section TAP Declaration Commands
3425 @c shouldn't this be(come) a {Config Command}?
3426 @anchor{jtag newtap}
3427 @deffn Command {jtag newtap} chipname tapname configparams...
3428 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3429 and configured according to the various @var{configparams}.
3431 The @var{chipname} is a symbolic name for the chip.
3432 Conventionally target config files use @code{$_CHIPNAME},
3433 defaulting to the model name given by the chip vendor but
3436 @cindex TAP naming convention
3437 The @var{tapname} reflects the role of that TAP,
3438 and should follow this convention:
3441 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3442 @item @code{cpu} -- The main CPU of the chip, alternatively
3443 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3444 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3445 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3446 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3447 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3448 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3449 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3451 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3452 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3453 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3454 a JTAG TAP; that TAP should be named @code{sdma}.
3457 Every TAP requires at least the following @var{configparams}:
3460 @item @code{-irlen} @var{NUMBER}
3461 @*The length in bits of the
3462 instruction register, such as 4 or 5 bits.
3465 A TAP may also provide optional @var{configparams}:
3468 @item @code{-disable} (or @code{-enable})
3469 @*Use the @code{-disable} parameter to flag a TAP which is not
3470 linked in to the scan chain after a reset using either TRST
3471 or the JTAG state machine's @sc{reset} state.
3472 You may use @code{-enable} to highlight the default state
3473 (the TAP is linked in).
3474 @xref{Enabling and Disabling TAPs}.
3475 @item @code{-expected-id} @var{number}
3476 @*A non-zero @var{number} represents a 32-bit IDCODE
3477 which you expect to find when the scan chain is examined.
3478 These codes are not required by all JTAG devices.
3479 @emph{Repeat the option} as many times as required if more than one
3480 ID code could appear (for example, multiple versions).
3481 Specify @var{number} as zero to suppress warnings about IDCODE
3482 values that were found but not included in the list.
3484 Provide this value if at all possible, since it lets OpenOCD
3485 tell when the scan chain it sees isn't right. These values
3486 are provided in vendors' chip documentation, usually a technical
3487 reference manual. Sometimes you may need to probe the JTAG
3488 hardware to find these values.
3490 @item @code{-ignore-version}
3491 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3492 option. When vendors put out multiple versions of a chip, or use the same
3493 JTAG-level ID for several largely-compatible chips, it may be more practical
3494 to ignore the version field than to update config files to handle all of
3495 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3496 @item @code{-ircapture} @var{NUMBER}
3497 @*The bit pattern loaded by the TAP into the JTAG shift register
3498 on entry to the @sc{ircapture} state, such as 0x01.
3499 JTAG requires the two LSBs of this value to be 01.
3500 By default, @code{-ircapture} and @code{-irmask} are set
3501 up to verify that two-bit value. You may provide
3502 additional bits, if you know them, or indicate that
3503 a TAP doesn't conform to the JTAG specification.
3504 @item @code{-irmask} @var{NUMBER}
3505 @*A mask used with @code{-ircapture}
3506 to verify that instruction scans work correctly.
3507 Such scans are not used by OpenOCD except to verify that
3508 there seems to be no problems with JTAG scan chain operations.
3512 @section Other TAP commands
3514 @deffn Command {jtag cget} dotted.name @option{-event} name
3515 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3516 At this writing this TAP attribute
3517 mechanism is used only for event handling.
3518 (It is not a direct analogue of the @code{cget}/@code{configure}
3519 mechanism for debugger targets.)
3520 See the next section for information about the available events.
3522 The @code{configure} subcommand assigns an event handler,
3523 a TCL string which is evaluated when the event is triggered.
3524 The @code{cget} subcommand returns that handler.
3532 OpenOCD includes two event mechanisms.
3533 The one presented here applies to all JTAG TAPs.
3534 The other applies to debugger targets,
3535 which are associated with certain TAPs.
3537 The TAP events currently defined are:
3540 @item @b{post-reset}
3541 @* The TAP has just completed a JTAG reset.
3542 The tap may still be in the JTAG @sc{reset} state.
3543 Handlers for these events might perform initialization sequences
3544 such as issuing TCK cycles, TMS sequences to ensure
3545 exit from the ARM SWD mode, and more.
3547 Because the scan chain has not yet been verified, handlers for these events
3548 @emph{should not issue commands which scan the JTAG IR or DR registers}
3549 of any particular target.
3550 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3552 @* The scan chain has been reset and verified.
3553 This handler may enable TAPs as needed.
3554 @item @b{tap-disable}
3555 @* The TAP needs to be disabled. This handler should
3556 implement @command{jtag tapdisable}
3557 by issuing the relevant JTAG commands.
3558 @item @b{tap-enable}
3559 @* The TAP needs to be enabled. This handler should
3560 implement @command{jtag tapenable}
3561 by issuing the relevant JTAG commands.
3564 If you need some action after each JTAG reset, which isn't actually
3565 specific to any TAP (since you can't yet trust the scan chain's
3566 contents to be accurate), you might:
3569 jtag configure CHIP.jrc -event post-reset @{
3570 echo "JTAG Reset done"
3571 ... non-scan jtag operations to be done after reset
3576 @anchor{Enabling and Disabling TAPs}
3577 @section Enabling and Disabling TAPs
3578 @cindex JTAG Route Controller
3581 In some systems, a @dfn{JTAG Route Controller} (JRC)
3582 is used to enable and/or disable specific JTAG TAPs.
3583 Many ARM based chips from Texas Instruments include
3584 an ``ICEpick'' module, which is a JRC.
3585 Such chips include DaVinci and OMAP3 processors.
3587 A given TAP may not be visible until the JRC has been
3588 told to link it into the scan chain; and if the JRC
3589 has been told to unlink that TAP, it will no longer
3591 Such routers address problems that JTAG ``bypass mode''
3595 @item The scan chain can only go as fast as its slowest TAP.
3596 @item Having many TAPs slows instruction scans, since all
3597 TAPs receive new instructions.
3598 @item TAPs in the scan chain must be powered up, which wastes
3599 power and prevents debugging some power management mechanisms.
3602 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3603 as implied by the existence of JTAG routers.
3604 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3605 does include a kind of JTAG router functionality.
3607 @c (a) currently the event handlers don't seem to be able to
3608 @c fail in a way that could lead to no-change-of-state.
3610 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3611 shown below, and is implemented using TAP event handlers.
3612 So for example, when defining a TAP for a CPU connected to
3613 a JTAG router, your @file{target.cfg} file
3614 should define TAP event handlers using
3615 code that looks something like this:
3618 jtag configure CHIP.cpu -event tap-enable @{
3619 ... jtag operations using CHIP.jrc
3621 jtag configure CHIP.cpu -event tap-disable @{
3622 ... jtag operations using CHIP.jrc
3626 Then you might want that CPU's TAP enabled almost all the time:
3629 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3632 Note how that particular setup event handler declaration
3633 uses quotes to evaluate @code{$CHIP} when the event is configured.
3634 Using brackets @{ @} would cause it to be evaluated later,
3635 at runtime, when it might have a different value.
3637 @deffn Command {jtag tapdisable} dotted.name
3638 If necessary, disables the tap
3639 by sending it a @option{tap-disable} event.
3640 Returns the string "1" if the tap
3641 specified by @var{dotted.name} is enabled,
3642 and "0" if it is disabled.
3645 @deffn Command {jtag tapenable} dotted.name
3646 If necessary, enables the tap
3647 by sending it a @option{tap-enable} event.
3648 Returns the string "1" if the tap
3649 specified by @var{dotted.name} is enabled,
3650 and "0" if it is disabled.
3653 @deffn Command {jtag tapisenabled} dotted.name
3654 Returns the string "1" if the tap
3655 specified by @var{dotted.name} is enabled,
3656 and "0" if it is disabled.
3659 Humans will find the @command{scan_chain} command more helpful
3660 for querying the state of the JTAG taps.
3664 @anchor{Autoprobing}
3665 @section Autoprobing
3667 @cindex JTAG autoprobe
3669 TAP configuration is the first thing that needs to be done
3670 after interface and reset configuration. Sometimes it's
3671 hard finding out what TAPs exist, or how they are identified.
3672 Vendor documentation is not always easy to find and use.
3674 To help you get past such problems, OpenOCD has a limited
3675 @emph{autoprobing} ability to look at the scan chain, doing
3676 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3677 To use this mechanism, start the OpenOCD server with only data
3678 that configures your JTAG interface, and arranges to come up
3679 with a slow clock (many devices don't support fast JTAG clocks
3680 right when they come out of reset).
3682 For example, your @file{openocd.cfg} file might have:
3685 source [find interface/olimex-arm-usb-tiny-h.cfg]
3686 reset_config trst_and_srst
3690 When you start the server without any TAPs configured, it will
3691 attempt to autoconfigure the TAPs. There are two parts to this:
3694 @item @emph{TAP discovery} ...
3695 After a JTAG reset (sometimes a system reset may be needed too),
3696 each TAP's data registers will hold the contents of either the
3697 IDCODE or BYPASS register.
3698 If JTAG communication is working, OpenOCD will see each TAP,
3699 and report what @option{-expected-id} to use with it.
3700 @item @emph{IR Length discovery} ...
3701 Unfortunately JTAG does not provide a reliable way to find out
3702 the value of the @option{-irlen} parameter to use with a TAP
3704 If OpenOCD can discover the length of a TAP's instruction
3705 register, it will report it.
3706 Otherwise you may need to consult vendor documentation, such
3707 as chip data sheets or BSDL files.
3710 In many cases your board will have a simple scan chain with just
3711 a single device. Here's what OpenOCD reported with one board
3712 that's a bit more complex:
3716 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3717 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3718 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3719 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3720 AUTO auto0.tap - use "... -irlen 4"
3721 AUTO auto1.tap - use "... -irlen 4"
3722 AUTO auto2.tap - use "... -irlen 6"
3723 no gdb ports allocated as no target has been specified
3726 Given that information, you should be able to either find some existing
3727 config files to use, or create your own. If you create your own, you
3728 would configure from the bottom up: first a @file{target.cfg} file
3729 with these TAPs, any targets associated with them, and any on-chip
3730 resources; then a @file{board.cfg} with off-chip resources, clocking,
3733 @node CPU Configuration
3734 @chapter CPU Configuration
3737 This chapter discusses how to set up GDB debug targets for CPUs.
3738 You can also access these targets without GDB
3739 (@pxref{Architecture and Core Commands},
3740 and @ref{Target State handling}) and
3741 through various kinds of NAND and NOR flash commands.
3742 If you have multiple CPUs you can have multiple such targets.
3744 We'll start by looking at how to examine the targets you have,
3745 then look at how to add one more target and how to configure it.
3747 @section Target List
3748 @cindex target, current
3749 @cindex target, list
3751 All targets that have been set up are part of a list,
3752 where each member has a name.
3753 That name should normally be the same as the TAP name.
3754 You can display the list with the @command{targets}
3756 This display often has only one CPU; here's what it might
3757 look like with more than one:
3759 TargetName Type Endian TapName State
3760 -- ------------------ ---------- ------ ------------------ ------------
3761 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3762 1 MyTarget cortex_m3 little mychip.foo tap-disabled
3765 One member of that list is the @dfn{current target}, which
3766 is implicitly referenced by many commands.
3767 It's the one marked with a @code{*} near the target name.
3768 In particular, memory addresses often refer to the address
3769 space seen by that current target.
3770 Commands like @command{mdw} (memory display words)
3771 and @command{flash erase_address} (erase NOR flash blocks)
3772 are examples; and there are many more.
3774 Several commands let you examine the list of targets:
3776 @deffn Command {target count}
3777 @emph{Note: target numbers are deprecated; don't use them.
3778 They will be removed shortly after August 2010, including this command.
3779 Iterate target using @command{target names}, not by counting.}
3781 Returns the number of targets, @math{N}.
3782 The highest numbered target is @math{N - 1}.
3784 set c [target count]
3785 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
3786 # Assuming you have created this function
3787 print_target_details $x
3792 @deffn Command {target current}
3793 Returns the name of the current target.
3796 @deffn Command {target names}
3797 Lists the names of all current targets in the list.
3799 foreach t [target names] @{
3800 puts [format "Target: %s\n" $t]
3805 @deffn Command {target number} number
3806 @emph{Note: target numbers are deprecated; don't use them.
3807 They will be removed shortly after August 2010, including this command.}
3809 The list of targets is numbered starting at zero.
3810 This command returns the name of the target at index @var{number}.
3812 set thename [target number $x]
3813 puts [format "Target %d is: %s\n" $x $thename]
3817 @c yep, "target list" would have been better.
3818 @c plus maybe "target setdefault".
3820 @deffn Command targets [name]
3821 @emph{Note: the name of this command is plural. Other target
3822 command names are singular.}
3824 With no parameter, this command displays a table of all known
3825 targets in a user friendly form.
3827 With a parameter, this command sets the current target to
3828 the given target with the given @var{name}; this is
3829 only relevant on boards which have more than one target.
3832 @section Target CPU Types and Variants
3837 Each target has a @dfn{CPU type}, as shown in the output of
3838 the @command{targets} command. You need to specify that type
3839 when calling @command{target create}.
3840 The CPU type indicates more than just the instruction set.
3841 It also indicates how that instruction set is implemented,
3842 what kind of debug support it integrates,
3843 whether it has an MMU (and if so, what kind),
3844 what core-specific commands may be available
3845 (@pxref{Architecture and Core Commands}),
3848 For some CPU types, OpenOCD also defines @dfn{variants} which
3849 indicate differences that affect their handling.
3850 For example, a particular implementation bug might need to be
3851 worked around in some chip versions.
3853 It's easy to see what target types are supported,
3854 since there's a command to list them.
3855 However, there is currently no way to list what target variants
3856 are supported (other than by reading the OpenOCD source code).
3858 @anchor{target types}
3859 @deffn Command {target types}
3860 Lists all supported target types.
3861 At this writing, the supported CPU types and variants are:
3864 @item @code{arm11} -- this is a generation of ARMv6 cores
3865 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3866 @item @code{arm7tdmi} -- this is an ARMv4 core
3867 @item @code{arm920t} -- this is an ARMv4 core with an MMU
3868 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
3869 @item @code{arm966e} -- this is an ARMv5 core
3870 @item @code{arm9tdmi} -- this is an ARMv4 core
3871 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
3872 (Support for this is preliminary and incomplete.)
3873 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
3874 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
3875 compact Thumb2 instruction set.
3876 @item @code{dragonite} -- resembles arm966e
3877 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
3878 (Support for this is still incomplete.)
3879 @item @code{fa526} -- resembles arm920 (w/o Thumb)
3880 @item @code{feroceon} -- resembles arm926
3881 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
3882 @item @code{xscale} -- this is actually an architecture,
3883 not a CPU type. It is based on the ARMv5 architecture.
3884 There are several variants defined:
3886 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
3887 @code{pxa27x} ... instruction register length is 7 bits
3888 @item @code{pxa250}, @code{pxa255},
3889 @code{pxa26x} ... instruction register length is 5 bits
3890 @item @code{pxa3xx} ... instruction register length is 11 bits
3895 To avoid being confused by the variety of ARM based cores, remember
3896 this key point: @emph{ARM is a technology licencing company}.
3897 (See: @url{http://www.arm.com}.)
3898 The CPU name used by OpenOCD will reflect the CPU design that was
3899 licenced, not a vendor brand which incorporates that design.
3900 Name prefixes like arm7, arm9, arm11, and cortex
3901 reflect design generations;
3902 while names like ARMv4, ARMv5, ARMv6, and ARMv7
3903 reflect an architecture version implemented by a CPU design.
3905 @anchor{Target Configuration}
3906 @section Target Configuration
3908 Before creating a ``target'', you must have added its TAP to the scan chain.
3909 When you've added that TAP, you will have a @code{dotted.name}
3910 which is used to set up the CPU support.
3911 The chip-specific configuration file will normally configure its CPU(s)
3912 right after it adds all of the chip's TAPs to the scan chain.
3914 Although you can set up a target in one step, it's often clearer if you
3915 use shorter commands and do it in two steps: create it, then configure
3917 All operations on the target after it's created will use a new
3918 command, created as part of target creation.
3920 The two main things to configure after target creation are
3921 a work area, which usually has target-specific defaults even
3922 if the board setup code overrides them later;
3923 and event handlers (@pxref{Target Events}), which tend
3924 to be much more board-specific.
3925 The key steps you use might look something like this
3928 target create MyTarget cortex_m3 -chain-position mychip.cpu
3929 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
3930 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
3931 $MyTarget configure -event reset-init @{ myboard_reinit @}
3934 You should specify a working area if you can; typically it uses some
3936 Such a working area can speed up many things, including bulk
3937 writes to target memory;
3938 flash operations like checking to see if memory needs to be erased;
3939 GDB memory checksumming;
3943 On more complex chips, the work area can become
3944 inaccessible when application code
3945 (such as an operating system)
3946 enables or disables the MMU.
3947 For example, the particular MMU context used to acess the virtual
3948 address will probably matter ... and that context might not have
3949 easy access to other addresses needed.
3950 At this writing, OpenOCD doesn't have much MMU intelligence.
3953 It's often very useful to define a @code{reset-init} event handler.
3954 For systems that are normally used with a boot loader,
3955 common tasks include updating clocks and initializing memory
3957 That may be needed to let you write the boot loader into flash,
3958 in order to ``de-brick'' your board; or to load programs into
3959 external DDR memory without having run the boot loader.
3961 @deffn Command {target create} target_name type configparams...
3962 This command creates a GDB debug target that refers to a specific JTAG tap.
3963 It enters that target into a list, and creates a new
3964 command (@command{@var{target_name}}) which is used for various
3965 purposes including additional configuration.
3968 @item @var{target_name} ... is the name of the debug target.
3969 By convention this should be the same as the @emph{dotted.name}
3970 of the TAP associated with this target, which must be specified here
3971 using the @code{-chain-position @var{dotted.name}} configparam.
3973 This name is also used to create the target object command,
3974 referred to here as @command{$target_name},
3975 and in other places the target needs to be identified.
3976 @item @var{type} ... specifies the target type. @xref{target types}.
3977 @item @var{configparams} ... all parameters accepted by
3978 @command{$target_name configure} are permitted.
3979 If the target is big-endian, set it here with @code{-endian big}.
3980 If the variant matters, set it here with @code{-variant}.
3982 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
3986 @deffn Command {$target_name configure} configparams...
3987 The options accepted by this command may also be
3988 specified as parameters to @command{target create}.
3989 Their values can later be queried one at a time by
3990 using the @command{$target_name cget} command.
3992 @emph{Warning:} changing some of these after setup is dangerous.
3993 For example, moving a target from one TAP to another;
3994 and changing its endianness or variant.
3998 @item @code{-chain-position} @var{dotted.name} -- names the TAP
3999 used to access this target.
4001 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4002 whether the CPU uses big or little endian conventions
4004 @item @code{-event} @var{event_name} @var{event_body} --
4005 @xref{Target Events}.
4006 Note that this updates a list of named event handlers.
4007 Calling this twice with two different event names assigns
4008 two different handlers, but calling it twice with the
4009 same event name assigns only one handler.
4011 @item @code{-variant} @var{name} -- specifies a variant of the target,
4012 which OpenOCD needs to know about.
4014 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4015 whether the work area gets backed up; by default,
4016 @emph{it is not backed up.}
4017 When possible, use a working_area that doesn't need to be backed up,
4018 since performing a backup slows down operations.
4019 For example, the beginning of an SRAM block is likely to
4020 be used by most build systems, but the end is often unused.
4022 @item @code{-work-area-size} @var{size} -- specify work are size,
4023 in bytes. The same size applies regardless of whether its physical
4024 or virtual address is being used.
4026 @item @code{-work-area-phys} @var{address} -- set the work area
4027 base @var{address} to be used when no MMU is active.
4029 @item @code{-work-area-virt} @var{address} -- set the work area
4030 base @var{address} to be used when an MMU is active.
4031 @emph{Do not specify a value for this except on targets with an MMU.}
4032 The value should normally correspond to a static mapping for the
4033 @code{-work-area-phys} address, set up by the current operating system.
4035 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4036 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4037 @option{FreeRTOS}|@option{linux}.
4042 @section Other $target_name Commands
4043 @cindex object command
4045 The Tcl/Tk language has the concept of object commands,
4046 and OpenOCD adopts that same model for targets.
4048 A good Tk example is a on screen button.
4049 Once a button is created a button
4050 has a name (a path in Tk terms) and that name is useable as a first
4051 class command. For example in Tk, one can create a button and later
4052 configure it like this:
4056 button .foobar -background red -command @{ foo @}
4058 .foobar configure -foreground blue
4060 set x [.foobar cget -background]
4062 puts [format "The button is %s" $x]
4065 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4066 button, and its object commands are invoked the same way.
4069 str912.cpu mww 0x1234 0x42
4070 omap3530.cpu mww 0x5555 123
4073 The commands supported by OpenOCD target objects are:
4075 @deffn Command {$target_name arp_examine}
4076 @deffnx Command {$target_name arp_halt}
4077 @deffnx Command {$target_name arp_poll}
4078 @deffnx Command {$target_name arp_reset}
4079 @deffnx Command {$target_name arp_waitstate}
4080 Internal OpenOCD scripts (most notably @file{startup.tcl})
4081 use these to deal with specific reset cases.
4082 They are not otherwise documented here.
4085 @deffn Command {$target_name array2mem} arrayname width address count
4086 @deffnx Command {$target_name mem2array} arrayname width address count
4087 These provide an efficient script-oriented interface to memory.
4088 The @code{array2mem} primitive writes bytes, halfwords, or words;
4089 while @code{mem2array} reads them.
4090 In both cases, the TCL side uses an array, and
4091 the target side uses raw memory.
4093 The efficiency comes from enabling the use of
4094 bulk JTAG data transfer operations.
4095 The script orientation comes from working with data
4096 values that are packaged for use by TCL scripts;
4097 @command{mdw} type primitives only print data they retrieve,
4098 and neither store nor return those values.
4101 @item @var{arrayname} ... is the name of an array variable
4102 @item @var{width} ... is 8/16/32 - indicating the memory access size
4103 @item @var{address} ... is the target memory address
4104 @item @var{count} ... is the number of elements to process
4108 @deffn Command {$target_name cget} queryparm
4109 Each configuration parameter accepted by
4110 @command{$target_name configure}
4111 can be individually queried, to return its current value.
4112 The @var{queryparm} is a parameter name
4113 accepted by that command, such as @code{-work-area-phys}.
4114 There are a few special cases:
4117 @item @code{-event} @var{event_name} -- returns the handler for the
4118 event named @var{event_name}.
4119 This is a special case because setting a handler requires
4121 @item @code{-type} -- returns the target type.
4122 This is a special case because this is set using
4123 @command{target create} and can't be changed
4124 using @command{$target_name configure}.
4127 For example, if you wanted to summarize information about
4128 all the targets you might use something like this:
4131 foreach name [target names] @{
4132 set y [$name cget -endian]
4133 set z [$name cget -type]
4134 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4140 @anchor{target curstate}
4141 @deffn Command {$target_name curstate}
4142 Displays the current target state:
4143 @code{debug-running},
4146 @code{running}, or @code{unknown}.
4147 (Also, @pxref{Event Polling}.)
4150 @deffn Command {$target_name eventlist}
4151 Displays a table listing all event handlers
4152 currently associated with this target.
4153 @xref{Target Events}.
4156 @deffn Command {$target_name invoke-event} event_name
4157 Invokes the handler for the event named @var{event_name}.
4158 (This is primarily intended for use by OpenOCD framework
4159 code, for example by the reset code in @file{startup.tcl}.)
4162 @deffn Command {$target_name mdw} addr [count]
4163 @deffnx Command {$target_name mdh} addr [count]
4164 @deffnx Command {$target_name mdb} addr [count]
4165 Display contents of address @var{addr}, as
4166 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4167 or 8-bit bytes (@command{mdb}).
4168 If @var{count} is specified, displays that many units.
4169 (If you want to manipulate the data instead of displaying it,
4170 see the @code{mem2array} primitives.)
4173 @deffn Command {$target_name mww} addr word
4174 @deffnx Command {$target_name mwh} addr halfword
4175 @deffnx Command {$target_name mwb} addr byte
4176 Writes the specified @var{word} (32 bits),
4177 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4178 at the specified address @var{addr}.
4181 @anchor{Target Events}
4182 @section Target Events
4183 @cindex target events
4185 At various times, certain things can happen, or you want them to happen.
4188 @item What should happen when GDB connects? Should your target reset?
4189 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4190 @item Is using SRST appropriate (and possible) on your system?
4191 Or instead of that, do you need to issue JTAG commands to trigger reset?
4192 SRST usually resets everything on the scan chain, which can be inappropriate.
4193 @item During reset, do you need to write to certain memory locations
4194 to set up system clocks or
4195 to reconfigure the SDRAM?
4196 How about configuring the watchdog timer, or other peripherals,
4197 to stop running while you hold the core stopped for debugging?
4200 All of the above items can be addressed by target event handlers.
4201 These are set up by @command{$target_name configure -event} or
4202 @command{target create ... -event}.
4204 The programmer's model matches the @code{-command} option used in Tcl/Tk
4205 buttons and events. The two examples below act the same, but one creates
4206 and invokes a small procedure while the other inlines it.
4209 proc my_attach_proc @{ @} @{
4213 mychip.cpu configure -event gdb-attach my_attach_proc
4214 mychip.cpu configure -event gdb-attach @{
4216 # To make flash probe and gdb load to flash work we need a reset init.
4221 The following target events are defined:
4224 @item @b{debug-halted}
4225 @* The target has halted for debug reasons (i.e.: breakpoint)
4226 @item @b{debug-resumed}
4227 @* The target has resumed (i.e.: gdb said run)
4228 @item @b{early-halted}
4229 @* Occurs early in the halt process
4231 @item @b{examine-end}
4232 @* Currently not used (goal: when JTAG examine completes)
4233 @item @b{examine-start}
4234 @* Currently not used (goal: when JTAG examine starts)
4236 @item @b{gdb-attach}
4237 @* When GDB connects. This is before any communication with the target, so this
4238 can be used to set up the target so it is possible to probe flash. Probing flash
4239 is necessary during gdb connect if gdb load is to write the image to flash. Another
4240 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4241 depending on whether the breakpoint is in RAM or read only memory.
4242 @item @b{gdb-detach}
4243 @* When GDB disconnects
4245 @* When the target has halted and GDB is not doing anything (see early halt)
4246 @item @b{gdb-flash-erase-start}
4247 @* Before the GDB flash process tries to erase the flash
4248 @item @b{gdb-flash-erase-end}
4249 @* After the GDB flash process has finished erasing the flash
4250 @item @b{gdb-flash-write-start}
4251 @* Before GDB writes to the flash
4252 @item @b{gdb-flash-write-end}
4253 @* After GDB writes to the flash
4255 @* Before the target steps, gdb is trying to start/resume the target
4257 @* The target has halted
4258 @item @b{reset-assert-pre}
4259 @* Issued as part of @command{reset} processing
4260 after @command{reset_init} was triggered
4261 but before either SRST alone is re-asserted on the scan chain,
4262 or @code{reset-assert} is triggered.
4263 @item @b{reset-assert}
4264 @* Issued as part of @command{reset} processing
4265 after @command{reset-assert-pre} was triggered.
4266 When such a handler is present, cores which support this event will use
4267 it instead of asserting SRST.
4268 This support is essential for debugging with JTAG interfaces which
4269 don't include an SRST line (JTAG doesn't require SRST), and for
4270 selective reset on scan chains that have multiple targets.
4271 @item @b{reset-assert-post}
4272 @* Issued as part of @command{reset} processing
4273 after @code{reset-assert} has been triggered.
4274 or the target asserted SRST on the entire scan chain.
4275 @item @b{reset-deassert-pre}
4276 @* Issued as part of @command{reset} processing
4277 after @code{reset-assert-post} has been triggered.
4278 @item @b{reset-deassert-post}
4279 @* Issued as part of @command{reset} processing
4280 after @code{reset-deassert-pre} has been triggered
4281 and (if the target is using it) after SRST has been
4282 released on the scan chain.
4284 @* Issued as the final step in @command{reset} processing.
4286 @item @b{reset-halt-post}
4287 @* Currently not used
4288 @item @b{reset-halt-pre}
4289 @* Currently not used
4291 @item @b{reset-init}
4292 @* Used by @b{reset init} command for board-specific initialization.
4293 This event fires after @emph{reset-deassert-post}.
4295 This is where you would configure PLLs and clocking, set up DRAM so
4296 you can download programs that don't fit in on-chip SRAM, set up pin
4297 multiplexing, and so on.
4298 (You may be able to switch to a fast JTAG clock rate here, after
4299 the target clocks are fully set up.)
4300 @item @b{reset-start}
4301 @* Issued as part of @command{reset} processing
4302 before @command{reset_init} is called.
4304 This is the most robust place to use @command{jtag_rclk}
4305 or @command{adapter_khz} to switch to a low JTAG clock rate,
4306 when reset disables PLLs needed to use a fast clock.
4308 @item @b{reset-wait-pos}
4309 @* Currently not used
4310 @item @b{reset-wait-pre}
4311 @* Currently not used
4313 @item @b{resume-start}
4314 @* Before any target is resumed
4315 @item @b{resume-end}
4316 @* After all targets have resumed
4318 @* Target has resumed
4322 @node Flash Commands
4323 @chapter Flash Commands
4325 OpenOCD has different commands for NOR and NAND flash;
4326 the ``flash'' command works with NOR flash, while
4327 the ``nand'' command works with NAND flash.
4328 This partially reflects different hardware technologies:
4329 NOR flash usually supports direct CPU instruction and data bus access,
4330 while data from a NAND flash must be copied to memory before it can be
4331 used. (SPI flash must also be copied to memory before use.)
4332 However, the documentation also uses ``flash'' as a generic term;
4333 for example, ``Put flash configuration in board-specific files''.
4337 @item Configure via the command @command{flash bank}
4338 @* Do this in a board-specific configuration file,
4339 passing parameters as needed by the driver.
4340 @item Operate on the flash via @command{flash subcommand}
4341 @* Often commands to manipulate the flash are typed by a human, or run
4342 via a script in some automated way. Common tasks include writing a
4343 boot loader, operating system, or other data.
4345 @* Flashing via GDB requires the flash be configured via ``flash
4346 bank'', and the GDB flash features be enabled.
4347 @xref{GDB Configuration}.
4350 Many CPUs have the ablity to ``boot'' from the first flash bank.
4351 This means that misprogramming that bank can ``brick'' a system,
4352 so that it can't boot.
4353 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4354 board by (re)installing working boot firmware.
4356 @anchor{NOR Configuration}
4357 @section Flash Configuration Commands
4358 @cindex flash configuration
4360 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4361 Configures a flash bank which provides persistent storage
4362 for addresses from @math{base} to @math{base + size - 1}.
4363 These banks will often be visible to GDB through the target's memory map.
4364 In some cases, configuring a flash bank will activate extra commands;
4365 see the driver-specific documentation.
4368 @item @var{name} ... may be used to reference the flash bank
4369 in other flash commands. A number is also available.
4370 @item @var{driver} ... identifies the controller driver
4371 associated with the flash bank being declared.
4372 This is usually @code{cfi} for external flash, or else
4373 the name of a microcontroller with embedded flash memory.
4374 @xref{Flash Driver List}.
4375 @item @var{base} ... Base address of the flash chip.
4376 @item @var{size} ... Size of the chip, in bytes.
4377 For some drivers, this value is detected from the hardware.
4378 @item @var{chip_width} ... Width of the flash chip, in bytes;
4379 ignored for most microcontroller drivers.
4380 @item @var{bus_width} ... Width of the data bus used to access the
4381 chip, in bytes; ignored for most microcontroller drivers.
4382 @item @var{target} ... Names the target used to issue
4383 commands to the flash controller.
4384 @comment Actually, it's currently a controller-specific parameter...
4385 @item @var{driver_options} ... drivers may support, or require,
4386 additional parameters. See the driver-specific documentation
4387 for more information.
4390 This command is not available after OpenOCD initialization has completed.
4391 Use it in board specific configuration files, not interactively.
4395 @comment the REAL name for this command is "ocd_flash_banks"
4396 @comment less confusing would be: "flash list" (like "nand list")
4397 @deffn Command {flash banks}
4398 Prints a one-line summary of each device that was
4399 declared using @command{flash bank}, numbered from zero.
4400 Note that this is the @emph{plural} form;
4401 the @emph{singular} form is a very different command.
4404 @deffn Command {flash list}
4405 Retrieves a list of associative arrays for each device that was
4406 declared using @command{flash bank}, numbered from zero.
4407 This returned list can be manipulated easily from within scripts.
4410 @deffn Command {flash probe} num
4411 Identify the flash, or validate the parameters of the configured flash. Operation
4412 depends on the flash type.
4413 The @var{num} parameter is a value shown by @command{flash banks}.
4414 Most flash commands will implicitly @emph{autoprobe} the bank;
4415 flash drivers can distinguish between probing and autoprobing,
4416 but most don't bother.
4419 @section Erasing, Reading, Writing to Flash
4420 @cindex flash erasing
4421 @cindex flash reading
4422 @cindex flash writing
4423 @cindex flash programming
4425 One feature distinguishing NOR flash from NAND or serial flash technologies
4426 is that for read access, it acts exactly like any other addressible memory.
4427 This means you can use normal memory read commands like @command{mdw} or
4428 @command{dump_image} with it, with no special @command{flash} subcommands.
4429 @xref{Memory access}, and @ref{Image access}.
4431 Write access works differently. Flash memory normally needs to be erased
4432 before it's written. Erasing a sector turns all of its bits to ones, and
4433 writing can turn ones into zeroes. This is why there are special commands
4434 for interactive erasing and writing, and why GDB needs to know which parts
4435 of the address space hold NOR flash memory.
4438 Most of these erase and write commands leverage the fact that NOR flash
4439 chips consume target address space. They implicitly refer to the current
4440 JTAG target, and map from an address in that target's address space
4441 back to a flash bank.
4442 @comment In May 2009, those mappings may fail if any bank associated
4443 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4444 A few commands use abstract addressing based on bank and sector numbers,
4445 and don't depend on searching the current target and its address space.
4446 Avoid confusing the two command models.
4449 Some flash chips implement software protection against accidental writes,
4450 since such buggy writes could in some cases ``brick'' a system.
4451 For such systems, erasing and writing may require sector protection to be
4453 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4454 and AT91SAM7 on-chip flash.
4455 @xref{flash protect}.
4457 @anchor{flash erase_sector}
4458 @deffn Command {flash erase_sector} num first last
4459 Erase sectors in bank @var{num}, starting at sector @var{first}
4460 up to and including @var{last}.
4461 Sector numbering starts at 0.
4462 Providing a @var{last} sector of @option{last}
4463 specifies "to the end of the flash bank".
4464 The @var{num} parameter is a value shown by @command{flash banks}.
4467 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4468 Erase sectors starting at @var{address} for @var{length} bytes.
4469 Unless @option{pad} is specified, @math{address} must begin a
4470 flash sector, and @math{address + length - 1} must end a sector.
4471 Specifying @option{pad} erases extra data at the beginning and/or
4472 end of the specified region, as needed to erase only full sectors.
4473 The flash bank to use is inferred from the @var{address}, and
4474 the specified length must stay within that bank.
4475 As a special case, when @var{length} is zero and @var{address} is
4476 the start of the bank, the whole flash is erased.
4477 If @option{unlock} is specified, then the flash is unprotected
4478 before erase starts.
4481 @deffn Command {flash fillw} address word length
4482 @deffnx Command {flash fillh} address halfword length
4483 @deffnx Command {flash fillb} address byte length
4484 Fills flash memory with the specified @var{word} (32 bits),
4485 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4486 starting at @var{address} and continuing
4487 for @var{length} units (word/halfword/byte).
4488 No erasure is done before writing; when needed, that must be done
4489 before issuing this command.
4490 Writes are done in blocks of up to 1024 bytes, and each write is
4491 verified by reading back the data and comparing it to what was written.
4492 The flash bank to use is inferred from the @var{address} of
4493 each block, and the specified length must stay within that bank.
4495 @comment no current checks for errors if fill blocks touch multiple banks!
4497 @anchor{flash write_bank}
4498 @deffn Command {flash write_bank} num filename offset
4499 Write the binary @file{filename} to flash bank @var{num},
4500 starting at @var{offset} bytes from the beginning of the bank.
4501 The @var{num} parameter is a value shown by @command{flash banks}.
4504 @anchor{flash write_image}
4505 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4506 Write the image @file{filename} to the current target's flash bank(s).
4507 A relocation @var{offset} may be specified, in which case it is added
4508 to the base address for each section in the image.
4509 The file [@var{type}] can be specified
4510 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4511 @option{elf} (ELF file), @option{s19} (Motorola s19).
4512 @option{mem}, or @option{builder}.
4513 The relevant flash sectors will be erased prior to programming
4514 if the @option{erase} parameter is given. If @option{unlock} is
4515 provided, then the flash banks are unlocked before erase and
4516 program. The flash bank to use is inferred from the address of
4520 Be careful using the @option{erase} flag when the flash is holding
4521 data you want to preserve.
4522 Portions of the flash outside those described in the image's
4523 sections might be erased with no notice.
4526 When a section of the image being written does not fill out all the
4527 sectors it uses, the unwritten parts of those sectors are necessarily
4528 also erased, because sectors can't be partially erased.
4530 Data stored in sector "holes" between image sections are also affected.
4531 For example, "@command{flash write_image erase ...}" of an image with
4532 one byte at the beginning of a flash bank and one byte at the end
4533 erases the entire bank -- not just the two sectors being written.
4535 Also, when flash protection is important, you must re-apply it after
4536 it has been removed by the @option{unlock} flag.
4541 @section Other Flash commands
4542 @cindex flash protection
4544 @deffn Command {flash erase_check} num
4545 Check erase state of sectors in flash bank @var{num},
4546 and display that status.
4547 The @var{num} parameter is a value shown by @command{flash banks}.
4550 @deffn Command {flash info} num
4551 Print info about flash bank @var{num}
4552 The @var{num} parameter is a value shown by @command{flash banks}.
4553 This command will first query the hardware, it does not print cached
4554 and possibly stale information.
4557 @anchor{flash protect}
4558 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4559 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4560 in flash bank @var{num}, starting at sector @var{first}
4561 and continuing up to and including @var{last}.
4562 Providing a @var{last} sector of @option{last}
4563 specifies "to the end of the flash bank".
4564 The @var{num} parameter is a value shown by @command{flash banks}.
4567 @anchor{Flash Driver List}
4568 @section Flash Driver List
4569 As noted above, the @command{flash bank} command requires a driver name,
4570 and allows driver-specific options and behaviors.
4571 Some drivers also activate driver-specific commands.
4573 @subsection External Flash
4575 @deffn {Flash Driver} cfi
4576 @cindex Common Flash Interface
4578 The ``Common Flash Interface'' (CFI) is the main standard for
4579 external NOR flash chips, each of which connects to a
4580 specific external chip select on the CPU.
4581 Frequently the first such chip is used to boot the system.
4582 Your board's @code{reset-init} handler might need to
4583 configure additional chip selects using other commands (like: @command{mww} to
4584 configure a bus and its timings), or
4585 perhaps configure a GPIO pin that controls the ``write protect'' pin
4587 The CFI driver can use a target-specific working area to significantly
4590 The CFI driver can accept the following optional parameters, in any order:
4593 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4594 like AM29LV010 and similar types.
4595 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4598 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4599 wide on a sixteen bit bus:
4602 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4603 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4606 To configure one bank of 32 MBytes
4607 built from two sixteen bit (two byte) wide parts wired in parallel
4608 to create a thirty-two bit (four byte) bus with doubled throughput:
4611 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4614 @c "cfi part_id" disabled
4617 @deffn {Flash Driver} stmsmi
4618 @cindex STMicroelectronics Serial Memory Interface
4621 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4622 SPEAr MPU family) include a proprietary
4623 ``Serial Memory Interface'' (SMI) controller able to drive external
4625 Depending on specific device and board configuration, up to 4 external
4626 flash devices can be connected.
4628 SMI makes the flash content directly accessible in the CPU address
4629 space; each external device is mapped in a memory bank.
4630 CPU can directly read data, execute code and boot from SMI banks.
4631 Normal OpenOCD commands like @command{mdw} can be used to display
4634 The setup command only requires the @var{base} parameter in order
4635 to identify the memory bank.
4636 All other parameters are ignored. Additional information, like
4637 flash size, are detected automatically.
4640 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4645 @subsection Internal Flash (Microcontrollers)
4647 @deffn {Flash Driver} aduc702x
4648 The ADUC702x analog microcontrollers from Analog Devices
4649 include internal flash and use ARM7TDMI cores.
4650 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4651 The setup command only requires the @var{target} argument
4652 since all devices in this family have the same memory layout.
4655 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4660 @deffn {Flash Driver} at91sam3
4662 All members of the AT91SAM3 microcontroller family from
4663 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
4664 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
4665 that the driver was orginaly developed and tested using the
4666 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
4667 the family was cribbed from the data sheet. @emph{Note to future
4668 readers/updaters: Please remove this worrysome comment after other
4669 chips are confirmed.}
4671 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
4672 have one flash bank. In all cases the flash banks are at
4673 the following fixed locations:
4676 # Flash bank 0 - all chips
4677 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
4678 # Flash bank 1 - only 256K chips
4679 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
4682 Internally, the AT91SAM3 flash memory is organized as follows.
4683 Unlike the AT91SAM7 chips, these are not used as parameters
4684 to the @command{flash bank} command:
4687 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
4688 @item @emph{Bank Size:} 128K/64K Per flash bank
4689 @item @emph{Sectors:} 16 or 8 per bank
4690 @item @emph{SectorSize:} 8K Per Sector
4691 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
4694 The AT91SAM3 driver adds some additional commands:
4696 @deffn Command {at91sam3 gpnvm}
4697 @deffnx Command {at91sam3 gpnvm clear} number
4698 @deffnx Command {at91sam3 gpnvm set} number
4699 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
4700 With no parameters, @command{show} or @command{show all},
4701 shows the status of all GPNVM bits.
4702 With @command{show} @var{number}, displays that bit.
4704 With @command{set} @var{number} or @command{clear} @var{number},
4705 modifies that GPNVM bit.
4708 @deffn Command {at91sam3 info}
4709 This command attempts to display information about the AT91SAM3
4710 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
4711 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
4712 document id: doc6430A] and decodes the values. @emph{Second} it reads the
4713 various clock configuration registers and attempts to display how it
4714 believes the chip is configured. By default, the SLOWCLK is assumed to
4715 be 32768 Hz, see the command @command{at91sam3 slowclk}.
4718 @deffn Command {at91sam3 slowclk} [value]
4719 This command shows/sets the slow clock frequency used in the
4720 @command{at91sam3 info} command calculations above.
4724 @deffn {Flash Driver} at91sam4
4726 All members of the AT91SAM4 microcontroller family from
4727 Atmel include internal flash and use ARM's Cortex-M4 core.
4728 This driver uses the same cmd names/syntax as @xref{at91sam3}.
4731 @deffn {Flash Driver} at91sam7
4732 All members of the AT91SAM7 microcontroller family from Atmel include
4733 internal flash and use ARM7TDMI cores. The driver automatically
4734 recognizes a number of these chips using the chip identification
4735 register, and autoconfigures itself.
4738 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
4741 For chips which are not recognized by the controller driver, you must
4742 provide additional parameters in the following order:
4745 @item @var{chip_model} ... label used with @command{flash info}
4747 @item @var{sectors_per_bank}
4748 @item @var{pages_per_sector}
4749 @item @var{pages_size}
4750 @item @var{num_nvm_bits}
4751 @item @var{freq_khz} ... required if an external clock is provided,
4752 optional (but recommended) when the oscillator frequency is known
4755 It is recommended that you provide zeroes for all of those values
4756 except the clock frequency, so that everything except that frequency
4757 will be autoconfigured.
4758 Knowing the frequency helps ensure correct timings for flash access.
4760 The flash controller handles erases automatically on a page (128/256 byte)
4761 basis, so explicit erase commands are not necessary for flash programming.
4762 However, there is an ``EraseAll`` command that can erase an entire flash
4763 plane (of up to 256KB), and it will be used automatically when you issue
4764 @command{flash erase_sector} or @command{flash erase_address} commands.
4766 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
4767 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
4768 bit for the processor. Each processor has a number of such bits,
4769 used for controlling features such as brownout detection (so they
4770 are not truly general purpose).
4772 This assumes that the first flash bank (number 0) is associated with
4773 the appropriate at91sam7 target.
4778 @deffn {Flash Driver} avr
4779 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
4780 @emph{The current implementation is incomplete.}
4781 @comment - defines mass_erase ... pointless given flash_erase_address
4784 @deffn {Flash Driver} lpc2000
4785 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
4786 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
4789 There are LPC2000 devices which are not supported by the @var{lpc2000}
4791 The LPC2888 is supported by the @var{lpc288x} driver.
4792 The LPC29xx family is supported by the @var{lpc2900} driver.
4795 The @var{lpc2000} driver defines two mandatory and one optional parameters,
4796 which must appear in the following order:
4799 @item @var{variant} ... required, may be
4800 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
4801 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
4802 or @option{lpc1700} (LPC175x and LPC176x)
4803 @item @var{clock_kHz} ... the frequency, in kiloHertz,
4804 at which the core is running
4805 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
4806 telling the driver to calculate a valid checksum for the exception vector table.
4808 If you don't provide @option{calc_checksum} when you're writing the vector
4809 table, the boot ROM will almost certainly ignore your flash image.
4810 However, if you do provide it,
4811 with most tool chains @command{verify_image} will fail.
4815 LPC flashes don't require the chip and bus width to be specified.
4818 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
4819 lpc2000_v2 14765 calc_checksum
4822 @deffn {Command} {lpc2000 part_id} bank
4823 Displays the four byte part identifier associated with
4824 the specified flash @var{bank}.
4828 @deffn {Flash Driver} lpc288x
4829 The LPC2888 microcontroller from NXP needs slightly different flash
4830 support from its lpc2000 siblings.
4831 The @var{lpc288x} driver defines one mandatory parameter,
4832 the programming clock rate in Hz.
4833 LPC flashes don't require the chip and bus width to be specified.
4836 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
4840 @deffn {Flash Driver} lpc2900
4841 This driver supports the LPC29xx ARM968E based microcontroller family
4844 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
4845 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
4846 sector layout are auto-configured by the driver.
4847 The driver has one additional mandatory parameter: The CPU clock rate
4848 (in kHz) at the time the flash operations will take place. Most of the time this
4849 will not be the crystal frequency, but a higher PLL frequency. The
4850 @code{reset-init} event handler in the board script is usually the place where
4853 The driver rejects flashless devices (currently the LPC2930).
4855 The EEPROM in LPC2900 devices is not mapped directly into the address space.
4856 It must be handled much more like NAND flash memory, and will therefore be
4857 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
4859 Sector protection in terms of the LPC2900 is handled transparently. Every time a
4860 sector needs to be erased or programmed, it is automatically unprotected.
4861 What is shown as protection status in the @code{flash info} command, is
4862 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
4863 sector from ever being erased or programmed again. As this is an irreversible
4864 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
4865 and not by the standard @code{flash protect} command.
4867 Example for a 125 MHz clock frequency:
4869 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
4872 Some @code{lpc2900}-specific commands are defined. In the following command list,
4873 the @var{bank} parameter is the bank number as obtained by the
4874 @code{flash banks} command.
4876 @deffn Command {lpc2900 signature} bank
4877 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
4878 content. This is a hardware feature of the flash block, hence the calculation is
4879 very fast. You may use this to verify the content of a programmed device against
4884 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
4888 @deffn Command {lpc2900 read_custom} bank filename
4889 Reads the 912 bytes of customer information from the flash index sector, and
4890 saves it to a file in binary format.
4893 lpc2900 read_custom 0 /path_to/customer_info.bin
4897 The index sector of the flash is a @emph{write-only} sector. It cannot be
4898 erased! In order to guard against unintentional write access, all following
4899 commands need to be preceeded by a successful call to the @code{password}
4902 @deffn Command {lpc2900 password} bank password
4903 You need to use this command right before each of the following commands:
4904 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
4905 @code{lpc2900 secure_jtag}.
4907 The password string is fixed to "I_know_what_I_am_doing".
4910 lpc2900 password 0 I_know_what_I_am_doing
4911 Potentially dangerous operation allowed in next command!
4915 @deffn Command {lpc2900 write_custom} bank filename type
4916 Writes the content of the file into the customer info space of the flash index
4917 sector. The filetype can be specified with the @var{type} field. Possible values
4918 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
4919 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
4920 contain a single section, and the contained data length must be exactly
4922 @quotation Attention
4923 This cannot be reverted! Be careful!
4927 lpc2900 write_custom 0 /path_to/customer_info.bin bin
4931 @deffn Command {lpc2900 secure_sector} bank first last
4932 Secures the sector range from @var{first} to @var{last} (including) against
4933 further program and erase operations. The sector security will be effective
4934 after the next power cycle.
4935 @quotation Attention
4936 This cannot be reverted! Be careful!
4938 Secured sectors appear as @emph{protected} in the @code{flash info} command.
4941 lpc2900 secure_sector 0 1 1
4943 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
4944 # 0: 0x00000000 (0x2000 8kB) not protected
4945 # 1: 0x00002000 (0x2000 8kB) protected
4946 # 2: 0x00004000 (0x2000 8kB) not protected
4950 @deffn Command {lpc2900 secure_jtag} bank
4951 Irreversibly disable the JTAG port. The new JTAG security setting will be
4952 effective after the next power cycle.
4953 @quotation Attention
4954 This cannot be reverted! Be careful!
4958 lpc2900 secure_jtag 0
4963 @deffn {Flash Driver} ocl
4964 @emph{No idea what this is, other than using some arm7/arm9 core.}
4967 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
4971 @deffn {Flash Driver} pic32mx
4972 The PIC32MX microcontrollers are based on the MIPS 4K cores,
4973 and integrate flash memory.
4976 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
4977 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
4980 @comment numerous *disabled* commands are defined:
4981 @comment - chip_erase ... pointless given flash_erase_address
4982 @comment - lock, unlock ... pointless given protect on/off (yes?)
4983 @comment - pgm_word ... shouldn't bank be deduced from address??
4984 Some pic32mx-specific commands are defined:
4985 @deffn Command {pic32mx pgm_word} address value bank
4986 Programs the specified 32-bit @var{value} at the given @var{address}
4987 in the specified chip @var{bank}.
4989 @deffn Command {pic32mx unlock} bank
4990 Unlock and erase specified chip @var{bank}.
4991 This will remove any Code Protection.
4995 @deffn {Flash Driver} stellaris
4996 All members of the Stellaris LM3Sxxx microcontroller family from
4998 include internal flash and use ARM Cortex M3 cores.
4999 The driver automatically recognizes a number of these chips using
5000 the chip identification register, and autoconfigures itself.
5001 @footnote{Currently there is a @command{stellaris mass_erase} command.
5002 That seems pointless since the same effect can be had using the
5003 standard @command{flash erase_address} command.}
5006 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
5010 @deffn Command {stellaris recover bank_id}
5011 Performs the @emph{Recovering a "Locked" Device} procedure to
5012 restore the flash specified by @var{bank_id} and its associated
5013 nonvolatile registers to their factory default values (erased).
5014 This is the only way to remove flash protection or re-enable
5015 debugging if that capability has been disabled.
5017 Note that the final "power cycle the chip" step in this procedure
5018 must be performed by hand, since OpenOCD can't do it.
5020 if more than one Stellaris chip is connected, the procedure is
5021 applied to all of them.
5025 @deffn {Flash Driver} stm32f1x
5026 All members of the STM32f1x microcontroller family from ST Microelectronics
5027 include internal flash and use ARM Cortex M3 cores.
5028 The driver automatically recognizes a number of these chips using
5029 the chip identification register, and autoconfigures itself.
5032 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
5035 If you have a target with dual flash banks then define the second bank
5036 as per the following example.
5038 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
5041 Some stm32f1x-specific commands
5042 @footnote{Currently there is a @command{stm32f1x mass_erase} command.
5043 That seems pointless since the same effect can be had using the
5044 standard @command{flash erase_address} command.}
5047 @deffn Command {stm32f1x lock} num
5048 Locks the entire stm32 device.
5049 The @var{num} parameter is a value shown by @command{flash banks}.
5052 @deffn Command {stm32f1x unlock} num
5053 Unlocks the entire stm32 device.
5054 The @var{num} parameter is a value shown by @command{flash banks}.
5057 @deffn Command {stm32f1x options_read} num
5058 Read and display the stm32 option bytes written by
5059 the @command{stm32f1x options_write} command.
5060 The @var{num} parameter is a value shown by @command{flash banks}.
5063 @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
5064 Writes the stm32 option byte with the specified values.
5065 The @var{num} parameter is a value shown by @command{flash banks}.
5069 @deffn {Flash Driver} stm32f2x
5070 All members of the STM32f2x microcontroller family from ST Microelectronics
5071 include internal flash and use ARM Cortex M3 cores.
5072 The driver automatically recognizes a number of these chips using
5073 the chip identification register, and autoconfigures itself.
5076 @deffn {Flash Driver} str7x
5077 All members of the STR7 microcontroller family from ST Microelectronics
5078 include internal flash and use ARM7TDMI cores.
5079 The @var{str7x} driver defines one mandatory parameter, @var{variant},
5080 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
5083 flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
5086 @deffn Command {str7x disable_jtag} bank
5087 Activate the Debug/Readout protection mechanism
5088 for the specified flash bank.
5092 @deffn {Flash Driver} str9x
5093 Most members of the STR9 microcontroller family from ST Microelectronics
5094 include internal flash and use ARM966E cores.
5095 The str9 needs the flash controller to be configured using
5096 the @command{str9x flash_config} command prior to Flash programming.
5099 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
5100 str9x flash_config 0 4 2 0 0x80000
5103 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
5104 Configures the str9 flash controller.
5105 The @var{num} parameter is a value shown by @command{flash banks}.
5108 @item @var{bbsr} - Boot Bank Size register
5109 @item @var{nbbsr} - Non Boot Bank Size register
5110 @item @var{bbadr} - Boot Bank Start Address register
5111 @item @var{nbbadr} - Boot Bank Start Address register
5117 @deffn {Flash Driver} tms470
5118 Most members of the TMS470 microcontroller family from Texas Instruments
5119 include internal flash and use ARM7TDMI cores.
5120 This driver doesn't require the chip and bus width to be specified.
5122 Some tms470-specific commands are defined:
5124 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
5125 Saves programming keys in a register, to enable flash erase and write commands.
5128 @deffn Command {tms470 osc_mhz} clock_mhz
5129 Reports the clock speed, which is used to calculate timings.
5132 @deffn Command {tms470 plldis} (0|1)
5133 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
5138 @deffn {Flash Driver} virtual
5139 This is a special driver that maps a previously defined bank to another
5140 address. All bank settings will be copied from the master physical bank.
5142 The @var{virtual} driver defines one mandatory parameters,
5145 @item @var{master_bank} The bank that this virtual address refers to.
5148 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5149 the flash bank defined at address 0x1fc00000. Any cmds executed on
5150 the virtual banks are actually performed on the physical banks.
5152 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5153 flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
5154 flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
5158 @deffn {Flash Driver} fm3
5159 All members of the FM3 microcontroller family from Fujitsu
5160 include internal flash and use ARM Cortex M3 cores.
5161 The @var{fm3} driver uses the @var{target} parameter to select the
5162 correct bank config, it can currently be one of the following:
5163 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
5164 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
5167 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
5171 @subsection str9xpec driver
5174 Here is some background info to help
5175 you better understand how this driver works. OpenOCD has two flash drivers for
5179 Standard driver @option{str9x} programmed via the str9 core. Normally used for
5180 flash programming as it is faster than the @option{str9xpec} driver.
5182 Direct programming @option{str9xpec} using the flash controller. This is an
5183 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
5184 core does not need to be running to program using this flash driver. Typical use
5185 for this driver is locking/unlocking the target and programming the option bytes.
5188 Before we run any commands using the @option{str9xpec} driver we must first disable
5189 the str9 core. This example assumes the @option{str9xpec} driver has been
5190 configured for flash bank 0.
5192 # assert srst, we do not want core running
5193 # while accessing str9xpec flash driver
5195 # turn off target polling
5198 str9xpec enable_turbo 0
5200 str9xpec options_read 0
5201 # re-enable str9 core
5202 str9xpec disable_turbo 0
5206 The above example will read the str9 option bytes.
5207 When performing a unlock remember that you will not be able to halt the str9 - it
5208 has been locked. Halting the core is not required for the @option{str9xpec} driver
5209 as mentioned above, just issue the commands above manually or from a telnet prompt.
5211 @deffn {Flash Driver} str9xpec
5212 Only use this driver for locking/unlocking the device or configuring the option bytes.
5213 Use the standard str9 driver for programming.
5214 Before using the flash commands the turbo mode must be enabled using the
5215 @command{str9xpec enable_turbo} command.
5217 Several str9xpec-specific commands are defined:
5219 @deffn Command {str9xpec disable_turbo} num
5220 Restore the str9 into JTAG chain.
5223 @deffn Command {str9xpec enable_turbo} num
5224 Enable turbo mode, will simply remove the str9 from the chain and talk
5225 directly to the embedded flash controller.
5228 @deffn Command {str9xpec lock} num
5229 Lock str9 device. The str9 will only respond to an unlock command that will
5233 @deffn Command {str9xpec part_id} num
5234 Prints the part identifier for bank @var{num}.
5237 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
5238 Configure str9 boot bank.
5241 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
5242 Configure str9 lvd source.
5245 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
5246 Configure str9 lvd threshold.
5249 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
5250 Configure str9 lvd reset warning source.
5253 @deffn Command {str9xpec options_read} num
5254 Read str9 option bytes.
5257 @deffn Command {str9xpec options_write} num
5258 Write str9 option bytes.
5261 @deffn Command {str9xpec unlock} num
5270 @subsection mFlash Configuration
5271 @cindex mFlash Configuration
5273 @deffn {Config Command} {mflash bank} soc base RST_pin target
5274 Configures a mflash for @var{soc} host bank at
5276 The pin number format depends on the host GPIO naming convention.
5277 Currently, the mflash driver supports s3c2440 and pxa270.
5279 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
5282 mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
5285 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
5288 mflash bank $_FLASHNAME pxa270 0x08000000 43 0
5292 @subsection mFlash commands
5293 @cindex mFlash commands
5295 @deffn Command {mflash config pll} frequency
5296 Configure mflash PLL.
5297 The @var{frequency} is the mflash input frequency, in Hz.
5298 Issuing this command will erase mflash's whole internal nand and write new pll.
5299 After this command, mflash needs power-on-reset for normal operation.
5300 If pll was newly configured, storage and boot(optional) info also need to be update.
5303 @deffn Command {mflash config boot}
5304 Configure bootable option.
5305 If bootable option is set, mflash offer the first 8 sectors
5309 @deffn Command {mflash config storage}
5310 Configure storage information.
5311 For the normal storage operation, this information must be
5315 @deffn Command {mflash dump} num filename offset size
5316 Dump @var{size} bytes, starting at @var{offset} bytes from the
5317 beginning of the bank @var{num}, to the file named @var{filename}.
5320 @deffn Command {mflash probe}
5324 @deffn Command {mflash write} num filename offset
5325 Write the binary file @var{filename} to mflash bank @var{num}, starting at
5326 @var{offset} bytes from the beginning of the bank.
5329 @node NAND Flash Commands
5330 @chapter NAND Flash Commands
5333 Compared to NOR or SPI flash, NAND devices are inexpensive
5334 and high density. Today's NAND chips, and multi-chip modules,
5335 commonly hold multiple GigaBytes of data.
5337 NAND chips consist of a number of ``erase blocks'' of a given
5338 size (such as 128 KBytes), each of which is divided into a
5339 number of pages (of perhaps 512 or 2048 bytes each). Each
5340 page of a NAND flash has an ``out of band'' (OOB) area to hold
5341 Error Correcting Code (ECC) and other metadata, usually 16 bytes
5342 of OOB for every 512 bytes of page data.
5344 One key characteristic of NAND flash is that its error rate
5345 is higher than that of NOR flash. In normal operation, that
5346 ECC is used to correct and detect errors. However, NAND
5347 blocks can also wear out and become unusable; those blocks
5348 are then marked "bad". NAND chips are even shipped from the
5349 manufacturer with a few bad blocks. The highest density chips
5350 use a technology (MLC) that wears out more quickly, so ECC
5351 support is increasingly important as a way to detect blocks
5352 that have begun to fail, and help to preserve data integrity
5353 with techniques such as wear leveling.
5355 Software is used to manage the ECC. Some controllers don't
5356 support ECC directly; in those cases, software ECC is used.
5357 Other controllers speed up the ECC calculations with hardware.
5358 Single-bit error correction hardware is routine. Controllers
5359 geared for newer MLC chips may correct 4 or more errors for
5360 every 512 bytes of data.
5362 You will need to make sure that any data you write using
5363 OpenOCD includes the apppropriate kind of ECC. For example,
5364 that may mean passing the @code{oob_softecc} flag when
5365 writing NAND data, or ensuring that the correct hardware
5368 The basic steps for using NAND devices include:
5370 @item Declare via the command @command{nand device}
5371 @* Do this in a board-specific configuration file,
5372 passing parameters as needed by the controller.
5373 @item Configure each device using @command{nand probe}.
5374 @* Do this only after the associated target is set up,
5375 such as in its reset-init script or in procures defined
5376 to access that device.
5377 @item Operate on the flash via @command{nand subcommand}
5378 @* Often commands to manipulate the flash are typed by a human, or run
5379 via a script in some automated way. Common task include writing a
5380 boot loader, operating system, or other data needed to initialize or
5384 @b{NOTE:} At the time this text was written, the largest NAND
5385 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
5386 This is because the variables used to hold offsets and lengths
5387 are only 32 bits wide.
5388 (Larger chips may work in some cases, unless an offset or length
5389 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
5390 Some larger devices will work, since they are actually multi-chip
5391 modules with two smaller chips and individual chipselect lines.
5393 @anchor{NAND Configuration}
5394 @section NAND Configuration Commands
5395 @cindex NAND configuration
5397 NAND chips must be declared in configuration scripts,
5398 plus some additional configuration that's done after
5399 OpenOCD has initialized.
5401 @deffn {Config Command} {nand device} name driver target [configparams...]
5402 Declares a NAND device, which can be read and written to
5403 after it has been configured through @command{nand probe}.
5404 In OpenOCD, devices are single chips; this is unlike some
5405 operating systems, which may manage multiple chips as if
5406 they were a single (larger) device.
5407 In some cases, configuring a device will activate extra
5408 commands; see the controller-specific documentation.
5410 @b{NOTE:} This command is not available after OpenOCD
5411 initialization has completed. Use it in board specific
5412 configuration files, not interactively.
5415 @item @var{name} ... may be used to reference the NAND bank
5416 in most other NAND commands. A number is also available.
5417 @item @var{driver} ... identifies the NAND controller driver
5418 associated with the NAND device being declared.
5419 @xref{NAND Driver List}.
5420 @item @var{target} ... names the target used when issuing
5421 commands to the NAND controller.
5422 @comment Actually, it's currently a controller-specific parameter...
5423 @item @var{configparams} ... controllers may support, or require,
5424 additional parameters. See the controller-specific documentation
5425 for more information.
5429 @deffn Command {nand list}
5430 Prints a summary of each device declared
5431 using @command{nand device}, numbered from zero.
5432 Note that un-probed devices show no details.
5435 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
5436 blocksize: 131072, blocks: 8192
5437 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
5438 blocksize: 131072, blocks: 8192
5443 @deffn Command {nand probe} num
5444 Probes the specified device to determine key characteristics
5445 like its page and block sizes, and how many blocks it has.
5446 The @var{num} parameter is the value shown by @command{nand list}.
5447 You must (successfully) probe a device before you can use
5448 it with most other NAND commands.
5451 @section Erasing, Reading, Writing to NAND Flash
5453 @deffn Command {nand dump} num filename offset length [oob_option]
5454 @cindex NAND reading
5455 Reads binary data from the NAND device and writes it to the file,
5456 starting at the specified offset.
5457 The @var{num} parameter is the value shown by @command{nand list}.
5459 Use a complete path name for @var{filename}, so you don't depend
5460 on the directory used to start the OpenOCD server.
5462 The @var{offset} and @var{length} must be exact multiples of the
5463 device's page size. They describe a data region; the OOB data
5464 associated with each such page may also be accessed.
5466 @b{NOTE:} At the time this text was written, no error correction
5467 was done on the data that's read, unless raw access was disabled
5468 and the underlying NAND controller driver had a @code{read_page}
5469 method which handled that error correction.
5471 By default, only page data is saved to the specified file.
5472 Use an @var{oob_option} parameter to save OOB data:
5474 @item no oob_* parameter
5475 @*Output file holds only page data; OOB is discarded.
5476 @item @code{oob_raw}
5477 @*Output file interleaves page data and OOB data;
5478 the file will be longer than "length" by the size of the
5479 spare areas associated with each data page.
5480 Note that this kind of "raw" access is different from
5481 what's implied by @command{nand raw_access}, which just
5482 controls whether a hardware-aware access method is used.
5483 @item @code{oob_only}
5484 @*Output file has only raw OOB data, and will
5485 be smaller than "length" since it will contain only the
5486 spare areas associated with each data page.
5490 @deffn Command {nand erase} num [offset length]
5491 @cindex NAND erasing
5492 @cindex NAND programming
5493 Erases blocks on the specified NAND device, starting at the
5494 specified @var{offset} and continuing for @var{length} bytes.
5495 Both of those values must be exact multiples of the device's
5496 block size, and the region they specify must fit entirely in the chip.
5497 If those parameters are not specified,
5498 the whole NAND chip will be erased.
5499 The @var{num} parameter is the value shown by @command{nand list}.
5501 @b{NOTE:} This command will try to erase bad blocks, when told
5502 to do so, which will probably invalidate the manufacturer's bad
5504 For the remainder of the current server session, @command{nand info}
5505 will still report that the block ``is'' bad.
5508 @deffn Command {nand write} num filename offset [option...]
5509 @cindex NAND writing
5510 @cindex NAND programming
5511 Writes binary data from the file into the specified NAND device,
5512 starting at the specified offset. Those pages should already
5513 have been erased; you can't change zero bits to one bits.
5514 The @var{num} parameter is the value shown by @command{nand list}.
5516 Use a complete path name for @var{filename}, so you don't depend
5517 on the directory used to start the OpenOCD server.
5519 The @var{offset} must be an exact multiple of the device's page size.
5520 All data in the file will be written, assuming it doesn't run
5521 past the end of the device.
5522 Only full pages are written, and any extra space in the last
5523 page will be filled with 0xff bytes. (That includes OOB data,
5524 if that's being written.)
5526 @b{NOTE:} At the time this text was written, bad blocks are
5527 ignored. That is, this routine will not skip bad blocks,
5528 but will instead try to write them. This can cause problems.
5530 Provide at most one @var{option} parameter. With some
5531 NAND drivers, the meanings of these parameters may change
5532 if @command{nand raw_access} was used to disable hardware ECC.
5534 @item no oob_* parameter
5535 @*File has only page data, which is written.
5536 If raw acccess is in use, the OOB area will not be written.
5537 Otherwise, if the underlying NAND controller driver has
5538 a @code{write_page} routine, that routine may write the OOB
5539 with hardware-computed ECC data.
5540 @item @code{oob_only}
5541 @*File has only raw OOB data, which is written to the OOB area.
5542 Each page's data area stays untouched. @i{This can be a dangerous
5543 option}, since it can invalidate the ECC data.
5544 You may need to force raw access to use this mode.
5545 @item @code{oob_raw}
5546 @*File interleaves data and OOB data, both of which are written
5547 If raw access is enabled, the data is written first, then the
5549 Otherwise, if the underlying NAND controller driver has
5550 a @code{write_page} routine, that routine may modify the OOB
5551 before it's written, to include hardware-computed ECC data.
5552 @item @code{oob_softecc}
5553 @*File has only page data, which is written.
5554 The OOB area is filled with 0xff, except for a standard 1-bit
5555 software ECC code stored in conventional locations.
5556 You might need to force raw access to use this mode, to prevent
5557 the underlying driver from applying hardware ECC.
5558 @item @code{oob_softecc_kw}
5559 @*File has only page data, which is written.
5560 The OOB area is filled with 0xff, except for a 4-bit software ECC
5561 specific to the boot ROM in Marvell Kirkwood SoCs.
5562 You might need to force raw access to use this mode, to prevent
5563 the underlying driver from applying hardware ECC.
5567 @deffn Command {nand verify} num filename offset [option...]
5568 @cindex NAND verification
5569 @cindex NAND programming
5570 Verify the binary data in the file has been programmed to the
5571 specified NAND device, starting at the specified offset.
5572 The @var{num} parameter is the value shown by @command{nand list}.
5574 Use a complete path name for @var{filename}, so you don't depend
5575 on the directory used to start the OpenOCD server.
5577 The @var{offset} must be an exact multiple of the device's page size.
5578 All data in the file will be read and compared to the contents of the
5579 flash, assuming it doesn't run past the end of the device.
5580 As with @command{nand write}, only full pages are verified, so any extra
5581 space in the last page will be filled with 0xff bytes.
5583 The same @var{options} accepted by @command{nand write},
5584 and the file will be processed similarly to produce the buffers that
5585 can be compared against the contents produced from @command{nand dump}.
5587 @b{NOTE:} This will not work when the underlying NAND controller
5588 driver's @code{write_page} routine must update the OOB with a
5589 hardward-computed ECC before the data is written. This limitation may
5590 be removed in a future release.
5593 @section Other NAND commands
5594 @cindex NAND other commands
5596 @deffn Command {nand check_bad_blocks} num [offset length]
5597 Checks for manufacturer bad block markers on the specified NAND
5598 device. If no parameters are provided, checks the whole
5599 device; otherwise, starts at the specified @var{offset} and
5600 continues for @var{length} bytes.
5601 Both of those values must be exact multiples of the device's
5602 block size, and the region they specify must fit entirely in the chip.
5603 The @var{num} parameter is the value shown by @command{nand list}.
5605 @b{NOTE:} Before using this command you should force raw access
5606 with @command{nand raw_access enable} to ensure that the underlying
5607 driver will not try to apply hardware ECC.
5610 @deffn Command {nand info} num
5611 The @var{num} parameter is the value shown by @command{nand list}.
5612 This prints the one-line summary from "nand list", plus for
5613 devices which have been probed this also prints any known
5614 status for each block.
5617 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
5618 Sets or clears an flag affecting how page I/O is done.
5619 The @var{num} parameter is the value shown by @command{nand list}.
5621 This flag is cleared (disabled) by default, but changing that
5622 value won't affect all NAND devices. The key factor is whether
5623 the underlying driver provides @code{read_page} or @code{write_page}
5624 methods. If it doesn't provide those methods, the setting of
5625 this flag is irrelevant; all access is effectively ``raw''.
5627 When those methods exist, they are normally used when reading
5628 data (@command{nand dump} or reading bad block markers) or
5629 writing it (@command{nand write}). However, enabling
5630 raw access (setting the flag) prevents use of those methods,
5631 bypassing hardware ECC logic.
5632 @i{This can be a dangerous option}, since writing blocks
5633 with the wrong ECC data can cause them to be marked as bad.
5636 @anchor{NAND Driver List}
5637 @section NAND Driver List
5638 As noted above, the @command{nand device} command allows
5639 driver-specific options and behaviors.
5640 Some controllers also activate controller-specific commands.
5642 @deffn {NAND Driver} at91sam9
5643 This driver handles the NAND controllers found on AT91SAM9 family chips from
5644 Atmel. It takes two extra parameters: address of the NAND chip;
5645 address of the ECC controller.
5647 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
5649 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
5650 @code{read_page} methods are used to utilize the ECC hardware unless they are
5651 disabled by using the @command{nand raw_access} command. There are four
5652 additional commands that are needed to fully configure the AT91SAM9 NAND
5653 controller. Two are optional; most boards use the same wiring for ALE/CLE:
5654 @deffn Command {at91sam9 cle} num addr_line
5655 Configure the address line used for latching commands. The @var{num}
5656 parameter is the value shown by @command{nand list}.
5658 @deffn Command {at91sam9 ale} num addr_line
5659 Configure the address line used for latching addresses. The @var{num}
5660 parameter is the value shown by @command{nand list}.
5663 For the next two commands, it is assumed that the pins have already been
5664 properly configured for input or output.
5665 @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
5666 Configure the RDY/nBUSY input from the NAND device. The @var{num}
5667 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
5668 is the base address of the PIO controller and @var{pin} is the pin number.
5670 @deffn Command {at91sam9 ce} num pio_base_addr pin
5671 Configure the chip enable input to the NAND device. The @var{num}
5672 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
5673 is the base address of the PIO controller and @var{pin} is the pin number.
5677 @deffn {NAND Driver} davinci
5678 This driver handles the NAND controllers found on DaVinci family
5679 chips from Texas Instruments.
5680 It takes three extra parameters:
5681 address of the NAND chip;
5682 hardware ECC mode to use (@option{hwecc1},
5683 @option{hwecc4}, @option{hwecc4_infix});
5684 address of the AEMIF controller on this processor.
5686 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
5688 All DaVinci processors support the single-bit ECC hardware,
5689 and newer ones also support the four-bit ECC hardware.
5690 The @code{write_page} and @code{read_page} methods are used
5691 to implement those ECC modes, unless they are disabled using
5692 the @command{nand raw_access} command.
5695 @deffn {NAND Driver} lpc3180
5696 These controllers require an extra @command{nand device}
5697 parameter: the clock rate used by the controller.
5698 @deffn Command {lpc3180 select} num [mlc|slc]
5699 Configures use of the MLC or SLC controller mode.
5700 MLC implies use of hardware ECC.
5701 The @var{num} parameter is the value shown by @command{nand list}.
5704 At this writing, this driver includes @code{write_page}
5705 and @code{read_page} methods. Using @command{nand raw_access}
5706 to disable those methods will prevent use of hardware ECC
5707 in the MLC controller mode, but won't change SLC behavior.
5709 @comment current lpc3180 code won't issue 5-byte address cycles
5711 @deffn {NAND Driver} mx3
5712 This driver handles the NAND controller in i.MX31. The mxc driver
5713 should work for this chip aswell.
5716 @deffn {NAND Driver} mxc
5717 This driver handles the NAND controller found in Freescale i.MX
5718 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
5719 The driver takes 3 extra arguments, chip (@option{mx27},
5720 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
5721 and optionally if bad block information should be swapped between
5722 main area and spare area (@option{biswap}), defaults to off.
5724 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
5726 @deffn Command {mxc biswap} bank_num [enable|disable]
5727 Turns on/off bad block information swaping from main area,
5728 without parameter query status.
5732 @deffn {NAND Driver} orion
5733 These controllers require an extra @command{nand device}
5734 parameter: the address of the controller.
5736 nand device orion 0xd8000000
5738 These controllers don't define any specialized commands.
5739 At this writing, their drivers don't include @code{write_page}
5740 or @code{read_page} methods, so @command{nand raw_access} won't
5741 change any behavior.
5744 @deffn {NAND Driver} s3c2410
5745 @deffnx {NAND Driver} s3c2412
5746 @deffnx {NAND Driver} s3c2440
5747 @deffnx {NAND Driver} s3c2443
5748 @deffnx {NAND Driver} s3c6400
5749 These S3C family controllers don't have any special
5750 @command{nand device} options, and don't define any
5751 specialized commands.
5752 At this writing, their drivers don't include @code{write_page}
5753 or @code{read_page} methods, so @command{nand raw_access} won't
5754 change any behavior.
5757 @node PLD/FPGA Commands
5758 @chapter PLD/FPGA Commands
5762 Programmable Logic Devices (PLDs) and the more flexible
5763 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
5764 OpenOCD can support programming them.
5765 Although PLDs are generally restrictive (cells are less functional, and
5766 there are no special purpose cells for memory or computational tasks),
5767 they share the same OpenOCD infrastructure.
5768 Accordingly, both are called PLDs here.
5770 @section PLD/FPGA Configuration and Commands
5772 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
5773 OpenOCD maintains a list of PLDs available for use in various commands.
5774 Also, each such PLD requires a driver.
5776 They are referenced by the number shown by the @command{pld devices} command,
5777 and new PLDs are defined by @command{pld device driver_name}.
5779 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
5780 Defines a new PLD device, supported by driver @var{driver_name},
5781 using the TAP named @var{tap_name}.
5782 The driver may make use of any @var{driver_options} to configure its
5786 @deffn {Command} {pld devices}
5787 Lists the PLDs and their numbers.
5790 @deffn {Command} {pld load} num filename
5791 Loads the file @file{filename} into the PLD identified by @var{num}.
5792 The file format must be inferred by the driver.
5795 @section PLD/FPGA Drivers, Options, and Commands
5797 Drivers may support PLD-specific options to the @command{pld device}
5798 definition command, and may also define commands usable only with
5799 that particular type of PLD.
5801 @deffn {FPGA Driver} virtex2
5802 Virtex-II is a family of FPGAs sold by Xilinx.
5803 It supports the IEEE 1532 standard for In-System Configuration (ISC).
5804 No driver-specific PLD definition options are used,
5805 and one driver-specific command is defined.
5807 @deffn {Command} {virtex2 read_stat} num
5808 Reads and displays the Virtex-II status register (STAT)
5813 @node General Commands
5814 @chapter General Commands
5817 The commands documented in this chapter here are common commands that
5818 you, as a human, may want to type and see the output of. Configuration type
5819 commands are documented elsewhere.
5823 @item @b{Source Of Commands}
5824 @* OpenOCD commands can occur in a configuration script (discussed
5825 elsewhere) or typed manually by a human or supplied programatically,
5826 or via one of several TCP/IP Ports.
5828 @item @b{From the human}
5829 @* A human should interact with the telnet interface (default port: 4444)
5830 or via GDB (default port 3333).
5832 To issue commands from within a GDB session, use the @option{monitor}
5833 command, e.g. use @option{monitor poll} to issue the @option{poll}
5834 command. All output is relayed through the GDB session.
5836 @item @b{Machine Interface}
5837 The Tcl interface's intent is to be a machine interface. The default Tcl
5842 @section Daemon Commands
5844 @deffn {Command} exit
5845 Exits the current telnet session.
5848 @deffn {Command} help [string]
5849 With no parameters, prints help text for all commands.
5850 Otherwise, prints each helptext containing @var{string}.
5851 Not every command provides helptext.
5853 Configuration commands, and commands valid at any time, are
5854 explicitly noted in parenthesis.
5855 In most cases, no such restriction is listed; this indicates commands
5856 which are only available after the configuration stage has completed.
5859 @deffn Command sleep msec [@option{busy}]
5860 Wait for at least @var{msec} milliseconds before resuming.
5861 If @option{busy} is passed, busy-wait instead of sleeping.
5862 (This option is strongly discouraged.)
5863 Useful in connection with script files
5864 (@command{script} command and @command{target_name} configuration).
5867 @deffn Command shutdown
5868 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
5871 @anchor{debug_level}
5872 @deffn Command debug_level [n]
5873 @cindex message level
5874 Display debug level.
5875 If @var{n} (from 0..3) is provided, then set it to that level.
5876 This affects the kind of messages sent to the server log.
5877 Level 0 is error messages only;
5878 level 1 adds warnings;
5879 level 2 adds informational messages;
5880 and level 3 adds debugging messages.
5881 The default is level 2, but that can be overridden on
5882 the command line along with the location of that log
5883 file (which is normally the server's standard output).
5887 @deffn Command echo [-n] message
5888 Logs a message at "user" priority.
5889 Output @var{message} to stdout.
5890 Option "-n" suppresses trailing newline.
5892 echo "Downloading kernel -- please wait"
5896 @deffn Command log_output [filename]
5897 Redirect logging to @var{filename};
5898 the initial log output channel is stderr.
5901 @deffn Command add_script_search_dir [directory]
5902 Add @var{directory} to the file/script search path.
5905 @anchor{Target State handling}
5906 @section Target State handling
5909 @cindex target initialization
5911 In this section ``target'' refers to a CPU configured as
5912 shown earlier (@pxref{CPU Configuration}).
5913 These commands, like many, implicitly refer to
5914 a current target which is used to perform the
5915 various operations. The current target may be changed
5916 by using @command{targets} command with the name of the
5917 target which should become current.
5919 @deffn Command reg [(number|name) [value]]
5920 Access a single register by @var{number} or by its @var{name}.
5921 The target must generally be halted before access to CPU core
5922 registers is allowed. Depending on the hardware, some other
5923 registers may be accessible while the target is running.
5925 @emph{With no arguments}:
5926 list all available registers for the current target,
5927 showing number, name, size, value, and cache status.
5928 For valid entries, a value is shown; valid entries
5929 which are also dirty (and will be written back later)
5930 are flagged as such.
5932 @emph{With number/name}: display that register's value.
5934 @emph{With both number/name and value}: set register's value.
5935 Writes may be held in a writeback cache internal to OpenOCD,
5936 so that setting the value marks the register as dirty instead
5937 of immediately flushing that value. Resuming CPU execution
5938 (including by single stepping) or otherwise activating the
5939 relevant module will flush such values.
5941 Cores may have surprisingly many registers in their
5942 Debug and trace infrastructure:
5947 (0) r0 (/32): 0x0000D3C2 (dirty)
5948 (1) r1 (/32): 0xFD61F31C
5951 (164) ETM_contextid_comparator_mask (/32)
5956 @deffn Command halt [ms]
5957 @deffnx Command wait_halt [ms]
5958 The @command{halt} command first sends a halt request to the target,
5959 which @command{wait_halt} doesn't.
5960 Otherwise these behave the same: wait up to @var{ms} milliseconds,
5961 or 5 seconds if there is no parameter, for the target to halt
5962 (and enter debug mode).
5963 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
5966 On ARM cores, software using the @emph{wait for interrupt} operation
5967 often blocks the JTAG access needed by a @command{halt} command.
5968 This is because that operation also puts the core into a low
5969 power mode by gating the core clock;
5970 but the core clock is needed to detect JTAG clock transitions.
5972 One partial workaround uses adaptive clocking: when the core is
5973 interrupted the operation completes, then JTAG clocks are accepted
5974 at least until the interrupt handler completes.
5975 However, this workaround is often unusable since the processor, board,
5976 and JTAG adapter must all support adaptive JTAG clocking.
5977 Also, it can't work until an interrupt is issued.
5979 A more complete workaround is to not use that operation while you
5980 work with a JTAG debugger.
5981 Tasking environments generaly have idle loops where the body is the
5982 @emph{wait for interrupt} operation.
5983 (On older cores, it is a coprocessor action;
5984 newer cores have a @option{wfi} instruction.)
5985 Such loops can just remove that operation, at the cost of higher
5986 power consumption (because the CPU is needlessly clocked).
5991 @deffn Command resume [address]
5992 Resume the target at its current code position,
5993 or the optional @var{address} if it is provided.
5994 OpenOCD will wait 5 seconds for the target to resume.
5997 @deffn Command step [address]
5998 Single-step the target at its current code position,
5999 or the optional @var{address} if it is provided.
6002 @anchor{Reset Command}
6003 @deffn Command reset
6004 @deffnx Command {reset run}
6005 @deffnx Command {reset halt}
6006 @deffnx Command {reset init}
6007 Perform as hard a reset as possible, using SRST if possible.
6008 @emph{All defined targets will be reset, and target
6009 events will fire during the reset sequence.}
6011 The optional parameter specifies what should
6012 happen after the reset.
6013 If there is no parameter, a @command{reset run} is executed.
6014 The other options will not work on all systems.
6015 @xref{Reset Configuration}.
6018 @item @b{run} Let the target run
6019 @item @b{halt} Immediately halt the target
6020 @item @b{init} Immediately halt the target, and execute the reset-init script
6024 @deffn Command soft_reset_halt
6025 Requesting target halt and executing a soft reset. This is often used
6026 when a target cannot be reset and halted. The target, after reset is
6027 released begins to execute code. OpenOCD attempts to stop the CPU and
6028 then sets the program counter back to the reset vector. Unfortunately
6029 the code that was executed may have left the hardware in an unknown
6033 @section I/O Utilities
6035 These commands are available when
6036 OpenOCD is built with @option{--enable-ioutil}.
6037 They are mainly useful on embedded targets,
6039 Hosts with operating systems have complementary tools.
6041 @emph{Note:} there are several more such commands.
6043 @deffn Command append_file filename [string]*
6044 Appends the @var{string} parameters to
6045 the text file @file{filename}.
6046 Each string except the last one is followed by one space.
6047 The last string is followed by a newline.
6050 @deffn Command cat filename
6051 Reads and displays the text file @file{filename}.
6054 @deffn Command cp src_filename dest_filename
6055 Copies contents from the file @file{src_filename}
6056 into @file{dest_filename}.
6060 @emph{No description provided.}
6064 @emph{No description provided.}
6068 @emph{No description provided.}
6071 @deffn Command meminfo
6072 Display available RAM memory on OpenOCD host.
6073 Used in OpenOCD regression testing scripts.
6077 @emph{No description provided.}
6081 @emph{No description provided.}
6084 @deffn Command rm filename
6085 @c "rm" has both normal and Jim-level versions??
6086 Unlinks the file @file{filename}.
6089 @deffn Command trunc filename
6090 Removes all data in the file @file{filename}.
6093 @anchor{Memory access}
6094 @section Memory access commands
6095 @cindex memory access
6097 These commands allow accesses of a specific size to the memory
6098 system. Often these are used to configure the current target in some
6099 special way. For example - one may need to write certain values to the
6100 SDRAM controller to enable SDRAM.
6103 @item Use the @command{targets} (plural) command
6104 to change the current target.
6105 @item In system level scripts these commands are deprecated.
6106 Please use their TARGET object siblings to avoid making assumptions
6107 about what TAP is the current target, or about MMU configuration.
6110 @deffn Command mdw [phys] addr [count]
6111 @deffnx Command mdh [phys] addr [count]
6112 @deffnx Command mdb [phys] addr [count]
6113 Display contents of address @var{addr}, as
6114 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
6115 or 8-bit bytes (@command{mdb}).
6116 When the current target has an MMU which is present and active,
6117 @var{addr} is interpreted as a virtual address.
6118 Otherwise, or if the optional @var{phys} flag is specified,
6119 @var{addr} is interpreted as a physical address.
6120 If @var{count} is specified, displays that many units.
6121 (If you want to manipulate the data instead of displaying it,
6122 see the @code{mem2array} primitives.)
6125 @deffn Command mww [phys] addr word
6126 @deffnx Command mwh [phys] addr halfword
6127 @deffnx Command mwb [phys] addr byte
6128 Writes the specified @var{word} (32 bits),
6129 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
6130 at the specified address @var{addr}.
6131 When the current target has an MMU which is present and active,
6132 @var{addr} is interpreted as a virtual address.
6133 Otherwise, or if the optional @var{phys} flag is specified,
6134 @var{addr} is interpreted as a physical address.
6138 @anchor{Image access}
6139 @section Image loading commands
6140 @cindex image loading
6141 @cindex image dumping
6144 @deffn Command {dump_image} filename address size
6145 Dump @var{size} bytes of target memory starting at @var{address} to the
6146 binary file named @var{filename}.
6149 @deffn Command {fast_load}
6150 Loads an image stored in memory by @command{fast_load_image} to the
6151 current target. Must be preceeded by fast_load_image.
6154 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
6155 Normally you should be using @command{load_image} or GDB load. However, for
6156 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
6157 host), storing the image in memory and uploading the image to the target
6158 can be a way to upload e.g. multiple debug sessions when the binary does not change.
6159 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
6160 memory, i.e. does not affect target. This approach is also useful when profiling
6161 target programming performance as I/O and target programming can easily be profiled
6166 @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
6167 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
6168 The file format may optionally be specified
6169 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
6170 In addition the following arguments may be specifed:
6171 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
6172 @var{max_length} - maximum number of bytes to load.
6174 proc load_image_bin @{fname foffset address length @} @{
6175 # Load data from fname filename at foffset offset to
6176 # target at address. Load at most length bytes.
6177 load_image $fname [expr $address - $foffset] bin $address $length
6182 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
6183 Displays image section sizes and addresses
6184 as if @var{filename} were loaded into target memory
6185 starting at @var{address} (defaults to zero).
6186 The file format may optionally be specified
6187 (@option{bin}, @option{ihex}, or @option{elf})
6190 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
6191 Verify @var{filename} against target memory starting at @var{address}.
6192 The file format may optionally be specified
6193 (@option{bin}, @option{ihex}, or @option{elf})
6194 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
6198 @section Breakpoint and Watchpoint commands
6202 CPUs often make debug modules accessible through JTAG, with
6203 hardware support for a handful of code breakpoints and data
6205 In addition, CPUs almost always support software breakpoints.
6207 @deffn Command {bp} [address len [@option{hw}]]
6208 With no parameters, lists all active breakpoints.
6209 Else sets a breakpoint on code execution starting
6210 at @var{address} for @var{length} bytes.
6211 This is a software breakpoint, unless @option{hw} is specified
6212 in which case it will be a hardware breakpoint.
6214 (@xref{arm9 vector_catch}, or @pxref{xscale vector_catch},
6215 for similar mechanisms that do not consume hardware breakpoints.)
6218 @deffn Command {rbp} address
6219 Remove the breakpoint at @var{address}.
6222 @deffn Command {rwp} address
6223 Remove data watchpoint on @var{address}
6226 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
6227 With no parameters, lists all active watchpoints.
6228 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
6229 The watch point is an "access" watchpoint unless
6230 the @option{r} or @option{w} parameter is provided,
6231 defining it as respectively a read or write watchpoint.
6232 If a @var{value} is provided, that value is used when determining if
6233 the watchpoint should trigger. The value may be first be masked
6234 using @var{mask} to mark ``don't care'' fields.
6237 @section Misc Commands
6240 @deffn Command {profile} seconds filename
6241 Profiling samples the CPU's program counter as quickly as possible,
6242 which is useful for non-intrusive stochastic profiling.
6243 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
6246 @deffn Command {version}
6247 Displays a string identifying the version of this OpenOCD server.
6250 @deffn Command {virt2phys} virtual_address
6251 Requests the current target to map the specified @var{virtual_address}
6252 to its corresponding physical address, and displays the result.
6255 @node Architecture and Core Commands
6256 @chapter Architecture and Core Commands
6257 @cindex Architecture Specific Commands
6258 @cindex Core Specific Commands
6260 Most CPUs have specialized JTAG operations to support debugging.
6261 OpenOCD packages most such operations in its standard command framework.
6262 Some of those operations don't fit well in that framework, so they are
6263 exposed here as architecture or implementation (core) specific commands.
6265 @anchor{ARM Hardware Tracing}
6266 @section ARM Hardware Tracing
6271 CPUs based on ARM cores may include standard tracing interfaces,
6272 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
6273 address and data bus trace records to a ``Trace Port''.
6277 Development-oriented boards will sometimes provide a high speed
6278 trace connector for collecting that data, when the particular CPU
6279 supports such an interface.
6280 (The standard connector is a 38-pin Mictor, with both JTAG
6281 and trace port support.)
6282 Those trace connectors are supported by higher end JTAG adapters
6283 and some logic analyzer modules; frequently those modules can
6284 buffer several megabytes of trace data.
6285 Configuring an ETM coupled to such an external trace port belongs
6286 in the board-specific configuration file.
6288 If the CPU doesn't provide an external interface, it probably
6289 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
6290 dedicated SRAM. 4KBytes is one common ETB size.
6291 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
6292 (target) configuration file, since it works the same on all boards.
6295 ETM support in OpenOCD doesn't seem to be widely used yet.
6298 ETM support may be buggy, and at least some @command{etm config}
6299 parameters should be detected by asking the ETM for them.
6301 ETM trigger events could also implement a kind of complex
6302 hardware breakpoint, much more powerful than the simple
6303 watchpoint hardware exported by EmbeddedICE modules.
6304 @emph{Such breakpoints can be triggered even when using the
6305 dummy trace port driver}.
6307 It seems like a GDB hookup should be possible,
6308 as well as tracing only during specific states
6309 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
6311 There should be GUI tools to manipulate saved trace data and help
6312 analyse it in conjunction with the source code.
6313 It's unclear how much of a common interface is shared
6314 with the current XScale trace support, or should be
6315 shared with eventual Nexus-style trace module support.
6317 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
6318 for ETM modules is available. The code should be able to
6319 work with some newer cores; but not all of them support
6320 this original style of JTAG access.
6323 @subsection ETM Configuration
6324 ETM setup is coupled with the trace port driver configuration.
6326 @deffn {Config Command} {etm config} target width mode clocking driver
6327 Declares the ETM associated with @var{target}, and associates it
6328 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
6330 Several of the parameters must reflect the trace port capabilities,
6331 which are a function of silicon capabilties (exposed later
6332 using @command{etm info}) and of what hardware is connected to
6333 that port (such as an external pod, or ETB).
6334 The @var{width} must be either 4, 8, or 16,
6335 except with ETMv3.0 and newer modules which may also
6336 support 1, 2, 24, 32, 48, and 64 bit widths.
6337 (With those versions, @command{etm info} also shows whether
6338 the selected port width and mode are supported.)
6340 The @var{mode} must be @option{normal}, @option{multiplexed},
6341 or @option{demultiplexed}.
6342 The @var{clocking} must be @option{half} or @option{full}.
6345 With ETMv3.0 and newer, the bits set with the @var{mode} and
6346 @var{clocking} parameters both control the mode.
6347 This modified mode does not map to the values supported by
6348 previous ETM modules, so this syntax is subject to change.
6352 You can see the ETM registers using the @command{reg} command.
6353 Not all possible registers are present in every ETM.
6354 Most of the registers are write-only, and are used to configure
6355 what CPU activities are traced.
6359 @deffn Command {etm info}
6360 Displays information about the current target's ETM.
6361 This includes resource counts from the @code{ETM_CONFIG} register,
6362 as well as silicon capabilities (except on rather old modules).
6363 from the @code{ETM_SYS_CONFIG} register.
6366 @deffn Command {etm status}
6367 Displays status of the current target's ETM and trace port driver:
6368 is the ETM idle, or is it collecting data?
6369 Did trace data overflow?
6373 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
6374 Displays what data that ETM will collect.
6375 If arguments are provided, first configures that data.
6376 When the configuration changes, tracing is stopped
6377 and any buffered trace data is invalidated.
6380 @item @var{type} ... describing how data accesses are traced,
6381 when they pass any ViewData filtering that that was set up.
6383 @option{none} (save nothing),
6384 @option{data} (save data),
6385 @option{address} (save addresses),
6386 @option{all} (save data and addresses)
6387 @item @var{context_id_bits} ... 0, 8, 16, or 32
6388 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
6389 cycle-accurate instruction tracing.
6390 Before ETMv3, enabling this causes much extra data to be recorded.
6391 @item @var{branch_output} ... @option{enable} or @option{disable}.
6392 Disable this unless you need to try reconstructing the instruction
6393 trace stream without an image of the code.
6397 @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
6398 Displays whether ETM triggering debug entry (like a breakpoint) is
6399 enabled or disabled, after optionally modifying that configuration.
6400 The default behaviour is @option{disable}.
6401 Any change takes effect after the next @command{etm start}.
6403 By using script commands to configure ETM registers, you can make the
6404 processor enter debug state automatically when certain conditions,
6405 more complex than supported by the breakpoint hardware, happen.
6408 @subsection ETM Trace Operation
6410 After setting up the ETM, you can use it to collect data.
6411 That data can be exported to files for later analysis.
6412 It can also be parsed with OpenOCD, for basic sanity checking.
6414 To configure what is being traced, you will need to write
6415 various trace registers using @command{reg ETM_*} commands.
6416 For the definitions of these registers, read ARM publication
6417 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
6418 Be aware that most of the relevant registers are write-only,
6419 and that ETM resources are limited. There are only a handful
6420 of address comparators, data comparators, counters, and so on.
6422 Examples of scenarios you might arrange to trace include:
6425 @item Code flow within a function, @emph{excluding} subroutines
6426 it calls. Use address range comparators to enable tracing
6427 for instruction access within that function's body.
6428 @item Code flow within a function, @emph{including} subroutines
6429 it calls. Use the sequencer and address comparators to activate
6430 tracing on an ``entered function'' state, then deactivate it by
6431 exiting that state when the function's exit code is invoked.
6432 @item Code flow starting at the fifth invocation of a function,
6433 combining one of the above models with a counter.
6434 @item CPU data accesses to the registers for a particular device,
6435 using address range comparators and the ViewData logic.
6436 @item Such data accesses only during IRQ handling, combining the above
6437 model with sequencer triggers which on entry and exit to the IRQ handler.
6438 @item @emph{... more}
6441 At this writing, September 2009, there are no Tcl utility
6442 procedures to help set up any common tracing scenarios.
6444 @deffn Command {etm analyze}
6445 Reads trace data into memory, if it wasn't already present.
6446 Decodes and prints the data that was collected.
6449 @deffn Command {etm dump} filename
6450 Stores the captured trace data in @file{filename}.
6453 @deffn Command {etm image} filename [base_address] [type]
6454 Opens an image file.
6457 @deffn Command {etm load} filename
6458 Loads captured trace data from @file{filename}.
6461 @deffn Command {etm start}
6462 Starts trace data collection.
6465 @deffn Command {etm stop}
6466 Stops trace data collection.
6469 @anchor{Trace Port Drivers}
6470 @subsection Trace Port Drivers
6472 To use an ETM trace port it must be associated with a driver.
6474 @deffn {Trace Port Driver} dummy
6475 Use the @option{dummy} driver if you are configuring an ETM that's
6476 not connected to anything (on-chip ETB or off-chip trace connector).
6477 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
6478 any trace data collection.}
6479 @deffn {Config Command} {etm_dummy config} target
6480 Associates the ETM for @var{target} with a dummy driver.
6484 @deffn {Trace Port Driver} etb
6485 Use the @option{etb} driver if you are configuring an ETM
6486 to use on-chip ETB memory.
6487 @deffn {Config Command} {etb config} target etb_tap
6488 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
6489 You can see the ETB registers using the @command{reg} command.
6491 @deffn Command {etb trigger_percent} [percent]
6492 This displays, or optionally changes, ETB behavior after the
6493 ETM's configured @emph{trigger} event fires.
6494 It controls how much more trace data is saved after the (single)
6495 trace trigger becomes active.
6498 @item The default corresponds to @emph{trace around} usage,
6499 recording 50 percent data before the event and the rest
6501 @item The minimum value of @var{percent} is 2 percent,
6502 recording almost exclusively data before the trigger.
6503 Such extreme @emph{trace before} usage can help figure out
6504 what caused that event to happen.
6505 @item The maximum value of @var{percent} is 100 percent,
6506 recording data almost exclusively after the event.
6507 This extreme @emph{trace after} usage might help sort out
6508 how the event caused trouble.
6510 @c REVISIT allow "break" too -- enter debug mode.
6515 @deffn {Trace Port Driver} oocd_trace
6516 This driver isn't available unless OpenOCD was explicitly configured
6517 with the @option{--enable-oocd_trace} option. You probably don't want
6518 to configure it unless you've built the appropriate prototype hardware;
6519 it's @emph{proof-of-concept} software.
6521 Use the @option{oocd_trace} driver if you are configuring an ETM that's
6522 connected to an off-chip trace connector.
6524 @deffn {Config Command} {oocd_trace config} target tty
6525 Associates the ETM for @var{target} with a trace driver which
6526 collects data through the serial port @var{tty}.
6529 @deffn Command {oocd_trace resync}
6530 Re-synchronizes with the capture clock.
6533 @deffn Command {oocd_trace status}
6534 Reports whether the capture clock is locked or not.
6539 @section Generic ARM
6542 These commands should be available on all ARM processors.
6543 They are available in addition to other core-specific
6544 commands that may be available.
6546 @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
6547 Displays the core_state, optionally changing it to process
6548 either @option{arm} or @option{thumb} instructions.
6549 The target may later be resumed in the currently set core_state.
6550 (Processors may also support the Jazelle state, but
6551 that is not currently supported in OpenOCD.)
6554 @deffn Command {arm disassemble} address [count [@option{thumb}]]
6556 Disassembles @var{count} instructions starting at @var{address}.
6557 If @var{count} is not specified, a single instruction is disassembled.
6558 If @option{thumb} is specified, or the low bit of the address is set,
6559 Thumb2 (mixed 16/32-bit) instructions are used;
6560 else ARM (32-bit) instructions are used.
6561 (Processors may also support the Jazelle state, but
6562 those instructions are not currently understood by OpenOCD.)
6564 Note that all Thumb instructions are Thumb2 instructions,
6565 so older processors (without Thumb2 support) will still
6566 see correct disassembly of Thumb code.
6567 Also, ThumbEE opcodes are the same as Thumb2,
6568 with a handful of exceptions.
6569 ThumbEE disassembly currently has no explicit support.
6572 @deffn Command {arm mcr} pX op1 CRn CRm op2 value
6573 Write @var{value} to a coprocessor @var{pX} register
6574 passing parameters @var{CRn},
6575 @var{CRm}, opcodes @var{opc1} and @var{opc2},
6576 and using the MCR instruction.
6577 (Parameter sequence matches the ARM instruction, but omits
6581 @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
6582 Read a coprocessor @var{pX} register passing parameters @var{CRn},
6583 @var{CRm}, opcodes @var{opc1} and @var{opc2},
6584 and the MRC instruction.
6585 Returns the result so it can be manipulated by Jim scripts.
6586 (Parameter sequence matches the ARM instruction, but omits
6590 @deffn Command {arm reg}
6591 Display a table of all banked core registers, fetching the current value from every
6592 core mode if necessary.
6595 @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
6596 @cindex ARM semihosting
6597 Display status of semihosting, after optionally changing that status.
6599 Semihosting allows for code executing on an ARM target to use the
6600 I/O facilities on the host computer i.e. the system where OpenOCD
6601 is running. The target application must be linked against a library
6602 implementing the ARM semihosting convention that forwards operation
6603 requests by using a special SVC instruction that is trapped at the
6604 Supervisor Call vector by OpenOCD.
6607 @section ARMv4 and ARMv5 Architecture
6611 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
6612 and introduced core parts of the instruction set in use today.
6613 That includes the Thumb instruction set, introduced in the ARMv4T
6616 @subsection ARM7 and ARM9 specific commands
6620 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
6621 ARM9TDMI, ARM920T or ARM926EJ-S.
6622 They are available in addition to the ARM commands,
6623 and any other core-specific commands that may be available.
6625 @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
6626 Displays the value of the flag controlling use of the
6627 the EmbeddedIce DBGRQ signal to force entry into debug mode,
6628 instead of breakpoints.
6629 If a boolean parameter is provided, first assigns that flag.
6632 safe for all but ARM7TDMI-S cores (like NXP LPC).
6633 This feature is enabled by default on most ARM9 cores,
6634 including ARM9TDMI, ARM920T, and ARM926EJ-S.
6637 @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
6639 Displays the value of the flag controlling use of the debug communications
6640 channel (DCC) to write larger (>128 byte) amounts of memory.
6641 If a boolean parameter is provided, first assigns that flag.
6643 DCC downloads offer a huge speed increase, but might be
6644 unsafe, especially with targets running at very low speeds. This command was introduced
6645 with OpenOCD rev. 60, and requires a few bytes of working area.
6648 @anchor{arm7_9 fast_memory_access}
6649 @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
6650 Displays the value of the flag controlling use of memory writes and reads
6651 that don't check completion of the operation.
6652 If a boolean parameter is provided, first assigns that flag.
6654 This provides a huge speed increase, especially with USB JTAG
6655 cables (FT2232), but might be unsafe if used with targets running at very low
6656 speeds, like the 32kHz startup clock of an AT91RM9200.
6659 @subsection ARM720T specific commands
6662 These commands are available to ARM720T based CPUs,
6663 which are implementations of the ARMv4T architecture
6664 based on the ARM7TDMI-S integer core.
6665 They are available in addition to the ARM and ARM7/ARM9 commands.
6667 @deffn Command {arm720t cp15} opcode [value]
6668 @emph{DEPRECATED -- avoid using this.
6669 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
6671 Display cp15 register returned by the ARM instruction @var{opcode};
6672 else if a @var{value} is provided, that value is written to that register.
6673 The @var{opcode} should be the value of either an MRC or MCR instruction.
6676 @subsection ARM9 specific commands
6679 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
6681 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
6683 @c 9-june-2009: tried this on arm920t, it didn't work.
6684 @c no-params always lists nothing caught, and that's how it acts.
6685 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
6686 @c versions have different rules about when they commit writes.
6688 @anchor{arm9 vector_catch}
6689 @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
6690 @cindex vector_catch
6691 Vector Catch hardware provides a sort of dedicated breakpoint
6692 for hardware events such as reset, interrupt, and abort.
6693 You can use this to conserve normal breakpoint resources,
6694 so long as you're not concerned with code that branches directly
6695 to those hardware vectors.
6697 This always finishes by listing the current configuration.
6698 If parameters are provided, it first reconfigures the
6699 vector catch hardware to intercept
6700 @option{all} of the hardware vectors,
6701 @option{none} of them,
6702 or a list with one or more of the following:
6703 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
6704 @option{irq} @option{fiq}.
6707 @subsection ARM920T specific commands
6710 These commands are available to ARM920T based CPUs,
6711 which are implementations of the ARMv4T architecture
6712 built using the ARM9TDMI integer core.
6713 They are available in addition to the ARM, ARM7/ARM9,
6716 @deffn Command {arm920t cache_info}
6717 Print information about the caches found. This allows to see whether your target
6718 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
6721 @deffn Command {arm920t cp15} regnum [value]
6722 Display cp15 register @var{regnum};
6723 else if a @var{value} is provided, that value is written to that register.
6724 This uses "physical access" and the register number is as
6725 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
6726 (Not all registers can be written.)
6729 @deffn Command {arm920t cp15i} opcode [value [address]]
6730 @emph{DEPRECATED -- avoid using this.
6731 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
6733 Interpreted access using ARM instruction @var{opcode}, which should
6734 be the value of either an MRC or MCR instruction
6735 (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
6736 If no @var{value} is provided, the result is displayed.
6737 Else if that value is written using the specified @var{address},
6738 or using zero if no other address is provided.
6741 @deffn Command {arm920t read_cache} filename
6742 Dump the content of ICache and DCache to a file named @file{filename}.
6745 @deffn Command {arm920t read_mmu} filename
6746 Dump the content of the ITLB and DTLB to a file named @file{filename}.
6749 @subsection ARM926ej-s specific commands
6752 These commands are available to ARM926ej-s based CPUs,
6753 which are implementations of the ARMv5TEJ architecture
6754 based on the ARM9EJ-S integer core.
6755 They are available in addition to the ARM, ARM7/ARM9,
6758 The Feroceon cores also support these commands, although
6759 they are not built from ARM926ej-s designs.
6761 @deffn Command {arm926ejs cache_info}
6762 Print information about the caches found.
6765 @subsection ARM966E specific commands
6768 These commands are available to ARM966 based CPUs,
6769 which are implementations of the ARMv5TE architecture.
6770 They are available in addition to the ARM, ARM7/ARM9,
6773 @deffn Command {arm966e cp15} regnum [value]
6774 Display cp15 register @var{regnum};
6775 else if a @var{value} is provided, that value is written to that register.
6776 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
6778 There is no current control over bits 31..30 from that table,
6779 as required for BIST support.
6782 @subsection XScale specific commands
6785 Some notes about the debug implementation on the XScale CPUs:
6787 The XScale CPU provides a special debug-only mini-instruction cache
6788 (mini-IC) in which exception vectors and target-resident debug handler
6789 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
6790 must point vector 0 (the reset vector) to the entry of the debug
6791 handler. However, this means that the complete first cacheline in the
6792 mini-IC is marked valid, which makes the CPU fetch all exception
6793 handlers from the mini-IC, ignoring the code in RAM.
6795 To address this situation, OpenOCD provides the @code{xscale
6796 vector_table} command, which allows the user to explicity write
6797 individual entries to either the high or low vector table stored in
6800 It is recommended to place a pc-relative indirect branch in the vector
6801 table, and put the branch destination somewhere in memory. Doing so
6802 makes sure the code in the vector table stays constant regardless of
6803 code layout in memory:
6806 ldr pc,[pc,#0x100-8]
6807 ldr pc,[pc,#0x100-8]
6808 ldr pc,[pc,#0x100-8]
6809 ldr pc,[pc,#0x100-8]
6810 ldr pc,[pc,#0x100-8]
6811 ldr pc,[pc,#0x100-8]
6812 ldr pc,[pc,#0x100-8]
6813 ldr pc,[pc,#0x100-8]
6815 .long real_reset_vector
6816 .long real_ui_handler
6817 .long real_swi_handler
6819 .long real_data_abort
6820 .long 0 /* unused */
6821 .long real_irq_handler
6822 .long real_fiq_handler
6825 Alternatively, you may choose to keep some or all of the mini-IC
6826 vector table entries synced with those written to memory by your
6827 system software. The mini-IC can not be modified while the processor
6828 is executing, but for each vector table entry not previously defined
6829 using the @code{xscale vector_table} command, OpenOCD will copy the
6830 value from memory to the mini-IC every time execution resumes from a
6831 halt. This is done for both high and low vector tables (although the
6832 table not in use may not be mapped to valid memory, and in this case
6833 that copy operation will silently fail). This means that you will
6834 need to briefly halt execution at some strategic point during system
6835 start-up; e.g., after the software has initialized the vector table,
6836 but before exceptions are enabled. A breakpoint can be used to
6837 accomplish this once the appropriate location in the start-up code has
6838 been identified. A watchpoint over the vector table region is helpful
6839 in finding the location if you're not sure. Note that the same
6840 situation exists any time the vector table is modified by the system
6843 The debug handler must be placed somewhere in the address space using
6844 the @code{xscale debug_handler} command. The allowed locations for the
6845 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
6846 0xfffff800). The default value is 0xfe000800.
6848 XScale has resources to support two hardware breakpoints and two
6849 watchpoints. However, the following restrictions on watchpoint
6850 functionality apply: (1) the value and mask arguments to the @code{wp}
6851 command are not supported, (2) the watchpoint length must be a
6852 power of two and not less than four, and can not be greater than the
6853 watchpoint address, and (3) a watchpoint with a length greater than
6854 four consumes all the watchpoint hardware resources. This means that
6855 at any one time, you can have enabled either two watchpoints with a
6856 length of four, or one watchpoint with a length greater than four.
6858 These commands are available to XScale based CPUs,
6859 which are implementations of the ARMv5TE architecture.
6861 @deffn Command {xscale analyze_trace}
6862 Displays the contents of the trace buffer.
6865 @deffn Command {xscale cache_clean_address} address
6866 Changes the address used when cleaning the data cache.
6869 @deffn Command {xscale cache_info}
6870 Displays information about the CPU caches.
6873 @deffn Command {xscale cp15} regnum [value]
6874 Display cp15 register @var{regnum};
6875 else if a @var{value} is provided, that value is written to that register.
6878 @deffn Command {xscale debug_handler} target address
6879 Changes the address used for the specified target's debug handler.
6882 @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
6883 Enables or disable the CPU's data cache.
6886 @deffn Command {xscale dump_trace} filename
6887 Dumps the raw contents of the trace buffer to @file{filename}.
6890 @deffn Command {xscale icache} [@option{enable}|@option{disable}]
6891 Enables or disable the CPU's instruction cache.
6894 @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
6895 Enables or disable the CPU's memory management unit.
6898 @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
6899 Displays the trace buffer status, after optionally
6900 enabling or disabling the trace buffer
6901 and modifying how it is emptied.
6904 @deffn Command {xscale trace_image} filename [offset [type]]
6905 Opens a trace image from @file{filename}, optionally rebasing
6906 its segment addresses by @var{offset}.
6907 The image @var{type} may be one of
6908 @option{bin} (binary), @option{ihex} (Intel hex),
6909 @option{elf} (ELF file), @option{s19} (Motorola s19),
6910 @option{mem}, or @option{builder}.
6913 @anchor{xscale vector_catch}
6914 @deffn Command {xscale vector_catch} [mask]
6915 @cindex vector_catch
6916 Display a bitmask showing the hardware vectors to catch.
6917 If the optional parameter is provided, first set the bitmask to that value.
6919 The mask bits correspond with bit 16..23 in the DCSR:
6922 0x02 Trap Undefined Instructions
6923 0x04 Trap Software Interrupt
6924 0x08 Trap Prefetch Abort
6925 0x10 Trap Data Abort
6932 @anchor{xscale vector_table}
6933 @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
6934 @cindex vector_table
6936 Set an entry in the mini-IC vector table. There are two tables: one for
6937 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
6938 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
6939 points to the debug handler entry and can not be overwritten.
6940 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
6942 Without arguments, the current settings are displayed.
6946 @section ARMv6 Architecture
6949 @subsection ARM11 specific commands
6952 @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
6953 Displays the value of the memwrite burst-enable flag,
6954 which is enabled by default.
6955 If a boolean parameter is provided, first assigns that flag.
6956 Burst writes are only used for memory writes larger than 1 word.
6957 They improve performance by assuming that the CPU has read each data
6958 word over JTAG and completed its write before the next word arrives,
6959 instead of polling for a status flag to verify that completion.
6960 This is usually safe, because JTAG runs much slower than the CPU.
6963 @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
6964 Displays the value of the memwrite error_fatal flag,
6965 which is enabled by default.
6966 If a boolean parameter is provided, first assigns that flag.
6967 When set, certain memory write errors cause earlier transfer termination.
6970 @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
6971 Displays the value of the flag controlling whether
6972 IRQs are enabled during single stepping;
6973 they are disabled by default.
6974 If a boolean parameter is provided, first assigns that.
6977 @deffn Command {arm11 vcr} [value]
6978 @cindex vector_catch
6979 Displays the value of the @emph{Vector Catch Register (VCR)},
6980 coprocessor 14 register 7.
6981 If @var{value} is defined, first assigns that.
6983 Vector Catch hardware provides dedicated breakpoints
6984 for certain hardware events.
6985 The specific bit values are core-specific (as in fact is using
6986 coprocessor 14 register 7 itself) but all current ARM11
6987 cores @emph{except the ARM1176} use the same six bits.
6990 @section ARMv7 Architecture
6993 @subsection ARMv7 Debug Access Port (DAP) specific commands
6994 @cindex Debug Access Port
6996 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
6997 included on Cortex-M3 and Cortex-A8 systems.
6998 They are available in addition to other core-specific commands that may be available.
7000 @deffn Command {dap apid} [num]
7001 Displays ID register from AP @var{num},
7002 defaulting to the currently selected AP.
7005 @deffn Command {dap apsel} [num]
7006 Select AP @var{num}, defaulting to 0.
7009 @deffn Command {dap baseaddr} [num]
7010 Displays debug base address from MEM-AP @var{num},
7011 defaulting to the currently selected AP.
7014 @deffn Command {dap info} [num]
7015 Displays the ROM table for MEM-AP @var{num},
7016 defaulting to the currently selected AP.
7019 @deffn Command {dap memaccess} [value]
7020 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
7021 memory bus access [0-255], giving additional time to respond to reads.
7022 If @var{value} is defined, first assigns that.
7025 @subsection Cortex-M3 specific commands
7028 @deffn Command {cortex_m3 maskisr} (@option{auto}|@option{on}|@option{off})
7029 Control masking (disabling) interrupts during target step/resume.
7031 The @option{auto} option handles interrupts during stepping a way they get
7032 served but don't disturb the program flow. The step command first allows
7033 pending interrupt handlers to execute, then disables interrupts and steps over
7034 the next instruction where the core was halted. After the step interrupts
7035 are enabled again. If the interrupt handlers don't complete within 500ms,
7036 the step command leaves with the core running.
7038 Note that a free breakpoint is required for the @option{auto} option. If no
7039 breakpoint is available at the time of the step, then the step is taken
7040 with interrupts enabled, i.e. the same way the @option{off} option does.
7042 Default is @option{auto}.
7045 @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
7046 @cindex vector_catch
7047 Vector Catch hardware provides dedicated breakpoints
7048 for certain hardware events.
7050 Parameters request interception of
7051 @option{all} of these hardware event vectors,
7052 @option{none} of them,
7053 or one or more of the following:
7054 @option{hard_err} for a HardFault exception;
7055 @option{mm_err} for a MemManage exception;
7056 @option{bus_err} for a BusFault exception;
7059 @option{chk_err}, or
7060 @option{nocp_err} for various UsageFault exceptions; or
7062 If NVIC setup code does not enable them,
7063 MemManage, BusFault, and UsageFault exceptions
7064 are mapped to HardFault.
7065 UsageFault checks for
7066 divide-by-zero and unaligned access
7067 must also be explicitly enabled.
7069 This finishes by listing the current vector catch configuration.
7072 @deffn Command {cortex_m3 reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
7073 Control reset handling. The default @option{srst} is to use srst if fitted,
7074 otherwise fallback to @option{vectreset}.
7076 @item @option{srst} use hardware srst if fitted otherwise fallback to @option{vectreset}.
7077 @item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
7078 @item @option{vectreset} use NVIC VECTRESET to reset system.
7080 Using @option{vectreset} is a safe option for all current Cortex-M3 cores.
7081 This however has the disadvantage of only resetting the core, all peripherals
7082 are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
7084 @xref{Target Events}.
7087 @anchor{Software Debug Messages and Tracing}
7088 @section Software Debug Messages and Tracing
7089 @cindex Linux-ARM DCC support
7093 OpenOCD can process certain requests from target software, when
7094 the target uses appropriate libraries.
7095 The most powerful mechanism is semihosting, but there is also
7096 a lighter weight mechanism using only the DCC channel.
7098 Currently @command{target_request debugmsgs}
7099 is supported only for @option{arm7_9} and @option{cortex_m3} cores.
7100 These messages are received as part of target polling, so
7101 you need to have @command{poll on} active to receive them.
7102 They are intrusive in that they will affect program execution
7103 times. If that is a problem, @pxref{ARM Hardware Tracing}.
7105 See @file{libdcc} in the contrib dir for more details.
7106 In addition to sending strings, characters, and
7107 arrays of various size integers from the target,
7108 @file{libdcc} also exports a software trace point mechanism.
7109 The target being debugged may
7110 issue trace messages which include a 24-bit @dfn{trace point} number.
7111 Trace point support includes two distinct mechanisms,
7112 each supported by a command:
7115 @item @emph{History} ... A circular buffer of trace points
7116 can be set up, and then displayed at any time.
7117 This tracks where code has been, which can be invaluable in
7118 finding out how some fault was triggered.
7120 The buffer may overflow, since it collects records continuously.
7121 It may be useful to use some of the 24 bits to represent a
7122 particular event, and other bits to hold data.
7124 @item @emph{Counting} ... An array of counters can be set up,
7125 and then displayed at any time.
7126 This can help establish code coverage and identify hot spots.
7128 The array of counters is directly indexed by the trace point
7129 number, so trace points with higher numbers are not counted.
7132 Linux-ARM kernels have a ``Kernel low-level debugging
7133 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
7134 depends on CONFIG_DEBUG_LL) which uses this mechanism to
7135 deliver messages before a serial console can be activated.
7136 This is not the same format used by @file{libdcc}.
7137 Other software, such as the U-Boot boot loader, sometimes
7138 does the same thing.
7140 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
7141 Displays current handling of target DCC message requests.
7142 These messages may be sent to the debugger while the target is running.
7143 The optional @option{enable} and @option{charmsg} parameters
7144 both enable the messages, while @option{disable} disables them.
7146 With @option{charmsg} the DCC words each contain one character,
7147 as used by Linux with CONFIG_DEBUG_ICEDCC;
7148 otherwise the libdcc format is used.
7151 @deffn Command {trace history} [@option{clear}|count]
7152 With no parameter, displays all the trace points that have triggered
7153 in the order they triggered.
7154 With the parameter @option{clear}, erases all current trace history records.
7155 With a @var{count} parameter, allocates space for that many
7159 @deffn Command {trace point} [@option{clear}|identifier]
7160 With no parameter, displays all trace point identifiers and how many times
7161 they have been triggered.
7162 With the parameter @option{clear}, erases all current trace point counters.
7163 With a numeric @var{identifier} parameter, creates a new a trace point counter
7164 and associates it with that identifier.
7166 @emph{Important:} The identifier and the trace point number
7167 are not related except by this command.
7168 These trace point numbers always start at zero (from server startup,
7169 or after @command{trace point clear}) and count up from there.
7174 @chapter JTAG Commands
7175 @cindex JTAG Commands
7176 Most general purpose JTAG commands have been presented earlier.
7177 (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
7178 Lower level JTAG commands, as presented here,
7179 may be needed to work with targets which require special
7180 attention during operations such as reset or initialization.
7182 To use these commands you will need to understand some
7183 of the basics of JTAG, including:
7186 @item A JTAG scan chain consists of a sequence of individual TAP
7187 devices such as a CPUs.
7188 @item Control operations involve moving each TAP through the same
7189 standard state machine (in parallel)
7190 using their shared TMS and clock signals.
7191 @item Data transfer involves shifting data through the chain of
7192 instruction or data registers of each TAP, writing new register values
7193 while the reading previous ones.
7194 @item Data register sizes are a function of the instruction active in
7195 a given TAP, while instruction register sizes are fixed for each TAP.
7196 All TAPs support a BYPASS instruction with a single bit data register.
7197 @item The way OpenOCD differentiates between TAP devices is by
7198 shifting different instructions into (and out of) their instruction
7202 @section Low Level JTAG Commands
7204 These commands are used by developers who need to access
7205 JTAG instruction or data registers, possibly controlling
7206 the order of TAP state transitions.
7207 If you're not debugging OpenOCD internals, or bringing up a
7208 new JTAG adapter or a new type of TAP device (like a CPU or
7209 JTAG router), you probably won't need to use these commands.
7210 In a debug session that doesn't use JTAG for its transport protocol,
7211 these commands are not available.
7213 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
7214 Loads the data register of @var{tap} with a series of bit fields
7215 that specify the entire register.
7216 Each field is @var{numbits} bits long with
7217 a numeric @var{value} (hexadecimal encouraged).
7218 The return value holds the original value of each
7221 For example, a 38 bit number might be specified as one
7222 field of 32 bits then one of 6 bits.
7223 @emph{For portability, never pass fields which are more
7224 than 32 bits long. Many OpenOCD implementations do not
7225 support 64-bit (or larger) integer values.}
7227 All TAPs other than @var{tap} must be in BYPASS mode.
7228 The single bit in their data registers does not matter.
7230 When @var{tap_state} is specified, the JTAG state machine is left
7232 For example @sc{drpause} might be specified, so that more
7233 instructions can be issued before re-entering the @sc{run/idle} state.
7234 If the end state is not specified, the @sc{run/idle} state is entered.
7237 OpenOCD does not record information about data register lengths,
7238 so @emph{it is important that you get the bit field lengths right}.
7239 Remember that different JTAG instructions refer to different
7240 data registers, which may have different lengths.
7241 Moreover, those lengths may not be fixed;
7242 the SCAN_N instruction can change the length of
7243 the register accessed by the INTEST instruction
7244 (by connecting a different scan chain).
7248 @deffn Command {flush_count}
7249 Returns the number of times the JTAG queue has been flushed.
7250 This may be used for performance tuning.
7252 For example, flushing a queue over USB involves a
7253 minimum latency, often several milliseconds, which does
7254 not change with the amount of data which is written.
7255 You may be able to identify performance problems by finding
7256 tasks which waste bandwidth by flushing small transfers too often,
7257 instead of batching them into larger operations.
7260 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
7261 For each @var{tap} listed, loads the instruction register
7262 with its associated numeric @var{instruction}.
7263 (The number of bits in that instruction may be displayed
7264 using the @command{scan_chain} command.)
7265 For other TAPs, a BYPASS instruction is loaded.
7267 When @var{tap_state} is specified, the JTAG state machine is left
7269 For example @sc{irpause} might be specified, so the data register
7270 can be loaded before re-entering the @sc{run/idle} state.
7271 If the end state is not specified, the @sc{run/idle} state is entered.
7274 OpenOCD currently supports only a single field for instruction
7275 register values, unlike data register values.
7276 For TAPs where the instruction register length is more than 32 bits,
7277 portable scripts currently must issue only BYPASS instructions.
7281 @deffn Command {jtag_reset} trst srst
7282 Set values of reset signals.
7283 The @var{trst} and @var{srst} parameter values may be
7284 @option{0}, indicating that reset is inactive (pulled or driven high),
7285 or @option{1}, indicating it is active (pulled or driven low).
7286 The @command{reset_config} command should already have been used
7287 to configure how the board and JTAG adapter treat these two
7288 signals, and to say if either signal is even present.
7289 @xref{Reset Configuration}.
7291 Note that TRST is specially handled.
7292 It actually signifies JTAG's @sc{reset} state.
7293 So if the board doesn't support the optional TRST signal,
7294 or it doesn't support it along with the specified SRST value,
7295 JTAG reset is triggered with TMS and TCK signals
7296 instead of the TRST signal.
7297 And no matter how that JTAG reset is triggered, once
7298 the scan chain enters @sc{reset} with TRST inactive,
7299 TAP @code{post-reset} events are delivered to all TAPs
7300 with handlers for that event.
7303 @deffn Command {pathmove} start_state [next_state ...]
7304 Start by moving to @var{start_state}, which
7305 must be one of the @emph{stable} states.
7306 Unless it is the only state given, this will often be the
7307 current state, so that no TCK transitions are needed.
7308 Then, in a series of single state transitions
7309 (conforming to the JTAG state machine) shift to
7310 each @var{next_state} in sequence, one per TCK cycle.
7311 The final state must also be stable.
7314 @deffn Command {runtest} @var{num_cycles}
7315 Move to the @sc{run/idle} state, and execute at least
7316 @var{num_cycles} of the JTAG clock (TCK).
7317 Instructions often need some time
7318 to execute before they take effect.
7321 @c tms_sequence (short|long)
7322 @c ... temporary, debug-only, other than USBprog bug workaround...
7324 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
7325 Verify values captured during @sc{ircapture} and returned
7326 during IR scans. Default is enabled, but this can be
7327 overridden by @command{verify_jtag}.
7328 This flag is ignored when validating JTAG chain configuration.
7331 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
7332 Enables verification of DR and IR scans, to help detect
7333 programming errors. For IR scans, @command{verify_ircapture}
7334 must also be enabled.
7338 @section TAP state names
7339 @cindex TAP state names
7341 The @var{tap_state} names used by OpenOCD in the @command{drscan},
7342 @command{irscan}, and @command{pathmove} commands are the same
7343 as those used in SVF boundary scan documents, except that
7344 SVF uses @sc{idle} instead of @sc{run/idle}.
7347 @item @b{RESET} ... @emph{stable} (with TMS high);
7348 acts as if TRST were pulsed
7349 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
7352 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
7353 through the data register
7355 @item @b{DRPAUSE} ... @emph{stable}; data register ready
7356 for update or more shifting
7361 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
7362 through the instruction register
7364 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
7365 for update or more shifting
7370 Note that only six of those states are fully ``stable'' in the
7371 face of TMS fixed (low except for @sc{reset})
7372 and a free-running JTAG clock. For all the
7373 others, the next TCK transition changes to a new state.
7376 @item From @sc{drshift} and @sc{irshift}, clock transitions will
7377 produce side effects by changing register contents. The values
7378 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
7379 may not be as expected.
7380 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
7381 choices after @command{drscan} or @command{irscan} commands,
7382 since they are free of JTAG side effects.
7383 @item @sc{run/idle} may have side effects that appear at non-JTAG
7384 levels, such as advancing the ARM9E-S instruction pipeline.
7385 Consult the documentation for the TAP(s) you are working with.
7388 @node Boundary Scan Commands
7389 @chapter Boundary Scan Commands
7391 One of the original purposes of JTAG was to support
7392 boundary scan based hardware testing.
7393 Although its primary focus is to support On-Chip Debugging,
7394 OpenOCD also includes some boundary scan commands.
7396 @section SVF: Serial Vector Format
7397 @cindex Serial Vector Format
7400 The Serial Vector Format, better known as @dfn{SVF}, is a
7401 way to represent JTAG test patterns in text files.
7402 In a debug session using JTAG for its transport protocol,
7403 OpenOCD supports running such test files.
7405 @deffn Command {svf} filename [@option{quiet}]
7406 This issues a JTAG reset (Test-Logic-Reset) and then
7407 runs the SVF script from @file{filename}.
7408 Unless the @option{quiet} option is specified,
7409 each command is logged before it is executed.
7412 @section XSVF: Xilinx Serial Vector Format
7413 @cindex Xilinx Serial Vector Format
7416 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
7417 binary representation of SVF which is optimized for use with
7419 In a debug session using JTAG for its transport protocol,
7420 OpenOCD supports running such test files.
7422 @quotation Important
7423 Not all XSVF commands are supported.
7426 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
7427 This issues a JTAG reset (Test-Logic-Reset) and then
7428 runs the XSVF script from @file{filename}.
7429 When a @var{tapname} is specified, the commands are directed at
7431 When @option{virt2} is specified, the @sc{xruntest} command counts
7432 are interpreted as TCK cycles instead of microseconds.
7433 Unless the @option{quiet} option is specified,
7434 messages are logged for comments and some retries.
7437 The OpenOCD sources also include two utility scripts
7438 for working with XSVF; they are not currently installed
7439 after building the software.
7440 You may find them useful:
7443 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
7444 syntax understood by the @command{xsvf} command; see notes below.
7445 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
7446 understands the OpenOCD extensions.
7449 The input format accepts a handful of non-standard extensions.
7450 These include three opcodes corresponding to SVF extensions
7451 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
7452 two opcodes supporting a more accurate translation of SVF
7453 (XTRST, XWAITSTATE).
7454 If @emph{xsvfdump} shows a file is using those opcodes, it
7455 probably will not be usable with other XSVF tools.
7461 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
7462 be used to access files on PCs (either the developer's PC or some other PC).
7464 The way this works on the ZY1000 is to prefix a filename by
7465 "/tftp/ip/" and append the TFTP path on the TFTP
7466 server (tftpd). For example,
7469 load_image /tftp/10.0.0.96/c:\temp\abc.elf
7472 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
7473 if the file was hosted on the embedded host.
7475 In order to achieve decent performance, you must choose a TFTP server
7476 that supports a packet size bigger than the default packet size (512 bytes). There
7477 are numerous TFTP servers out there (free and commercial) and you will have to do
7478 a bit of googling to find something that fits your requirements.
7480 @node GDB and OpenOCD
7481 @chapter GDB and OpenOCD
7483 OpenOCD complies with the remote gdbserver protocol, and as such can be used
7484 to debug remote targets.
7485 Setting up GDB to work with OpenOCD can involve several components:
7488 @item The OpenOCD server support for GDB may need to be configured.
7489 @xref{GDB Configuration}.
7490 @item GDB's support for OpenOCD may need configuration,
7491 as shown in this chapter.
7492 @item If you have a GUI environment like Eclipse,
7493 that also will probably need to be configured.
7496 Of course, the version of GDB you use will need to be one which has
7497 been built to know about the target CPU you're using. It's probably
7498 part of the tool chain you're using. For example, if you are doing
7499 cross-development for ARM on an x86 PC, instead of using the native
7500 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
7501 if that's the tool chain used to compile your code.
7503 @anchor{Connecting to GDB}
7504 @section Connecting to GDB
7505 @cindex Connecting to GDB
7506 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
7507 instance GDB 6.3 has a known bug that produces bogus memory access
7508 errors, which has since been fixed; see
7509 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
7511 OpenOCD can communicate with GDB in two ways:
7515 A socket (TCP/IP) connection is typically started as follows:
7517 target remote localhost:3333
7519 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
7521 A pipe connection is typically started as follows:
7523 target remote | openocd -c "gdb_port pipe; log_output openocd.log"
7525 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
7526 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
7527 session. log_output sends the log output to a file to ensure that the pipe is
7528 not saturated when using higher debug level outputs.
7531 To list the available OpenOCD commands type @command{monitor help} on the
7534 @section Sample GDB session startup
7536 With the remote protocol, GDB sessions start a little differently
7537 than they do when you're debugging locally.
7538 Here's an examples showing how to start a debug session with a
7540 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
7541 Most programs would be written into flash (address 0) and run from there.
7544 $ arm-none-eabi-gdb example.elf
7545 (gdb) target remote localhost:3333
7546 Remote debugging using localhost:3333
7548 (gdb) monitor reset halt
7551 Loading section .vectors, size 0x100 lma 0x20000000
7552 Loading section .text, size 0x5a0 lma 0x20000100
7553 Loading section .data, size 0x18 lma 0x200006a0
7554 Start address 0x2000061c, load size 1720
7555 Transfer rate: 22 KB/sec, 573 bytes/write.
7561 You could then interrupt the GDB session to make the program break,
7562 type @command{where} to show the stack, @command{list} to show the
7563 code around the program counter, @command{step} through code,
7564 set breakpoints or watchpoints, and so on.
7566 @section Configuring GDB for OpenOCD
7568 OpenOCD supports the gdb @option{qSupported} packet, this enables information
7569 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
7570 packet size and the device's memory map.
7571 You do not need to configure the packet size by hand,
7572 and the relevant parts of the memory map should be automatically
7573 set up when you declare (NOR) flash banks.
7575 However, there are other things which GDB can't currently query.
7576 You may need to set those up by hand.
7577 As OpenOCD starts up, you will often see a line reporting
7581 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
7584 You can pass that information to GDB with these commands:
7587 set remote hardware-breakpoint-limit 6
7588 set remote hardware-watchpoint-limit 4
7591 With that particular hardware (Cortex-M3) the hardware breakpoints
7592 only work for code running from flash memory. Most other ARM systems
7593 do not have such restrictions.
7595 Another example of useful GDB configuration came from a user who
7596 found that single stepping his Cortex-M3 didn't work well with IRQs
7597 and an RTOS until he told GDB to disable the IRQs while stepping:
7601 mon cortex_m3 maskisr on
7603 define hookpost-step
7604 mon cortex_m3 maskisr off
7608 Rather than typing such commands interactively, you may prefer to
7609 save them in a file and have GDB execute them as it starts, perhaps
7610 using a @file{.gdbinit} in your project directory or starting GDB
7611 using @command{gdb -x filename}.
7613 @section Programming using GDB
7614 @cindex Programming using GDB
7616 By default the target memory map is sent to GDB. This can be disabled by
7617 the following OpenOCD configuration option:
7619 gdb_memory_map disable
7621 For this to function correctly a valid flash configuration must also be set
7622 in OpenOCD. For faster performance you should also configure a valid
7625 Informing GDB of the memory map of the target will enable GDB to protect any
7626 flash areas of the target and use hardware breakpoints by default. This means
7627 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
7628 using a memory map. @xref{gdb_breakpoint_override}.
7630 To view the configured memory map in GDB, use the GDB command @option{info mem}
7631 All other unassigned addresses within GDB are treated as RAM.
7633 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
7634 This can be changed to the old behaviour by using the following GDB command
7636 set mem inaccessible-by-default off
7639 If @command{gdb_flash_program enable} is also used, GDB will be able to
7640 program any flash memory using the vFlash interface.
7642 GDB will look at the target memory map when a load command is given, if any
7643 areas to be programmed lie within the target flash area the vFlash packets
7646 If the target needs configuring before GDB programming, an event
7647 script can be executed:
7649 $_TARGETNAME configure -event EVENTNAME BODY
7652 To verify any flash programming the GDB command @option{compare-sections}
7654 @anchor{Using openocd SMP with GDB}
7655 @section Using openocd SMP with GDB
7657 For SMP support following GDB serial protocol packet have been defined :
7659 @item j - smp status request
7660 @item J - smp set request
7663 OpenOCD implements :
7665 @item @option{jc} packet for reading core id displayed by
7666 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
7667 @option{E01} for target not smp.
7668 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
7669 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
7670 for target not smp or @option{OK} on success.
7673 Handling of this packet within GDB can be done :
7675 @item by the creation of an internal variable (i.e @option{_core}) by mean
7676 of function allocate_computed_value allowing following GDB command.
7679 #Jc01 packet is sent
7681 #jc packet is sent and result is affected in $
7684 @item by the usage of GDB maintenance command as described in following example (2
7685 cpus in SMP with core id 0 and 1 @pxref{Define CPU targets working in SMP}).
7688 # toggle0 : force display of coreid 0
7694 # toggle1 : force display of coreid 1
7704 @node Tcl Scripting API
7705 @chapter Tcl Scripting API
7706 @cindex Tcl Scripting API
7710 The commands are stateless. E.g. the telnet command line has a concept
7711 of currently active target, the Tcl API proc's take this sort of state
7712 information as an argument to each proc.
7714 There are three main types of return values: single value, name value
7715 pair list and lists.
7717 Name value pair. The proc 'foo' below returns a name/value pair
7723 > set foo(you) Oyvind
7724 > set foo(mouse) Micky
7725 > set foo(duck) Donald
7733 me Duane you Oyvind mouse Micky duck Donald
7735 Thus, to get the names of the associative array is easy:
7737 foreach { name value } [set foo] {
7738 puts "Name: $name, Value: $value"
7742 Lists returned must be relatively small. Otherwise a range
7743 should be passed in to the proc in question.
7745 @section Internal low-level Commands
7747 By low-level, the intent is a human would not directly use these commands.
7749 Low-level commands are (should be) prefixed with "ocd_", e.g.
7750 @command{ocd_flash_banks}
7751 is the low level API upon which @command{flash banks} is implemented.
7754 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
7756 Read memory and return as a Tcl array for script processing
7757 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
7759 Convert a Tcl array to memory locations and write the values
7760 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
7762 Return information about the flash banks
7765 OpenOCD commands can consist of two words, e.g. "flash banks". The
7766 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
7767 called "flash_banks".
7769 @section OpenOCD specific Global Variables
7771 Real Tcl has ::tcl_platform(), and platform::identify, and many other
7772 variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
7773 holds one of the following values:
7776 @item @b{cygwin} Running under Cygwin
7777 @item @b{darwin} Darwin (Mac-OS) is the underlying operating sytem.
7778 @item @b{freebsd} Running under FreeBSD
7779 @item @b{linux} Linux is the underlying operating sytem
7780 @item @b{mingw32} Running under MingW32
7781 @item @b{winxx} Built using Microsoft Visual Studio
7782 @item @b{other} Unknown, none of the above.
7785 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
7788 We should add support for a variable like Tcl variable
7789 @code{tcl_platform(platform)}, it should be called
7790 @code{jim_platform} (because it
7791 is jim, not real tcl).
7799 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
7801 @cindex adaptive clocking
7804 In digital circuit design it is often refered to as ``clock
7805 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
7806 operating at some speed, your CPU target is operating at another.
7807 The two clocks are not synchronised, they are ``asynchronous''
7809 In order for the two to work together they must be synchronised
7810 well enough to work; JTAG can't go ten times faster than the CPU,
7811 for example. There are 2 basic options:
7814 Use a special "adaptive clocking" circuit to change the JTAG
7815 clock rate to match what the CPU currently supports.
7817 The JTAG clock must be fixed at some speed that's enough slower than
7818 the CPU clock that all TMS and TDI transitions can be detected.
7821 @b{Does this really matter?} For some chips and some situations, this
7822 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
7823 the CPU has no difficulty keeping up with JTAG.
7824 Startup sequences are often problematic though, as are other
7825 situations where the CPU clock rate changes (perhaps to save
7828 For example, Atmel AT91SAM chips start operation from reset with
7829 a 32kHz system clock. Boot firmware may activate the main oscillator
7830 and PLL before switching to a faster clock (perhaps that 500 MHz
7832 If you're using JTAG to debug that startup sequence, you must slow
7833 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
7834 JTAG can use a faster clock.
7836 Consider also debugging a 500MHz ARM926 hand held battery powered
7837 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
7838 clock, between keystrokes unless it has work to do. When would
7839 that 5 MHz JTAG clock be usable?
7841 @b{Solution #1 - A special circuit}
7843 In order to make use of this,
7844 your CPU, board, and JTAG adapter must all support the RTCK
7845 feature. Not all of them support this; keep reading!
7847 The RTCK ("Return TCK") signal in some ARM chips is used to help with
7848 this problem. ARM has a good description of the problem described at
7849 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
7850 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
7851 work? / how does adaptive clocking work?''.
7853 The nice thing about adaptive clocking is that ``battery powered hand
7854 held device example'' - the adaptiveness works perfectly all the
7855 time. One can set a break point or halt the system in the deep power
7856 down code, slow step out until the system speeds up.
7858 Note that adaptive clocking may also need to work at the board level,
7859 when a board-level scan chain has multiple chips.
7860 Parallel clock voting schemes are good way to implement this,
7861 both within and between chips, and can easily be implemented
7863 It's not difficult to have logic fan a module's input TCK signal out
7864 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
7865 back with the right polarity before changing the output RTCK signal.
7866 Texas Instruments makes some clock voting logic available
7867 for free (with no support) in VHDL form; see
7868 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
7870 @b{Solution #2 - Always works - but may be slower}
7872 Often this is a perfectly acceptable solution.
7874 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
7875 the target clock speed. But what that ``magic division'' is varies
7876 depending on the chips on your board.
7877 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
7878 ARM11 cores use an 8:1 division.
7879 @b{Xilinx rule of thumb} is 1/12 the clock speed.
7881 Note: most full speed FT2232 based JTAG adapters are limited to a
7882 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
7883 often support faster clock rates (and adaptive clocking).
7885 You can still debug the 'low power' situations - you just need to
7886 either use a fixed and very slow JTAG clock rate ... or else
7887 manually adjust the clock speed at every step. (Adjusting is painful
7888 and tedious, and is not always practical.)
7890 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
7891 have a special debug mode in your application that does a ``high power
7892 sleep''. If you are careful - 98% of your problems can be debugged
7895 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
7896 operation in your idle loops even if you don't otherwise change the CPU
7898 That operation gates the CPU clock, and thus the JTAG clock; which
7899 prevents JTAG access. One consequence is not being able to @command{halt}
7900 cores which are executing that @emph{wait for interrupt} operation.
7902 To set the JTAG frequency use the command:
7910 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
7912 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
7913 around Windows filenames.
7926 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
7928 Make sure you have Cygwin installed, or at least a version of OpenOCD that
7929 claims to come with all the necessary DLLs. When using Cygwin, try launching
7930 OpenOCD from the Cygwin shell.
7932 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
7933 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
7934 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
7936 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
7937 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
7938 software breakpoints consume one of the two available hardware breakpoints.
7940 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
7942 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
7943 clock at the time you're programming the flash. If you've specified the crystal's
7944 frequency, make sure the PLL is disabled. If you've specified the full core speed
7945 (e.g. 60MHz), make sure the PLL is enabled.
7947 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
7948 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
7949 out while waiting for end of scan, rtck was disabled".
7951 Make sure your PC's parallel port operates in EPP mode. You might have to try several
7952 settings in your PC BIOS (ECP, EPP, and different versions of those).
7954 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
7955 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
7956 memory read caused data abort".
7958 The errors are non-fatal, and are the result of GDB trying to trace stack frames
7959 beyond the last valid frame. It might be possible to prevent this by setting up
7960 a proper "initial" stack frame, if you happen to know what exactly has to
7961 be done, feel free to add this here.
7963 @b{Simple:} In your startup code - push 8 registers of zeros onto the
7964 stack before calling main(). What GDB is doing is ``climbing'' the run
7965 time stack by reading various values on the stack using the standard
7966 call frame for the target. GDB keeps going - until one of 2 things
7967 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
7968 stackframes have been processed. By pushing zeros on the stack, GDB
7971 @b{Debugging Interrupt Service Routines} - In your ISR before you call
7972 your C code, do the same - artifically push some zeros onto the stack,
7973 remember to pop them off when the ISR is done.
7975 @b{Also note:} If you have a multi-threaded operating system, they
7976 often do not @b{in the intrest of saving memory} waste these few
7980 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
7981 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
7983 This warning doesn't indicate any serious problem, as long as you don't want to
7984 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
7985 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
7986 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
7987 independently. With this setup, it's not possible to halt the core right out of
7988 reset, everything else should work fine.
7990 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
7991 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
7992 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
7993 quit with an error message. Is there a stability issue with OpenOCD?
7995 No, this is not a stability issue concerning OpenOCD. Most users have solved
7996 this issue by simply using a self-powered USB hub, which they connect their
7997 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
7998 supply stable enough for the Amontec JTAGkey to be operated.
8000 @b{Laptops running on battery have this problem too...}
8002 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
8003 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
8004 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
8005 What does that mean and what might be the reason for this?
8007 First of all, the reason might be the USB power supply. Try using a self-powered
8008 hub instead of a direct connection to your computer. Secondly, the error code 4
8009 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
8010 chip ran into some sort of error - this points us to a USB problem.
8012 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
8013 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
8014 What does that mean and what might be the reason for this?
8016 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
8017 has closed the connection to OpenOCD. This might be a GDB issue.
8019 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
8020 are described, there is a parameter for specifying the clock frequency
8021 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
8022 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
8023 specified in kilohertz. However, I do have a quartz crystal of a
8024 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
8025 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
8028 No. The clock frequency specified here must be given as an integral number.
8029 However, this clock frequency is used by the In-Application-Programming (IAP)
8030 routines of the LPC2000 family only, which seems to be very tolerant concerning
8031 the given clock frequency, so a slight difference between the specified clock
8032 frequency and the actual clock frequency will not cause any trouble.
8034 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
8036 Well, yes and no. Commands can be given in arbitrary order, yet the
8037 devices listed for the JTAG scan chain must be given in the right
8038 order (jtag newdevice), with the device closest to the TDO-Pin being
8039 listed first. In general, whenever objects of the same type exist
8040 which require an index number, then these objects must be given in the
8041 right order (jtag newtap, targets and flash banks - a target
8042 references a jtag newtap and a flash bank references a target).
8044 You can use the ``scan_chain'' command to verify and display the tap order.
8046 Also, some commands can't execute until after @command{init} has been
8047 processed. Such commands include @command{nand probe} and everything
8048 else that needs to write to controller registers, perhaps for setting
8049 up DRAM and loading it with code.
8051 @anchor{FAQ TAP Order}
8052 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
8055 Yes; whenever you have more than one, you must declare them in
8056 the same order used by the hardware.
8058 Many newer devices have multiple JTAG TAPs. For example: ST
8059 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
8060 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
8061 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
8062 connected to the boundary scan TAP, which then connects to the
8063 Cortex-M3 TAP, which then connects to the TDO pin.
8065 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
8066 (2) The boundary scan TAP. If your board includes an additional JTAG
8067 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
8068 place it before or after the STM32 chip in the chain. For example:
8071 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
8072 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
8073 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
8074 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
8075 @item Xilinx TDO Pin -> OpenOCD TDO (input)
8078 The ``jtag device'' commands would thus be in the order shown below. Note:
8081 @item jtag newtap Xilinx tap -irlen ...
8082 @item jtag newtap stm32 cpu -irlen ...
8083 @item jtag newtap stm32 bs -irlen ...
8084 @item # Create the debug target and say where it is
8085 @item target create stm32.cpu -chain-position stm32.cpu ...
8089 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
8090 log file, I can see these error messages: Error: arm7_9_common.c:561
8091 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
8097 @node Tcl Crash Course
8098 @chapter Tcl Crash Course
8101 Not everyone knows Tcl - this is not intended to be a replacement for
8102 learning Tcl, the intent of this chapter is to give you some idea of
8103 how the Tcl scripts work.
8105 This chapter is written with two audiences in mind. (1) OpenOCD users
8106 who need to understand a bit more of how Jim-Tcl works so they can do
8107 something useful, and (2) those that want to add a new command to
8110 @section Tcl Rule #1
8111 There is a famous joke, it goes like this:
8113 @item Rule #1: The wife is always correct
8114 @item Rule #2: If you think otherwise, See Rule #1
8117 The Tcl equal is this:
8120 @item Rule #1: Everything is a string
8121 @item Rule #2: If you think otherwise, See Rule #1
8124 As in the famous joke, the consequences of Rule #1 are profound. Once
8125 you understand Rule #1, you will understand Tcl.
8127 @section Tcl Rule #1b
8128 There is a second pair of rules.
8130 @item Rule #1: Control flow does not exist. Only commands
8131 @* For example: the classic FOR loop or IF statement is not a control
8132 flow item, they are commands, there is no such thing as control flow
8134 @item Rule #2: If you think otherwise, See Rule #1
8135 @* Actually what happens is this: There are commands that by
8136 convention, act like control flow key words in other languages. One of
8137 those commands is the word ``for'', another command is ``if''.
8140 @section Per Rule #1 - All Results are strings
8141 Every Tcl command results in a string. The word ``result'' is used
8142 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
8143 Everything is a string}
8145 @section Tcl Quoting Operators
8146 In life of a Tcl script, there are two important periods of time, the
8147 difference is subtle.
8150 @item Evaluation Time
8153 The two key items here are how ``quoted things'' work in Tcl. Tcl has
8154 three primary quoting constructs, the [square-brackets] the
8155 @{curly-braces@} and ``double-quotes''
8157 By now you should know $VARIABLES always start with a $DOLLAR
8158 sign. BTW: To set a variable, you actually use the command ``set'', as
8159 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
8160 = 1'' statement, but without the equal sign.
8163 @item @b{[square-brackets]}
8164 @* @b{[square-brackets]} are command substitutions. It operates much
8165 like Unix Shell `back-ticks`. The result of a [square-bracket]
8166 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
8167 string}. These two statements are roughly identical:
8171 echo "The Date is: $X"
8174 puts "The Date is: $X"
8176 @item @b{``double-quoted-things''}
8177 @* @b{``double-quoted-things''} are just simply quoted
8178 text. $VARIABLES and [square-brackets] are expanded in place - the
8179 result however is exactly 1 string. @i{Remember Rule #1 - Everything
8183 puts "It is now \"[date]\", $x is in 1 hour"
8185 @item @b{@{Curly-Braces@}}
8186 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
8187 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
8188 'single-quote' operators in BASH shell scripts, with the added
8189 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
8190 nested 3 times@}@}@} NOTE: [date] is a bad example;
8191 at this writing, Jim/OpenOCD does not have a date command.
8194 @section Consequences of Rule 1/2/3/4
8196 The consequences of Rule 1 are profound.
8198 @subsection Tokenisation & Execution.
8200 Of course, whitespace, blank lines and #comment lines are handled in
8203 As a script is parsed, each (multi) line in the script file is
8204 tokenised and according to the quoting rules. After tokenisation, that
8205 line is immedatly executed.
8207 Multi line statements end with one or more ``still-open''
8208 @{curly-braces@} which - eventually - closes a few lines later.
8210 @subsection Command Execution
8212 Remember earlier: There are no ``control flow''
8213 statements in Tcl. Instead there are COMMANDS that simply act like
8214 control flow operators.
8216 Commands are executed like this:
8219 @item Parse the next line into (argc) and (argv[]).
8220 @item Look up (argv[0]) in a table and call its function.
8221 @item Repeat until End Of File.
8224 It sort of works like this:
8227 ReadAndParse( &argc, &argv );
8229 cmdPtr = LookupCommand( argv[0] );
8231 (*cmdPtr->Execute)( argc, argv );
8235 When the command ``proc'' is parsed (which creates a procedure
8236 function) it gets 3 parameters on the command line. @b{1} the name of
8237 the proc (function), @b{2} the list of parameters, and @b{3} the body
8238 of the function. Not the choice of words: LIST and BODY. The PROC
8239 command stores these items in a table somewhere so it can be found by
8242 @subsection The FOR command
8244 The most interesting command to look at is the FOR command. In Tcl,
8245 the FOR command is normally implemented in C. Remember, FOR is a
8246 command just like any other command.
8248 When the ascii text containing the FOR command is parsed, the parser
8249 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
8253 @item The ascii text 'for'
8254 @item The start text
8255 @item The test expression
8260 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
8261 Remember @i{Rule #1 - Everything is a string.} The key point is this:
8262 Often many of those parameters are in @{curly-braces@} - thus the
8263 variables inside are not expanded or replaced until later.
8265 Remember that every Tcl command looks like the classic ``main( argc,
8266 argv )'' function in C. In JimTCL - they actually look like this:
8270 MyCommand( Jim_Interp *interp,
8272 Jim_Obj * const *argvs );
8275 Real Tcl is nearly identical. Although the newer versions have
8276 introduced a byte-code parser and intepreter, but at the core, it
8277 still operates in the same basic way.
8279 @subsection FOR command implementation
8281 To understand Tcl it is perhaps most helpful to see the FOR
8282 command. Remember, it is a COMMAND not a control flow structure.
8284 In Tcl there are two underlying C helper functions.
8286 Remember Rule #1 - You are a string.
8288 The @b{first} helper parses and executes commands found in an ascii
8289 string. Commands can be seperated by semicolons, or newlines. While
8290 parsing, variables are expanded via the quoting rules.
8292 The @b{second} helper evaluates an ascii string as a numerical
8293 expression and returns a value.
8295 Here is an example of how the @b{FOR} command could be
8296 implemented. The pseudo code below does not show error handling.
8298 void Execute_AsciiString( void *interp, const char *string );
8300 int Evaluate_AsciiExpression( void *interp, const char *string );
8303 MyForCommand( void *interp,
8308 SetResult( interp, "WRONG number of parameters");
8312 // argv[0] = the ascii string just like C
8314 // Execute the start statement.
8315 Execute_AsciiString( interp, argv[1] );
8319 i = Evaluate_AsciiExpression(interp, argv[2]);
8324 Execute_AsciiString( interp, argv[3] );
8326 // Execute the LOOP part
8327 Execute_AsciiString( interp, argv[4] );
8331 SetResult( interp, "" );
8336 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
8337 in the same basic way.
8339 @section OpenOCD Tcl Usage
8341 @subsection source and find commands
8342 @b{Where:} In many configuration files
8343 @* Example: @b{ source [find FILENAME] }
8344 @*Remember the parsing rules
8346 @item The @command{find} command is in square brackets,
8347 and is executed with the parameter FILENAME. It should find and return
8348 the full path to a file with that name; it uses an internal search path.
8349 The RESULT is a string, which is substituted into the command line in
8350 place of the bracketed @command{find} command.
8351 (Don't try to use a FILENAME which includes the "#" character.
8352 That character begins Tcl comments.)
8353 @item The @command{source} command is executed with the resulting filename;
8354 it reads a file and executes as a script.
8356 @subsection format command
8357 @b{Where:} Generally occurs in numerous places.
8358 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
8364 puts [format "The answer: %d" [expr $x * $y]]
8367 @item The SET command creates 2 variables, X and Y.
8368 @item The double [nested] EXPR command performs math
8369 @* The EXPR command produces numerical result as a string.
8371 @item The format command is executed, producing a single string
8372 @* Refer to Rule #1.
8373 @item The PUTS command outputs the text.
8375 @subsection Body or Inlined Text
8376 @b{Where:} Various TARGET scripts.
8379 proc someproc @{@} @{
8380 ... multiple lines of stuff ...
8382 $_TARGETNAME configure -event FOO someproc
8383 #2 Good - no variables
8384 $_TARGETNAME confgure -event foo "this ; that;"
8385 #3 Good Curly Braces
8386 $_TARGETNAME configure -event FOO @{
8389 #4 DANGER DANGER DANGER
8390 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
8393 @item The $_TARGETNAME is an OpenOCD variable convention.
8394 @*@b{$_TARGETNAME} represents the last target created, the value changes
8395 each time a new target is created. Remember the parsing rules. When
8396 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
8397 the name of the target which happens to be a TARGET (object)
8399 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
8400 @*There are 4 examples:
8402 @item The TCLBODY is a simple string that happens to be a proc name
8403 @item The TCLBODY is several simple commands seperated by semicolons
8404 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
8405 @item The TCLBODY is a string with variables that get expanded.
8408 In the end, when the target event FOO occurs the TCLBODY is
8409 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
8410 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
8412 Remember the parsing rules. In case #3, @{curly-braces@} mean the
8413 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
8414 and the text is evaluated. In case #4, they are replaced before the
8415 ``Target Object Command'' is executed. This occurs at the same time
8416 $_TARGETNAME is replaced. In case #4 the date will never
8417 change. @{BTW: [date] is a bad example; at this writing,
8418 Jim/OpenOCD does not have a date command@}
8420 @subsection Global Variables
8421 @b{Where:} You might discover this when writing your own procs @* In
8422 simple terms: Inside a PROC, if you need to access a global variable
8423 you must say so. See also ``upvar''. Example:
8425 proc myproc @{ @} @{
8426 set y 0 #Local variable Y
8427 global x #Global variable X
8428 puts [format "X=%d, Y=%d" $x $y]
8431 @section Other Tcl Hacks
8432 @b{Dynamic variable creation}
8434 # Dynamically create a bunch of variables.
8435 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
8437 set vn [format "BIT%d" $x]
8441 set $vn [expr (1 << $x)]
8444 @b{Dynamic proc/command creation}
8446 # One "X" function - 5 uart functions.
8447 foreach who @{A B C D E@}
8448 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
8454 @node OpenOCD Concept Index
8455 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
8456 @comment case issue with ``Index.html'' and ``index.html''
8457 @comment Occurs when creating ``--html --no-split'' output
8458 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
8459 @unnumbered OpenOCD Concept Index
8463 @node Command and Driver Index
8464 @unnumbered Command and Driver Index