1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
107 @section What is OpenOCD?
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board can be directly connected to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD only supports
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
154 based, parallel port based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
159 Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
160 debugged via the GDB protocol.
162 @b{Flash Programing:} Flash writing is supported for external CFI
163 compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) controller is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.sourceforge.net/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.sourceforge.net/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
209 @chapter OpenOCD Developer Resources
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD GIT Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a GIT repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard GIT tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a GIT client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration in the top of the source tree.
264 @section OpenOCD Developer Mailing List
266 The OpenOCD Developer Mailing List provides the primary means of
267 communication between developers:
269 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
271 Discuss and submit patches to this list.
272 The @file{HACKING} file contains basic information about how
275 @section OpenOCD Bug Database
277 During the 0.4.x release cycle the OpenOCD project team began
278 using Trac for its bug database:
280 @uref{https://sourceforge.net/apps/trac/openocd}
283 @node Debug Adapter Hardware
284 @chapter Debug Adapter Hardware
293 Defined: @b{dongle}: A small device that plugins into a computer and serves as
294 an adapter .... [snip]
296 In the OpenOCD case, this generally refers to @b{a small adapter} that
297 attaches to your computer via USB or the Parallel Printer Port. One
298 exception is the Zylin ZY1000, packaged as a small box you attach via
299 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
300 require any drivers to be installed on the developer PC. It also has
301 a built in web interface. It supports RTCK/RCLK or adaptive clocking
302 and has a built in relay to power cycle targets remotely.
305 @section Choosing a Dongle
307 There are several things you should keep in mind when choosing a dongle.
310 @item @b{Transport} Does it support the kind of communication that you need?
311 OpenOCD focusses mostly on JTAG. Your version may also support
312 other ways to communicate with target devices.
313 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
314 Does your dongle support it? You might need a level converter.
315 @item @b{Pinout} What pinout does your target board use?
316 Does your dongle support it? You may be able to use jumper
317 wires, or an "octopus" connector, to convert pinouts.
318 @item @b{Connection} Does your computer have the USB, printer, or
319 Ethernet port needed?
320 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
321 RTCK support? Also known as ``adaptive clocking''
324 @section Stand alone Systems
326 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe}
327 Technically, not a dongle, but a standalone box. The ZY1000 has the advantage that it does
328 not require any drivers installed on the developer PC. It also has
329 a built in web interface. It supports RTCK/RCLK or adaptive clocking
330 and has a built in relay to power cycle targets remotely.
332 @section USB FT2232 Based
334 There are many USB JTAG dongles on the market, many of them are based
335 on a chip from ``Future Technology Devices International'' (FTDI)
336 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
337 See: @url{http://www.ftdichip.com} for more information.
338 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
339 chips are starting to become available in JTAG adapters. (Adapters
340 using those high speed FT2232H chips may support adaptive clocking.)
342 The FT2232 chips are flexible enough to support some other
343 transport options, such as SWD or the SPI variants used to
344 program some chips. They have two communications channels,
345 and one can be used for a UART adapter at the same time the
346 other one is used to provide a debug adapter.
348 Also, some development boards integrate an FT2232 chip to serve as
349 a built-in low cost debug adapter and usb-to-serial solution.
353 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
355 @* See: @url{http://www.amontec.com/jtagkey.shtml}
357 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
359 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
361 @* See: @url{http://www.signalyzer.com}
362 @item @b{Stellaris Eval Boards}
363 @* See: @url{http://www.ti.com} - The Stellaris eval boards
364 bundle FT2232-based JTAG and SWD support, which can be used to debug
365 the Stellaris chips. Using separate JTAG adapters is optional.
366 These boards can also be used in a "pass through" mode as JTAG adapters
367 to other target boards, disabling the Stellaris chip.
368 @item @b{TI/Luminary ICDI}
369 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
370 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
371 Evaluation Kits. Like the non-detachable FT2232 support on the other
372 Stellaris eval boards, they can be used to debug other target boards.
373 @item @b{olimex-jtag}
374 @* See: @url{http://www.olimex.com}
375 @item @b{Flyswatter/Flyswatter2}
376 @* See: @url{http://www.tincantools.com}
377 @item @b{turtelizer2}
379 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
380 @url{http://www.ethernut.de}
382 @* Link: @url{http://www.hitex.com/index.php?id=383}
384 @* Link @url{http://www.hitex.com/stm32-stick}
385 @item @b{axm0432_jtag}
386 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
387 to be available anymore as of April 2012.
389 @* Link @url{http://www.hitex.com/index.php?id=cortino}
390 @item @b{dlp-usb1232h}
391 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
392 @item @b{digilent-hs1}
393 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
395 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
399 @section USB-JTAG / Altera USB-Blaster compatibles
401 These devices also show up as FTDI devices, but are not
402 protocol-compatible with the FT2232 devices. They are, however,
403 protocol-compatible among themselves. USB-JTAG devices typically consist
404 of a FT245 followed by a CPLD that understands a particular protocol,
405 or emulate this protocol using some other hardware.
407 They may appear under different USB VID/PID depending on the particular
408 product. The driver can be configured to search for any VID/PID pair
409 (see the section on driver commands).
412 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
413 @* Link: @url{http://ixo-jtag.sourceforge.net/}
414 @item @b{Altera USB-Blaster}
415 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
418 @section USB JLINK based
419 There are several OEM versions of the Segger @b{JLINK} adapter. It is
420 an example of a micro controller based JTAG adapter, it uses an
421 AT91SAM764 internally.
424 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
425 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
426 @item @b{SEGGER JLINK}
427 @* Link: @url{http://www.segger.com/jlink.html}
429 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
432 @section USB RLINK based
433 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
434 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
435 SWD and not JTAG, thus not supported.
438 @item @b{Raisonance RLink}
439 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
440 @item @b{STM32 Primer}
441 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
442 @item @b{STM32 Primer2}
443 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
446 @section USB ST-LINK based
447 ST Micro has an adapter called @b{ST-LINK}.
448 They only work with ST Micro chips, notably STM32 and STM8.
452 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
453 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
455 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
456 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
459 For info the original ST-LINK enumerates using the mass storage usb class, however
460 it's implementation is completely broken. The result is this causes issues under linux.
461 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
463 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
464 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
467 @section USB TI/Stellaris ICDI based
468 Texas Instruments has an adapter called @b{ICDI}.
469 It is not to be confused with the FTDI based adapters that were originally fitted to their
470 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
475 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
477 @item @b{USB - Presto}
478 @* Link: @url{http://tools.asix.net/prg_presto.htm}
480 @item @b{Versaloon-Link}
481 @* Link: @url{http://www.versaloon.com}
483 @item @b{ARM-JTAG-EW}
484 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
487 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
490 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
493 @* Link: @url{http://code.google.com/p/estick-jtag/}
495 @item @b{Keil ULINK v1}
496 @* Link: @url{http://www.keil.com/ulink1/}
499 @section IBM PC Parallel Printer Port Based
501 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
502 and the Macraigor Wiggler. There are many clones and variations of
505 Note that parallel ports are becoming much less common, so if you
506 have the choice you should probably avoid these adapters in favor
511 @item @b{Wiggler} - There are many clones of this.
512 @* Link: @url{http://www.macraigor.com/wiggler.htm}
514 @item @b{DLC5} - From XILINX - There are many clones of this
515 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
516 produced, PDF schematics are easily found and it is easy to make.
518 @item @b{Amontec - JTAG Accelerator}
519 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
522 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
525 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
527 @item @b{Wiggler_ntrst_inverted}
528 @* Yet another variation - See the source code, src/jtag/parport.c
530 @item @b{old_amt_wiggler}
531 @* Unknown - probably not on the market today
534 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
537 @* Link: @url{http://www.amontec.com/chameleon.shtml}
543 @* ispDownload from Lattice Semiconductor
544 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
547 @* From ST Microsystems;
548 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
556 @* An EP93xx based Linux machine using the GPIO pins directly.
559 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
564 @chapter About Jim-Tcl
568 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
569 This programming language provides a simple and extensible
572 All commands presented in this Guide are extensions to Jim-Tcl.
573 You can use them as simple commands, without needing to learn
574 much of anything about Tcl.
575 Alternatively, can write Tcl programs with them.
577 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
578 There is an active and responsive community, get on the mailing list
579 if you have any questions. Jim-Tcl maintainers also lurk on the
580 OpenOCD mailing list.
583 @item @b{Jim vs. Tcl}
584 @* Jim-Tcl is a stripped down version of the well known Tcl language,
585 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
586 fewer features. Jim-Tcl is several dozens of .C files and .H files and
587 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
588 4.2 MB .zip file containing 1540 files.
590 @item @b{Missing Features}
591 @* Our practice has been: Add/clone the real Tcl feature if/when
592 needed. We welcome Jim-Tcl improvements, not bloat. Also there
593 are a large number of optional Jim-Tcl features that are not
597 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
598 command interpreter today is a mixture of (newer)
599 Jim-Tcl commands, and (older) the orginal command interpreter.
602 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
603 can type a Tcl for() loop, set variables, etc.
604 Some of the commands documented in this guide are implemented
605 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
607 @item @b{Historical Note}
608 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
609 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
610 as a git submodule, which greatly simplified upgrading Jim Tcl
611 to benefit from new features and bugfixes in Jim Tcl.
613 @item @b{Need a crash course in Tcl?}
614 @*@xref{Tcl Crash Course}.
619 @cindex command line options
621 @cindex directory search
623 Properly installing OpenOCD sets up your operating system to grant it access
624 to the debug adapters. On Linux, this usually involves installing a file
625 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
626 complex and confusing driver configuration for every peripheral. Such issues
627 are unique to each operating system, and are not detailed in this User's Guide.
629 Then later you will invoke the OpenOCD server, with various options to
630 tell it how each debug session should work.
631 The @option{--help} option shows:
635 --help | -h display this help
636 --version | -v display OpenOCD version
637 --file | -f use configuration file <name>
638 --search | -s dir to search for config files and scripts
639 --debug | -d set debug level <0-3>
640 --log_output | -l redirect log output to file <name>
641 --command | -c run <command>
644 If you don't give any @option{-f} or @option{-c} options,
645 OpenOCD tries to read the configuration file @file{openocd.cfg}.
646 To specify one or more different
647 configuration files, use @option{-f} options. For example:
650 openocd -f config1.cfg -f config2.cfg -f config3.cfg
653 Configuration files and scripts are searched for in
655 @item the current directory,
656 @item any search dir specified on the command line using the @option{-s} option,
657 @item any search dir specified using the @command{add_script_search_dir} command,
658 @item @file{$HOME/.openocd} (not on Windows),
659 @item the site wide script library @file{$pkgdatadir/site} and
660 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
662 The first found file with a matching file name will be used.
665 Don't try to use configuration script names or paths which
666 include the "#" character. That character begins Tcl comments.
669 @section Simple setup, no customization
671 In the best case, you can use two scripts from one of the script
672 libraries, hook up your JTAG adapter, and start the server ... and
673 your JTAG setup will just work "out of the box". Always try to
674 start by reusing those scripts, but assume you'll need more
675 customization even if this works. @xref{OpenOCD Project Setup}.
677 If you find a script for your JTAG adapter, and for your board or
678 target, you may be able to hook up your JTAG adapter then start
682 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
685 You might also need to configure which reset signals are present,
686 using @option{-c 'reset_config trst_and_srst'} or something similar.
687 If all goes well you'll see output something like
690 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
691 For bug reports, read
692 http://openocd.sourceforge.net/doc/doxygen/bugs.html
693 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
694 (mfg: 0x23b, part: 0xba00, ver: 0x3)
697 Seeing that "tap/device found" message, and no warnings, means
698 the JTAG communication is working. That's a key milestone, but
699 you'll probably need more project-specific setup.
701 @section What OpenOCD does as it starts
703 OpenOCD starts by processing the configuration commands provided
704 on the command line or, if there were no @option{-c command} or
705 @option{-f file.cfg} options given, in @file{openocd.cfg}.
706 @xref{configurationstage,,Configuration Stage}.
707 At the end of the configuration stage it verifies the JTAG scan
708 chain defined using those commands; your configuration should
709 ensure that this always succeeds.
710 Normally, OpenOCD then starts running as a daemon.
711 Alternatively, commands may be used to terminate the configuration
712 stage early, perform work (such as updating some flash memory),
713 and then shut down without acting as a daemon.
715 Once OpenOCD starts running as a daemon, it waits for connections from
716 clients (Telnet, GDB, Other) and processes the commands issued through
719 If you are having problems, you can enable internal debug messages via
720 the @option{-d} option.
722 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
723 @option{-c} command line switch.
725 To enable debug output (when reporting problems or working on OpenOCD
726 itself), use the @option{-d} command line switch. This sets the
727 @option{debug_level} to "3", outputting the most information,
728 including debug messages. The default setting is "2", outputting only
729 informational messages, warnings and errors. You can also change this
730 setting from within a telnet or gdb session using @command{debug_level<n>}
731 (@pxref{debuglevel,,debug_level}).
733 You can redirect all output from the daemon to a file using the
734 @option{-l <logfile>} switch.
736 Note! OpenOCD will launch the GDB & telnet server even if it can not
737 establish a connection with the target. In general, it is possible for
738 the JTAG controller to be unresponsive until the target is set up
739 correctly via e.g. GDB monitor commands in a GDB init script.
741 @node OpenOCD Project Setup
742 @chapter OpenOCD Project Setup
744 To use OpenOCD with your development projects, you need to do more than
745 just connecting the JTAG adapter hardware (dongle) to your development board
746 and then starting the OpenOCD server.
747 You also need to configure that server so that it knows
748 about that adapter and board, and helps your work.
749 You may also want to connect OpenOCD to GDB, possibly
750 using Eclipse or some other GUI.
752 @section Hooking up the JTAG Adapter
754 Today's most common case is a dongle with a JTAG cable on one side
755 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
756 and a USB cable on the other.
757 Instead of USB, some cables use Ethernet;
758 older ones may use a PC parallel port, or even a serial port.
761 @item @emph{Start with power to your target board turned off},
762 and nothing connected to your JTAG adapter.
763 If you're particularly paranoid, unplug power to the board.
764 It's important to have the ground signal properly set up,
765 unless you are using a JTAG adapter which provides
766 galvanic isolation between the target board and the
769 @item @emph{Be sure it's the right kind of JTAG connector.}
770 If your dongle has a 20-pin ARM connector, you need some kind
771 of adapter (or octopus, see below) to hook it up to
772 boards using 14-pin or 10-pin connectors ... or to 20-pin
773 connectors which don't use ARM's pinout.
775 In the same vein, make sure the voltage levels are compatible.
776 Not all JTAG adapters have the level shifters needed to work
777 with 1.2 Volt boards.
779 @item @emph{Be certain the cable is properly oriented} or you might
780 damage your board. In most cases there are only two possible
781 ways to connect the cable.
782 Connect the JTAG cable from your adapter to the board.
783 Be sure it's firmly connected.
785 In the best case, the connector is keyed to physically
786 prevent you from inserting it wrong.
787 This is most often done using a slot on the board's male connector
788 housing, which must match a key on the JTAG cable's female connector.
789 If there's no housing, then you must look carefully and
790 make sure pin 1 on the cable hooks up to pin 1 on the board.
791 Ribbon cables are frequently all grey except for a wire on one
792 edge, which is red. The red wire is pin 1.
794 Sometimes dongles provide cables where one end is an ``octopus'' of
795 color coded single-wire connectors, instead of a connector block.
796 These are great when converting from one JTAG pinout to another,
797 but are tedious to set up.
798 Use these with connector pinout diagrams to help you match up the
799 adapter signals to the right board pins.
801 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
802 A USB, parallel, or serial port connector will go to the host which
803 you are using to run OpenOCD.
804 For Ethernet, consult the documentation and your network administrator.
806 For USB based JTAG adapters you have an easy sanity check at this point:
807 does the host operating system see the JTAG adapter? If that host is an
808 MS-Windows host, you'll need to install a driver before OpenOCD works.
810 @item @emph{Connect the adapter's power supply, if needed.}
811 This step is primarily for non-USB adapters,
812 but sometimes USB adapters need extra power.
814 @item @emph{Power up the target board.}
815 Unless you just let the magic smoke escape,
816 you're now ready to set up the OpenOCD server
817 so you can use JTAG to work with that board.
821 Talk with the OpenOCD server using
822 telnet (@code{telnet localhost 4444} on many systems) or GDB.
823 @xref{GDB and OpenOCD}.
825 @section Project Directory
827 There are many ways you can configure OpenOCD and start it up.
829 A simple way to organize them all involves keeping a
830 single directory for your work with a given board.
831 When you start OpenOCD from that directory,
832 it searches there first for configuration files, scripts,
833 files accessed through semihosting,
834 and for code you upload to the target board.
835 It is also the natural place to write files,
836 such as log files and data you download from the board.
838 @section Configuration Basics
840 There are two basic ways of configuring OpenOCD, and
841 a variety of ways you can mix them.
842 Think of the difference as just being how you start the server:
845 @item Many @option{-f file} or @option{-c command} options on the command line
846 @item No options, but a @dfn{user config file}
847 in the current directory named @file{openocd.cfg}
850 Here is an example @file{openocd.cfg} file for a setup
851 using a Signalyzer FT2232-based JTAG adapter to talk to
852 a board with an Atmel AT91SAM7X256 microcontroller:
855 source [find interface/signalyzer.cfg]
857 # GDB can also flash my flash!
858 gdb_memory_map enable
859 gdb_flash_program enable
861 source [find target/sam7x256.cfg]
864 Here is the command line equivalent of that configuration:
867 openocd -f interface/signalyzer.cfg \
868 -c "gdb_memory_map enable" \
869 -c "gdb_flash_program enable" \
870 -f target/sam7x256.cfg
873 You could wrap such long command lines in shell scripts,
874 each supporting a different development task.
875 One might re-flash the board with a specific firmware version.
876 Another might set up a particular debugging or run-time environment.
879 At this writing (October 2009) the command line method has
880 problems with how it treats variables.
881 For example, after @option{-c "set VAR value"}, or doing the
882 same in a script, the variable @var{VAR} will have no value
883 that can be tested in a later script.
886 Here we will focus on the simpler solution: one user config
887 file, including basic configuration plus any TCL procedures
888 to simplify your work.
890 @section User Config Files
891 @cindex config file, user
892 @cindex user config file
893 @cindex config file, overview
895 A user configuration file ties together all the parts of a project
897 One of the following will match your situation best:
900 @item Ideally almost everything comes from configuration files
901 provided by someone else.
902 For example, OpenOCD distributes a @file{scripts} directory
903 (probably in @file{/usr/share/openocd/scripts} on Linux).
904 Board and tool vendors can provide these too, as can individual
905 user sites; the @option{-s} command line option lets you say
906 where to find these files. (@xref{Running}.)
907 The AT91SAM7X256 example above works this way.
909 Three main types of non-user configuration file each have their
910 own subdirectory in the @file{scripts} directory:
913 @item @b{interface} -- one for each different debug adapter;
914 @item @b{board} -- one for each different board
915 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
918 Best case: include just two files, and they handle everything else.
919 The first is an interface config file.
920 The second is board-specific, and it sets up the JTAG TAPs and
921 their GDB targets (by deferring to some @file{target.cfg} file),
922 declares all flash memory, and leaves you nothing to do except
926 source [find interface/olimex-jtag-tiny.cfg]
927 source [find board/csb337.cfg]
930 Boards with a single microcontroller often won't need more
931 than the target config file, as in the AT91SAM7X256 example.
932 That's because there is no external memory (flash, DDR RAM), and
933 the board differences are encapsulated by application code.
935 @item Maybe you don't know yet what your board looks like to JTAG.
936 Once you know the @file{interface.cfg} file to use, you may
937 need help from OpenOCD to discover what's on the board.
938 Once you find the JTAG TAPs, you can just search for appropriate
940 configuration files ... or write your own, from the bottom up.
941 @xref{autoprobing,,Autoprobing}.
943 @item You can often reuse some standard config files but
944 need to write a few new ones, probably a @file{board.cfg} file.
945 You will be using commands described later in this User's Guide,
946 and working with the guidelines in the next chapter.
948 For example, there may be configuration files for your JTAG adapter
949 and target chip, but you need a new board-specific config file
950 giving access to your particular flash chips.
951 Or you might need to write another target chip configuration file
952 for a new chip built around the Cortex M3 core.
955 When you write new configuration files, please submit
956 them for inclusion in the next OpenOCD release.
957 For example, a @file{board/newboard.cfg} file will help the
958 next users of that board, and a @file{target/newcpu.cfg}
959 will help support users of any board using that chip.
963 You may may need to write some C code.
964 It may be as simple as a supporting a new ft2232 or parport
965 based adapter; a bit more involved, like a NAND or NOR flash
966 controller driver; or a big piece of work like supporting
967 a new chip architecture.
970 Reuse the existing config files when you can.
971 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
972 You may find a board configuration that's a good example to follow.
974 When you write config files, separate the reusable parts
975 (things every user of that interface, chip, or board needs)
976 from ones specific to your environment and debugging approach.
980 For example, a @code{gdb-attach} event handler that invokes
981 the @command{reset init} command will interfere with debugging
982 early boot code, which performs some of the same actions
983 that the @code{reset-init} event handler does.
986 Likewise, the @command{arm9 vector_catch} command (or
988 its siblings @command{xscale vector_catch}
989 and @command{cortex_m vector_catch}) can be a timesaver
990 during some debug sessions, but don't make everyone use that either.
991 Keep those kinds of debugging aids in your user config file,
992 along with messaging and tracing setup.
993 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
996 You might need to override some defaults.
997 For example, you might need to move, shrink, or back up the target's
998 work area if your application needs much SRAM.
1001 TCP/IP port configuration is another example of something which
1002 is environment-specific, and should only appear in
1003 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1006 @section Project-Specific Utilities
1008 A few project-specific utility
1009 routines may well speed up your work.
1010 Write them, and keep them in your project's user config file.
1012 For example, if you are making a boot loader work on a
1013 board, it's nice to be able to debug the ``after it's
1014 loaded to RAM'' parts separately from the finicky early
1015 code which sets up the DDR RAM controller and clocks.
1016 A script like this one, or a more GDB-aware sibling,
1020 proc ramboot @{ @} @{
1021 # Reset, running the target's "reset-init" scripts
1022 # to initialize clocks and the DDR RAM controller.
1023 # Leave the CPU halted.
1026 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1027 load_image u-boot.bin 0x20000000
1034 Then once that code is working you will need to make it
1035 boot from NOR flash; a different utility would help.
1036 Alternatively, some developers write to flash using GDB.
1037 (You might use a similar script if you're working with a flash
1038 based microcontroller application instead of a boot loader.)
1041 proc newboot @{ @} @{
1042 # Reset, leaving the CPU halted. The "reset-init" event
1043 # proc gives faster access to the CPU and to NOR flash;
1044 # "reset halt" would be slower.
1047 # Write standard version of U-Boot into the first two
1048 # sectors of NOR flash ... the standard version should
1049 # do the same lowlevel init as "reset-init".
1050 flash protect 0 0 1 off
1051 flash erase_sector 0 0 1
1052 flash write_bank 0 u-boot.bin 0x0
1053 flash protect 0 0 1 on
1055 # Reboot from scratch using that new boot loader.
1060 You may need more complicated utility procedures when booting
1062 That often involves an extra bootloader stage,
1063 running from on-chip SRAM to perform DDR RAM setup so it can load
1064 the main bootloader code (which won't fit into that SRAM).
1066 Other helper scripts might be used to write production system images,
1067 involving considerably more than just a three stage bootloader.
1069 @section Target Software Changes
1071 Sometimes you may want to make some small changes to the software
1072 you're developing, to help make JTAG debugging work better.
1073 For example, in C or assembly language code you might
1074 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1075 handling issues like:
1079 @item @b{Watchdog Timers}...
1080 Watchog timers are typically used to automatically reset systems if
1081 some application task doesn't periodically reset the timer. (The
1082 assumption is that the system has locked up if the task can't run.)
1083 When a JTAG debugger halts the system, that task won't be able to run
1084 and reset the timer ... potentially causing resets in the middle of
1085 your debug sessions.
1087 It's rarely a good idea to disable such watchdogs, since their usage
1088 needs to be debugged just like all other parts of your firmware.
1089 That might however be your only option.
1091 Look instead for chip-specific ways to stop the watchdog from counting
1092 while the system is in a debug halt state. It may be simplest to set
1093 that non-counting mode in your debugger startup scripts. You may however
1094 need a different approach when, for example, a motor could be physically
1095 damaged by firmware remaining inactive in a debug halt state. That might
1096 involve a type of firmware mode where that "non-counting" mode is disabled
1097 at the beginning then re-enabled at the end; a watchdog reset might fire
1098 and complicate the debug session, but hardware (or people) would be
1099 protected.@footnote{Note that many systems support a "monitor mode" debug
1100 that is a somewhat cleaner way to address such issues. You can think of
1101 it as only halting part of the system, maybe just one task,
1102 instead of the whole thing.
1103 At this writing, January 2010, OpenOCD based debugging does not support
1104 monitor mode debug, only "halt mode" debug.}
1106 @item @b{ARM Semihosting}...
1107 @cindex ARM semihosting
1108 When linked with a special runtime library provided with many
1109 toolchains@footnote{See chapter 8 "Semihosting" in
1110 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1111 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1112 The CodeSourcery EABI toolchain also includes a semihosting library.},
1113 your target code can use I/O facilities on the debug host. That library
1114 provides a small set of system calls which are handled by OpenOCD.
1115 It can let the debugger provide your system console and a file system,
1116 helping with early debugging or providing a more capable environment
1117 for sometimes-complex tasks like installing system firmware onto
1120 @item @b{ARM Wait-For-Interrupt}...
1121 Many ARM chips synchronize the JTAG clock using the core clock.
1122 Low power states which stop that core clock thus prevent JTAG access.
1123 Idle loops in tasking environments often enter those low power states
1124 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1126 You may want to @emph{disable that instruction} in source code,
1127 or otherwise prevent using that state,
1128 to ensure you can get JTAG access at any time.@footnote{As a more
1129 polite alternative, some processors have special debug-oriented
1130 registers which can be used to change various features including
1131 how the low power states are clocked while debugging.
1132 The STM32 DBGMCU_CR register is an example; at the cost of extra
1133 power consumption, JTAG can be used during low power states.}
1134 For example, the OpenOCD @command{halt} command may not
1135 work for an idle processor otherwise.
1137 @item @b{Delay after reset}...
1138 Not all chips have good support for debugger access
1139 right after reset; many LPC2xxx chips have issues here.
1140 Similarly, applications that reconfigure pins used for
1141 JTAG access as they start will also block debugger access.
1143 To work with boards like this, @emph{enable a short delay loop}
1144 the first thing after reset, before "real" startup activities.
1145 For example, one second's delay is usually more than enough
1146 time for a JTAG debugger to attach, so that
1147 early code execution can be debugged
1148 or firmware can be replaced.
1150 @item @b{Debug Communications Channel (DCC)}...
1151 Some processors include mechanisms to send messages over JTAG.
1152 Many ARM cores support these, as do some cores from other vendors.
1153 (OpenOCD may be able to use this DCC internally, speeding up some
1154 operations like writing to memory.)
1156 Your application may want to deliver various debugging messages
1157 over JTAG, by @emph{linking with a small library of code}
1158 provided with OpenOCD and using the utilities there to send
1159 various kinds of message.
1160 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1164 @section Target Hardware Setup
1166 Chip vendors often provide software development boards which
1167 are highly configurable, so that they can support all options
1168 that product boards may require. @emph{Make sure that any
1169 jumpers or switches match the system configuration you are
1172 Common issues include:
1176 @item @b{JTAG setup} ...
1177 Boards may support more than one JTAG configuration.
1178 Examples include jumpers controlling pullups versus pulldowns
1179 on the nTRST and/or nSRST signals, and choice of connectors
1180 (e.g. which of two headers on the base board,
1181 or one from a daughtercard).
1182 For some Texas Instruments boards, you may need to jumper the
1183 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1185 @item @b{Boot Modes} ...
1186 Complex chips often support multiple boot modes, controlled
1187 by external jumpers. Make sure this is set up correctly.
1188 For example many i.MX boards from NXP need to be jumpered
1189 to "ATX mode" to start booting using the on-chip ROM, when
1190 using second stage bootloader code stored in a NAND flash chip.
1192 Such explicit configuration is common, and not limited to
1193 booting from NAND. You might also need to set jumpers to
1194 start booting using code loaded from an MMC/SD card; external
1195 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1196 flash; some external host; or various other sources.
1199 @item @b{Memory Addressing} ...
1200 Boards which support multiple boot modes may also have jumpers
1201 to configure memory addressing. One board, for example, jumpers
1202 external chipselect 0 (used for booting) to address either
1203 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1204 or NAND flash. When it's jumpered to address NAND flash, that
1205 board must also be told to start booting from on-chip ROM.
1207 Your @file{board.cfg} file may also need to be told this jumper
1208 configuration, so that it can know whether to declare NOR flash
1209 using @command{flash bank} or instead declare NAND flash with
1210 @command{nand device}; and likewise which probe to perform in
1211 its @code{reset-init} handler.
1213 A closely related issue is bus width. Jumpers might need to
1214 distinguish between 8 bit or 16 bit bus access for the flash
1215 used to start booting.
1217 @item @b{Peripheral Access} ...
1218 Development boards generally provide access to every peripheral
1219 on the chip, sometimes in multiple modes (such as by providing
1220 multiple audio codec chips).
1221 This interacts with software
1222 configuration of pin multiplexing, where for example a
1223 given pin may be routed either to the MMC/SD controller
1224 or the GPIO controller. It also often interacts with
1225 configuration jumpers. One jumper may be used to route
1226 signals to an MMC/SD card slot or an expansion bus (which
1227 might in turn affect booting); others might control which
1228 audio or video codecs are used.
1232 Plus you should of course have @code{reset-init} event handlers
1233 which set up the hardware to match that jumper configuration.
1234 That includes in particular any oscillator or PLL used to clock
1235 the CPU, and any memory controllers needed to access external
1236 memory and peripherals. Without such handlers, you won't be
1237 able to access those resources without working target firmware
1238 which can do that setup ... this can be awkward when you're
1239 trying to debug that target firmware. Even if there's a ROM
1240 bootloader which handles a few issues, it rarely provides full
1241 access to all board-specific capabilities.
1244 @node Config File Guidelines
1245 @chapter Config File Guidelines
1247 This chapter is aimed at any user who needs to write a config file,
1248 including developers and integrators of OpenOCD and any user who
1249 needs to get a new board working smoothly.
1250 It provides guidelines for creating those files.
1252 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1253 with files including the ones listed here.
1254 Use them as-is where you can; or as models for new files.
1256 @item @file{interface} ...
1257 These are for debug adapters.
1258 Files that configure JTAG adapters go here.
1262 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1263 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1264 at91rm9200.cfg icebear.cfg osbdm.cfg
1265 axm0432.cfg jlink.cfg parport.cfg
1266 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1267 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1268 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1269 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1270 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1271 chameleon.cfg kt-link.cfg signalyzer.cfg
1272 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1273 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1274 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1275 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1276 estick.cfg minimodule.cfg stlink-v2.cfg
1277 flashlink.cfg neodb.cfg stm32-stick.cfg
1278 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1279 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1280 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1281 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1282 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1283 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1284 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1285 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1286 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1289 axm0432.cfg icebear.cfg oocdlink.cfg
1290 calao-usb-a9260-c01.cfg jtagkey2.cfg opendous_ftdi.cfg
1291 calao-usb-a9260-c02.cfg jtagkey2p.cfg openocd-usb.cfg
1292 cortino.cfg jtagkey.cfg openocd-usb-hs.cfg
1293 dlp-usb1232h.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1294 dp_busblaster.cfg kt-link.cfg redbee-econotag.cfg
1295 flossjtag.cfg lisa-l.cfg redbee-usb.cfg
1296 flossjtag-noeeprom.cfg luminary.cfg sheevaplug.cfg
1297 flyswatter2.cfg luminary-icdi.cfg signalyzer.cfg
1298 flyswatter.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1299 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1300 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1301 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1302 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1303 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1304 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1305 hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1308 @item @file{board} ...
1309 think Circuit Board, PWA, PCB, they go by many names. Board files
1310 contain initialization items that are specific to a board.
1311 They reuse target configuration files, since the same
1312 microprocessor chips are used on many boards,
1313 but support for external parts varies widely. For
1314 example, the SDRAM initialization sequence for the board, or the type
1315 of external flash and what address it uses. Any initialization
1316 sequence to enable that external flash or SDRAM should be found in the
1317 board file. Boards may also contain multiple targets: two CPUs; or
1321 actux3.cfg lpc1850_spifi_generic.cfg
1322 am3517evm.cfg lpc4350_spifi_generic.cfg
1323 arm_evaluator7t.cfg lubbock.cfg
1324 at91cap7a-stk-sdram.cfg mcb1700.cfg
1325 at91eb40a.cfg microchip_explorer16.cfg
1326 at91rm9200-dk.cfg mini2440.cfg
1327 at91rm9200-ek.cfg mini6410.cfg
1328 at91sam9261-ek.cfg netgear-dg834v3.cfg
1329 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1330 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1331 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1332 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1333 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1334 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1335 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1336 atmel_sam3u_ek.cfg omap2420_h4.cfg
1337 atmel_sam3x_ek.cfg open-bldc.cfg
1338 atmel_sam4s_ek.cfg openrd.cfg
1339 balloon3-cpu.cfg osk5912.cfg
1340 colibri.cfg phone_se_j100i.cfg
1341 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1342 csb337.cfg pic-p32mx.cfg
1343 csb732.cfg propox_mmnet1001.cfg
1344 da850evm.cfg pxa255_sst.cfg
1345 digi_connectcore_wi-9c.cfg redbee.cfg
1346 diolan_lpc4350-db1.cfg rsc-w910.cfg
1347 dm355evm.cfg sheevaplug.cfg
1348 dm365evm.cfg smdk6410.cfg
1349 dm6446evm.cfg spear300evb.cfg
1350 efikamx.cfg spear300evb_mod.cfg
1351 eir.cfg spear310evb20.cfg
1352 ek-lm3s1968.cfg spear310evb20_mod.cfg
1353 ek-lm3s3748.cfg spear320cpu.cfg
1354 ek-lm3s6965.cfg spear320cpu_mod.cfg
1355 ek-lm3s811.cfg steval_pcc010.cfg
1356 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1357 ek-lm3s8962.cfg stm32100b_eval.cfg
1358 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1359 ek-lm3s9d92.cfg stm3210c_eval.cfg
1360 ek-lm4f120xl.cfg stm3210e_eval.cfg
1361 ek-lm4f232.cfg stm3220g_eval.cfg
1362 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1363 ethernut3.cfg stm3241g_eval.cfg
1364 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1365 hammer.cfg stm32f0discovery.cfg
1366 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1367 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1368 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1369 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1370 hilscher_nxhx50.cfg str910-eval.cfg
1371 hilscher_nxsb100.cfg telo.cfg
1372 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1373 hitex_lpc2929.cfg ti_beagleboard.cfg
1374 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1375 hitex_str9-comstick.cfg ti_beaglebone.cfg
1376 iar_lpc1768.cfg ti_blaze.cfg
1377 iar_str912_sk.cfg ti_pandaboard.cfg
1378 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1379 icnova_sam9g45_sodimm.cfg topas910.cfg
1380 imx27ads.cfg topasa900.cfg
1381 imx27lnst.cfg twr-k60f120m.cfg
1382 imx28evk.cfg twr-k60n512.cfg
1383 imx31pdk.cfg tx25_stk5.cfg
1384 imx35pdk.cfg tx27_stk5.cfg
1385 imx53loco.cfg unknown_at91sam9260.cfg
1386 keil_mcb1700.cfg uptech_2410.cfg
1387 keil_mcb2140.cfg verdex.cfg
1388 kwikstik.cfg voipac.cfg
1389 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1390 lisa-l.cfg x300t.cfg
1391 logicpd_imx27.cfg zy1000.cfg
1394 @item @file{target} ...
1395 think chip. The ``target'' directory represents the JTAG TAPs
1397 which OpenOCD should control, not a board. Two common types of targets
1398 are ARM chips and FPGA or CPLD chips.
1399 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1400 the target config file defines all of them.
1403 aduc702x.cfg lpc1763.cfg
1404 am335x.cfg lpc1764.cfg
1405 amdm37x.cfg lpc1765.cfg
1406 ar71xx.cfg lpc1766.cfg
1407 at32ap7000.cfg lpc1767.cfg
1408 at91r40008.cfg lpc1768.cfg
1409 at91rm9200.cfg lpc1769.cfg
1410 at91sam3ax_4x.cfg lpc1788.cfg
1411 at91sam3ax_8x.cfg lpc17xx.cfg
1412 at91sam3ax_xx.cfg lpc1850.cfg
1413 at91sam3nXX.cfg lpc2103.cfg
1414 at91sam3sXX.cfg lpc2124.cfg
1415 at91sam3u1c.cfg lpc2129.cfg
1416 at91sam3u1e.cfg lpc2148.cfg
1417 at91sam3u2c.cfg lpc2294.cfg
1418 at91sam3u2e.cfg lpc2378.cfg
1419 at91sam3u4c.cfg lpc2460.cfg
1420 at91sam3u4e.cfg lpc2478.cfg
1421 at91sam3uxx.cfg lpc2900.cfg
1422 at91sam3XXX.cfg lpc2xxx.cfg
1423 at91sam4sd32x.cfg lpc3131.cfg
1424 at91sam4sXX.cfg lpc3250.cfg
1425 at91sam4XXX.cfg lpc4350.cfg
1426 at91sam7se512.cfg lpc4350.cfg.orig
1427 at91sam7sx.cfg mc13224v.cfg
1428 at91sam7x256.cfg nuc910.cfg
1429 at91sam7x512.cfg omap2420.cfg
1430 at91sam9260.cfg omap3530.cfg
1431 at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
1432 at91sam9261.cfg omap4460.cfg
1433 at91sam9263.cfg omap5912.cfg
1434 at91sam9.cfg omapl138.cfg
1435 at91sam9g10.cfg pic32mx.cfg
1436 at91sam9g20.cfg pxa255.cfg
1437 at91sam9g45.cfg pxa270.cfg
1438 at91sam9rl.cfg pxa3xx.cfg
1439 atmega128.cfg readme.txt
1440 avr32.cfg samsung_s3c2410.cfg
1441 c100.cfg samsung_s3c2440.cfg
1442 c100config.tcl samsung_s3c2450.cfg
1443 c100helper.tcl samsung_s3c4510.cfg
1444 c100regs.tcl samsung_s3c6410.cfg
1445 cs351x.cfg sharp_lh79532.cfg
1446 davinci.cfg smp8634.cfg
1447 dragonite.cfg spear3xx.cfg
1448 dsp56321.cfg stellaris.cfg
1449 dsp568013.cfg stellaris_icdi.cfg
1450 dsp568037.cfg stm32f0x_stlink.cfg
1451 efm32_stlink.cfg stm32f1x.cfg
1452 epc9301.cfg stm32f1x_stlink.cfg
1453 faux.cfg stm32f2x.cfg
1454 feroceon.cfg stm32f2x_stlink.cfg
1455 fm3.cfg stm32f3x.cfg
1456 hilscher_netx10.cfg stm32f3x_stlink.cfg
1457 hilscher_netx500.cfg stm32f4x.cfg
1458 hilscher_netx50.cfg stm32f4x_stlink.cfg
1459 icepick.cfg stm32l.cfg
1460 imx21.cfg stm32lx_dual_bank.cfg
1461 imx25.cfg stm32lx_stlink.cfg
1462 imx27.cfg stm32_stlink.cfg
1463 imx28.cfg stm32w108_stlink.cfg
1464 imx31.cfg stm32xl.cfg
1465 imx35.cfg str710.cfg
1466 imx51.cfg str730.cfg
1467 imx53.cfg str750.cfg
1470 is5114.cfg test_reset_syntax_error.cfg
1471 ixp42x.cfg test_syntax_error.cfg
1473 k60.cfg ti_calypso.cfg
1474 lpc1751.cfg ti_dm355.cfg
1475 lpc1752.cfg ti_dm365.cfg
1476 lpc1754.cfg ti_dm6446.cfg
1477 lpc1756.cfg tmpa900.cfg
1478 lpc1758.cfg tmpa910.cfg
1479 lpc1759.cfg u8500.cfg
1481 @item @emph{more} ... browse for other library files which may be useful.
1482 For example, there are various generic and CPU-specific utilities.
1485 The @file{openocd.cfg} user config
1486 file may override features in any of the above files by
1487 setting variables before sourcing the target file, or by adding
1488 commands specific to their situation.
1490 @section Interface Config Files
1492 The user config file
1493 should be able to source one of these files with a command like this:
1496 source [find interface/FOOBAR.cfg]
1499 A preconfigured interface file should exist for every debug adapter
1500 in use today with OpenOCD.
1501 That said, perhaps some of these config files
1502 have only been used by the developer who created it.
1504 A separate chapter gives information about how to set these up.
1505 @xref{Debug Adapter Configuration}.
1506 Read the OpenOCD source code (and Developer's Guide)
1507 if you have a new kind of hardware interface
1508 and need to provide a driver for it.
1510 @section Board Config Files
1511 @cindex config file, board
1512 @cindex board config file
1514 The user config file
1515 should be able to source one of these files with a command like this:
1518 source [find board/FOOBAR.cfg]
1521 The point of a board config file is to package everything
1522 about a given board that user config files need to know.
1523 In summary the board files should contain (if present)
1526 @item One or more @command{source [target/...cfg]} statements
1527 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1528 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1529 @item Target @code{reset} handlers for SDRAM and I/O configuration
1530 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1531 @item All things that are not ``inside a chip''
1534 Generic things inside target chips belong in target config files,
1535 not board config files. So for example a @code{reset-init} event
1536 handler should know board-specific oscillator and PLL parameters,
1537 which it passes to target-specific utility code.
1539 The most complex task of a board config file is creating such a
1540 @code{reset-init} event handler.
1541 Define those handlers last, after you verify the rest of the board
1542 configuration works.
1544 @subsection Communication Between Config files
1546 In addition to target-specific utility code, another way that
1547 board and target config files communicate is by following a
1548 convention on how to use certain variables.
1550 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1551 Thus the rule we follow in OpenOCD is this: Variables that begin with
1552 a leading underscore are temporary in nature, and can be modified and
1553 used at will within a target configuration file.
1555 Complex board config files can do the things like this,
1556 for a board with three chips:
1559 # Chip #1: PXA270 for network side, big endian
1560 set CHIPNAME network
1562 source [find target/pxa270.cfg]
1563 # on return: _TARGETNAME = network.cpu
1564 # other commands can refer to the "network.cpu" target.
1565 $_TARGETNAME configure .... events for this CPU..
1567 # Chip #2: PXA270 for video side, little endian
1570 source [find target/pxa270.cfg]
1571 # on return: _TARGETNAME = video.cpu
1572 # other commands can refer to the "video.cpu" target.
1573 $_TARGETNAME configure .... events for this CPU..
1575 # Chip #3: Xilinx FPGA for glue logic
1578 source [find target/spartan3.cfg]
1581 That example is oversimplified because it doesn't show any flash memory,
1582 or the @code{reset-init} event handlers to initialize external DRAM
1583 or (assuming it needs it) load a configuration into the FPGA.
1584 Such features are usually needed for low-level work with many boards,
1585 where ``low level'' implies that the board initialization software may
1586 not be working. (That's a common reason to need JTAG tools. Another
1587 is to enable working with microcontroller-based systems, which often
1588 have no debugging support except a JTAG connector.)
1590 Target config files may also export utility functions to board and user
1591 config files. Such functions should use name prefixes, to help avoid
1594 Board files could also accept input variables from user config files.
1595 For example, there might be a @code{J4_JUMPER} setting used to identify
1596 what kind of flash memory a development board is using, or how to set
1597 up other clocks and peripherals.
1599 @subsection Variable Naming Convention
1600 @cindex variable names
1602 Most boards have only one instance of a chip.
1603 However, it should be easy to create a board with more than
1604 one such chip (as shown above).
1605 Accordingly, we encourage these conventions for naming
1606 variables associated with different @file{target.cfg} files,
1607 to promote consistency and
1608 so that board files can override target defaults.
1610 Inputs to target config files include:
1613 @item @code{CHIPNAME} ...
1614 This gives a name to the overall chip, and is used as part of
1615 tap identifier dotted names.
1616 While the default is normally provided by the chip manufacturer,
1617 board files may need to distinguish between instances of a chip.
1618 @item @code{ENDIAN} ...
1619 By default @option{little} - although chips may hard-wire @option{big}.
1620 Chips that can't change endianness don't need to use this variable.
1621 @item @code{CPUTAPID} ...
1622 When OpenOCD examines the JTAG chain, it can be told verify the
1623 chips against the JTAG IDCODE register.
1624 The target file will hold one or more defaults, but sometimes the
1625 chip in a board will use a different ID (perhaps a newer revision).
1628 Outputs from target config files include:
1631 @item @code{_TARGETNAME} ...
1632 By convention, this variable is created by the target configuration
1633 script. The board configuration file may make use of this variable to
1634 configure things like a ``reset init'' script, or other things
1635 specific to that board and that target.
1636 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1637 @code{_TARGETNAME1}, ... etc.
1640 @subsection The reset-init Event Handler
1641 @cindex event, reset-init
1642 @cindex reset-init handler
1644 Board config files run in the OpenOCD configuration stage;
1645 they can't use TAPs or targets, since they haven't been
1647 This means you can't write memory or access chip registers;
1648 you can't even verify that a flash chip is present.
1649 That's done later in event handlers, of which the target @code{reset-init}
1650 handler is one of the most important.
1652 Except on microcontrollers, the basic job of @code{reset-init} event
1653 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1654 Microcontrollers rarely use boot loaders; they run right out of their
1655 on-chip flash and SRAM memory. But they may want to use one of these
1656 handlers too, if just for developer convenience.
1659 Because this is so very board-specific, and chip-specific, no examples
1661 Instead, look at the board config files distributed with OpenOCD.
1662 If you have a boot loader, its source code will help; so will
1663 configuration files for other JTAG tools
1664 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1667 Some of this code could probably be shared between different boards.
1668 For example, setting up a DRAM controller often doesn't differ by
1669 much except the bus width (16 bits or 32?) and memory timings, so a
1670 reusable TCL procedure loaded by the @file{target.cfg} file might take
1671 those as parameters.
1672 Similarly with oscillator, PLL, and clock setup;
1673 and disabling the watchdog.
1674 Structure the code cleanly, and provide comments to help
1675 the next developer doing such work.
1676 (@emph{You might be that next person} trying to reuse init code!)
1678 The last thing normally done in a @code{reset-init} handler is probing
1679 whatever flash memory was configured. For most chips that needs to be
1680 done while the associated target is halted, either because JTAG memory
1681 access uses the CPU or to prevent conflicting CPU access.
1683 @subsection JTAG Clock Rate
1685 Before your @code{reset-init} handler has set up
1686 the PLLs and clocking, you may need to run with
1687 a low JTAG clock rate.
1688 @xref{jtagspeed,,JTAG Speed}.
1689 Then you'd increase that rate after your handler has
1690 made it possible to use the faster JTAG clock.
1691 When the initial low speed is board-specific, for example
1692 because it depends on a board-specific oscillator speed, then
1693 you should probably set it up in the board config file;
1694 if it's target-specific, it belongs in the target config file.
1696 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1697 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1698 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1699 Consult chip documentation to determine the peak JTAG clock rate,
1700 which might be less than that.
1703 On most ARMs, JTAG clock detection is coupled to the core clock, so
1704 software using a @option{wait for interrupt} operation blocks JTAG access.
1705 Adaptive clocking provides a partial workaround, but a more complete
1706 solution just avoids using that instruction with JTAG debuggers.
1709 If both the chip and the board support adaptive clocking,
1710 use the @command{jtag_rclk}
1711 command, in case your board is used with JTAG adapter which
1712 also supports it. Otherwise use @command{adapter_khz}.
1713 Set the slow rate at the beginning of the reset sequence,
1714 and the faster rate as soon as the clocks are at full speed.
1716 @anchor{theinitboardprocedure}
1717 @subsection The init_board procedure
1718 @cindex init_board procedure
1720 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1721 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1722 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1723 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1724 spearate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1725 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1726 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1727 Additionally ``linear'' board config file will most likely fail when target config file uses
1728 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1729 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1730 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1731 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1733 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1734 the original), allowing greater code reuse.
1737 ### board_file.cfg ###
1739 # source target file that does most of the config in init_targets
1740 source [find target/target.cfg]
1742 proc enable_fast_clock @{@} @{
1743 # enables fast on-board clock source
1744 # configures the chip to use it
1747 # initialize only board specifics - reset, clock, adapter frequency
1748 proc init_board @{@} @{
1749 reset_config trst_and_srst trst_pulls_srst
1751 $_TARGETNAME configure -event reset-init @{
1759 @section Target Config Files
1760 @cindex config file, target
1761 @cindex target config file
1763 Board config files communicate with target config files using
1764 naming conventions as described above, and may source one or
1765 more target config files like this:
1768 source [find target/FOOBAR.cfg]
1771 The point of a target config file is to package everything
1772 about a given chip that board config files need to know.
1773 In summary the target files should contain
1777 @item Add TAPs to the scan chain
1778 @item Add CPU targets (includes GDB support)
1779 @item CPU/Chip/CPU-Core specific features
1783 As a rule of thumb, a target file sets up only one chip.
1784 For a microcontroller, that will often include a single TAP,
1785 which is a CPU needing a GDB target, and its on-chip flash.
1787 More complex chips may include multiple TAPs, and the target
1788 config file may need to define them all before OpenOCD
1789 can talk to the chip.
1790 For example, some phone chips have JTAG scan chains that include
1791 an ARM core for operating system use, a DSP,
1792 another ARM core embedded in an image processing engine,
1793 and other processing engines.
1795 @subsection Default Value Boiler Plate Code
1797 All target configuration files should start with code like this,
1798 letting board config files express environment-specific
1799 differences in how things should be set up.
1802 # Boards may override chip names, perhaps based on role,
1803 # but the default should match what the vendor uses
1804 if @{ [info exists CHIPNAME] @} @{
1805 set _CHIPNAME $CHIPNAME
1807 set _CHIPNAME sam7x256
1810 # ONLY use ENDIAN with targets that can change it.
1811 if @{ [info exists ENDIAN] @} @{
1817 # TAP identifiers may change as chips mature, for example with
1818 # new revision fields (the "3" here). Pick a good default; you
1819 # can pass several such identifiers to the "jtag newtap" command.
1820 if @{ [info exists CPUTAPID ] @} @{
1821 set _CPUTAPID $CPUTAPID
1823 set _CPUTAPID 0x3f0f0f0f
1826 @c but 0x3f0f0f0f is for an str73x part ...
1828 @emph{Remember:} Board config files may include multiple target
1829 config files, or the same target file multiple times
1830 (changing at least @code{CHIPNAME}).
1832 Likewise, the target configuration file should define
1833 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1834 use it later on when defining debug targets:
1837 set _TARGETNAME $_CHIPNAME.cpu
1838 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1841 @subsection Adding TAPs to the Scan Chain
1842 After the ``defaults'' are set up,
1843 add the TAPs on each chip to the JTAG scan chain.
1844 @xref{TAP Declaration}, and the naming convention
1847 In the simplest case the chip has only one TAP,
1848 probably for a CPU or FPGA.
1849 The config file for the Atmel AT91SAM7X256
1850 looks (in part) like this:
1853 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1856 A board with two such at91sam7 chips would be able
1857 to source such a config file twice, with different
1858 values for @code{CHIPNAME}, so
1859 it adds a different TAP each time.
1861 If there are nonzero @option{-expected-id} values,
1862 OpenOCD attempts to verify the actual tap id against those values.
1863 It will issue error messages if there is mismatch, which
1864 can help to pinpoint problems in OpenOCD configurations.
1867 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1868 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1869 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1870 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1871 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1874 There are more complex examples too, with chips that have
1875 multiple TAPs. Ones worth looking at include:
1878 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1879 plus a JRC to enable them
1880 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1881 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1882 is not currently used)
1885 @subsection Add CPU targets
1887 After adding a TAP for a CPU, you should set it up so that
1888 GDB and other commands can use it.
1889 @xref{CPU Configuration}.
1890 For the at91sam7 example above, the command can look like this;
1891 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1892 to little endian, and this chip doesn't support changing that.
1895 set _TARGETNAME $_CHIPNAME.cpu
1896 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1899 Work areas are small RAM areas associated with CPU targets.
1900 They are used by OpenOCD to speed up downloads,
1901 and to download small snippets of code to program flash chips.
1902 If the chip includes a form of ``on-chip-ram'' - and many do - define
1903 a work area if you can.
1904 Again using the at91sam7 as an example, this can look like:
1907 $_TARGETNAME configure -work-area-phys 0x00200000 \
1908 -work-area-size 0x4000 -work-area-backup 0
1911 @anchor{definecputargetsworkinginsmp}
1912 @subsection Define CPU targets working in SMP
1914 After setting targets, you can define a list of targets working in SMP.
1917 set _TARGETNAME_1 $_CHIPNAME.cpu1
1918 set _TARGETNAME_2 $_CHIPNAME.cpu2
1919 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1920 -coreid 0 -dbgbase $_DAP_DBG1
1921 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1922 -coreid 1 -dbgbase $_DAP_DBG2
1923 #define 2 targets working in smp.
1924 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1926 In the above example on cortex_a, 2 cpus are working in SMP.
1927 In SMP only one GDB instance is created and :
1929 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1930 @item halt command triggers the halt of all targets in the list.
1931 @item resume command triggers the write context and the restart of all targets in the list.
1932 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1933 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1934 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1937 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1938 command have been implemented.
1940 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1941 @item cortex_a smp_off : disable SMP mode, the current target is the one
1942 displayed in the GDB session, only this target is now controlled by GDB
1943 session. This behaviour is useful during system boot up.
1944 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1951 #0 : coreid 0 is displayed to GDB ,
1952 #-> -1 : next resume triggers a real resume
1953 > cortex_a smp_gdb 1
1955 #0 :coreid 0 is displayed to GDB ,
1956 #->1 : next resume displays coreid 1 to GDB
1960 #1 :coreid 1 is displayed to GDB ,
1961 #->1 : next resume displays coreid 1 to GDB
1962 > cortex_a smp_gdb -1
1964 #1 :coreid 1 is displayed to GDB,
1965 #->-1 : next resume triggers a real resume
1969 @subsection Chip Reset Setup
1971 As a rule, you should put the @command{reset_config} command
1972 into the board file. Most things you think you know about a
1973 chip can be tweaked by the board.
1975 Some chips have specific ways the TRST and SRST signals are
1976 managed. In the unusual case that these are @emph{chip specific}
1977 and can never be changed by board wiring, they could go here.
1978 For example, some chips can't support JTAG debugging without
1981 Provide a @code{reset-assert} event handler if you can.
1982 Such a handler uses JTAG operations to reset the target,
1983 letting this target config be used in systems which don't
1984 provide the optional SRST signal, or on systems where you
1985 don't want to reset all targets at once.
1986 Such a handler might write to chip registers to force a reset,
1987 use a JRC to do that (preferable -- the target may be wedged!),
1988 or force a watchdog timer to trigger.
1989 (For Cortex-M targets, this is not necessary. The target
1990 driver knows how to use trigger an NVIC reset when SRST is
1993 Some chips need special attention during reset handling if
1994 they're going to be used with JTAG.
1995 An example might be needing to send some commands right
1996 after the target's TAP has been reset, providing a
1997 @code{reset-deassert-post} event handler that writes a chip
1998 register to report that JTAG debugging is being done.
1999 Another would be reconfiguring the watchdog so that it stops
2000 counting while the core is halted in the debugger.
2002 JTAG clocking constraints often change during reset, and in
2003 some cases target config files (rather than board config files)
2004 are the right places to handle some of those issues.
2005 For example, immediately after reset most chips run using a
2006 slower clock than they will use later.
2007 That means that after reset (and potentially, as OpenOCD
2008 first starts up) they must use a slower JTAG clock rate
2009 than they will use later.
2010 @xref{jtagspeed,,JTAG Speed}.
2012 @quotation Important
2013 When you are debugging code that runs right after chip
2014 reset, getting these issues right is critical.
2015 In particular, if you see intermittent failures when
2016 OpenOCD verifies the scan chain after reset,
2017 look at how you are setting up JTAG clocking.
2020 @anchor{theinittargetsprocedure}
2021 @subsection The init_targets procedure
2022 @cindex init_targets procedure
2024 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2025 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2026 procedure called @code{init_targets}, which will be executed when entering run stage
2027 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2028 Such procedure can be overriden by ``next level'' script (which sources the original).
2029 This concept faciliates code reuse when basic target config files provide generic configuration
2030 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2031 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2032 because sourcing them executes every initialization commands they provide.
2035 ### generic_file.cfg ###
2037 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2038 # basic initialization procedure ...
2041 proc init_targets @{@} @{
2042 # initializes generic chip with 4kB of flash and 1kB of RAM
2043 setup_my_chip MY_GENERIC_CHIP 4096 1024
2046 ### specific_file.cfg ###
2048 source [find target/generic_file.cfg]
2050 proc init_targets @{@} @{
2051 # initializes specific chip with 128kB of flash and 64kB of RAM
2052 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2056 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2057 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2059 For an example of this scheme see LPC2000 target config files.
2061 The @code{init_boards} procedure is a similar concept concerning board config files
2062 (@xref{theinitboardprocedure,,The init_board procedure}.)
2064 @subsection ARM Core Specific Hacks
2066 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2067 special high speed download features - enable it.
2069 If present, the MMU, the MPU and the CACHE should be disabled.
2071 Some ARM cores are equipped with trace support, which permits
2072 examination of the instruction and data bus activity. Trace
2073 activity is controlled through an ``Embedded Trace Module'' (ETM)
2074 on one of the core's scan chains. The ETM emits voluminous data
2075 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2076 If you are using an external trace port,
2077 configure it in your board config file.
2078 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2079 configure it in your target config file.
2082 etm config $_TARGETNAME 16 normal full etb
2083 etb config $_TARGETNAME $_CHIPNAME.etb
2086 @subsection Internal Flash Configuration
2088 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2090 @b{Never ever} in the ``target configuration file'' define any type of
2091 flash that is external to the chip. (For example a BOOT flash on
2092 Chip Select 0.) Such flash information goes in a board file - not
2093 the TARGET (chip) file.
2097 @item at91sam7x256 - has 256K flash YES enable it.
2098 @item str912 - has flash internal YES enable it.
2099 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2100 @item pxa270 - again - CS0 flash - it goes in the board file.
2103 @anchor{translatingconfigurationfiles}
2104 @section Translating Configuration Files
2106 If you have a configuration file for another hardware debugger
2107 or toolset (Abatron, BDI2000, BDI3000, CCS,
2108 Lauterbach, Segger, Macraigor, etc.), translating
2109 it into OpenOCD syntax is often quite straightforward. The most tricky
2110 part of creating a configuration script is oftentimes the reset init
2111 sequence where e.g. PLLs, DRAM and the like is set up.
2113 One trick that you can use when translating is to write small
2114 Tcl procedures to translate the syntax into OpenOCD syntax. This
2115 can avoid manual translation errors and make it easier to
2116 convert other scripts later on.
2118 Example of transforming quirky arguments to a simple search and
2122 # Lauterbach syntax(?)
2124 # Data.Set c15:0x042f %long 0x40000015
2126 # OpenOCD syntax when using procedure below.
2128 # setc15 0x01 0x00050078
2130 proc setc15 @{regs value@} @{
2133 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2135 arm mcr 15 [expr ($regs>>12)&0x7] \
2136 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2137 [expr ($regs>>8)&0x7] $value
2143 @node Daemon Configuration
2144 @chapter Daemon Configuration
2145 @cindex initialization
2146 The commands here are commonly found in the openocd.cfg file and are
2147 used to specify what TCP/IP ports are used, and how GDB should be
2150 @anchor{configurationstage}
2151 @section Configuration Stage
2152 @cindex configuration stage
2153 @cindex config command
2155 When the OpenOCD server process starts up, it enters a
2156 @emph{configuration stage} which is the only time that
2157 certain commands, @emph{configuration commands}, may be issued.
2158 Normally, configuration commands are only available
2159 inside startup scripts.
2161 In this manual, the definition of a configuration command is
2162 presented as a @emph{Config Command}, not as a @emph{Command}
2163 which may be issued interactively.
2164 The runtime @command{help} command also highlights configuration
2165 commands, and those which may be issued at any time.
2167 Those configuration commands include declaration of TAPs,
2169 the interface used for JTAG communication,
2170 and other basic setup.
2171 The server must leave the configuration stage before it
2172 may access or activate TAPs.
2173 After it leaves this stage, configuration commands may no
2176 @anchor{enteringtherunstage}
2177 @section Entering the Run Stage
2179 The first thing OpenOCD does after leaving the configuration
2180 stage is to verify that it can talk to the scan chain
2181 (list of TAPs) which has been configured.
2182 It will warn if it doesn't find TAPs it expects to find,
2183 or finds TAPs that aren't supposed to be there.
2184 You should see no errors at this point.
2185 If you see errors, resolve them by correcting the
2186 commands you used to configure the server.
2187 Common errors include using an initial JTAG speed that's too
2188 fast, and not providing the right IDCODE values for the TAPs
2191 Once OpenOCD has entered the run stage, a number of commands
2193 A number of these relate to the debug targets you may have declared.
2194 For example, the @command{mww} command will not be available until
2195 a target has been successfuly instantiated.
2196 If you want to use those commands, you may need to force
2197 entry to the run stage.
2199 @deffn {Config Command} init
2200 This command terminates the configuration stage and
2201 enters the run stage. This helps when you need to have
2202 the startup scripts manage tasks such as resetting the target,
2203 programming flash, etc. To reset the CPU upon startup, add "init" and
2204 "reset" at the end of the config script or at the end of the OpenOCD
2205 command line using the @option{-c} command line switch.
2207 If this command does not appear in any startup/configuration file
2208 OpenOCD executes the command for you after processing all
2209 configuration files and/or command line options.
2211 @b{NOTE:} This command normally occurs at or near the end of your
2212 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2213 targets ready. For example: If your openocd.cfg file needs to
2214 read/write memory on your target, @command{init} must occur before
2215 the memory read/write commands. This includes @command{nand probe}.
2218 @deffn {Overridable Procedure} jtag_init
2219 This is invoked at server startup to verify that it can talk
2220 to the scan chain (list of TAPs) which has been configured.
2222 The default implementation first tries @command{jtag arp_init},
2223 which uses only a lightweight JTAG reset before examining the
2225 If that fails, it tries again, using a harder reset
2226 from the overridable procedure @command{init_reset}.
2228 Implementations must have verified the JTAG scan chain before
2230 This is done by calling @command{jtag arp_init}
2231 (or @command{jtag arp_init-reset}).
2235 @section TCP/IP Ports
2240 The OpenOCD server accepts remote commands in several syntaxes.
2241 Each syntax uses a different TCP/IP port, which you may specify
2242 only during configuration (before those ports are opened).
2244 For reasons including security, you may wish to prevent remote
2245 access using one or more of these ports.
2246 In such cases, just specify the relevant port number as zero.
2247 If you disable all access through TCP/IP, you will need to
2248 use the command line @option{-pipe} option.
2250 @deffn {Command} gdb_port [number]
2252 Normally gdb listens to a TCP/IP port, but GDB can also
2253 communicate via pipes(stdin/out or named pipes). The name
2254 "gdb_port" stuck because it covers probably more than 90% of
2255 the normal use cases.
2257 No arguments reports GDB port. "pipe" means listen to stdin
2258 output to stdout, an integer is base port number, "disable"
2259 disables the gdb server.
2261 When using "pipe", also use log_output to redirect the log
2262 output to a file so as not to flood the stdin/out pipes.
2264 The -p/--pipe option is deprecated and a warning is printed
2265 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2267 Any other string is interpreted as named pipe to listen to.
2268 Output pipe is the same name as input pipe, but with 'o' appended,
2269 e.g. /var/gdb, /var/gdbo.
2271 The GDB port for the first target will be the base port, the
2272 second target will listen on gdb_port + 1, and so on.
2273 When not specified during the configuration stage,
2274 the port @var{number} defaults to 3333.
2277 @deffn {Command} tcl_port [number]
2278 Specify or query the port used for a simplified RPC
2279 connection that can be used by clients to issue TCL commands and get the
2280 output from the Tcl engine.
2281 Intended as a machine interface.
2282 When not specified during the configuration stage,
2283 the port @var{number} defaults to 6666.
2287 @deffn {Command} telnet_port [number]
2288 Specify or query the
2289 port on which to listen for incoming telnet connections.
2290 This port is intended for interaction with one human through TCL commands.
2291 When not specified during the configuration stage,
2292 the port @var{number} defaults to 4444.
2293 When specified as zero, this port is not activated.
2296 @anchor{gdbconfiguration}
2297 @section GDB Configuration
2299 @cindex GDB configuration
2300 You can reconfigure some GDB behaviors if needed.
2301 The ones listed here are static and global.
2302 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2303 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2305 @anchor{gdbbreakpointoverride}
2306 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2307 Force breakpoint type for gdb @command{break} commands.
2308 This option supports GDB GUIs which don't
2309 distinguish hard versus soft breakpoints, if the default OpenOCD and
2310 GDB behaviour is not sufficient. GDB normally uses hardware
2311 breakpoints if the memory map has been set up for flash regions.
2314 @anchor{gdbflashprogram}
2315 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2316 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2317 vFlash packet is received.
2318 The default behaviour is @option{enable}.
2321 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2322 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2323 requested. GDB will then know when to set hardware breakpoints, and program flash
2324 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2325 for flash programming to work.
2326 Default behaviour is @option{enable}.
2327 @xref{gdbflashprogram,,gdb_flash_program}.
2330 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2331 Specifies whether data aborts cause an error to be reported
2332 by GDB memory read packets.
2333 The default behaviour is @option{disable};
2334 use @option{enable} see these errors reported.
2337 @anchor{eventpolling}
2338 @section Event Polling
2340 Hardware debuggers are parts of asynchronous systems,
2341 where significant events can happen at any time.
2342 The OpenOCD server needs to detect some of these events,
2343 so it can report them to through TCL command line
2346 Examples of such events include:
2349 @item One of the targets can stop running ... maybe it triggers
2350 a code breakpoint or data watchpoint, or halts itself.
2351 @item Messages may be sent over ``debug message'' channels ... many
2352 targets support such messages sent over JTAG,
2353 for receipt by the person debugging or tools.
2354 @item Loss of power ... some adapters can detect these events.
2355 @item Resets not issued through JTAG ... such reset sources
2356 can include button presses or other system hardware, sometimes
2357 including the target itself (perhaps through a watchdog).
2358 @item Debug instrumentation sometimes supports event triggering
2359 such as ``trace buffer full'' (so it can quickly be emptied)
2360 or other signals (to correlate with code behavior).
2363 None of those events are signaled through standard JTAG signals.
2364 However, most conventions for JTAG connectors include voltage
2365 level and system reset (SRST) signal detection.
2366 Some connectors also include instrumentation signals, which
2367 can imply events when those signals are inputs.
2369 In general, OpenOCD needs to periodically check for those events,
2370 either by looking at the status of signals on the JTAG connector
2371 or by sending synchronous ``tell me your status'' JTAG requests
2372 to the various active targets.
2373 There is a command to manage and monitor that polling,
2374 which is normally done in the background.
2376 @deffn Command poll [@option{on}|@option{off}]
2377 Poll the current target for its current state.
2378 (Also, @pxref{targetcurstate,,target curstate}.)
2379 If that target is in debug mode, architecture
2380 specific information about the current state is printed.
2381 An optional parameter
2382 allows background polling to be enabled and disabled.
2384 You could use this from the TCL command shell, or
2385 from GDB using @command{monitor poll} command.
2386 Leave background polling enabled while you're using GDB.
2389 background polling: on
2390 target state: halted
2391 target halted in ARM state due to debug-request, \
2392 current mode: Supervisor
2393 cpsr: 0x800000d3 pc: 0x11081bfc
2394 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2399 @node Debug Adapter Configuration
2400 @chapter Debug Adapter Configuration
2401 @cindex config file, interface
2402 @cindex interface config file
2404 Correctly installing OpenOCD includes making your operating system give
2405 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2406 are used to select which one is used, and to configure how it is used.
2409 Because OpenOCD started out with a focus purely on JTAG, you may find
2410 places where it wrongly presumes JTAG is the only transport protocol
2411 in use. Be aware that recent versions of OpenOCD are removing that
2412 limitation. JTAG remains more functional than most other transports.
2413 Other transports do not support boundary scan operations, or may be
2414 specific to a given chip vendor. Some might be usable only for
2415 programming flash memory, instead of also for debugging.
2418 Debug Adapters/Interfaces/Dongles are normally configured
2419 through commands in an interface configuration
2420 file which is sourced by your @file{openocd.cfg} file, or
2421 through a command line @option{-f interface/....cfg} option.
2424 source [find interface/olimex-jtag-tiny.cfg]
2428 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2429 A few cases are so simple that you only need to say what driver to use:
2436 Most adapters need a bit more configuration than that.
2439 @section Interface Configuration
2441 The interface command tells OpenOCD what type of debug adapter you are
2442 using. Depending on the type of adapter, you may need to use one or
2443 more additional commands to further identify or configure the adapter.
2445 @deffn {Config Command} {interface} name
2446 Use the interface driver @var{name} to connect to the
2450 @deffn Command {interface_list}
2451 List the debug adapter drivers that have been built into
2452 the running copy of OpenOCD.
2454 @deffn Command {interface transports} transport_name+
2455 Specifies the transports supported by this debug adapter.
2456 The adapter driver builds-in similar knowledge; use this only
2457 when external configuration (such as jumpering) changes what
2458 the hardware can support.
2463 @deffn Command {adapter_name}
2464 Returns the name of the debug adapter driver being used.
2467 @section Interface Drivers
2469 Each of the interface drivers listed here must be explicitly
2470 enabled when OpenOCD is configured, in order to be made
2471 available at run time.
2473 @deffn {Interface Driver} {amt_jtagaccel}
2474 Amontec Chameleon in its JTAG Accelerator configuration,
2475 connected to a PC's EPP mode parallel port.
2476 This defines some driver-specific commands:
2478 @deffn {Config Command} {parport_port} number
2479 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2480 the number of the @file{/dev/parport} device.
2483 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2484 Displays status of RTCK option.
2485 Optionally sets that option first.
2489 @deffn {Interface Driver} {arm-jtag-ew}
2490 Olimex ARM-JTAG-EW USB adapter
2491 This has one driver-specific command:
2493 @deffn Command {armjtagew_info}
2498 @deffn {Interface Driver} {at91rm9200}
2499 Supports bitbanged JTAG from the local system,
2500 presuming that system is an Atmel AT91rm9200
2501 and a specific set of GPIOs is used.
2502 @c command: at91rm9200_device NAME
2503 @c chooses among list of bit configs ... only one option
2506 @deffn {Interface Driver} {dummy}
2507 A dummy software-only driver for debugging.
2510 @deffn {Interface Driver} {ep93xx}
2511 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2514 @deffn {Interface Driver} {ft2232}
2515 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2517 Note that this driver has several flaws and the @command{ftdi} driver is
2518 recommended as its replacement.
2520 These interfaces have several commands, used to configure the driver
2521 before initializing the JTAG scan chain:
2523 @deffn {Config Command} {ft2232_device_desc} description
2524 Provides the USB device description (the @emph{iProduct string})
2525 of the FTDI FT2232 device. If not
2526 specified, the FTDI default value is used. This setting is only valid
2527 if compiled with FTD2XX support.
2530 @deffn {Config Command} {ft2232_serial} serial-number
2531 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2532 in case the vendor provides unique IDs and more than one FT2232 device
2533 is connected to the host.
2534 If not specified, serial numbers are not considered.
2535 (Note that USB serial numbers can be arbitrary Unicode strings,
2536 and are not restricted to containing only decimal digits.)
2539 @deffn {Config Command} {ft2232_layout} name
2540 Each vendor's FT2232 device can use different GPIO signals
2541 to control output-enables, reset signals, and LEDs.
2542 Currently valid layout @var{name} values include:
2544 @item @b{axm0432_jtag} Axiom AXM-0432
2545 @item @b{comstick} Hitex STR9 comstick
2546 @item @b{cortino} Hitex Cortino JTAG interface
2547 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2548 either for the local Cortex-M3 (SRST only)
2549 or in a passthrough mode (neither SRST nor TRST)
2550 This layout can not support the SWO trace mechanism, and should be
2551 used only for older boards (before rev C).
2552 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2553 eval boards, including Rev C LM3S811 eval boards and the eponymous
2554 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2555 to debug some other target. It can support the SWO trace mechanism.
2556 @item @b{flyswatter} Tin Can Tools Flyswatter
2557 @item @b{icebear} ICEbear JTAG adapter from Section 5
2558 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2559 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2560 @item @b{m5960} American Microsystems M5960
2561 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2562 @item @b{oocdlink} OOCDLink
2563 @c oocdlink ~= jtagkey_prototype_v1
2564 @item @b{redbee-econotag} Integrated with a Redbee development board.
2565 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2566 @item @b{sheevaplug} Marvell Sheevaplug development kit
2567 @item @b{signalyzer} Xverve Signalyzer
2568 @item @b{stm32stick} Hitex STM32 Performance Stick
2569 @item @b{turtelizer2} egnite Software turtelizer2
2570 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2574 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2575 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2576 default values are used.
2577 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2579 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2583 @deffn {Config Command} {ft2232_latency} ms
2584 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2585 ft2232_read() fails to return the expected number of bytes. This can be caused by
2586 USB communication delays and has proved hard to reproduce and debug. Setting the
2587 FT2232 latency timer to a larger value increases delays for short USB packets but it
2588 also reduces the risk of timeouts before receiving the expected number of bytes.
2589 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2592 @deffn {Config Command} {ft2232_channel} channel
2593 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2594 The default value is 1.
2597 For example, the interface config file for a
2598 Turtelizer JTAG Adapter looks something like this:
2602 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2603 ft2232_layout turtelizer2
2604 ft2232_vid_pid 0x0403 0xbdc8
2608 @deffn {Interface Driver} {ftdi}
2609 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2610 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2611 It is a complete rewrite to address a large number of problems with the ft2232
2614 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2615 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2616 consistently faster than the ft2232 driver, sometimes several times faster.
2618 A major improvement of this driver is that support for new FTDI based adapters
2619 can be added competely through configuration files, without the need to patch
2620 and rebuild OpenOCD.
2622 The driver uses a signal abstraction to enable Tcl configuration files to
2623 define outputs for one or several FTDI GPIO. These outputs can then be
2624 controlled using the @command{ftdi_set_signal} command. Special signal names
2625 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2626 will be used for their customary purpose.
2628 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2629 be controlled differently. In order to support tristateable signals such as
2630 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2631 signal. The following output buffer configurations are supported:
2634 @item Push-pull with one FTDI output as (non-)inverted data line
2635 @item Open drain with one FTDI output as (non-)inverted output-enable
2636 @item Tristate with one FTDI output as (non-)inverted data line and another
2637 FTDI output as (non-)inverted output-enable
2638 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2639 switching data and direction as necessary
2642 These interfaces have several commands, used to configure the driver
2643 before initializing the JTAG scan chain:
2645 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2646 The vendor ID and product ID of the adapter. If not specified, the FTDI
2647 default values are used.
2648 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2650 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2654 @deffn {Config Command} {ftdi_device_desc} description
2655 Provides the USB device description (the @emph{iProduct string})
2656 of the adapter. If not specified, the device description is ignored
2657 during device selection.
2660 @deffn {Config Command} {ftdi_serial} serial-number
2661 Specifies the @var{serial-number} of the adapter to use,
2662 in case the vendor provides unique IDs and more than one adapter
2663 is connected to the host.
2664 If not specified, serial numbers are not considered.
2665 (Note that USB serial numbers can be arbitrary Unicode strings,
2666 and are not restricted to containing only decimal digits.)
2669 @deffn {Config Command} {ftdi_channel} channel
2670 Selects the channel of the FTDI device to use for MPSSE operations. Most
2671 adapters use the default, channel 0, but there are exceptions.
2674 @deffn {Config Command} {ftdi_layout_init} data direction
2675 Specifies the initial values of the FTDI GPIO data and direction registers.
2676 Each value is a 16-bit number corresponding to the concatenation of the high
2677 and low FTDI GPIO registers. The values should be selected based on the
2678 schematics of the adapter, such that all signals are set to safe levels with
2679 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2680 and initially asserted reset signals.
2683 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2684 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2685 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2686 register bitmasks to tell the driver the connection and type of the output
2687 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2688 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2689 used with inverting data inputs and @option{-data} with non-inverting inputs.
2690 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2691 not-output-enable) input to the output buffer is connected.
2693 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2694 simple open-collector transistor driver would be specified with @option{-oe}
2695 only. In that case the signal can only be set to drive low or to Hi-Z and the
2696 driver will complain if the signal is set to drive high. Which means that if
2697 it's a reset signal, @command{reset_config} must be specified as
2698 @option{srst_open_drain}, not @option{srst_push_pull}.
2700 A special case is provided when @option{-data} and @option{-oe} is set to the
2701 same bitmask. Then the FTDI pin is considered being connected straight to the
2702 target without any buffer. The FTDI pin is then switched between output and
2703 input as necessary to provide the full set of low, high and Hi-Z
2704 characteristics. In all other cases, the pins specified in a signal definition
2705 are always driven by the FTDI.
2708 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2709 Set a previously defined signal to the specified level.
2711 @item @option{0}, drive low
2712 @item @option{1}, drive high
2713 @item @option{z}, set to high-impedance
2717 For example adapter definitions, see the configuration files shipped in the
2718 @file{interface/ftdi} directory.
2721 @deffn {Interface Driver} {remote_bitbang}
2722 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2723 with a remote process and sends ASCII encoded bitbang requests to that process
2724 instead of directly driving JTAG.
2726 The remote_bitbang driver is useful for debugging software running on
2727 processors which are being simulated.
2729 @deffn {Config Command} {remote_bitbang_port} number
2730 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2731 sockets instead of TCP.
2734 @deffn {Config Command} {remote_bitbang_host} hostname
2735 Specifies the hostname of the remote process to connect to using TCP, or the
2736 name of the UNIX socket to use if remote_bitbang_port is 0.
2739 For example, to connect remotely via TCP to the host foobar you might have
2743 interface remote_bitbang
2744 remote_bitbang_port 3335
2745 remote_bitbang_host foobar
2748 To connect to another process running locally via UNIX sockets with socket
2752 interface remote_bitbang
2753 remote_bitbang_port 0
2754 remote_bitbang_host mysocket
2758 @deffn {Interface Driver} {usb_blaster}
2759 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2760 for FTDI chips. These interfaces have several commands, used to
2761 configure the driver before initializing the JTAG scan chain:
2763 @deffn {Config Command} {usb_blaster_device_desc} description
2764 Provides the USB device description (the @emph{iProduct string})
2765 of the FTDI FT245 device. If not
2766 specified, the FTDI default value is used. This setting is only valid
2767 if compiled with FTD2XX support.
2770 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2771 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2772 default values are used.
2773 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2774 Altera USB-Blaster (default):
2776 usb_blaster_vid_pid 0x09FB 0x6001
2778 The following VID/PID is for Kolja Waschk's USB JTAG:
2780 usb_blaster_vid_pid 0x16C0 0x06AD
2784 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2785 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2786 female JTAG header). These pins can be used as SRST and/or TRST provided the
2787 appropriate connections are made on the target board.
2789 For example, to use pin 6 as SRST (as with an AVR board):
2791 $_TARGETNAME configure -event reset-assert \
2792 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2798 @deffn {Interface Driver} {gw16012}
2799 Gateworks GW16012 JTAG programmer.
2800 This has one driver-specific command:
2802 @deffn {Config Command} {parport_port} [port_number]
2803 Display either the address of the I/O port
2804 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2805 If a parameter is provided, first switch to use that port.
2806 This is a write-once setting.
2810 @deffn {Interface Driver} {jlink}
2811 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2813 @quotation Compatibility Note
2814 Segger released many firmware versions for the many harware versions they
2815 produced. OpenOCD was extensively tested and intended to run on all of them,
2816 but some combinations were reported as incompatible. As a general
2817 recommendation, it is advisable to use the latest firmware version
2818 available for each hardware version. However the current V8 is a moving
2819 target, and Segger firmware versions released after the OpenOCD was
2820 released may not be compatible. In such cases it is recommended to
2821 revert to the last known functional version. For 0.5.0, this is from
2822 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2823 version is from "May 3 2012 18:36:22", packed with 4.46f.
2826 @deffn {Command} {jlink caps}
2827 Display the device firmware capabilities.
2829 @deffn {Command} {jlink info}
2830 Display various device information, like hardware version, firmware version, current bus status.
2832 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2833 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2835 @deffn {Command} {jlink config}
2836 Display the J-Link configuration.
2838 @deffn {Command} {jlink config kickstart} [val]
2839 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2841 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2842 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2844 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2845 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2846 E the bit of the subnet mask and
2847 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2849 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2850 Set the USB address; this will also change the product id. Without argument, show the USB address.
2852 @deffn {Command} {jlink config reset}
2853 Reset the current configuration.
2855 @deffn {Command} {jlink config save}
2856 Save the current configuration to the internal persistent storage.
2858 @deffn {Config} {jlink pid} val
2859 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2863 @deffn {Interface Driver} {parport}
2864 Supports PC parallel port bit-banging cables:
2865 Wigglers, PLD download cable, and more.
2866 These interfaces have several commands, used to configure the driver
2867 before initializing the JTAG scan chain:
2869 @deffn {Config Command} {parport_cable} name
2870 Set the layout of the parallel port cable used to connect to the target.
2871 This is a write-once setting.
2872 Currently valid cable @var{name} values include:
2875 @item @b{altium} Altium Universal JTAG cable.
2876 @item @b{arm-jtag} Same as original wiggler except SRST and
2877 TRST connections reversed and TRST is also inverted.
2878 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2879 in configuration mode. This is only used to
2880 program the Chameleon itself, not a connected target.
2881 @item @b{dlc5} The Xilinx Parallel cable III.
2882 @item @b{flashlink} The ST Parallel cable.
2883 @item @b{lattice} Lattice ispDOWNLOAD Cable
2884 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2886 Amontec's Chameleon Programmer. The new version available from
2887 the website uses the original Wiggler layout ('@var{wiggler}')
2888 @item @b{triton} The parallel port adapter found on the
2889 ``Karo Triton 1 Development Board''.
2890 This is also the layout used by the HollyGates design
2891 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2892 @item @b{wiggler} The original Wiggler layout, also supported by
2893 several clones, such as the Olimex ARM-JTAG
2894 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2895 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2899 @deffn {Config Command} {parport_port} [port_number]
2900 Display either the address of the I/O port
2901 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2902 If a parameter is provided, first switch to use that port.
2903 This is a write-once setting.
2905 When using PPDEV to access the parallel port, use the number of the parallel port:
2906 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2907 you may encounter a problem.
2910 @deffn Command {parport_toggling_time} [nanoseconds]
2911 Displays how many nanoseconds the hardware needs to toggle TCK;
2912 the parport driver uses this value to obey the
2913 @command{adapter_khz} configuration.
2914 When the optional @var{nanoseconds} parameter is given,
2915 that setting is changed before displaying the current value.
2917 The default setting should work reasonably well on commodity PC hardware.
2918 However, you may want to calibrate for your specific hardware.
2920 To measure the toggling time with a logic analyzer or a digital storage
2921 oscilloscope, follow the procedure below:
2923 > parport_toggling_time 1000
2926 This sets the maximum JTAG clock speed of the hardware, but
2927 the actual speed probably deviates from the requested 500 kHz.
2928 Now, measure the time between the two closest spaced TCK transitions.
2929 You can use @command{runtest 1000} or something similar to generate a
2930 large set of samples.
2931 Update the setting to match your measurement:
2933 > parport_toggling_time <measured nanoseconds>
2935 Now the clock speed will be a better match for @command{adapter_khz rate}
2936 commands given in OpenOCD scripts and event handlers.
2938 You can do something similar with many digital multimeters, but note
2939 that you'll probably need to run the clock continuously for several
2940 seconds before it decides what clock rate to show. Adjust the
2941 toggling time up or down until the measured clock rate is a good
2942 match for the adapter_khz rate you specified; be conservative.
2946 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2947 This will configure the parallel driver to write a known
2948 cable-specific value to the parallel interface on exiting OpenOCD.
2951 For example, the interface configuration file for a
2952 classic ``Wiggler'' cable on LPT2 might look something like this:
2957 parport_cable wiggler
2961 @deffn {Interface Driver} {presto}
2962 ASIX PRESTO USB JTAG programmer.
2963 @deffn {Config Command} {presto_serial} serial_string
2964 Configures the USB serial number of the Presto device to use.
2968 @deffn {Interface Driver} {rlink}
2969 Raisonance RLink USB adapter
2972 @deffn {Interface Driver} {usbprog}
2973 usbprog is a freely programmable USB adapter.
2976 @deffn {Interface Driver} {vsllink}
2977 vsllink is part of Versaloon which is a versatile USB programmer.
2980 This defines quite a few driver-specific commands,
2981 which are not currently documented here.
2985 @deffn {Interface Driver} {hla}
2986 This is a driver that supports multiple High Level Adapters.
2987 This type of adapter does not expose some of the lower level api's
2988 that OpenOCD would normally use to access the target.
2990 Currently supported adapters include the ST STLINK and TI ICDI.
2992 @deffn {Config Command} {hla_device_desc} description
2993 Currently Not Supported.
2996 @deffn {Config Command} {hla_serial} serial
2997 Currently Not Supported.
3000 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3001 Specifies the adapter layout to use.
3004 @deffn {Config Command} {hla_vid_pid} vid pid
3005 The vendor ID and product ID of the device.
3008 @deffn {Config Command} {stlink_api} api_level
3009 Manually sets the stlink api used, valid options are 1 or 2. (@b{STLINK Only}).
3013 @deffn {Interface Driver} {opendous}
3014 opendous-jtag is a freely programmable USB adapter.
3017 @deffn {Interface Driver} {ulink}
3018 This is the Keil ULINK v1 JTAG debugger.
3021 @deffn {Interface Driver} {ZY1000}
3022 This is the Zylin ZY1000 JTAG debugger.
3026 This defines some driver-specific commands,
3027 which are not currently documented here.
3030 @deffn Command power [@option{on}|@option{off}]
3031 Turn power switch to target on/off.
3032 No arguments: print status.
3035 @section Transport Configuration
3037 As noted earlier, depending on the version of OpenOCD you use,
3038 and the debug adapter you are using,
3039 several transports may be available to
3040 communicate with debug targets (or perhaps to program flash memory).
3041 @deffn Command {transport list}
3042 displays the names of the transports supported by this
3046 @deffn Command {transport select} transport_name
3047 Select which of the supported transports to use in this OpenOCD session.
3048 The transport must be supported by the debug adapter hardware and by the
3049 version of OPenOCD you are using (including the adapter's driver).
3050 No arguments: returns name of session's selected transport.
3053 @subsection JTAG Transport
3055 JTAG is the original transport supported by OpenOCD, and most
3056 of the OpenOCD commands support it.
3057 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3058 each of which must be explicitly declared.
3059 JTAG supports both debugging and boundary scan testing.
3060 Flash programming support is built on top of debug support.
3061 @subsection SWD Transport
3063 @cindex Serial Wire Debug
3064 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3065 Debug Access Point (DAP, which must be explicitly declared.
3066 (SWD uses fewer signal wires than JTAG.)
3067 SWD is debug-oriented, and does not support boundary scan testing.
3068 Flash programming support is built on top of debug support.
3069 (Some processors support both JTAG and SWD.)
3070 @deffn Command {swd newdap} ...
3071 Declares a single DAP which uses SWD transport.
3072 Parameters are currently the same as "jtag newtap" but this is
3075 @deffn Command {swd wcr trn prescale}
3076 Updates TRN (turnaraound delay) and prescaling.fields of the
3077 Wire Control Register (WCR).
3078 No parameters: displays current settings.
3081 @subsection SPI Transport
3083 @cindex Serial Peripheral Interface
3084 The Serial Peripheral Interface (SPI) is a general purpose transport
3085 which uses four wire signaling. Some processors use it as part of a
3086 solution for flash programming.
3090 JTAG clock setup is part of system setup.
3091 It @emph{does not belong with interface setup} since any interface
3092 only knows a few of the constraints for the JTAG clock speed.
3093 Sometimes the JTAG speed is
3094 changed during the target initialization process: (1) slow at
3095 reset, (2) program the CPU clocks, (3) run fast.
3096 Both the "slow" and "fast" clock rates are functions of the
3097 oscillators used, the chip, the board design, and sometimes
3098 power management software that may be active.
3100 The speed used during reset, and the scan chain verification which
3101 follows reset, can be adjusted using a @code{reset-start}
3102 target event handler.
3103 It can then be reconfigured to a faster speed by a
3104 @code{reset-init} target event handler after it reprograms those
3105 CPU clocks, or manually (if something else, such as a boot loader,
3106 sets up those clocks).
3107 @xref{targetevents,,Target Events}.
3108 When the initial low JTAG speed is a chip characteristic, perhaps
3109 because of a required oscillator speed, provide such a handler
3110 in the target config file.
3111 When that speed is a function of a board-specific characteristic
3112 such as which speed oscillator is used, it belongs in the board
3113 config file instead.
3114 In both cases it's safest to also set the initial JTAG clock rate
3115 to that same slow speed, so that OpenOCD never starts up using a
3116 clock speed that's faster than the scan chain can support.
3120 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3123 If your system supports adaptive clocking (RTCK), configuring
3124 JTAG to use that is probably the most robust approach.
3125 However, it introduces delays to synchronize clocks; so it
3126 may not be the fastest solution.
3128 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3129 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3130 which support adaptive clocking.
3132 @deffn {Command} adapter_khz max_speed_kHz
3133 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3134 JTAG interfaces usually support a limited number of
3135 speeds. The speed actually used won't be faster
3136 than the speed specified.
3138 Chip data sheets generally include a top JTAG clock rate.
3139 The actual rate is often a function of a CPU core clock,
3140 and is normally less than that peak rate.
3141 For example, most ARM cores accept at most one sixth of the CPU clock.
3143 Speed 0 (khz) selects RTCK method.
3144 @xref{faqrtck,,FAQ RTCK}.
3145 If your system uses RTCK, you won't need to change the
3146 JTAG clocking after setup.
3147 Not all interfaces, boards, or targets support ``rtck''.
3148 If the interface device can not
3149 support it, an error is returned when you try to use RTCK.
3152 @defun jtag_rclk fallback_speed_kHz
3153 @cindex adaptive clocking
3155 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3156 If that fails (maybe the interface, board, or target doesn't
3157 support it), falls back to the specified frequency.
3159 # Fall back to 3mhz if RTCK is not supported
3164 @node Reset Configuration
3165 @chapter Reset Configuration
3166 @cindex Reset Configuration
3168 Every system configuration may require a different reset
3169 configuration. This can also be quite confusing.
3170 Resets also interact with @var{reset-init} event handlers,
3171 which do things like setting up clocks and DRAM, and
3172 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3173 They can also interact with JTAG routers.
3174 Please see the various board files for examples.
3177 To maintainers and integrators:
3178 Reset configuration touches several things at once.
3179 Normally the board configuration file
3180 should define it and assume that the JTAG adapter supports
3181 everything that's wired up to the board's JTAG connector.
3183 However, the target configuration file could also make note
3184 of something the silicon vendor has done inside the chip,
3185 which will be true for most (or all) boards using that chip.
3186 And when the JTAG adapter doesn't support everything, the
3187 user configuration file will need to override parts of
3188 the reset configuration provided by other files.
3191 @section Types of Reset
3193 There are many kinds of reset possible through JTAG, but
3194 they may not all work with a given board and adapter.
3195 That's part of why reset configuration can be error prone.
3199 @emph{System Reset} ... the @emph{SRST} hardware signal
3200 resets all chips connected to the JTAG adapter, such as processors,
3201 power management chips, and I/O controllers. Normally resets triggered
3202 with this signal behave exactly like pressing a RESET button.
3204 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3205 just the TAP controllers connected to the JTAG adapter.
3206 Such resets should not be visible to the rest of the system; resetting a
3207 device's TAP controller just puts that controller into a known state.
3209 @emph{Emulation Reset} ... many devices can be reset through JTAG
3210 commands. These resets are often distinguishable from system
3211 resets, either explicitly (a "reset reason" register says so)
3212 or implicitly (not all parts of the chip get reset).
3214 @emph{Other Resets} ... system-on-chip devices often support
3215 several other types of reset.
3216 You may need to arrange that a watchdog timer stops
3217 while debugging, preventing a watchdog reset.
3218 There may be individual module resets.
3221 In the best case, OpenOCD can hold SRST, then reset
3222 the TAPs via TRST and send commands through JTAG to halt the
3223 CPU at the reset vector before the 1st instruction is executed.
3224 Then when it finally releases the SRST signal, the system is
3225 halted under debugger control before any code has executed.
3226 This is the behavior required to support the @command{reset halt}
3227 and @command{reset init} commands; after @command{reset init} a
3228 board-specific script might do things like setting up DRAM.
3229 (@xref{resetcommand,,Reset Command}.)
3231 @anchor{srstandtrstissues}
3232 @section SRST and TRST Issues
3234 Because SRST and TRST are hardware signals, they can have a
3235 variety of system-specific constraints. Some of the most
3240 @item @emph{Signal not available} ... Some boards don't wire
3241 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3242 support such signals even if they are wired up.
3243 Use the @command{reset_config} @var{signals} options to say
3244 when either of those signals is not connected.
3245 When SRST is not available, your code might not be able to rely
3246 on controllers having been fully reset during code startup.
3247 Missing TRST is not a problem, since JTAG-level resets can
3248 be triggered using with TMS signaling.
3250 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3251 adapter will connect SRST to TRST, instead of keeping them separate.
3252 Use the @command{reset_config} @var{combination} options to say
3253 when those signals aren't properly independent.
3255 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3256 delay circuit, reset supervisor, or on-chip features can extend
3257 the effect of a JTAG adapter's reset for some time after the adapter
3258 stops issuing the reset. For example, there may be chip or board
3259 requirements that all reset pulses last for at least a
3260 certain amount of time; and reset buttons commonly have
3261 hardware debouncing.
3262 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3263 commands to say when extra delays are needed.
3265 @item @emph{Drive type} ... Reset lines often have a pullup
3266 resistor, letting the JTAG interface treat them as open-drain
3267 signals. But that's not a requirement, so the adapter may need
3268 to use push/pull output drivers.
3269 Also, with weak pullups it may be advisable to drive
3270 signals to both levels (push/pull) to minimize rise times.
3271 Use the @command{reset_config} @var{trst_type} and
3272 @var{srst_type} parameters to say how to drive reset signals.
3274 @item @emph{Special initialization} ... Targets sometimes need
3275 special JTAG initialization sequences to handle chip-specific
3276 issues (not limited to errata).
3277 For example, certain JTAG commands might need to be issued while
3278 the system as a whole is in a reset state (SRST active)
3279 but the JTAG scan chain is usable (TRST inactive).
3280 Many systems treat combined assertion of SRST and TRST as a
3281 trigger for a harder reset than SRST alone.
3282 Such custom reset handling is discussed later in this chapter.
3285 There can also be other issues.
3286 Some devices don't fully conform to the JTAG specifications.
3287 Trivial system-specific differences are common, such as
3288 SRST and TRST using slightly different names.
3289 There are also vendors who distribute key JTAG documentation for
3290 their chips only to developers who have signed a Non-Disclosure
3293 Sometimes there are chip-specific extensions like a requirement to use
3294 the normally-optional TRST signal (precluding use of JTAG adapters which
3295 don't pass TRST through), or needing extra steps to complete a TAP reset.
3297 In short, SRST and especially TRST handling may be very finicky,
3298 needing to cope with both architecture and board specific constraints.
3300 @section Commands for Handling Resets
3302 @deffn {Command} adapter_nsrst_assert_width milliseconds
3303 Minimum amount of time (in milliseconds) OpenOCD should wait
3304 after asserting nSRST (active-low system reset) before
3305 allowing it to be deasserted.
3308 @deffn {Command} adapter_nsrst_delay milliseconds
3309 How long (in milliseconds) OpenOCD should wait after deasserting
3310 nSRST (active-low system reset) before starting new JTAG operations.
3311 When a board has a reset button connected to SRST line it will
3312 probably have hardware debouncing, implying you should use this.
3315 @deffn {Command} jtag_ntrst_assert_width milliseconds
3316 Minimum amount of time (in milliseconds) OpenOCD should wait
3317 after asserting nTRST (active-low JTAG TAP reset) before
3318 allowing it to be deasserted.
3321 @deffn {Command} jtag_ntrst_delay milliseconds
3322 How long (in milliseconds) OpenOCD should wait after deasserting
3323 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3326 @deffn {Command} reset_config mode_flag ...
3327 This command displays or modifies the reset configuration
3328 of your combination of JTAG board and target in target
3329 configuration scripts.
3331 Information earlier in this section describes the kind of problems
3332 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3333 As a rule this command belongs only in board config files,
3334 describing issues like @emph{board doesn't connect TRST};
3335 or in user config files, addressing limitations derived
3336 from a particular combination of interface and board.
3337 (An unlikely example would be using a TRST-only adapter
3338 with a board that only wires up SRST.)
3340 The @var{mode_flag} options can be specified in any order, but only one
3341 of each type -- @var{signals}, @var{combination}, @var{gates},
3342 @var{trst_type}, @var{srst_type} and @var{connect_type}
3343 -- may be specified at a time.
3344 If you don't provide a new value for a given type, its previous
3345 value (perhaps the default) is unchanged.
3346 For example, this means that you don't need to say anything at all about
3347 TRST just to declare that if the JTAG adapter should want to drive SRST,
3348 it must explicitly be driven high (@option{srst_push_pull}).
3352 @var{signals} can specify which of the reset signals are connected.
3353 For example, If the JTAG interface provides SRST, but the board doesn't
3354 connect that signal properly, then OpenOCD can't use it.
3355 Possible values are @option{none} (the default), @option{trst_only},
3356 @option{srst_only} and @option{trst_and_srst}.
3359 If your board provides SRST and/or TRST through the JTAG connector,
3360 you must declare that so those signals can be used.
3364 The @var{combination} is an optional value specifying broken reset
3365 signal implementations.
3366 The default behaviour if no option given is @option{separate},
3367 indicating everything behaves normally.
3368 @option{srst_pulls_trst} states that the
3369 test logic is reset together with the reset of the system (e.g. NXP
3370 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3371 the system is reset together with the test logic (only hypothetical, I
3372 haven't seen hardware with such a bug, and can be worked around).
3373 @option{combined} implies both @option{srst_pulls_trst} and
3374 @option{trst_pulls_srst}.
3377 The @var{gates} tokens control flags that describe some cases where
3378 JTAG may be unvailable during reset.
3379 @option{srst_gates_jtag} (default)
3380 indicates that asserting SRST gates the
3381 JTAG clock. This means that no communication can happen on JTAG
3382 while SRST is asserted.
3383 Its converse is @option{srst_nogate}, indicating that JTAG commands
3384 can safely be issued while SRST is active.
3387 The @var{connect_type} tokens control flags that describe some cases where
3388 SRST is asserted while connecting to the target. @option{srst_nogate}
3389 is required to use this option.
3390 @option{connect_deassert_srst} (default)
3391 indicates that SRST will not be asserted while connecting to the target.
3392 Its converse is @option{connect_assert_srst}, indicating that SRST will
3393 be asserted before any target connection.
3394 Only some targets support this feature, STM32 and STR9 are examples.
3395 This feature is useful if you are unable to connect to your target due
3396 to incorrect options byte config or illegal program execution.
3399 The optional @var{trst_type} and @var{srst_type} parameters allow the
3400 driver mode of each reset line to be specified. These values only affect
3401 JTAG interfaces with support for different driver modes, like the Amontec
3402 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3403 relevant signal (TRST or SRST) is not connected.
3407 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3408 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3409 Most boards connect this signal to a pulldown, so the JTAG TAPs
3410 never leave reset unless they are hooked up to a JTAG adapter.
3413 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3414 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3415 Most boards connect this signal to a pullup, and allow the
3416 signal to be pulled low by various events including system
3417 powerup and pressing a reset button.
3421 @section Custom Reset Handling
3424 OpenOCD has several ways to help support the various reset
3425 mechanisms provided by chip and board vendors.
3426 The commands shown in the previous section give standard parameters.
3427 There are also @emph{event handlers} associated with TAPs or Targets.
3428 Those handlers are Tcl procedures you can provide, which are invoked
3429 at particular points in the reset sequence.
3431 @emph{When SRST is not an option} you must set
3432 up a @code{reset-assert} event handler for your target.
3433 For example, some JTAG adapters don't include the SRST signal;
3434 and some boards have multiple targets, and you won't always
3435 want to reset everything at once.
3437 After configuring those mechanisms, you might still
3438 find your board doesn't start up or reset correctly.
3439 For example, maybe it needs a slightly different sequence
3440 of SRST and/or TRST manipulations, because of quirks that
3441 the @command{reset_config} mechanism doesn't address;
3442 or asserting both might trigger a stronger reset, which
3443 needs special attention.
3445 Experiment with lower level operations, such as @command{jtag_reset}
3446 and the @command{jtag arp_*} operations shown here,
3447 to find a sequence of operations that works.
3448 @xref{JTAG Commands}.
3449 When you find a working sequence, it can be used to override
3450 @command{jtag_init}, which fires during OpenOCD startup
3451 (@pxref{configurationstage,,Configuration Stage});
3452 or @command{init_reset}, which fires during reset processing.
3454 You might also want to provide some project-specific reset
3455 schemes. For example, on a multi-target board the standard
3456 @command{reset} command would reset all targets, but you
3457 may need the ability to reset only one target at time and
3458 thus want to avoid using the board-wide SRST signal.
3460 @deffn {Overridable Procedure} init_reset mode
3461 This is invoked near the beginning of the @command{reset} command,
3462 usually to provide as much of a cold (power-up) reset as practical.
3463 By default it is also invoked from @command{jtag_init} if
3464 the scan chain does not respond to pure JTAG operations.
3465 The @var{mode} parameter is the parameter given to the
3466 low level reset command (@option{halt},
3467 @option{init}, or @option{run}), @option{setup},
3468 or potentially some other value.
3470 The default implementation just invokes @command{jtag arp_init-reset}.
3471 Replacements will normally build on low level JTAG
3472 operations such as @command{jtag_reset}.
3473 Operations here must not address individual TAPs
3474 (or their associated targets)
3475 until the JTAG scan chain has first been verified to work.
3477 Implementations must have verified the JTAG scan chain before
3479 This is done by calling @command{jtag arp_init}
3480 (or @command{jtag arp_init-reset}).
3483 @deffn Command {jtag arp_init}
3484 This validates the scan chain using just the four
3485 standard JTAG signals (TMS, TCK, TDI, TDO).
3486 It starts by issuing a JTAG-only reset.
3487 Then it performs checks to verify that the scan chain configuration
3488 matches the TAPs it can observe.
3489 Those checks include checking IDCODE values for each active TAP,
3490 and verifying the length of their instruction registers using
3491 TAP @code{-ircapture} and @code{-irmask} values.
3492 If these tests all pass, TAP @code{setup} events are
3493 issued to all TAPs with handlers for that event.
3496 @deffn Command {jtag arp_init-reset}
3497 This uses TRST and SRST to try resetting
3498 everything on the JTAG scan chain
3499 (and anything else connected to SRST).
3500 It then invokes the logic of @command{jtag arp_init}.
3504 @node TAP Declaration
3505 @chapter TAP Declaration
3506 @cindex TAP declaration
3507 @cindex TAP configuration
3509 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3510 TAPs serve many roles, including:
3513 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3514 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3515 Others do it indirectly, making a CPU do it.
3516 @item @b{Program Download} Using the same CPU support GDB uses,
3517 you can initialize a DRAM controller, download code to DRAM, and then
3518 start running that code.
3519 @item @b{Boundary Scan} Most chips support boundary scan, which
3520 helps test for board assembly problems like solder bridges
3521 and missing connections
3524 OpenOCD must know about the active TAPs on your board(s).
3525 Setting up the TAPs is the core task of your configuration files.
3526 Once those TAPs are set up, you can pass their names to code
3527 which sets up CPUs and exports them as GDB targets,
3528 probes flash memory, performs low-level JTAG operations, and more.
3530 @section Scan Chains
3533 TAPs are part of a hardware @dfn{scan chain},
3534 which is daisy chain of TAPs.
3535 They also need to be added to
3536 OpenOCD's software mirror of that hardware list,
3537 giving each member a name and associating other data with it.
3538 Simple scan chains, with a single TAP, are common in
3539 systems with a single microcontroller or microprocessor.
3540 More complex chips may have several TAPs internally.
3541 Very complex scan chains might have a dozen or more TAPs:
3542 several in one chip, more in the next, and connecting
3543 to other boards with their own chips and TAPs.
3545 You can display the list with the @command{scan_chain} command.
3546 (Don't confuse this with the list displayed by the @command{targets}
3547 command, presented in the next chapter.
3548 That only displays TAPs for CPUs which are configured as
3550 Here's what the scan chain might look like for a chip more than one TAP:
3553 TapName Enabled IdCode Expected IrLen IrCap IrMask
3554 -- ------------------ ------- ---------- ---------- ----- ----- ------
3555 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3556 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3557 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3560 OpenOCD can detect some of that information, but not all
3561 of it. @xref{autoprobing,,Autoprobing}.
3562 Unfortunately those TAPs can't always be autoconfigured,
3563 because not all devices provide good support for that.
3564 JTAG doesn't require supporting IDCODE instructions, and
3565 chips with JTAG routers may not link TAPs into the chain
3566 until they are told to do so.
3568 The configuration mechanism currently supported by OpenOCD
3569 requires explicit configuration of all TAP devices using
3570 @command{jtag newtap} commands, as detailed later in this chapter.
3571 A command like this would declare one tap and name it @code{chip1.cpu}:
3574 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3577 Each target configuration file lists the TAPs provided
3579 Board configuration files combine all the targets on a board,
3581 Note that @emph{the order in which TAPs are declared is very important.}
3582 It must match the order in the JTAG scan chain, both inside
3583 a single chip and between them.
3584 @xref{faqtaporder,,FAQ TAP Order}.
3586 For example, the ST Microsystems STR912 chip has
3587 three separate TAPs@footnote{See the ST
3588 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3589 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3590 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3591 To configure those taps, @file{target/str912.cfg}
3592 includes commands something like this:
3595 jtag newtap str912 flash ... params ...
3596 jtag newtap str912 cpu ... params ...
3597 jtag newtap str912 bs ... params ...
3600 Actual config files use a variable instead of literals like
3601 @option{str912}, to support more than one chip of each type.
3602 @xref{Config File Guidelines}.
3604 @deffn Command {jtag names}
3605 Returns the names of all current TAPs in the scan chain.
3606 Use @command{jtag cget} or @command{jtag tapisenabled}
3607 to examine attributes and state of each TAP.
3609 foreach t [jtag names] @{
3610 puts [format "TAP: %s\n" $t]
3615 @deffn Command {scan_chain}
3616 Displays the TAPs in the scan chain configuration,
3618 The set of TAPs listed by this command is fixed by
3619 exiting the OpenOCD configuration stage,
3620 but systems with a JTAG router can
3621 enable or disable TAPs dynamically.
3624 @c FIXME! "jtag cget" should be able to return all TAP
3625 @c attributes, like "$target_name cget" does for targets.
3627 @c Probably want "jtag eventlist", and a "tap-reset" event
3628 @c (on entry to RESET state).
3633 When TAP objects are declared with @command{jtag newtap},
3634 a @dfn{dotted.name} is created for the TAP, combining the
3635 name of a module (usually a chip) and a label for the TAP.
3636 For example: @code{xilinx.tap}, @code{str912.flash},
3637 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3638 Many other commands use that dotted.name to manipulate or
3639 refer to the TAP. For example, CPU configuration uses the
3640 name, as does declaration of NAND or NOR flash banks.
3642 The components of a dotted name should follow ``C'' symbol
3643 name rules: start with an alphabetic character, then numbers
3644 and underscores are OK; while others (including dots!) are not.
3647 In older code, JTAG TAPs were numbered from 0..N.
3648 This feature is still present.
3649 However its use is highly discouraged, and
3650 should not be relied on; it will be removed by mid-2010.
3651 Update all of your scripts to use TAP names rather than numbers,
3652 by paying attention to the runtime warnings they trigger.
3653 Using TAP numbers in target configuration scripts prevents
3654 reusing those scripts on boards with multiple targets.
3657 @section TAP Declaration Commands
3659 @c shouldn't this be(come) a {Config Command}?
3660 @deffn Command {jtag newtap} chipname tapname configparams...
3661 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3662 and configured according to the various @var{configparams}.
3664 The @var{chipname} is a symbolic name for the chip.
3665 Conventionally target config files use @code{$_CHIPNAME},
3666 defaulting to the model name given by the chip vendor but
3669 @cindex TAP naming convention
3670 The @var{tapname} reflects the role of that TAP,
3671 and should follow this convention:
3674 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3675 @item @code{cpu} -- The main CPU of the chip, alternatively
3676 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3677 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3678 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3679 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3680 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3681 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3682 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3684 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3685 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3686 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3687 a JTAG TAP; that TAP should be named @code{sdma}.
3690 Every TAP requires at least the following @var{configparams}:
3693 @item @code{-irlen} @var{NUMBER}
3694 @*The length in bits of the
3695 instruction register, such as 4 or 5 bits.
3698 A TAP may also provide optional @var{configparams}:
3701 @item @code{-disable} (or @code{-enable})
3702 @*Use the @code{-disable} parameter to flag a TAP which is not
3703 linked in to the scan chain after a reset using either TRST
3704 or the JTAG state machine's @sc{reset} state.
3705 You may use @code{-enable} to highlight the default state
3706 (the TAP is linked in).
3707 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3708 @item @code{-expected-id} @var{number}
3709 @*A non-zero @var{number} represents a 32-bit IDCODE
3710 which you expect to find when the scan chain is examined.
3711 These codes are not required by all JTAG devices.
3712 @emph{Repeat the option} as many times as required if more than one
3713 ID code could appear (for example, multiple versions).
3714 Specify @var{number} as zero to suppress warnings about IDCODE
3715 values that were found but not included in the list.
3717 Provide this value if at all possible, since it lets OpenOCD
3718 tell when the scan chain it sees isn't right. These values
3719 are provided in vendors' chip documentation, usually a technical
3720 reference manual. Sometimes you may need to probe the JTAG
3721 hardware to find these values.
3722 @xref{autoprobing,,Autoprobing}.
3723 @item @code{-ignore-version}
3724 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3725 option. When vendors put out multiple versions of a chip, or use the same
3726 JTAG-level ID for several largely-compatible chips, it may be more practical
3727 to ignore the version field than to update config files to handle all of
3728 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3729 @item @code{-ircapture} @var{NUMBER}
3730 @*The bit pattern loaded by the TAP into the JTAG shift register
3731 on entry to the @sc{ircapture} state, such as 0x01.
3732 JTAG requires the two LSBs of this value to be 01.
3733 By default, @code{-ircapture} and @code{-irmask} are set
3734 up to verify that two-bit value. You may provide
3735 additional bits, if you know them, or indicate that
3736 a TAP doesn't conform to the JTAG specification.
3737 @item @code{-irmask} @var{NUMBER}
3738 @*A mask used with @code{-ircapture}
3739 to verify that instruction scans work correctly.
3740 Such scans are not used by OpenOCD except to verify that
3741 there seems to be no problems with JTAG scan chain operations.
3745 @section Other TAP commands
3747 @deffn Command {jtag cget} dotted.name @option{-event} name
3748 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3749 At this writing this TAP attribute
3750 mechanism is used only for event handling.
3751 (It is not a direct analogue of the @code{cget}/@code{configure}
3752 mechanism for debugger targets.)
3753 See the next section for information about the available events.
3755 The @code{configure} subcommand assigns an event handler,
3756 a TCL string which is evaluated when the event is triggered.
3757 The @code{cget} subcommand returns that handler.
3764 OpenOCD includes two event mechanisms.
3765 The one presented here applies to all JTAG TAPs.
3766 The other applies to debugger targets,
3767 which are associated with certain TAPs.
3769 The TAP events currently defined are:
3772 @item @b{post-reset}
3773 @* The TAP has just completed a JTAG reset.
3774 The tap may still be in the JTAG @sc{reset} state.
3775 Handlers for these events might perform initialization sequences
3776 such as issuing TCK cycles, TMS sequences to ensure
3777 exit from the ARM SWD mode, and more.
3779 Because the scan chain has not yet been verified, handlers for these events
3780 @emph{should not issue commands which scan the JTAG IR or DR registers}
3781 of any particular target.
3782 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3784 @* The scan chain has been reset and verified.
3785 This handler may enable TAPs as needed.
3786 @item @b{tap-disable}
3787 @* The TAP needs to be disabled. This handler should
3788 implement @command{jtag tapdisable}
3789 by issuing the relevant JTAG commands.
3790 @item @b{tap-enable}
3791 @* The TAP needs to be enabled. This handler should
3792 implement @command{jtag tapenable}
3793 by issuing the relevant JTAG commands.
3796 If you need some action after each JTAG reset, which isn't actually
3797 specific to any TAP (since you can't yet trust the scan chain's
3798 contents to be accurate), you might:
3801 jtag configure CHIP.jrc -event post-reset @{
3802 echo "JTAG Reset done"
3803 ... non-scan jtag operations to be done after reset
3808 @anchor{enablinganddisablingtaps}
3809 @section Enabling and Disabling TAPs
3810 @cindex JTAG Route Controller
3813 In some systems, a @dfn{JTAG Route Controller} (JRC)
3814 is used to enable and/or disable specific JTAG TAPs.
3815 Many ARM based chips from Texas Instruments include
3816 an ``ICEpick'' module, which is a JRC.
3817 Such chips include DaVinci and OMAP3 processors.
3819 A given TAP may not be visible until the JRC has been
3820 told to link it into the scan chain; and if the JRC
3821 has been told to unlink that TAP, it will no longer
3823 Such routers address problems that JTAG ``bypass mode''
3827 @item The scan chain can only go as fast as its slowest TAP.
3828 @item Having many TAPs slows instruction scans, since all
3829 TAPs receive new instructions.
3830 @item TAPs in the scan chain must be powered up, which wastes
3831 power and prevents debugging some power management mechanisms.
3834 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3835 as implied by the existence of JTAG routers.
3836 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3837 does include a kind of JTAG router functionality.
3839 @c (a) currently the event handlers don't seem to be able to
3840 @c fail in a way that could lead to no-change-of-state.
3842 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3843 shown below, and is implemented using TAP event handlers.
3844 So for example, when defining a TAP for a CPU connected to
3845 a JTAG router, your @file{target.cfg} file
3846 should define TAP event handlers using
3847 code that looks something like this:
3850 jtag configure CHIP.cpu -event tap-enable @{
3851 ... jtag operations using CHIP.jrc
3853 jtag configure CHIP.cpu -event tap-disable @{
3854 ... jtag operations using CHIP.jrc
3858 Then you might want that CPU's TAP enabled almost all the time:
3861 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3864 Note how that particular setup event handler declaration
3865 uses quotes to evaluate @code{$CHIP} when the event is configured.
3866 Using brackets @{ @} would cause it to be evaluated later,
3867 at runtime, when it might have a different value.
3869 @deffn Command {jtag tapdisable} dotted.name
3870 If necessary, disables the tap
3871 by sending it a @option{tap-disable} event.
3872 Returns the string "1" if the tap
3873 specified by @var{dotted.name} is enabled,
3874 and "0" if it is disabled.
3877 @deffn Command {jtag tapenable} dotted.name
3878 If necessary, enables the tap
3879 by sending it a @option{tap-enable} event.
3880 Returns the string "1" if the tap
3881 specified by @var{dotted.name} is enabled,
3882 and "0" if it is disabled.
3885 @deffn Command {jtag tapisenabled} dotted.name
3886 Returns the string "1" if the tap
3887 specified by @var{dotted.name} is enabled,
3888 and "0" if it is disabled.
3891 Humans will find the @command{scan_chain} command more helpful
3892 for querying the state of the JTAG taps.
3896 @anchor{autoprobing}
3897 @section Autoprobing
3899 @cindex JTAG autoprobe
3901 TAP configuration is the first thing that needs to be done
3902 after interface and reset configuration. Sometimes it's
3903 hard finding out what TAPs exist, or how they are identified.
3904 Vendor documentation is not always easy to find and use.
3906 To help you get past such problems, OpenOCD has a limited
3907 @emph{autoprobing} ability to look at the scan chain, doing
3908 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3909 To use this mechanism, start the OpenOCD server with only data
3910 that configures your JTAG interface, and arranges to come up
3911 with a slow clock (many devices don't support fast JTAG clocks
3912 right when they come out of reset).
3914 For example, your @file{openocd.cfg} file might have:
3917 source [find interface/olimex-arm-usb-tiny-h.cfg]
3918 reset_config trst_and_srst
3922 When you start the server without any TAPs configured, it will
3923 attempt to autoconfigure the TAPs. There are two parts to this:
3926 @item @emph{TAP discovery} ...
3927 After a JTAG reset (sometimes a system reset may be needed too),
3928 each TAP's data registers will hold the contents of either the
3929 IDCODE or BYPASS register.
3930 If JTAG communication is working, OpenOCD will see each TAP,
3931 and report what @option{-expected-id} to use with it.
3932 @item @emph{IR Length discovery} ...
3933 Unfortunately JTAG does not provide a reliable way to find out
3934 the value of the @option{-irlen} parameter to use with a TAP
3936 If OpenOCD can discover the length of a TAP's instruction
3937 register, it will report it.
3938 Otherwise you may need to consult vendor documentation, such
3939 as chip data sheets or BSDL files.
3942 In many cases your board will have a simple scan chain with just
3943 a single device. Here's what OpenOCD reported with one board
3944 that's a bit more complex:
3948 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3949 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3950 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3951 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3952 AUTO auto0.tap - use "... -irlen 4"
3953 AUTO auto1.tap - use "... -irlen 4"
3954 AUTO auto2.tap - use "... -irlen 6"
3955 no gdb ports allocated as no target has been specified
3958 Given that information, you should be able to either find some existing
3959 config files to use, or create your own. If you create your own, you
3960 would configure from the bottom up: first a @file{target.cfg} file
3961 with these TAPs, any targets associated with them, and any on-chip
3962 resources; then a @file{board.cfg} with off-chip resources, clocking,
3965 @node CPU Configuration
3966 @chapter CPU Configuration
3969 This chapter discusses how to set up GDB debug targets for CPUs.
3970 You can also access these targets without GDB
3971 (@pxref{Architecture and Core Commands},
3972 and @ref{targetstatehandling,,Target State handling}) and
3973 through various kinds of NAND and NOR flash commands.
3974 If you have multiple CPUs you can have multiple such targets.
3976 We'll start by looking at how to examine the targets you have,
3977 then look at how to add one more target and how to configure it.
3979 @section Target List
3980 @cindex target, current
3981 @cindex target, list
3983 All targets that have been set up are part of a list,
3984 where each member has a name.
3985 That name should normally be the same as the TAP name.
3986 You can display the list with the @command{targets}
3988 This display often has only one CPU; here's what it might
3989 look like with more than one:
3991 TargetName Type Endian TapName State
3992 -- ------------------ ---------- ------ ------------------ ------------
3993 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3994 1 MyTarget cortex_m little mychip.foo tap-disabled
3997 One member of that list is the @dfn{current target}, which
3998 is implicitly referenced by many commands.
3999 It's the one marked with a @code{*} near the target name.
4000 In particular, memory addresses often refer to the address
4001 space seen by that current target.
4002 Commands like @command{mdw} (memory display words)
4003 and @command{flash erase_address} (erase NOR flash blocks)
4004 are examples; and there are many more.
4006 Several commands let you examine the list of targets:
4008 @deffn Command {target count}
4009 @emph{Note: target numbers are deprecated; don't use them.
4010 They will be removed shortly after August 2010, including this command.
4011 Iterate target using @command{target names}, not by counting.}
4013 Returns the number of targets, @math{N}.
4014 The highest numbered target is @math{N - 1}.
4016 set c [target count]
4017 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4018 # Assuming you have created this function
4019 print_target_details $x
4024 @deffn Command {target current}
4025 Returns the name of the current target.
4028 @deffn Command {target names}
4029 Lists the names of all current targets in the list.
4031 foreach t [target names] @{
4032 puts [format "Target: %s\n" $t]
4037 @deffn Command {target number} number
4038 @emph{Note: target numbers are deprecated; don't use them.
4039 They will be removed shortly after August 2010, including this command.}
4041 The list of targets is numbered starting at zero.
4042 This command returns the name of the target at index @var{number}.
4044 set thename [target number $x]
4045 puts [format "Target %d is: %s\n" $x $thename]
4049 @c yep, "target list" would have been better.
4050 @c plus maybe "target setdefault".
4052 @deffn Command targets [name]
4053 @emph{Note: the name of this command is plural. Other target
4054 command names are singular.}
4056 With no parameter, this command displays a table of all known
4057 targets in a user friendly form.
4059 With a parameter, this command sets the current target to
4060 the given target with the given @var{name}; this is
4061 only relevant on boards which have more than one target.
4064 @section Target CPU Types and Variants
4069 Each target has a @dfn{CPU type}, as shown in the output of
4070 the @command{targets} command. You need to specify that type
4071 when calling @command{target create}.
4072 The CPU type indicates more than just the instruction set.
4073 It also indicates how that instruction set is implemented,
4074 what kind of debug support it integrates,
4075 whether it has an MMU (and if so, what kind),
4076 what core-specific commands may be available
4077 (@pxref{Architecture and Core Commands}),
4080 For some CPU types, OpenOCD also defines @dfn{variants} which
4081 indicate differences that affect their handling.
4082 For example, a particular implementation bug might need to be
4083 worked around in some chip versions.
4085 It's easy to see what target types are supported,
4086 since there's a command to list them.
4087 However, there is currently no way to list what target variants
4088 are supported (other than by reading the OpenOCD source code).
4090 @anchor{targettypes}
4091 @deffn Command {target types}
4092 Lists all supported target types.
4093 At this writing, the supported CPU types and variants are:
4096 @item @code{arm11} -- this is a generation of ARMv6 cores
4097 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4098 @item @code{arm7tdmi} -- this is an ARMv4 core
4099 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4100 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4101 @item @code{arm966e} -- this is an ARMv5 core
4102 @item @code{arm9tdmi} -- this is an ARMv4 core
4103 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4104 (Support for this is preliminary and incomplete.)
4105 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4106 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4107 compact Thumb2 instruction set.
4108 @item @code{dragonite} -- resembles arm966e
4109 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4110 (Support for this is still incomplete.)
4111 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4112 @item @code{feroceon} -- resembles arm926
4113 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
4114 @item @code{xscale} -- this is actually an architecture,
4115 not a CPU type. It is based on the ARMv5 architecture.
4116 There are several variants defined:
4118 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
4119 @code{pxa27x} ... instruction register length is 7 bits
4120 @item @code{pxa250}, @code{pxa255},
4121 @code{pxa26x} ... instruction register length is 5 bits
4122 @item @code{pxa3xx} ... instruction register length is 11 bits
4127 To avoid being confused by the variety of ARM based cores, remember
4128 this key point: @emph{ARM is a technology licencing company}.
4129 (See: @url{http://www.arm.com}.)
4130 The CPU name used by OpenOCD will reflect the CPU design that was
4131 licenced, not a vendor brand which incorporates that design.
4132 Name prefixes like arm7, arm9, arm11, and cortex
4133 reflect design generations;
4134 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4135 reflect an architecture version implemented by a CPU design.
4137 @anchor{targetconfiguration}
4138 @section Target Configuration
4140 Before creating a ``target'', you must have added its TAP to the scan chain.
4141 When you've added that TAP, you will have a @code{dotted.name}
4142 which is used to set up the CPU support.
4143 The chip-specific configuration file will normally configure its CPU(s)
4144 right after it adds all of the chip's TAPs to the scan chain.
4146 Although you can set up a target in one step, it's often clearer if you
4147 use shorter commands and do it in two steps: create it, then configure
4149 All operations on the target after it's created will use a new
4150 command, created as part of target creation.
4152 The two main things to configure after target creation are
4153 a work area, which usually has target-specific defaults even
4154 if the board setup code overrides them later;
4155 and event handlers (@pxref{targetevents,,Target Events}), which tend
4156 to be much more board-specific.
4157 The key steps you use might look something like this
4160 target create MyTarget cortex_m -chain-position mychip.cpu
4161 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4162 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4163 $MyTarget configure -event reset-init @{ myboard_reinit @}
4166 You should specify a working area if you can; typically it uses some
4168 Such a working area can speed up many things, including bulk
4169 writes to target memory;
4170 flash operations like checking to see if memory needs to be erased;
4171 GDB memory checksumming;
4175 On more complex chips, the work area can become
4176 inaccessible when application code
4177 (such as an operating system)
4178 enables or disables the MMU.
4179 For example, the particular MMU context used to acess the virtual
4180 address will probably matter ... and that context might not have
4181 easy access to other addresses needed.
4182 At this writing, OpenOCD doesn't have much MMU intelligence.
4185 It's often very useful to define a @code{reset-init} event handler.
4186 For systems that are normally used with a boot loader,
4187 common tasks include updating clocks and initializing memory
4189 That may be needed to let you write the boot loader into flash,
4190 in order to ``de-brick'' your board; or to load programs into
4191 external DDR memory without having run the boot loader.
4193 @deffn Command {target create} target_name type configparams...
4194 This command creates a GDB debug target that refers to a specific JTAG tap.
4195 It enters that target into a list, and creates a new
4196 command (@command{@var{target_name}}) which is used for various
4197 purposes including additional configuration.
4200 @item @var{target_name} ... is the name of the debug target.
4201 By convention this should be the same as the @emph{dotted.name}
4202 of the TAP associated with this target, which must be specified here
4203 using the @code{-chain-position @var{dotted.name}} configparam.
4205 This name is also used to create the target object command,
4206 referred to here as @command{$target_name},
4207 and in other places the target needs to be identified.
4208 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4209 @item @var{configparams} ... all parameters accepted by
4210 @command{$target_name configure} are permitted.
4211 If the target is big-endian, set it here with @code{-endian big}.
4212 If the variant matters, set it here with @code{-variant}.
4214 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4218 @deffn Command {$target_name configure} configparams...
4219 The options accepted by this command may also be
4220 specified as parameters to @command{target create}.
4221 Their values can later be queried one at a time by
4222 using the @command{$target_name cget} command.
4224 @emph{Warning:} changing some of these after setup is dangerous.
4225 For example, moving a target from one TAP to another;
4226 and changing its endianness or variant.
4230 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4231 used to access this target.
4233 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4234 whether the CPU uses big or little endian conventions
4236 @item @code{-event} @var{event_name} @var{event_body} --
4237 @xref{targetevents,,Target Events}.
4238 Note that this updates a list of named event handlers.
4239 Calling this twice with two different event names assigns
4240 two different handlers, but calling it twice with the
4241 same event name assigns only one handler.
4243 @item @code{-variant} @var{name} -- specifies a variant of the target,
4244 which OpenOCD needs to know about.
4246 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4247 whether the work area gets backed up; by default,
4248 @emph{it is not backed up.}
4249 When possible, use a working_area that doesn't need to be backed up,
4250 since performing a backup slows down operations.
4251 For example, the beginning of an SRAM block is likely to
4252 be used by most build systems, but the end is often unused.
4254 @item @code{-work-area-size} @var{size} -- specify work are size,
4255 in bytes. The same size applies regardless of whether its physical
4256 or virtual address is being used.
4258 @item @code{-work-area-phys} @var{address} -- set the work area
4259 base @var{address} to be used when no MMU is active.
4261 @item @code{-work-area-virt} @var{address} -- set the work area
4262 base @var{address} to be used when an MMU is active.
4263 @emph{Do not specify a value for this except on targets with an MMU.}
4264 The value should normally correspond to a static mapping for the
4265 @code{-work-area-phys} address, set up by the current operating system.
4267 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4268 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4269 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}.
4274 @section Other $target_name Commands
4275 @cindex object command
4277 The Tcl/Tk language has the concept of object commands,
4278 and OpenOCD adopts that same model for targets.
4280 A good Tk example is a on screen button.
4281 Once a button is created a button
4282 has a name (a path in Tk terms) and that name is useable as a first
4283 class command. For example in Tk, one can create a button and later
4284 configure it like this:
4288 button .foobar -background red -command @{ foo @}
4290 .foobar configure -foreground blue
4292 set x [.foobar cget -background]
4294 puts [format "The button is %s" $x]
4297 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4298 button, and its object commands are invoked the same way.
4301 str912.cpu mww 0x1234 0x42
4302 omap3530.cpu mww 0x5555 123
4305 The commands supported by OpenOCD target objects are:
4307 @deffn Command {$target_name arp_examine}
4308 @deffnx Command {$target_name arp_halt}
4309 @deffnx Command {$target_name arp_poll}
4310 @deffnx Command {$target_name arp_reset}
4311 @deffnx Command {$target_name arp_waitstate}
4312 Internal OpenOCD scripts (most notably @file{startup.tcl})
4313 use these to deal with specific reset cases.
4314 They are not otherwise documented here.
4317 @deffn Command {$target_name array2mem} arrayname width address count
4318 @deffnx Command {$target_name mem2array} arrayname width address count
4319 These provide an efficient script-oriented interface to memory.
4320 The @code{array2mem} primitive writes bytes, halfwords, or words;
4321 while @code{mem2array} reads them.
4322 In both cases, the TCL side uses an array, and
4323 the target side uses raw memory.
4325 The efficiency comes from enabling the use of
4326 bulk JTAG data transfer operations.
4327 The script orientation comes from working with data
4328 values that are packaged for use by TCL scripts;
4329 @command{mdw} type primitives only print data they retrieve,
4330 and neither store nor return those values.
4333 @item @var{arrayname} ... is the name of an array variable
4334 @item @var{width} ... is 8/16/32 - indicating the memory access size
4335 @item @var{address} ... is the target memory address
4336 @item @var{count} ... is the number of elements to process
4340 @deffn Command {$target_name cget} queryparm
4341 Each configuration parameter accepted by
4342 @command{$target_name configure}
4343 can be individually queried, to return its current value.
4344 The @var{queryparm} is a parameter name
4345 accepted by that command, such as @code{-work-area-phys}.
4346 There are a few special cases:
4349 @item @code{-event} @var{event_name} -- returns the handler for the
4350 event named @var{event_name}.
4351 This is a special case because setting a handler requires
4353 @item @code{-type} -- returns the target type.
4354 This is a special case because this is set using
4355 @command{target create} and can't be changed
4356 using @command{$target_name configure}.
4359 For example, if you wanted to summarize information about
4360 all the targets you might use something like this:
4363 foreach name [target names] @{
4364 set y [$name cget -endian]
4365 set z [$name cget -type]
4366 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4372 @anchor{targetcurstate}
4373 @deffn Command {$target_name curstate}
4374 Displays the current target state:
4375 @code{debug-running},
4378 @code{running}, or @code{unknown}.
4379 (Also, @pxref{eventpolling,,Event Polling}.)
4382 @deffn Command {$target_name eventlist}
4383 Displays a table listing all event handlers
4384 currently associated with this target.
4385 @xref{targetevents,,Target Events}.
4388 @deffn Command {$target_name invoke-event} event_name
4389 Invokes the handler for the event named @var{event_name}.
4390 (This is primarily intended for use by OpenOCD framework
4391 code, for example by the reset code in @file{startup.tcl}.)
4394 @deffn Command {$target_name mdw} addr [count]
4395 @deffnx Command {$target_name mdh} addr [count]
4396 @deffnx Command {$target_name mdb} addr [count]
4397 Display contents of address @var{addr}, as
4398 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4399 or 8-bit bytes (@command{mdb}).
4400 If @var{count} is specified, displays that many units.
4401 (If you want to manipulate the data instead of displaying it,
4402 see the @code{mem2array} primitives.)
4405 @deffn Command {$target_name mww} addr word
4406 @deffnx Command {$target_name mwh} addr halfword
4407 @deffnx Command {$target_name mwb} addr byte
4408 Writes the specified @var{word} (32 bits),
4409 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4410 at the specified address @var{addr}.
4413 @anchor{targetevents}
4414 @section Target Events
4415 @cindex target events
4417 At various times, certain things can happen, or you want them to happen.
4420 @item What should happen when GDB connects? Should your target reset?
4421 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4422 @item Is using SRST appropriate (and possible) on your system?
4423 Or instead of that, do you need to issue JTAG commands to trigger reset?
4424 SRST usually resets everything on the scan chain, which can be inappropriate.
4425 @item During reset, do you need to write to certain memory locations
4426 to set up system clocks or
4427 to reconfigure the SDRAM?
4428 How about configuring the watchdog timer, or other peripherals,
4429 to stop running while you hold the core stopped for debugging?
4432 All of the above items can be addressed by target event handlers.
4433 These are set up by @command{$target_name configure -event} or
4434 @command{target create ... -event}.
4436 The programmer's model matches the @code{-command} option used in Tcl/Tk
4437 buttons and events. The two examples below act the same, but one creates
4438 and invokes a small procedure while the other inlines it.
4441 proc my_attach_proc @{ @} @{
4445 mychip.cpu configure -event gdb-attach my_attach_proc
4446 mychip.cpu configure -event gdb-attach @{
4448 # To make flash probe and gdb load to flash work we need a reset init.
4453 The following target events are defined:
4456 @item @b{debug-halted}
4457 @* The target has halted for debug reasons (i.e.: breakpoint)
4458 @item @b{debug-resumed}
4459 @* The target has resumed (i.e.: gdb said run)
4460 @item @b{early-halted}
4461 @* Occurs early in the halt process
4462 @item @b{examine-start}
4463 @* Before target examine is called.
4464 @item @b{examine-end}
4465 @* After target examine is called with no errors.
4466 @item @b{gdb-attach}
4467 @* When GDB connects. This is before any communication with the target, so this
4468 can be used to set up the target so it is possible to probe flash. Probing flash
4469 is necessary during gdb connect if gdb load is to write the image to flash. Another
4470 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4471 depending on whether the breakpoint is in RAM or read only memory.
4472 @item @b{gdb-detach}
4473 @* When GDB disconnects
4475 @* When the target has halted and GDB is not doing anything (see early halt)
4476 @item @b{gdb-flash-erase-start}
4477 @* Before the GDB flash process tries to erase the flash
4478 @item @b{gdb-flash-erase-end}
4479 @* After the GDB flash process has finished erasing the flash
4480 @item @b{gdb-flash-write-start}
4481 @* Before GDB writes to the flash
4482 @item @b{gdb-flash-write-end}
4483 @* After GDB writes to the flash
4485 @* Before the target steps, gdb is trying to start/resume the target
4487 @* The target has halted
4488 @item @b{reset-assert-pre}
4489 @* Issued as part of @command{reset} processing
4490 after @command{reset_init} was triggered
4491 but before either SRST alone is re-asserted on the scan chain,
4492 or @code{reset-assert} is triggered.
4493 @item @b{reset-assert}
4494 @* Issued as part of @command{reset} processing
4495 after @command{reset-assert-pre} was triggered.
4496 When such a handler is present, cores which support this event will use
4497 it instead of asserting SRST.
4498 This support is essential for debugging with JTAG interfaces which
4499 don't include an SRST line (JTAG doesn't require SRST), and for
4500 selective reset on scan chains that have multiple targets.
4501 @item @b{reset-assert-post}
4502 @* Issued as part of @command{reset} processing
4503 after @code{reset-assert} has been triggered.
4504 or the target asserted SRST on the entire scan chain.
4505 @item @b{reset-deassert-pre}
4506 @* Issued as part of @command{reset} processing
4507 after @code{reset-assert-post} has been triggered.
4508 @item @b{reset-deassert-post}
4509 @* Issued as part of @command{reset} processing
4510 after @code{reset-deassert-pre} has been triggered
4511 and (if the target is using it) after SRST has been
4512 released on the scan chain.
4514 @* Issued as the final step in @command{reset} processing.
4516 @item @b{reset-halt-post}
4517 @* Currently not used
4518 @item @b{reset-halt-pre}
4519 @* Currently not used
4521 @item @b{reset-init}
4522 @* Used by @b{reset init} command for board-specific initialization.
4523 This event fires after @emph{reset-deassert-post}.
4525 This is where you would configure PLLs and clocking, set up DRAM so
4526 you can download programs that don't fit in on-chip SRAM, set up pin
4527 multiplexing, and so on.
4528 (You may be able to switch to a fast JTAG clock rate here, after
4529 the target clocks are fully set up.)
4530 @item @b{reset-start}
4531 @* Issued as part of @command{reset} processing
4532 before @command{reset_init} is called.
4534 This is the most robust place to use @command{jtag_rclk}
4535 or @command{adapter_khz} to switch to a low JTAG clock rate,
4536 when reset disables PLLs needed to use a fast clock.
4538 @item @b{reset-wait-pos}
4539 @* Currently not used
4540 @item @b{reset-wait-pre}
4541 @* Currently not used
4543 @item @b{resume-start}
4544 @* Before any target is resumed
4545 @item @b{resume-end}
4546 @* After all targets have resumed
4548 @* Target has resumed
4551 @node Flash Commands
4552 @chapter Flash Commands
4554 OpenOCD has different commands for NOR and NAND flash;
4555 the ``flash'' command works with NOR flash, while
4556 the ``nand'' command works with NAND flash.
4557 This partially reflects different hardware technologies:
4558 NOR flash usually supports direct CPU instruction and data bus access,
4559 while data from a NAND flash must be copied to memory before it can be
4560 used. (SPI flash must also be copied to memory before use.)
4561 However, the documentation also uses ``flash'' as a generic term;
4562 for example, ``Put flash configuration in board-specific files''.
4566 @item Configure via the command @command{flash bank}
4567 @* Do this in a board-specific configuration file,
4568 passing parameters as needed by the driver.
4569 @item Operate on the flash via @command{flash subcommand}
4570 @* Often commands to manipulate the flash are typed by a human, or run
4571 via a script in some automated way. Common tasks include writing a
4572 boot loader, operating system, or other data.
4574 @* Flashing via GDB requires the flash be configured via ``flash
4575 bank'', and the GDB flash features be enabled.
4576 @xref{gdbconfiguration,,GDB Configuration}.
4579 Many CPUs have the ablity to ``boot'' from the first flash bank.
4580 This means that misprogramming that bank can ``brick'' a system,
4581 so that it can't boot.
4582 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4583 board by (re)installing working boot firmware.
4585 @anchor{norconfiguration}
4586 @section Flash Configuration Commands
4587 @cindex flash configuration
4589 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4590 Configures a flash bank which provides persistent storage
4591 for addresses from @math{base} to @math{base + size - 1}.
4592 These banks will often be visible to GDB through the target's memory map.
4593 In some cases, configuring a flash bank will activate extra commands;
4594 see the driver-specific documentation.
4597 @item @var{name} ... may be used to reference the flash bank
4598 in other flash commands. A number is also available.
4599 @item @var{driver} ... identifies the controller driver
4600 associated with the flash bank being declared.
4601 This is usually @code{cfi} for external flash, or else
4602 the name of a microcontroller with embedded flash memory.
4603 @xref{flashdriverlist,,Flash Driver List}.
4604 @item @var{base} ... Base address of the flash chip.
4605 @item @var{size} ... Size of the chip, in bytes.
4606 For some drivers, this value is detected from the hardware.
4607 @item @var{chip_width} ... Width of the flash chip, in bytes;
4608 ignored for most microcontroller drivers.
4609 @item @var{bus_width} ... Width of the data bus used to access the
4610 chip, in bytes; ignored for most microcontroller drivers.
4611 @item @var{target} ... Names the target used to issue
4612 commands to the flash controller.
4613 @comment Actually, it's currently a controller-specific parameter...
4614 @item @var{driver_options} ... drivers may support, or require,
4615 additional parameters. See the driver-specific documentation
4616 for more information.
4619 This command is not available after OpenOCD initialization has completed.
4620 Use it in board specific configuration files, not interactively.
4624 @comment the REAL name for this command is "ocd_flash_banks"
4625 @comment less confusing would be: "flash list" (like "nand list")
4626 @deffn Command {flash banks}
4627 Prints a one-line summary of each device that was
4628 declared using @command{flash bank}, numbered from zero.
4629 Note that this is the @emph{plural} form;
4630 the @emph{singular} form is a very different command.
4633 @deffn Command {flash list}
4634 Retrieves a list of associative arrays for each device that was
4635 declared using @command{flash bank}, numbered from zero.
4636 This returned list can be manipulated easily from within scripts.
4639 @deffn Command {flash probe} num
4640 Identify the flash, or validate the parameters of the configured flash. Operation
4641 depends on the flash type.
4642 The @var{num} parameter is a value shown by @command{flash banks}.
4643 Most flash commands will implicitly @emph{autoprobe} the bank;
4644 flash drivers can distinguish between probing and autoprobing,
4645 but most don't bother.
4648 @section Erasing, Reading, Writing to Flash
4649 @cindex flash erasing
4650 @cindex flash reading
4651 @cindex flash writing
4652 @cindex flash programming
4653 @anchor{flashprogrammingcommands}
4655 One feature distinguishing NOR flash from NAND or serial flash technologies
4656 is that for read access, it acts exactly like any other addressible memory.
4657 This means you can use normal memory read commands like @command{mdw} or
4658 @command{dump_image} with it, with no special @command{flash} subcommands.
4659 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4661 Write access works differently. Flash memory normally needs to be erased
4662 before it's written. Erasing a sector turns all of its bits to ones, and
4663 writing can turn ones into zeroes. This is why there are special commands
4664 for interactive erasing and writing, and why GDB needs to know which parts
4665 of the address space hold NOR flash memory.
4668 Most of these erase and write commands leverage the fact that NOR flash
4669 chips consume target address space. They implicitly refer to the current
4670 JTAG target, and map from an address in that target's address space
4671 back to a flash bank.
4672 @comment In May 2009, those mappings may fail if any bank associated
4673 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4674 A few commands use abstract addressing based on bank and sector numbers,
4675 and don't depend on searching the current target and its address space.
4676 Avoid confusing the two command models.
4679 Some flash chips implement software protection against accidental writes,
4680 since such buggy writes could in some cases ``brick'' a system.
4681 For such systems, erasing and writing may require sector protection to be
4683 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4684 and AT91SAM7 on-chip flash.
4685 @xref{flashprotect,,flash protect}.
4687 @deffn Command {flash erase_sector} num first last
4688 Erase sectors in bank @var{num}, starting at sector @var{first}
4689 up to and including @var{last}.
4690 Sector numbering starts at 0.
4691 Providing a @var{last} sector of @option{last}
4692 specifies "to the end of the flash bank".
4693 The @var{num} parameter is a value shown by @command{flash banks}.
4696 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4697 Erase sectors starting at @var{address} for @var{length} bytes.
4698 Unless @option{pad} is specified, @math{address} must begin a
4699 flash sector, and @math{address + length - 1} must end a sector.
4700 Specifying @option{pad} erases extra data at the beginning and/or
4701 end of the specified region, as needed to erase only full sectors.
4702 The flash bank to use is inferred from the @var{address}, and
4703 the specified length must stay within that bank.
4704 As a special case, when @var{length} is zero and @var{address} is
4705 the start of the bank, the whole flash is erased.
4706 If @option{unlock} is specified, then the flash is unprotected
4707 before erase starts.
4710 @deffn Command {flash fillw} address word length
4711 @deffnx Command {flash fillh} address halfword length
4712 @deffnx Command {flash fillb} address byte length
4713 Fills flash memory with the specified @var{word} (32 bits),
4714 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4715 starting at @var{address} and continuing
4716 for @var{length} units (word/halfword/byte).
4717 No erasure is done before writing; when needed, that must be done
4718 before issuing this command.
4719 Writes are done in blocks of up to 1024 bytes, and each write is
4720 verified by reading back the data and comparing it to what was written.
4721 The flash bank to use is inferred from the @var{address} of
4722 each block, and the specified length must stay within that bank.
4724 @comment no current checks for errors if fill blocks touch multiple banks!
4726 @deffn Command {flash write_bank} num filename offset
4727 Write the binary @file{filename} to flash bank @var{num},
4728 starting at @var{offset} bytes from the beginning of the bank.
4729 The @var{num} parameter is a value shown by @command{flash banks}.
4732 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4733 Write the image @file{filename} to the current target's flash bank(s).
4734 A relocation @var{offset} may be specified, in which case it is added
4735 to the base address for each section in the image.
4736 The file [@var{type}] can be specified
4737 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4738 @option{elf} (ELF file), @option{s19} (Motorola s19).
4739 @option{mem}, or @option{builder}.
4740 The relevant flash sectors will be erased prior to programming
4741 if the @option{erase} parameter is given. If @option{unlock} is
4742 provided, then the flash banks are unlocked before erase and
4743 program. The flash bank to use is inferred from the address of
4747 Be careful using the @option{erase} flag when the flash is holding
4748 data you want to preserve.
4749 Portions of the flash outside those described in the image's
4750 sections might be erased with no notice.
4753 When a section of the image being written does not fill out all the
4754 sectors it uses, the unwritten parts of those sectors are necessarily
4755 also erased, because sectors can't be partially erased.
4757 Data stored in sector "holes" between image sections are also affected.
4758 For example, "@command{flash write_image erase ...}" of an image with
4759 one byte at the beginning of a flash bank and one byte at the end
4760 erases the entire bank -- not just the two sectors being written.
4762 Also, when flash protection is important, you must re-apply it after
4763 it has been removed by the @option{unlock} flag.
4768 @section Other Flash commands
4769 @cindex flash protection
4771 @deffn Command {flash erase_check} num
4772 Check erase state of sectors in flash bank @var{num},
4773 and display that status.
4774 The @var{num} parameter is a value shown by @command{flash banks}.
4777 @deffn Command {flash info} num
4778 Print info about flash bank @var{num}
4779 The @var{num} parameter is a value shown by @command{flash banks}.
4780 This command will first query the hardware, it does not print cached
4781 and possibly stale information.
4784 @anchor{flashprotect}
4785 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4786 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4787 in flash bank @var{num}, starting at sector @var{first}
4788 and continuing up to and including @var{last}.
4789 Providing a @var{last} sector of @option{last}
4790 specifies "to the end of the flash bank".
4791 The @var{num} parameter is a value shown by @command{flash banks}.
4795 @deffn Command {program} filename [verify] [reset] [offset]
4796 This is a helper script that simplifies using OpenOCD as a standalone
4797 programmer. The only required parameter is @option{filename}, the others are optional.
4798 @xref{Flash Programming}.
4801 @anchor{flashdriverlist}
4802 @section Flash Driver List
4803 As noted above, the @command{flash bank} command requires a driver name,
4804 and allows driver-specific options and behaviors.
4805 Some drivers also activate driver-specific commands.
4807 @subsection External Flash
4809 @deffn {Flash Driver} cfi
4810 @cindex Common Flash Interface
4812 The ``Common Flash Interface'' (CFI) is the main standard for
4813 external NOR flash chips, each of which connects to a
4814 specific external chip select on the CPU.
4815 Frequently the first such chip is used to boot the system.
4816 Your board's @code{reset-init} handler might need to
4817 configure additional chip selects using other commands (like: @command{mww} to
4818 configure a bus and its timings), or
4819 perhaps configure a GPIO pin that controls the ``write protect'' pin
4821 The CFI driver can use a target-specific working area to significantly
4824 The CFI driver can accept the following optional parameters, in any order:
4827 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4828 like AM29LV010 and similar types.
4829 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4832 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4833 wide on a sixteen bit bus:
4836 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4837 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4840 To configure one bank of 32 MBytes
4841 built from two sixteen bit (two byte) wide parts wired in parallel
4842 to create a thirty-two bit (four byte) bus with doubled throughput:
4845 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4848 @c "cfi part_id" disabled
4851 @deffn {Flash Driver} lpcspifi
4852 @cindex NXP SPI Flash Interface
4855 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4856 Flash Interface (SPIFI) peripheral that can drive and provide
4857 memory mapped access to external SPI flash devices.
4859 The lpcspifi driver initializes this interface and provides
4860 program and erase functionality for these serial flash devices.
4861 Use of this driver @b{requires} a working area of at least 1kB
4862 to be configured on the target device; more than this will
4863 significantly reduce flash programming times.
4865 The setup command only requires the @var{base} parameter. All
4866 other parameters are ignored, and the flash size and layout
4867 are configured by the driver.
4870 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4875 @deffn {Flash Driver} stmsmi
4876 @cindex STMicroelectronics Serial Memory Interface
4879 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4880 SPEAr MPU family) include a proprietary
4881 ``Serial Memory Interface'' (SMI) controller able to drive external
4883 Depending on specific device and board configuration, up to 4 external
4884 flash devices can be connected.
4886 SMI makes the flash content directly accessible in the CPU address
4887 space; each external device is mapped in a memory bank.
4888 CPU can directly read data, execute code and boot from SMI banks.
4889 Normal OpenOCD commands like @command{mdw} can be used to display
4892 The setup command only requires the @var{base} parameter in order
4893 to identify the memory bank.
4894 All other parameters are ignored. Additional information, like
4895 flash size, are detected automatically.
4898 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4903 @subsection Internal Flash (Microcontrollers)
4905 @deffn {Flash Driver} aduc702x
4906 The ADUC702x analog microcontrollers from Analog Devices
4907 include internal flash and use ARM7TDMI cores.
4908 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4909 The setup command only requires the @var{target} argument
4910 since all devices in this family have the same memory layout.
4913 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4918 @deffn {Flash Driver} at91sam3
4920 All members of the AT91SAM3 microcontroller family from
4921 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
4922 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
4923 that the driver was orginaly developed and tested using the
4924 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
4925 the family was cribbed from the data sheet. @emph{Note to future
4926 readers/updaters: Please remove this worrysome comment after other
4927 chips are confirmed.}
4929 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
4930 have one flash bank. In all cases the flash banks are at
4931 the following fixed locations:
4934 # Flash bank 0 - all chips
4935 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
4936 # Flash bank 1 - only 256K chips
4937 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
4940 Internally, the AT91SAM3 flash memory is organized as follows.
4941 Unlike the AT91SAM7 chips, these are not used as parameters
4942 to the @command{flash bank} command:
4945 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
4946 @item @emph{Bank Size:} 128K/64K Per flash bank
4947 @item @emph{Sectors:} 16 or 8 per bank
4948 @item @emph{SectorSize:} 8K Per Sector
4949 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
4952 The AT91SAM3 driver adds some additional commands:
4954 @deffn Command {at91sam3 gpnvm}
4955 @deffnx Command {at91sam3 gpnvm clear} number
4956 @deffnx Command {at91sam3 gpnvm set} number
4957 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
4958 With no parameters, @command{show} or @command{show all},
4959 shows the status of all GPNVM bits.
4960 With @command{show} @var{number}, displays that bit.
4962 With @command{set} @var{number} or @command{clear} @var{number},
4963 modifies that GPNVM bit.
4966 @deffn Command {at91sam3 info}
4967 This command attempts to display information about the AT91SAM3
4968 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
4969 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
4970 document id: doc6430A] and decodes the values. @emph{Second} it reads the
4971 various clock configuration registers and attempts to display how it
4972 believes the chip is configured. By default, the SLOWCLK is assumed to
4973 be 32768 Hz, see the command @command{at91sam3 slowclk}.
4976 @deffn Command {at91sam3 slowclk} [value]
4977 This command shows/sets the slow clock frequency used in the
4978 @command{at91sam3 info} command calculations above.
4982 @deffn {Flash Driver} at91sam4
4984 All members of the AT91SAM4 microcontroller family from
4985 Atmel include internal flash and use ARM's Cortex-M4 core.
4986 This driver uses the same cmd names/syntax as @xref{at91sam3}.
4989 @deffn {Flash Driver} at91sam7
4990 All members of the AT91SAM7 microcontroller family from Atmel include
4991 internal flash and use ARM7TDMI cores. The driver automatically
4992 recognizes a number of these chips using the chip identification
4993 register, and autoconfigures itself.
4996 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
4999 For chips which are not recognized by the controller driver, you must
5000 provide additional parameters in the following order:
5003 @item @var{chip_model} ... label used with @command{flash info}
5005 @item @var{sectors_per_bank}
5006 @item @var{pages_per_sector}
5007 @item @var{pages_size}
5008 @item @var{num_nvm_bits}
5009 @item @var{freq_khz} ... required if an external clock is provided,
5010 optional (but recommended) when the oscillator frequency is known
5013 It is recommended that you provide zeroes for all of those values
5014 except the clock frequency, so that everything except that frequency
5015 will be autoconfigured.
5016 Knowing the frequency helps ensure correct timings for flash access.
5018 The flash controller handles erases automatically on a page (128/256 byte)
5019 basis, so explicit erase commands are not necessary for flash programming.
5020 However, there is an ``EraseAll`` command that can erase an entire flash
5021 plane (of up to 256KB), and it will be used automatically when you issue
5022 @command{flash erase_sector} or @command{flash erase_address} commands.
5024 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
5025 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
5026 bit for the processor. Each processor has a number of such bits,
5027 used for controlling features such as brownout detection (so they
5028 are not truly general purpose).
5030 This assumes that the first flash bank (number 0) is associated with
5031 the appropriate at91sam7 target.
5036 @deffn {Flash Driver} avr
5037 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
5038 @emph{The current implementation is incomplete.}
5039 @comment - defines mass_erase ... pointless given flash_erase_address
5042 @deffn {Flash Driver} efm32
5043 All members of the EFM32 microcontroller family from Energy Micro include
5044 internal flash and use ARM Cortex M3 cores. The driver automatically recognizes
5045 a number of these chips using the chip identification register, and
5046 autoconfigures itself.
5048 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
5050 @emph{The current implementation is incomplete. Unprotecting flash pages is not
5054 @deffn {Flash Driver} lpc2000
5055 Most members of the LPC1700, LPC1800, LPC2000 and LPC4300 microcontroller
5056 families from NXP include internal flash and use Cortex-M3 (LPC1700, LPC1800),
5057 Cortex-M4 (LPC4300) or ARM7TDMI (LPC2000) cores.
5060 There are LPC2000 devices which are not supported by the @var{lpc2000}
5062 The LPC2888 is supported by the @var{lpc288x} driver.
5063 The LPC29xx family is supported by the @var{lpc2900} driver.
5066 The @var{lpc2000} driver defines two mandatory and one optional parameters,
5067 which must appear in the following order:
5070 @item @var{variant} ... required, may be
5071 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
5072 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
5073 @option{lpc1700} (LPC175x and LPC176x)
5074 or @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
5076 @item @var{clock_kHz} ... the frequency, in kiloHertz,
5077 at which the core is running
5078 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
5079 telling the driver to calculate a valid checksum for the exception vector table.
5081 If you don't provide @option{calc_checksum} when you're writing the vector
5082 table, the boot ROM will almost certainly ignore your flash image.
5083 However, if you do provide it,
5084 with most tool chains @command{verify_image} will fail.
5088 LPC flashes don't require the chip and bus width to be specified.
5091 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
5092 lpc2000_v2 14765 calc_checksum
5095 @deffn {Command} {lpc2000 part_id} bank
5096 Displays the four byte part identifier associated with
5097 the specified flash @var{bank}.
5101 @deffn {Flash Driver} lpc288x
5102 The LPC2888 microcontroller from NXP needs slightly different flash
5103 support from its lpc2000 siblings.
5104 The @var{lpc288x} driver defines one mandatory parameter,
5105 the programming clock rate in Hz.
5106 LPC flashes don't require the chip and bus width to be specified.
5109 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
5113 @deffn {Flash Driver} lpc2900
5114 This driver supports the LPC29xx ARM968E based microcontroller family
5117 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
5118 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
5119 sector layout are auto-configured by the driver.
5120 The driver has one additional mandatory parameter: The CPU clock rate
5121 (in kHz) at the time the flash operations will take place. Most of the time this
5122 will not be the crystal frequency, but a higher PLL frequency. The
5123 @code{reset-init} event handler in the board script is usually the place where
5126 The driver rejects flashless devices (currently the LPC2930).
5128 The EEPROM in LPC2900 devices is not mapped directly into the address space.
5129 It must be handled much more like NAND flash memory, and will therefore be
5130 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
5132 Sector protection in terms of the LPC2900 is handled transparently. Every time a
5133 sector needs to be erased or programmed, it is automatically unprotected.
5134 What is shown as protection status in the @code{flash info} command, is
5135 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
5136 sector from ever being erased or programmed again. As this is an irreversible
5137 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
5138 and not by the standard @code{flash protect} command.
5140 Example for a 125 MHz clock frequency:
5142 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
5145 Some @code{lpc2900}-specific commands are defined. In the following command list,
5146 the @var{bank} parameter is the bank number as obtained by the
5147 @code{flash banks} command.
5149 @deffn Command {lpc2900 signature} bank
5150 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
5151 content. This is a hardware feature of the flash block, hence the calculation is
5152 very fast. You may use this to verify the content of a programmed device against
5157 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
5161 @deffn Command {lpc2900 read_custom} bank filename
5162 Reads the 912 bytes of customer information from the flash index sector, and
5163 saves it to a file in binary format.
5166 lpc2900 read_custom 0 /path_to/customer_info.bin
5170 The index sector of the flash is a @emph{write-only} sector. It cannot be
5171 erased! In order to guard against unintentional write access, all following
5172 commands need to be preceeded by a successful call to the @code{password}
5175 @deffn Command {lpc2900 password} bank password
5176 You need to use this command right before each of the following commands:
5177 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
5178 @code{lpc2900 secure_jtag}.
5180 The password string is fixed to "I_know_what_I_am_doing".
5183 lpc2900 password 0 I_know_what_I_am_doing
5184 Potentially dangerous operation allowed in next command!
5188 @deffn Command {lpc2900 write_custom} bank filename type
5189 Writes the content of the file into the customer info space of the flash index
5190 sector. The filetype can be specified with the @var{type} field. Possible values
5191 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
5192 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
5193 contain a single section, and the contained data length must be exactly
5195 @quotation Attention
5196 This cannot be reverted! Be careful!
5200 lpc2900 write_custom 0 /path_to/customer_info.bin bin
5204 @deffn Command {lpc2900 secure_sector} bank first last
5205 Secures the sector range from @var{first} to @var{last} (including) against
5206 further program and erase operations. The sector security will be effective
5207 after the next power cycle.
5208 @quotation Attention
5209 This cannot be reverted! Be careful!
5211 Secured sectors appear as @emph{protected} in the @code{flash info} command.
5214 lpc2900 secure_sector 0 1 1
5216 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
5217 # 0: 0x00000000 (0x2000 8kB) not protected
5218 # 1: 0x00002000 (0x2000 8kB) protected
5219 # 2: 0x00004000 (0x2000 8kB) not protected
5223 @deffn Command {lpc2900 secure_jtag} bank
5224 Irreversibly disable the JTAG port. The new JTAG security setting will be
5225 effective after the next power cycle.
5226 @quotation Attention
5227 This cannot be reverted! Be careful!
5231 lpc2900 secure_jtag 0
5236 @deffn {Flash Driver} ocl
5237 @emph{No idea what this is, other than using some arm7/arm9 core.}
5240 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
5244 @deffn {Flash Driver} pic32mx
5245 The PIC32MX microcontrollers are based on the MIPS 4K cores,
5246 and integrate flash memory.
5249 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
5250 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
5253 @comment numerous *disabled* commands are defined:
5254 @comment - chip_erase ... pointless given flash_erase_address
5255 @comment - lock, unlock ... pointless given protect on/off (yes?)
5256 @comment - pgm_word ... shouldn't bank be deduced from address??
5257 Some pic32mx-specific commands are defined:
5258 @deffn Command {pic32mx pgm_word} address value bank
5259 Programs the specified 32-bit @var{value} at the given @var{address}
5260 in the specified chip @var{bank}.
5262 @deffn Command {pic32mx unlock} bank
5263 Unlock and erase specified chip @var{bank}.
5264 This will remove any Code Protection.
5268 @deffn {Flash Driver} stellaris
5269 All members of the Stellaris LM3Sxxx microcontroller family from
5271 include internal flash and use ARM Cortex M3 cores.
5272 The driver automatically recognizes a number of these chips using
5273 the chip identification register, and autoconfigures itself.
5274 @footnote{Currently there is a @command{stellaris mass_erase} command.
5275 That seems pointless since the same effect can be had using the
5276 standard @command{flash erase_address} command.}
5279 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
5282 @deffn Command {stellaris recover bank_id}
5283 Performs the @emph{Recovering a "Locked" Device} procedure to
5284 restore the flash specified by @var{bank_id} and its associated
5285 nonvolatile registers to their factory default values (erased).
5286 This is the only way to remove flash protection or re-enable
5287 debugging if that capability has been disabled.
5289 Note that the final "power cycle the chip" step in this procedure
5290 must be performed by hand, since OpenOCD can't do it.
5292 if more than one Stellaris chip is connected, the procedure is
5293 applied to all of them.
5298 @deffn {Flash Driver} stm32f1x
5299 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
5300 from ST Microelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
5301 The driver automatically recognizes a number of these chips using
5302 the chip identification register, and autoconfigures itself.
5305 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
5308 Note that some devices have been found that have a flash size register that contains
5309 an invalid value, to workaround this issue you can override the probed value used by
5313 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
5316 If you have a target with dual flash banks then define the second bank
5317 as per the following example.
5319 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
5322 Some stm32f1x-specific commands
5323 @footnote{Currently there is a @command{stm32f1x mass_erase} command.
5324 That seems pointless since the same effect can be had using the
5325 standard @command{flash erase_address} command.}
5328 @deffn Command {stm32f1x lock} num
5329 Locks the entire stm32 device.
5330 The @var{num} parameter is a value shown by @command{flash banks}.
5333 @deffn Command {stm32f1x unlock} num
5334 Unlocks the entire stm32 device.
5335 The @var{num} parameter is a value shown by @command{flash banks}.
5338 @deffn Command {stm32f1x options_read} num
5339 Read and display the stm32 option bytes written by
5340 the @command{stm32f1x options_write} command.
5341 The @var{num} parameter is a value shown by @command{flash banks}.
5344 @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
5345 Writes the stm32 option byte with the specified values.
5346 The @var{num} parameter is a value shown by @command{flash banks}.
5350 @deffn {Flash Driver} stm32f2x
5351 All members of the STM32F2 and STM32F4 microcontroller families from ST Microelectronics
5352 include internal flash and use ARM Cortex-M3/M4 cores.
5353 The driver automatically recognizes a number of these chips using
5354 the chip identification register, and autoconfigures itself.
5356 Note that some devices have been found that have a flash size register that contains
5357 an invalid value, to workaround this issue you can override the probed value used by
5361 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
5364 Some stm32f2x-specific commands are defined:
5366 @deffn Command {stm32f2x lock} num
5367 Locks the entire stm32 device.
5368 The @var{num} parameter is a value shown by @command{flash banks}.
5371 @deffn Command {stm32f2x unlock} num
5372 Unlocks the entire stm32 device.
5373 The @var{num} parameter is a value shown by @command{flash banks}.
5377 @deffn {Flash Driver} stm32lx
5378 All members of the STM32L microcontroller families from ST Microelectronics
5379 include internal flash and use ARM Cortex-M3 cores.
5380 The driver automatically recognizes a number of these chips using
5381 the chip identification register, and autoconfigures itself.
5383 Note that some devices have been found that have a flash size register that contains
5384 an invalid value, to workaround this issue you can override the probed value used by
5388 flash bank $_FLASHNAME stm32lx 0 0x20000 0 0 $_TARGETNAME
5392 @deffn {Flash Driver} str7x
5393 All members of the STR7 microcontroller family from ST Microelectronics
5394 include internal flash and use ARM7TDMI cores.
5395 The @var{str7x} driver defines one mandatory parameter, @var{variant},
5396 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
5399 flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
5402 @deffn Command {str7x disable_jtag} bank
5403 Activate the Debug/Readout protection mechanism
5404 for the specified flash bank.
5408 @deffn {Flash Driver} str9x
5409 Most members of the STR9 microcontroller family from ST Microelectronics
5410 include internal flash and use ARM966E cores.
5411 The str9 needs the flash controller to be configured using
5412 the @command{str9x flash_config} command prior to Flash programming.
5415 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
5416 str9x flash_config 0 4 2 0 0x80000
5419 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
5420 Configures the str9 flash controller.
5421 The @var{num} parameter is a value shown by @command{flash banks}.
5424 @item @var{bbsr} - Boot Bank Size register
5425 @item @var{nbbsr} - Non Boot Bank Size register
5426 @item @var{bbadr} - Boot Bank Start Address register
5427 @item @var{nbbadr} - Boot Bank Start Address register
5433 @deffn {Flash Driver} tms470
5434 Most members of the TMS470 microcontroller family from Texas Instruments
5435 include internal flash and use ARM7TDMI cores.
5436 This driver doesn't require the chip and bus width to be specified.
5438 Some tms470-specific commands are defined:
5440 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
5441 Saves programming keys in a register, to enable flash erase and write commands.
5444 @deffn Command {tms470 osc_mhz} clock_mhz
5445 Reports the clock speed, which is used to calculate timings.
5448 @deffn Command {tms470 plldis} (0|1)
5449 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
5454 @deffn {Flash Driver} virtual
5455 This is a special driver that maps a previously defined bank to another
5456 address. All bank settings will be copied from the master physical bank.
5458 The @var{virtual} driver defines one mandatory parameters,
5461 @item @var{master_bank} The bank that this virtual address refers to.
5464 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5465 the flash bank defined at address 0x1fc00000. Any cmds executed on
5466 the virtual banks are actually performed on the physical banks.
5468 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5469 flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
5470 flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
5474 @deffn {Flash Driver} fm3
5475 All members of the FM3 microcontroller family from Fujitsu
5476 include internal flash and use ARM Cortex M3 cores.
5477 The @var{fm3} driver uses the @var{target} parameter to select the
5478 correct bank config, it can currently be one of the following:
5479 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
5480 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
5483 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
5487 @subsection str9xpec driver
5490 Here is some background info to help
5491 you better understand how this driver works. OpenOCD has two flash drivers for
5495 Standard driver @option{str9x} programmed via the str9 core. Normally used for
5496 flash programming as it is faster than the @option{str9xpec} driver.
5498 Direct programming @option{str9xpec} using the flash controller. This is an
5499 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
5500 core does not need to be running to program using this flash driver. Typical use
5501 for this driver is locking/unlocking the target and programming the option bytes.
5504 Before we run any commands using the @option{str9xpec} driver we must first disable
5505 the str9 core. This example assumes the @option{str9xpec} driver has been
5506 configured for flash bank 0.
5508 # assert srst, we do not want core running
5509 # while accessing str9xpec flash driver
5511 # turn off target polling
5514 str9xpec enable_turbo 0
5516 str9xpec options_read 0
5517 # re-enable str9 core
5518 str9xpec disable_turbo 0
5522 The above example will read the str9 option bytes.
5523 When performing a unlock remember that you will not be able to halt the str9 - it
5524 has been locked. Halting the core is not required for the @option{str9xpec} driver
5525 as mentioned above, just issue the commands above manually or from a telnet prompt.
5527 @deffn {Flash Driver} str9xpec
5528 Only use this driver for locking/unlocking the device or configuring the option bytes.
5529 Use the standard str9 driver for programming.
5530 Before using the flash commands the turbo mode must be enabled using the
5531 @command{str9xpec enable_turbo} command.
5533 Several str9xpec-specific commands are defined:
5535 @deffn Command {str9xpec disable_turbo} num
5536 Restore the str9 into JTAG chain.
5539 @deffn Command {str9xpec enable_turbo} num
5540 Enable turbo mode, will simply remove the str9 from the chain and talk
5541 directly to the embedded flash controller.
5544 @deffn Command {str9xpec lock} num
5545 Lock str9 device. The str9 will only respond to an unlock command that will
5549 @deffn Command {str9xpec part_id} num
5550 Prints the part identifier for bank @var{num}.
5553 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
5554 Configure str9 boot bank.
5557 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
5558 Configure str9 lvd source.
5561 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
5562 Configure str9 lvd threshold.
5565 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
5566 Configure str9 lvd reset warning source.
5569 @deffn Command {str9xpec options_read} num
5570 Read str9 option bytes.
5573 @deffn Command {str9xpec options_write} num
5574 Write str9 option bytes.
5577 @deffn Command {str9xpec unlock} num
5586 @subsection mFlash Configuration
5587 @cindex mFlash Configuration
5589 @deffn {Config Command} {mflash bank} soc base RST_pin target
5590 Configures a mflash for @var{soc} host bank at
5592 The pin number format depends on the host GPIO naming convention.
5593 Currently, the mflash driver supports s3c2440 and pxa270.
5595 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
5598 mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
5601 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
5604 mflash bank $_FLASHNAME pxa270 0x08000000 43 0
5608 @subsection mFlash commands
5609 @cindex mFlash commands
5611 @deffn Command {mflash config pll} frequency
5612 Configure mflash PLL.
5613 The @var{frequency} is the mflash input frequency, in Hz.
5614 Issuing this command will erase mflash's whole internal nand and write new pll.
5615 After this command, mflash needs power-on-reset for normal operation.
5616 If pll was newly configured, storage and boot(optional) info also need to be update.
5619 @deffn Command {mflash config boot}
5620 Configure bootable option.
5621 If bootable option is set, mflash offer the first 8 sectors
5625 @deffn Command {mflash config storage}
5626 Configure storage information.
5627 For the normal storage operation, this information must be
5631 @deffn Command {mflash dump} num filename offset size
5632 Dump @var{size} bytes, starting at @var{offset} bytes from the
5633 beginning of the bank @var{num}, to the file named @var{filename}.
5636 @deffn Command {mflash probe}
5640 @deffn Command {mflash write} num filename offset
5641 Write the binary file @var{filename} to mflash bank @var{num}, starting at
5642 @var{offset} bytes from the beginning of the bank.
5645 @node Flash Programming
5646 @chapter Flash Programming
5648 OpenOCD implements numerous ways to program the target flash, whether internal or external.
5649 Programming can be acheived by either using GDB @ref{programmingusinggdb,,Programming using GDB},
5650 or using the cmds given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
5652 @*To simplify using the flash cmds directly a jimtcl script is available that handles the programming and verify stage.
5653 OpenOCD will program/verify/reset the target and shutdown.
5655 The script is executed as follows and by default the following actions will be peformed.
5657 @item 'init' is executed.
5658 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
5659 @item @code{flash write_image} is called to erase and write any flash using the filename given.
5660 @item @code{verify_image} is called if @option{verify} parameter is given.
5661 @item @code{reset run} is called if @option{reset} parameter is given.
5662 @item OpenOCD is shutdown.
5665 An example of usage is given below. @xref{program}.
5668 # program and verify using elf/hex/s19. verify and reset
5669 # are optional parameters
5670 openocd -f board/stm32f3discovery.cfg \
5671 -c "program filename.elf verify reset"
5673 # binary files need the flash address passing
5674 openocd -f board/stm32f3discovery.cfg \
5675 -c "program filename.bin 0x08000000"
5678 @node NAND Flash Commands
5679 @chapter NAND Flash Commands
5682 Compared to NOR or SPI flash, NAND devices are inexpensive
5683 and high density. Today's NAND chips, and multi-chip modules,
5684 commonly hold multiple GigaBytes of data.
5686 NAND chips consist of a number of ``erase blocks'' of a given
5687 size (such as 128 KBytes), each of which is divided into a
5688 number of pages (of perhaps 512 or 2048 bytes each). Each
5689 page of a NAND flash has an ``out of band'' (OOB) area to hold
5690 Error Correcting Code (ECC) and other metadata, usually 16 bytes
5691 of OOB for every 512 bytes of page data.
5693 One key characteristic of NAND flash is that its error rate
5694 is higher than that of NOR flash. In normal operation, that
5695 ECC is used to correct and detect errors. However, NAND
5696 blocks can also wear out and become unusable; those blocks
5697 are then marked "bad". NAND chips are even shipped from the
5698 manufacturer with a few bad blocks. The highest density chips
5699 use a technology (MLC) that wears out more quickly, so ECC
5700 support is increasingly important as a way to detect blocks
5701 that have begun to fail, and help to preserve data integrity
5702 with techniques such as wear leveling.
5704 Software is used to manage the ECC. Some controllers don't
5705 support ECC directly; in those cases, software ECC is used.
5706 Other controllers speed up the ECC calculations with hardware.
5707 Single-bit error correction hardware is routine. Controllers
5708 geared for newer MLC chips may correct 4 or more errors for
5709 every 512 bytes of data.
5711 You will need to make sure that any data you write using
5712 OpenOCD includes the apppropriate kind of ECC. For example,
5713 that may mean passing the @code{oob_softecc} flag when
5714 writing NAND data, or ensuring that the correct hardware
5717 The basic steps for using NAND devices include:
5719 @item Declare via the command @command{nand device}
5720 @* Do this in a board-specific configuration file,
5721 passing parameters as needed by the controller.
5722 @item Configure each device using @command{nand probe}.
5723 @* Do this only after the associated target is set up,
5724 such as in its reset-init script or in procures defined
5725 to access that device.
5726 @item Operate on the flash via @command{nand subcommand}
5727 @* Often commands to manipulate the flash are typed by a human, or run
5728 via a script in some automated way. Common task include writing a
5729 boot loader, operating system, or other data needed to initialize or
5733 @b{NOTE:} At the time this text was written, the largest NAND
5734 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
5735 This is because the variables used to hold offsets and lengths
5736 are only 32 bits wide.
5737 (Larger chips may work in some cases, unless an offset or length
5738 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
5739 Some larger devices will work, since they are actually multi-chip
5740 modules with two smaller chips and individual chipselect lines.
5742 @anchor{nandconfiguration}
5743 @section NAND Configuration Commands
5744 @cindex NAND configuration
5746 NAND chips must be declared in configuration scripts,
5747 plus some additional configuration that's done after
5748 OpenOCD has initialized.
5750 @deffn {Config Command} {nand device} name driver target [configparams...]
5751 Declares a NAND device, which can be read and written to
5752 after it has been configured through @command{nand probe}.
5753 In OpenOCD, devices are single chips; this is unlike some
5754 operating systems, which may manage multiple chips as if
5755 they were a single (larger) device.
5756 In some cases, configuring a device will activate extra
5757 commands; see the controller-specific documentation.
5759 @b{NOTE:} This command is not available after OpenOCD
5760 initialization has completed. Use it in board specific
5761 configuration files, not interactively.
5764 @item @var{name} ... may be used to reference the NAND bank
5765 in most other NAND commands. A number is also available.
5766 @item @var{driver} ... identifies the NAND controller driver
5767 associated with the NAND device being declared.
5768 @xref{nanddriverlist,,NAND Driver List}.
5769 @item @var{target} ... names the target used when issuing
5770 commands to the NAND controller.
5771 @comment Actually, it's currently a controller-specific parameter...
5772 @item @var{configparams} ... controllers may support, or require,
5773 additional parameters. See the controller-specific documentation
5774 for more information.
5778 @deffn Command {nand list}
5779 Prints a summary of each device declared
5780 using @command{nand device}, numbered from zero.
5781 Note that un-probed devices show no details.
5784 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
5785 blocksize: 131072, blocks: 8192
5786 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
5787 blocksize: 131072, blocks: 8192
5792 @deffn Command {nand probe} num
5793 Probes the specified device to determine key characteristics
5794 like its page and block sizes, and how many blocks it has.
5795 The @var{num} parameter is the value shown by @command{nand list}.
5796 You must (successfully) probe a device before you can use
5797 it with most other NAND commands.
5800 @section Erasing, Reading, Writing to NAND Flash
5802 @deffn Command {nand dump} num filename offset length [oob_option]
5803 @cindex NAND reading
5804 Reads binary data from the NAND device and writes it to the file,
5805 starting at the specified offset.
5806 The @var{num} parameter is the value shown by @command{nand list}.
5808 Use a complete path name for @var{filename}, so you don't depend
5809 on the directory used to start the OpenOCD server.
5811 The @var{offset} and @var{length} must be exact multiples of the
5812 device's page size. They describe a data region; the OOB data
5813 associated with each such page may also be accessed.
5815 @b{NOTE:} At the time this text was written, no error correction
5816 was done on the data that's read, unless raw access was disabled
5817 and the underlying NAND controller driver had a @code{read_page}
5818 method which handled that error correction.
5820 By default, only page data is saved to the specified file.
5821 Use an @var{oob_option} parameter to save OOB data:
5823 @item no oob_* parameter
5824 @*Output file holds only page data; OOB is discarded.
5825 @item @code{oob_raw}
5826 @*Output file interleaves page data and OOB data;
5827 the file will be longer than "length" by the size of the
5828 spare areas associated with each data page.
5829 Note that this kind of "raw" access is different from
5830 what's implied by @command{nand raw_access}, which just
5831 controls whether a hardware-aware access method is used.
5832 @item @code{oob_only}
5833 @*Output file has only raw OOB data, and will
5834 be smaller than "length" since it will contain only the
5835 spare areas associated with each data page.
5839 @deffn Command {nand erase} num [offset length]
5840 @cindex NAND erasing
5841 @cindex NAND programming
5842 Erases blocks on the specified NAND device, starting at the
5843 specified @var{offset} and continuing for @var{length} bytes.
5844 Both of those values must be exact multiples of the device's
5845 block size, and the region they specify must fit entirely in the chip.
5846 If those parameters are not specified,
5847 the whole NAND chip will be erased.
5848 The @var{num} parameter is the value shown by @command{nand list}.
5850 @b{NOTE:} This command will try to erase bad blocks, when told
5851 to do so, which will probably invalidate the manufacturer's bad
5853 For the remainder of the current server session, @command{nand info}
5854 will still report that the block ``is'' bad.
5857 @deffn Command {nand write} num filename offset [option...]
5858 @cindex NAND writing
5859 @cindex NAND programming
5860 Writes binary data from the file into the specified NAND device,
5861 starting at the specified offset. Those pages should already
5862 have been erased; you can't change zero bits to one bits.
5863 The @var{num} parameter is the value shown by @command{nand list}.
5865 Use a complete path name for @var{filename}, so you don't depend
5866 on the directory used to start the OpenOCD server.
5868 The @var{offset} must be an exact multiple of the device's page size.
5869 All data in the file will be written, assuming it doesn't run
5870 past the end of the device.
5871 Only full pages are written, and any extra space in the last
5872 page will be filled with 0xff bytes. (That includes OOB data,
5873 if that's being written.)
5875 @b{NOTE:} At the time this text was written, bad blocks are
5876 ignored. That is, this routine will not skip bad blocks,
5877 but will instead try to write them. This can cause problems.
5879 Provide at most one @var{option} parameter. With some
5880 NAND drivers, the meanings of these parameters may change
5881 if @command{nand raw_access} was used to disable hardware ECC.
5883 @item no oob_* parameter
5884 @*File has only page data, which is written.
5885 If raw acccess is in use, the OOB area will not be written.
5886 Otherwise, if the underlying NAND controller driver has
5887 a @code{write_page} routine, that routine may write the OOB
5888 with hardware-computed ECC data.
5889 @item @code{oob_only}
5890 @*File has only raw OOB data, which is written to the OOB area.
5891 Each page's data area stays untouched. @i{This can be a dangerous
5892 option}, since it can invalidate the ECC data.
5893 You may need to force raw access to use this mode.
5894 @item @code{oob_raw}
5895 @*File interleaves data and OOB data, both of which are written
5896 If raw access is enabled, the data is written first, then the
5898 Otherwise, if the underlying NAND controller driver has
5899 a @code{write_page} routine, that routine may modify the OOB
5900 before it's written, to include hardware-computed ECC data.
5901 @item @code{oob_softecc}
5902 @*File has only page data, which is written.
5903 The OOB area is filled with 0xff, except for a standard 1-bit
5904 software ECC code stored in conventional locations.
5905 You might need to force raw access to use this mode, to prevent
5906 the underlying driver from applying hardware ECC.
5907 @item @code{oob_softecc_kw}
5908 @*File has only page data, which is written.
5909 The OOB area is filled with 0xff, except for a 4-bit software ECC
5910 specific to the boot ROM in Marvell Kirkwood SoCs.
5911 You might need to force raw access to use this mode, to prevent
5912 the underlying driver from applying hardware ECC.
5916 @deffn Command {nand verify} num filename offset [option...]
5917 @cindex NAND verification
5918 @cindex NAND programming
5919 Verify the binary data in the file has been programmed to the
5920 specified NAND device, starting at the specified offset.
5921 The @var{num} parameter is the value shown by @command{nand list}.
5923 Use a complete path name for @var{filename}, so you don't depend
5924 on the directory used to start the OpenOCD server.
5926 The @var{offset} must be an exact multiple of the device's page size.
5927 All data in the file will be read and compared to the contents of the
5928 flash, assuming it doesn't run past the end of the device.
5929 As with @command{nand write}, only full pages are verified, so any extra
5930 space in the last page will be filled with 0xff bytes.
5932 The same @var{options} accepted by @command{nand write},
5933 and the file will be processed similarly to produce the buffers that
5934 can be compared against the contents produced from @command{nand dump}.
5936 @b{NOTE:} This will not work when the underlying NAND controller
5937 driver's @code{write_page} routine must update the OOB with a
5938 hardward-computed ECC before the data is written. This limitation may
5939 be removed in a future release.
5942 @section Other NAND commands
5943 @cindex NAND other commands
5945 @deffn Command {nand check_bad_blocks} num [offset length]
5946 Checks for manufacturer bad block markers on the specified NAND
5947 device. If no parameters are provided, checks the whole
5948 device; otherwise, starts at the specified @var{offset} and
5949 continues for @var{length} bytes.
5950 Both of those values must be exact multiples of the device's
5951 block size, and the region they specify must fit entirely in the chip.
5952 The @var{num} parameter is the value shown by @command{nand list}.
5954 @b{NOTE:} Before using this command you should force raw access
5955 with @command{nand raw_access enable} to ensure that the underlying
5956 driver will not try to apply hardware ECC.
5959 @deffn Command {nand info} num
5960 The @var{num} parameter is the value shown by @command{nand list}.
5961 This prints the one-line summary from "nand list", plus for
5962 devices which have been probed this also prints any known
5963 status for each block.
5966 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
5967 Sets or clears an flag affecting how page I/O is done.
5968 The @var{num} parameter is the value shown by @command{nand list}.
5970 This flag is cleared (disabled) by default, but changing that
5971 value won't affect all NAND devices. The key factor is whether
5972 the underlying driver provides @code{read_page} or @code{write_page}
5973 methods. If it doesn't provide those methods, the setting of
5974 this flag is irrelevant; all access is effectively ``raw''.
5976 When those methods exist, they are normally used when reading
5977 data (@command{nand dump} or reading bad block markers) or
5978 writing it (@command{nand write}). However, enabling
5979 raw access (setting the flag) prevents use of those methods,
5980 bypassing hardware ECC logic.
5981 @i{This can be a dangerous option}, since writing blocks
5982 with the wrong ECC data can cause them to be marked as bad.
5985 @anchor{nanddriverlist}
5986 @section NAND Driver List
5987 As noted above, the @command{nand device} command allows
5988 driver-specific options and behaviors.
5989 Some controllers also activate controller-specific commands.
5991 @deffn {NAND Driver} at91sam9
5992 This driver handles the NAND controllers found on AT91SAM9 family chips from
5993 Atmel. It takes two extra parameters: address of the NAND chip;
5994 address of the ECC controller.
5996 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
5998 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
5999 @code{read_page} methods are used to utilize the ECC hardware unless they are
6000 disabled by using the @command{nand raw_access} command. There are four
6001 additional commands that are needed to fully configure the AT91SAM9 NAND
6002 controller. Two are optional; most boards use the same wiring for ALE/CLE:
6003 @deffn Command {at91sam9 cle} num addr_line
6004 Configure the address line used for latching commands. The @var{num}
6005 parameter is the value shown by @command{nand list}.
6007 @deffn Command {at91sam9 ale} num addr_line
6008 Configure the address line used for latching addresses. The @var{num}
6009 parameter is the value shown by @command{nand list}.
6012 For the next two commands, it is assumed that the pins have already been
6013 properly configured for input or output.
6014 @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
6015 Configure the RDY/nBUSY input from the NAND device. The @var{num}
6016 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
6017 is the base address of the PIO controller and @var{pin} is the pin number.
6019 @deffn Command {at91sam9 ce} num pio_base_addr pin
6020 Configure the chip enable input to the NAND device. The @var{num}
6021 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
6022 is the base address of the PIO controller and @var{pin} is the pin number.
6026 @deffn {NAND Driver} davinci
6027 This driver handles the NAND controllers found on DaVinci family
6028 chips from Texas Instruments.
6029 It takes three extra parameters:
6030 address of the NAND chip;
6031 hardware ECC mode to use (@option{hwecc1},
6032 @option{hwecc4}, @option{hwecc4_infix});
6033 address of the AEMIF controller on this processor.
6035 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
6037 All DaVinci processors support the single-bit ECC hardware,
6038 and newer ones also support the four-bit ECC hardware.
6039 The @code{write_page} and @code{read_page} methods are used
6040 to implement those ECC modes, unless they are disabled using
6041 the @command{nand raw_access} command.
6044 @deffn {NAND Driver} lpc3180
6045 These controllers require an extra @command{nand device}
6046 parameter: the clock rate used by the controller.
6047 @deffn Command {lpc3180 select} num [mlc|slc]
6048 Configures use of the MLC or SLC controller mode.
6049 MLC implies use of hardware ECC.
6050 The @var{num} parameter is the value shown by @command{nand list}.
6053 At this writing, this driver includes @code{write_page}
6054 and @code{read_page} methods. Using @command{nand raw_access}
6055 to disable those methods will prevent use of hardware ECC
6056 in the MLC controller mode, but won't change SLC behavior.
6058 @comment current lpc3180 code won't issue 5-byte address cycles
6060 @deffn {NAND Driver} mx3
6061 This driver handles the NAND controller in i.MX31. The mxc driver
6062 should work for this chip aswell.
6065 @deffn {NAND Driver} mxc
6066 This driver handles the NAND controller found in Freescale i.MX
6067 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
6068 The driver takes 3 extra arguments, chip (@option{mx27},
6069 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
6070 and optionally if bad block information should be swapped between
6071 main area and spare area (@option{biswap}), defaults to off.
6073 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
6075 @deffn Command {mxc biswap} bank_num [enable|disable]
6076 Turns on/off bad block information swaping from main area,
6077 without parameter query status.
6081 @deffn {NAND Driver} orion
6082 These controllers require an extra @command{nand device}
6083 parameter: the address of the controller.
6085 nand device orion 0xd8000000
6087 These controllers don't define any specialized commands.
6088 At this writing, their drivers don't include @code{write_page}
6089 or @code{read_page} methods, so @command{nand raw_access} won't
6090 change any behavior.
6093 @deffn {NAND Driver} s3c2410
6094 @deffnx {NAND Driver} s3c2412
6095 @deffnx {NAND Driver} s3c2440
6096 @deffnx {NAND Driver} s3c2443
6097 @deffnx {NAND Driver} s3c6400
6098 These S3C family controllers don't have any special
6099 @command{nand device} options, and don't define any
6100 specialized commands.
6101 At this writing, their drivers don't include @code{write_page}
6102 or @code{read_page} methods, so @command{nand raw_access} won't
6103 change any behavior.
6106 @node PLD/FPGA Commands
6107 @chapter PLD/FPGA Commands
6111 Programmable Logic Devices (PLDs) and the more flexible
6112 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
6113 OpenOCD can support programming them.
6114 Although PLDs are generally restrictive (cells are less functional, and
6115 there are no special purpose cells for memory or computational tasks),
6116 they share the same OpenOCD infrastructure.
6117 Accordingly, both are called PLDs here.
6119 @section PLD/FPGA Configuration and Commands
6121 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
6122 OpenOCD maintains a list of PLDs available for use in various commands.
6123 Also, each such PLD requires a driver.
6125 They are referenced by the number shown by the @command{pld devices} command,
6126 and new PLDs are defined by @command{pld device driver_name}.
6128 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
6129 Defines a new PLD device, supported by driver @var{driver_name},
6130 using the TAP named @var{tap_name}.
6131 The driver may make use of any @var{driver_options} to configure its
6135 @deffn {Command} {pld devices}
6136 Lists the PLDs and their numbers.
6139 @deffn {Command} {pld load} num filename
6140 Loads the file @file{filename} into the PLD identified by @var{num}.
6141 The file format must be inferred by the driver.
6144 @section PLD/FPGA Drivers, Options, and Commands
6146 Drivers may support PLD-specific options to the @command{pld device}
6147 definition command, and may also define commands usable only with
6148 that particular type of PLD.
6150 @deffn {FPGA Driver} virtex2
6151 Virtex-II is a family of FPGAs sold by Xilinx.
6152 It supports the IEEE 1532 standard for In-System Configuration (ISC).
6153 No driver-specific PLD definition options are used,
6154 and one driver-specific command is defined.
6156 @deffn {Command} {virtex2 read_stat} num
6157 Reads and displays the Virtex-II status register (STAT)
6162 @node General Commands
6163 @chapter General Commands
6166 The commands documented in this chapter here are common commands that
6167 you, as a human, may want to type and see the output of. Configuration type
6168 commands are documented elsewhere.
6172 @item @b{Source Of Commands}
6173 @* OpenOCD commands can occur in a configuration script (discussed
6174 elsewhere) or typed manually by a human or supplied programatically,
6175 or via one of several TCP/IP Ports.
6177 @item @b{From the human}
6178 @* A human should interact with the telnet interface (default port: 4444)
6179 or via GDB (default port 3333).
6181 To issue commands from within a GDB session, use the @option{monitor}
6182 command, e.g. use @option{monitor poll} to issue the @option{poll}
6183 command. All output is relayed through the GDB session.
6185 @item @b{Machine Interface}
6186 The Tcl interface's intent is to be a machine interface. The default Tcl
6191 @section Daemon Commands
6193 @deffn {Command} exit
6194 Exits the current telnet session.
6197 @deffn {Command} help [string]
6198 With no parameters, prints help text for all commands.
6199 Otherwise, prints each helptext containing @var{string}.
6200 Not every command provides helptext.
6202 Configuration commands, and commands valid at any time, are
6203 explicitly noted in parenthesis.
6204 In most cases, no such restriction is listed; this indicates commands
6205 which are only available after the configuration stage has completed.
6208 @deffn Command sleep msec [@option{busy}]
6209 Wait for at least @var{msec} milliseconds before resuming.
6210 If @option{busy} is passed, busy-wait instead of sleeping.
6211 (This option is strongly discouraged.)
6212 Useful in connection with script files
6213 (@command{script} command and @command{target_name} configuration).
6216 @deffn Command shutdown
6217 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
6221 @deffn Command debug_level [n]
6222 @cindex message level
6223 Display debug level.
6224 If @var{n} (from 0..3) is provided, then set it to that level.
6225 This affects the kind of messages sent to the server log.
6226 Level 0 is error messages only;
6227 level 1 adds warnings;
6228 level 2 adds informational messages;
6229 and level 3 adds debugging messages.
6230 The default is level 2, but that can be overridden on
6231 the command line along with the location of that log
6232 file (which is normally the server's standard output).
6236 @deffn Command echo [-n] message
6237 Logs a message at "user" priority.
6238 Output @var{message} to stdout.
6239 Option "-n" suppresses trailing newline.
6241 echo "Downloading kernel -- please wait"
6245 @deffn Command log_output [filename]
6246 Redirect logging to @var{filename};
6247 the initial log output channel is stderr.
6250 @deffn Command add_script_search_dir [directory]
6251 Add @var{directory} to the file/script search path.
6254 @anchor{targetstatehandling}
6255 @section Target State handling
6258 @cindex target initialization
6260 In this section ``target'' refers to a CPU configured as
6261 shown earlier (@pxref{CPU Configuration}).
6262 These commands, like many, implicitly refer to
6263 a current target which is used to perform the
6264 various operations. The current target may be changed
6265 by using @command{targets} command with the name of the
6266 target which should become current.
6268 @deffn Command reg [(number|name) [value]]
6269 Access a single register by @var{number} or by its @var{name}.
6270 The target must generally be halted before access to CPU core
6271 registers is allowed. Depending on the hardware, some other
6272 registers may be accessible while the target is running.
6274 @emph{With no arguments}:
6275 list all available registers for the current target,
6276 showing number, name, size, value, and cache status.
6277 For valid entries, a value is shown; valid entries
6278 which are also dirty (and will be written back later)
6279 are flagged as such.
6281 @emph{With number/name}: display that register's value.
6283 @emph{With both number/name and value}: set register's value.
6284 Writes may be held in a writeback cache internal to OpenOCD,
6285 so that setting the value marks the register as dirty instead
6286 of immediately flushing that value. Resuming CPU execution
6287 (including by single stepping) or otherwise activating the
6288 relevant module will flush such values.
6290 Cores may have surprisingly many registers in their
6291 Debug and trace infrastructure:
6296 (0) r0 (/32): 0x0000D3C2 (dirty)
6297 (1) r1 (/32): 0xFD61F31C
6300 (164) ETM_contextid_comparator_mask (/32)
6305 @deffn Command halt [ms]
6306 @deffnx Command wait_halt [ms]
6307 The @command{halt} command first sends a halt request to the target,
6308 which @command{wait_halt} doesn't.
6309 Otherwise these behave the same: wait up to @var{ms} milliseconds,
6310 or 5 seconds if there is no parameter, for the target to halt
6311 (and enter debug mode).
6312 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
6315 On ARM cores, software using the @emph{wait for interrupt} operation
6316 often blocks the JTAG access needed by a @command{halt} command.
6317 This is because that operation also puts the core into a low
6318 power mode by gating the core clock;
6319 but the core clock is needed to detect JTAG clock transitions.
6321 One partial workaround uses adaptive clocking: when the core is
6322 interrupted the operation completes, then JTAG clocks are accepted
6323 at least until the interrupt handler completes.
6324 However, this workaround is often unusable since the processor, board,
6325 and JTAG adapter must all support adaptive JTAG clocking.
6326 Also, it can't work until an interrupt is issued.
6328 A more complete workaround is to not use that operation while you
6329 work with a JTAG debugger.
6330 Tasking environments generaly have idle loops where the body is the
6331 @emph{wait for interrupt} operation.
6332 (On older cores, it is a coprocessor action;
6333 newer cores have a @option{wfi} instruction.)
6334 Such loops can just remove that operation, at the cost of higher
6335 power consumption (because the CPU is needlessly clocked).
6340 @deffn Command resume [address]
6341 Resume the target at its current code position,
6342 or the optional @var{address} if it is provided.
6343 OpenOCD will wait 5 seconds for the target to resume.
6346 @deffn Command step [address]
6347 Single-step the target at its current code position,
6348 or the optional @var{address} if it is provided.
6351 @anchor{resetcommand}
6352 @deffn Command reset
6353 @deffnx Command {reset run}
6354 @deffnx Command {reset halt}
6355 @deffnx Command {reset init}
6356 Perform as hard a reset as possible, using SRST if possible.
6357 @emph{All defined targets will be reset, and target
6358 events will fire during the reset sequence.}
6360 The optional parameter specifies what should
6361 happen after the reset.
6362 If there is no parameter, a @command{reset run} is executed.
6363 The other options will not work on all systems.
6364 @xref{Reset Configuration}.
6367 @item @b{run} Let the target run
6368 @item @b{halt} Immediately halt the target
6369 @item @b{init} Immediately halt the target, and execute the reset-init script
6373 @deffn Command soft_reset_halt
6374 Requesting target halt and executing a soft reset. This is often used
6375 when a target cannot be reset and halted. The target, after reset is
6376 released begins to execute code. OpenOCD attempts to stop the CPU and
6377 then sets the program counter back to the reset vector. Unfortunately
6378 the code that was executed may have left the hardware in an unknown
6382 @section I/O Utilities
6384 These commands are available when
6385 OpenOCD is built with @option{--enable-ioutil}.
6386 They are mainly useful on embedded targets,
6388 Hosts with operating systems have complementary tools.
6390 @emph{Note:} there are several more such commands.
6392 @deffn Command append_file filename [string]*
6393 Appends the @var{string} parameters to
6394 the text file @file{filename}.
6395 Each string except the last one is followed by one space.
6396 The last string is followed by a newline.
6399 @deffn Command cat filename
6400 Reads and displays the text file @file{filename}.
6403 @deffn Command cp src_filename dest_filename
6404 Copies contents from the file @file{src_filename}
6405 into @file{dest_filename}.
6409 @emph{No description provided.}
6413 @emph{No description provided.}
6417 @emph{No description provided.}
6420 @deffn Command meminfo
6421 Display available RAM memory on OpenOCD host.
6422 Used in OpenOCD regression testing scripts.
6426 @emph{No description provided.}
6430 @emph{No description provided.}
6433 @deffn Command rm filename
6434 @c "rm" has both normal and Jim-level versions??
6435 Unlinks the file @file{filename}.
6438 @deffn Command trunc filename
6439 Removes all data in the file @file{filename}.
6442 @anchor{memoryaccess}
6443 @section Memory access commands
6444 @cindex memory access
6446 These commands allow accesses of a specific size to the memory
6447 system. Often these are used to configure the current target in some
6448 special way. For example - one may need to write certain values to the
6449 SDRAM controller to enable SDRAM.
6452 @item Use the @command{targets} (plural) command
6453 to change the current target.
6454 @item In system level scripts these commands are deprecated.
6455 Please use their TARGET object siblings to avoid making assumptions
6456 about what TAP is the current target, or about MMU configuration.
6459 @deffn Command mdw [phys] addr [count]
6460 @deffnx Command mdh [phys] addr [count]
6461 @deffnx Command mdb [phys] addr [count]
6462 Display contents of address @var{addr}, as
6463 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
6464 or 8-bit bytes (@command{mdb}).
6465 When the current target has an MMU which is present and active,
6466 @var{addr} is interpreted as a virtual address.
6467 Otherwise, or if the optional @var{phys} flag is specified,
6468 @var{addr} is interpreted as a physical address.
6469 If @var{count} is specified, displays that many units.
6470 (If you want to manipulate the data instead of displaying it,
6471 see the @code{mem2array} primitives.)
6474 @deffn Command mww [phys] addr word
6475 @deffnx Command mwh [phys] addr halfword
6476 @deffnx Command mwb [phys] addr byte
6477 Writes the specified @var{word} (32 bits),
6478 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
6479 at the specified address @var{addr}.
6480 When the current target has an MMU which is present and active,
6481 @var{addr} is interpreted as a virtual address.
6482 Otherwise, or if the optional @var{phys} flag is specified,
6483 @var{addr} is interpreted as a physical address.
6486 @anchor{imageaccess}
6487 @section Image loading commands
6488 @cindex image loading
6489 @cindex image dumping
6491 @deffn Command {dump_image} filename address size
6492 Dump @var{size} bytes of target memory starting at @var{address} to the
6493 binary file named @var{filename}.
6496 @deffn Command {fast_load}
6497 Loads an image stored in memory by @command{fast_load_image} to the
6498 current target. Must be preceeded by fast_load_image.
6501 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
6502 Normally you should be using @command{load_image} or GDB load. However, for
6503 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
6504 host), storing the image in memory and uploading the image to the target
6505 can be a way to upload e.g. multiple debug sessions when the binary does not change.
6506 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
6507 memory, i.e. does not affect target. This approach is also useful when profiling
6508 target programming performance as I/O and target programming can easily be profiled
6512 @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
6513 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
6514 The file format may optionally be specified
6515 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
6516 In addition the following arguments may be specifed:
6517 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
6518 @var{max_length} - maximum number of bytes to load.
6520 proc load_image_bin @{fname foffset address length @} @{
6521 # Load data from fname filename at foffset offset to
6522 # target at address. Load at most length bytes.
6523 load_image $fname [expr $address - $foffset] bin $address $length
6528 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
6529 Displays image section sizes and addresses
6530 as if @var{filename} were loaded into target memory
6531 starting at @var{address} (defaults to zero).
6532 The file format may optionally be specified
6533 (@option{bin}, @option{ihex}, or @option{elf})
6536 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
6537 Verify @var{filename} against target memory starting at @var{address}.
6538 The file format may optionally be specified
6539 (@option{bin}, @option{ihex}, or @option{elf})
6540 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
6544 @section Breakpoint and Watchpoint commands
6548 CPUs often make debug modules accessible through JTAG, with
6549 hardware support for a handful of code breakpoints and data
6551 In addition, CPUs almost always support software breakpoints.
6553 @deffn Command {bp} [address len [@option{hw}]]
6554 With no parameters, lists all active breakpoints.
6555 Else sets a breakpoint on code execution starting
6556 at @var{address} for @var{length} bytes.
6557 This is a software breakpoint, unless @option{hw} is specified
6558 in which case it will be a hardware breakpoint.
6560 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
6561 for similar mechanisms that do not consume hardware breakpoints.)
6564 @deffn Command {rbp} address
6565 Remove the breakpoint at @var{address}.
6568 @deffn Command {rwp} address
6569 Remove data watchpoint on @var{address}
6572 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
6573 With no parameters, lists all active watchpoints.
6574 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
6575 The watch point is an "access" watchpoint unless
6576 the @option{r} or @option{w} parameter is provided,
6577 defining it as respectively a read or write watchpoint.
6578 If a @var{value} is provided, that value is used when determining if
6579 the watchpoint should trigger. The value may be first be masked
6580 using @var{mask} to mark ``don't care'' fields.
6583 @section Misc Commands
6586 @deffn Command {profile} seconds filename
6587 Profiling samples the CPU's program counter as quickly as possible,
6588 which is useful for non-intrusive stochastic profiling.
6589 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
6592 @deffn Command {version}
6593 Displays a string identifying the version of this OpenOCD server.
6596 @deffn Command {virt2phys} virtual_address
6597 Requests the current target to map the specified @var{virtual_address}
6598 to its corresponding physical address, and displays the result.
6601 @node Architecture and Core Commands
6602 @chapter Architecture and Core Commands
6603 @cindex Architecture Specific Commands
6604 @cindex Core Specific Commands
6606 Most CPUs have specialized JTAG operations to support debugging.
6607 OpenOCD packages most such operations in its standard command framework.
6608 Some of those operations don't fit well in that framework, so they are
6609 exposed here as architecture or implementation (core) specific commands.
6611 @anchor{armhardwaretracing}
6612 @section ARM Hardware Tracing
6617 CPUs based on ARM cores may include standard tracing interfaces,
6618 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
6619 address and data bus trace records to a ``Trace Port''.
6623 Development-oriented boards will sometimes provide a high speed
6624 trace connector for collecting that data, when the particular CPU
6625 supports such an interface.
6626 (The standard connector is a 38-pin Mictor, with both JTAG
6627 and trace port support.)
6628 Those trace connectors are supported by higher end JTAG adapters
6629 and some logic analyzer modules; frequently those modules can
6630 buffer several megabytes of trace data.
6631 Configuring an ETM coupled to such an external trace port belongs
6632 in the board-specific configuration file.
6634 If the CPU doesn't provide an external interface, it probably
6635 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
6636 dedicated SRAM. 4KBytes is one common ETB size.
6637 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
6638 (target) configuration file, since it works the same on all boards.
6641 ETM support in OpenOCD doesn't seem to be widely used yet.
6644 ETM support may be buggy, and at least some @command{etm config}
6645 parameters should be detected by asking the ETM for them.
6647 ETM trigger events could also implement a kind of complex
6648 hardware breakpoint, much more powerful than the simple
6649 watchpoint hardware exported by EmbeddedICE modules.
6650 @emph{Such breakpoints can be triggered even when using the
6651 dummy trace port driver}.
6653 It seems like a GDB hookup should be possible,
6654 as well as tracing only during specific states
6655 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
6657 There should be GUI tools to manipulate saved trace data and help
6658 analyse it in conjunction with the source code.
6659 It's unclear how much of a common interface is shared
6660 with the current XScale trace support, or should be
6661 shared with eventual Nexus-style trace module support.
6663 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
6664 for ETM modules is available. The code should be able to
6665 work with some newer cores; but not all of them support
6666 this original style of JTAG access.
6669 @subsection ETM Configuration
6670 ETM setup is coupled with the trace port driver configuration.
6672 @deffn {Config Command} {etm config} target width mode clocking driver
6673 Declares the ETM associated with @var{target}, and associates it
6674 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
6676 Several of the parameters must reflect the trace port capabilities,
6677 which are a function of silicon capabilties (exposed later
6678 using @command{etm info}) and of what hardware is connected to
6679 that port (such as an external pod, or ETB).
6680 The @var{width} must be either 4, 8, or 16,
6681 except with ETMv3.0 and newer modules which may also
6682 support 1, 2, 24, 32, 48, and 64 bit widths.
6683 (With those versions, @command{etm info} also shows whether
6684 the selected port width and mode are supported.)
6686 The @var{mode} must be @option{normal}, @option{multiplexed},
6687 or @option{demultiplexed}.
6688 The @var{clocking} must be @option{half} or @option{full}.
6691 With ETMv3.0 and newer, the bits set with the @var{mode} and
6692 @var{clocking} parameters both control the mode.
6693 This modified mode does not map to the values supported by
6694 previous ETM modules, so this syntax is subject to change.
6698 You can see the ETM registers using the @command{reg} command.
6699 Not all possible registers are present in every ETM.
6700 Most of the registers are write-only, and are used to configure
6701 what CPU activities are traced.
6705 @deffn Command {etm info}
6706 Displays information about the current target's ETM.
6707 This includes resource counts from the @code{ETM_CONFIG} register,
6708 as well as silicon capabilities (except on rather old modules).
6709 from the @code{ETM_SYS_CONFIG} register.
6712 @deffn Command {etm status}
6713 Displays status of the current target's ETM and trace port driver:
6714 is the ETM idle, or is it collecting data?
6715 Did trace data overflow?
6719 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
6720 Displays what data that ETM will collect.
6721 If arguments are provided, first configures that data.
6722 When the configuration changes, tracing is stopped
6723 and any buffered trace data is invalidated.
6726 @item @var{type} ... describing how data accesses are traced,
6727 when they pass any ViewData filtering that that was set up.
6729 @option{none} (save nothing),
6730 @option{data} (save data),
6731 @option{address} (save addresses),
6732 @option{all} (save data and addresses)
6733 @item @var{context_id_bits} ... 0, 8, 16, or 32
6734 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
6735 cycle-accurate instruction tracing.
6736 Before ETMv3, enabling this causes much extra data to be recorded.
6737 @item @var{branch_output} ... @option{enable} or @option{disable}.
6738 Disable this unless you need to try reconstructing the instruction
6739 trace stream without an image of the code.
6743 @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
6744 Displays whether ETM triggering debug entry (like a breakpoint) is
6745 enabled or disabled, after optionally modifying that configuration.
6746 The default behaviour is @option{disable}.
6747 Any change takes effect after the next @command{etm start}.
6749 By using script commands to configure ETM registers, you can make the
6750 processor enter debug state automatically when certain conditions,
6751 more complex than supported by the breakpoint hardware, happen.
6754 @subsection ETM Trace Operation
6756 After setting up the ETM, you can use it to collect data.
6757 That data can be exported to files for later analysis.
6758 It can also be parsed with OpenOCD, for basic sanity checking.
6760 To configure what is being traced, you will need to write
6761 various trace registers using @command{reg ETM_*} commands.
6762 For the definitions of these registers, read ARM publication
6763 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
6764 Be aware that most of the relevant registers are write-only,
6765 and that ETM resources are limited. There are only a handful
6766 of address comparators, data comparators, counters, and so on.
6768 Examples of scenarios you might arrange to trace include:
6771 @item Code flow within a function, @emph{excluding} subroutines
6772 it calls. Use address range comparators to enable tracing
6773 for instruction access within that function's body.
6774 @item Code flow within a function, @emph{including} subroutines
6775 it calls. Use the sequencer and address comparators to activate
6776 tracing on an ``entered function'' state, then deactivate it by
6777 exiting that state when the function's exit code is invoked.
6778 @item Code flow starting at the fifth invocation of a function,
6779 combining one of the above models with a counter.
6780 @item CPU data accesses to the registers for a particular device,
6781 using address range comparators and the ViewData logic.
6782 @item Such data accesses only during IRQ handling, combining the above
6783 model with sequencer triggers which on entry and exit to the IRQ handler.
6784 @item @emph{... more}
6787 At this writing, September 2009, there are no Tcl utility
6788 procedures to help set up any common tracing scenarios.
6790 @deffn Command {etm analyze}
6791 Reads trace data into memory, if it wasn't already present.
6792 Decodes and prints the data that was collected.
6795 @deffn Command {etm dump} filename
6796 Stores the captured trace data in @file{filename}.
6799 @deffn Command {etm image} filename [base_address] [type]
6800 Opens an image file.
6803 @deffn Command {etm load} filename
6804 Loads captured trace data from @file{filename}.
6807 @deffn Command {etm start}
6808 Starts trace data collection.
6811 @deffn Command {etm stop}
6812 Stops trace data collection.
6815 @anchor{traceportdrivers}
6816 @subsection Trace Port Drivers
6818 To use an ETM trace port it must be associated with a driver.
6820 @deffn {Trace Port Driver} dummy
6821 Use the @option{dummy} driver if you are configuring an ETM that's
6822 not connected to anything (on-chip ETB or off-chip trace connector).
6823 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
6824 any trace data collection.}
6825 @deffn {Config Command} {etm_dummy config} target
6826 Associates the ETM for @var{target} with a dummy driver.
6830 @deffn {Trace Port Driver} etb
6831 Use the @option{etb} driver if you are configuring an ETM
6832 to use on-chip ETB memory.
6833 @deffn {Config Command} {etb config} target etb_tap
6834 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
6835 You can see the ETB registers using the @command{reg} command.
6837 @deffn Command {etb trigger_percent} [percent]
6838 This displays, or optionally changes, ETB behavior after the
6839 ETM's configured @emph{trigger} event fires.
6840 It controls how much more trace data is saved after the (single)
6841 trace trigger becomes active.
6844 @item The default corresponds to @emph{trace around} usage,
6845 recording 50 percent data before the event and the rest
6847 @item The minimum value of @var{percent} is 2 percent,
6848 recording almost exclusively data before the trigger.
6849 Such extreme @emph{trace before} usage can help figure out
6850 what caused that event to happen.
6851 @item The maximum value of @var{percent} is 100 percent,
6852 recording data almost exclusively after the event.
6853 This extreme @emph{trace after} usage might help sort out
6854 how the event caused trouble.
6856 @c REVISIT allow "break" too -- enter debug mode.
6861 @deffn {Trace Port Driver} oocd_trace
6862 This driver isn't available unless OpenOCD was explicitly configured
6863 with the @option{--enable-oocd_trace} option. You probably don't want
6864 to configure it unless you've built the appropriate prototype hardware;
6865 it's @emph{proof-of-concept} software.
6867 Use the @option{oocd_trace} driver if you are configuring an ETM that's
6868 connected to an off-chip trace connector.
6870 @deffn {Config Command} {oocd_trace config} target tty
6871 Associates the ETM for @var{target} with a trace driver which
6872 collects data through the serial port @var{tty}.
6875 @deffn Command {oocd_trace resync}
6876 Re-synchronizes with the capture clock.
6879 @deffn Command {oocd_trace status}
6880 Reports whether the capture clock is locked or not.
6885 @section Generic ARM
6888 These commands should be available on all ARM processors.
6889 They are available in addition to other core-specific
6890 commands that may be available.
6892 @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
6893 Displays the core_state, optionally changing it to process
6894 either @option{arm} or @option{thumb} instructions.
6895 The target may later be resumed in the currently set core_state.
6896 (Processors may also support the Jazelle state, but
6897 that is not currently supported in OpenOCD.)
6900 @deffn Command {arm disassemble} address [count [@option{thumb}]]
6902 Disassembles @var{count} instructions starting at @var{address}.
6903 If @var{count} is not specified, a single instruction is disassembled.
6904 If @option{thumb} is specified, or the low bit of the address is set,
6905 Thumb2 (mixed 16/32-bit) instructions are used;
6906 else ARM (32-bit) instructions are used.
6907 (Processors may also support the Jazelle state, but
6908 those instructions are not currently understood by OpenOCD.)
6910 Note that all Thumb instructions are Thumb2 instructions,
6911 so older processors (without Thumb2 support) will still
6912 see correct disassembly of Thumb code.
6913 Also, ThumbEE opcodes are the same as Thumb2,
6914 with a handful of exceptions.
6915 ThumbEE disassembly currently has no explicit support.
6918 @deffn Command {arm mcr} pX op1 CRn CRm op2 value
6919 Write @var{value} to a coprocessor @var{pX} register
6920 passing parameters @var{CRn},
6921 @var{CRm}, opcodes @var{opc1} and @var{opc2},
6922 and using the MCR instruction.
6923 (Parameter sequence matches the ARM instruction, but omits
6927 @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
6928 Read a coprocessor @var{pX} register passing parameters @var{CRn},
6929 @var{CRm}, opcodes @var{opc1} and @var{opc2},
6930 and the MRC instruction.
6931 Returns the result so it can be manipulated by Jim scripts.
6932 (Parameter sequence matches the ARM instruction, but omits
6936 @deffn Command {arm reg}
6937 Display a table of all banked core registers, fetching the current value from every
6938 core mode if necessary.
6941 @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
6942 @cindex ARM semihosting
6943 Display status of semihosting, after optionally changing that status.
6945 Semihosting allows for code executing on an ARM target to use the
6946 I/O facilities on the host computer i.e. the system where OpenOCD
6947 is running. The target application must be linked against a library
6948 implementing the ARM semihosting convention that forwards operation
6949 requests by using a special SVC instruction that is trapped at the
6950 Supervisor Call vector by OpenOCD.
6953 @section ARMv4 and ARMv5 Architecture
6957 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
6958 and introduced core parts of the instruction set in use today.
6959 That includes the Thumb instruction set, introduced in the ARMv4T
6962 @subsection ARM7 and ARM9 specific commands
6966 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
6967 ARM9TDMI, ARM920T or ARM926EJ-S.
6968 They are available in addition to the ARM commands,
6969 and any other core-specific commands that may be available.
6971 @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
6972 Displays the value of the flag controlling use of the
6973 the EmbeddedIce DBGRQ signal to force entry into debug mode,
6974 instead of breakpoints.
6975 If a boolean parameter is provided, first assigns that flag.
6978 safe for all but ARM7TDMI-S cores (like NXP LPC).
6979 This feature is enabled by default on most ARM9 cores,
6980 including ARM9TDMI, ARM920T, and ARM926EJ-S.
6983 @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
6985 Displays the value of the flag controlling use of the debug communications
6986 channel (DCC) to write larger (>128 byte) amounts of memory.
6987 If a boolean parameter is provided, first assigns that flag.
6989 DCC downloads offer a huge speed increase, but might be
6990 unsafe, especially with targets running at very low speeds. This command was introduced
6991 with OpenOCD rev. 60, and requires a few bytes of working area.
6994 @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
6995 Displays the value of the flag controlling use of memory writes and reads
6996 that don't check completion of the operation.
6997 If a boolean parameter is provided, first assigns that flag.
6999 This provides a huge speed increase, especially with USB JTAG
7000 cables (FT2232), but might be unsafe if used with targets running at very low
7001 speeds, like the 32kHz startup clock of an AT91RM9200.
7004 @subsection ARM720T specific commands
7007 These commands are available to ARM720T based CPUs,
7008 which are implementations of the ARMv4T architecture
7009 based on the ARM7TDMI-S integer core.
7010 They are available in addition to the ARM and ARM7/ARM9 commands.
7012 @deffn Command {arm720t cp15} opcode [value]
7013 @emph{DEPRECATED -- avoid using this.
7014 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
7016 Display cp15 register returned by the ARM instruction @var{opcode};
7017 else if a @var{value} is provided, that value is written to that register.
7018 The @var{opcode} should be the value of either an MRC or MCR instruction.
7021 @subsection ARM9 specific commands
7024 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
7026 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
7028 @c 9-june-2009: tried this on arm920t, it didn't work.
7029 @c no-params always lists nothing caught, and that's how it acts.
7030 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
7031 @c versions have different rules about when they commit writes.
7033 @anchor{arm9vectorcatch}
7034 @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
7035 @cindex vector_catch
7036 Vector Catch hardware provides a sort of dedicated breakpoint
7037 for hardware events such as reset, interrupt, and abort.
7038 You can use this to conserve normal breakpoint resources,
7039 so long as you're not concerned with code that branches directly
7040 to those hardware vectors.
7042 This always finishes by listing the current configuration.
7043 If parameters are provided, it first reconfigures the
7044 vector catch hardware to intercept
7045 @option{all} of the hardware vectors,
7046 @option{none} of them,
7047 or a list with one or more of the following:
7048 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
7049 @option{irq} @option{fiq}.
7052 @subsection ARM920T specific commands
7055 These commands are available to ARM920T based CPUs,
7056 which are implementations of the ARMv4T architecture
7057 built using the ARM9TDMI integer core.
7058 They are available in addition to the ARM, ARM7/ARM9,
7061 @deffn Command {arm920t cache_info}
7062 Print information about the caches found. This allows to see whether your target
7063 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
7066 @deffn Command {arm920t cp15} regnum [value]
7067 Display cp15 register @var{regnum};
7068 else if a @var{value} is provided, that value is written to that register.
7069 This uses "physical access" and the register number is as
7070 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
7071 (Not all registers can be written.)
7074 @deffn Command {arm920t cp15i} opcode [value [address]]
7075 @emph{DEPRECATED -- avoid using this.
7076 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
7078 Interpreted access using ARM instruction @var{opcode}, which should
7079 be the value of either an MRC or MCR instruction
7080 (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
7081 If no @var{value} is provided, the result is displayed.
7082 Else if that value is written using the specified @var{address},
7083 or using zero if no other address is provided.
7086 @deffn Command {arm920t read_cache} filename
7087 Dump the content of ICache and DCache to a file named @file{filename}.
7090 @deffn Command {arm920t read_mmu} filename
7091 Dump the content of the ITLB and DTLB to a file named @file{filename}.
7094 @subsection ARM926ej-s specific commands
7097 These commands are available to ARM926ej-s based CPUs,
7098 which are implementations of the ARMv5TEJ architecture
7099 based on the ARM9EJ-S integer core.
7100 They are available in addition to the ARM, ARM7/ARM9,
7103 The Feroceon cores also support these commands, although
7104 they are not built from ARM926ej-s designs.
7106 @deffn Command {arm926ejs cache_info}
7107 Print information about the caches found.
7110 @subsection ARM966E specific commands
7113 These commands are available to ARM966 based CPUs,
7114 which are implementations of the ARMv5TE architecture.
7115 They are available in addition to the ARM, ARM7/ARM9,
7118 @deffn Command {arm966e cp15} regnum [value]
7119 Display cp15 register @var{regnum};
7120 else if a @var{value} is provided, that value is written to that register.
7121 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
7123 There is no current control over bits 31..30 from that table,
7124 as required for BIST support.
7127 @subsection XScale specific commands
7130 Some notes about the debug implementation on the XScale CPUs:
7132 The XScale CPU provides a special debug-only mini-instruction cache
7133 (mini-IC) in which exception vectors and target-resident debug handler
7134 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
7135 must point vector 0 (the reset vector) to the entry of the debug
7136 handler. However, this means that the complete first cacheline in the
7137 mini-IC is marked valid, which makes the CPU fetch all exception
7138 handlers from the mini-IC, ignoring the code in RAM.
7140 To address this situation, OpenOCD provides the @code{xscale
7141 vector_table} command, which allows the user to explicity write
7142 individual entries to either the high or low vector table stored in
7145 It is recommended to place a pc-relative indirect branch in the vector
7146 table, and put the branch destination somewhere in memory. Doing so
7147 makes sure the code in the vector table stays constant regardless of
7148 code layout in memory:
7151 ldr pc,[pc,#0x100-8]
7152 ldr pc,[pc,#0x100-8]
7153 ldr pc,[pc,#0x100-8]
7154 ldr pc,[pc,#0x100-8]
7155 ldr pc,[pc,#0x100-8]
7156 ldr pc,[pc,#0x100-8]
7157 ldr pc,[pc,#0x100-8]
7158 ldr pc,[pc,#0x100-8]
7160 .long real_reset_vector
7161 .long real_ui_handler
7162 .long real_swi_handler
7164 .long real_data_abort
7165 .long 0 /* unused */
7166 .long real_irq_handler
7167 .long real_fiq_handler
7170 Alternatively, you may choose to keep some or all of the mini-IC
7171 vector table entries synced with those written to memory by your
7172 system software. The mini-IC can not be modified while the processor
7173 is executing, but for each vector table entry not previously defined
7174 using the @code{xscale vector_table} command, OpenOCD will copy the
7175 value from memory to the mini-IC every time execution resumes from a
7176 halt. This is done for both high and low vector tables (although the
7177 table not in use may not be mapped to valid memory, and in this case
7178 that copy operation will silently fail). This means that you will
7179 need to briefly halt execution at some strategic point during system
7180 start-up; e.g., after the software has initialized the vector table,
7181 but before exceptions are enabled. A breakpoint can be used to
7182 accomplish this once the appropriate location in the start-up code has
7183 been identified. A watchpoint over the vector table region is helpful
7184 in finding the location if you're not sure. Note that the same
7185 situation exists any time the vector table is modified by the system
7188 The debug handler must be placed somewhere in the address space using
7189 the @code{xscale debug_handler} command. The allowed locations for the
7190 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
7191 0xfffff800). The default value is 0xfe000800.
7193 XScale has resources to support two hardware breakpoints and two
7194 watchpoints. However, the following restrictions on watchpoint
7195 functionality apply: (1) the value and mask arguments to the @code{wp}
7196 command are not supported, (2) the watchpoint length must be a
7197 power of two and not less than four, and can not be greater than the
7198 watchpoint address, and (3) a watchpoint with a length greater than
7199 four consumes all the watchpoint hardware resources. This means that
7200 at any one time, you can have enabled either two watchpoints with a
7201 length of four, or one watchpoint with a length greater than four.
7203 These commands are available to XScale based CPUs,
7204 which are implementations of the ARMv5TE architecture.
7206 @deffn Command {xscale analyze_trace}
7207 Displays the contents of the trace buffer.
7210 @deffn Command {xscale cache_clean_address} address
7211 Changes the address used when cleaning the data cache.
7214 @deffn Command {xscale cache_info}
7215 Displays information about the CPU caches.
7218 @deffn Command {xscale cp15} regnum [value]
7219 Display cp15 register @var{regnum};
7220 else if a @var{value} is provided, that value is written to that register.
7223 @deffn Command {xscale debug_handler} target address
7224 Changes the address used for the specified target's debug handler.
7227 @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
7228 Enables or disable the CPU's data cache.
7231 @deffn Command {xscale dump_trace} filename
7232 Dumps the raw contents of the trace buffer to @file{filename}.
7235 @deffn Command {xscale icache} [@option{enable}|@option{disable}]
7236 Enables or disable the CPU's instruction cache.
7239 @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
7240 Enables or disable the CPU's memory management unit.
7243 @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
7244 Displays the trace buffer status, after optionally
7245 enabling or disabling the trace buffer
7246 and modifying how it is emptied.
7249 @deffn Command {xscale trace_image} filename [offset [type]]
7250 Opens a trace image from @file{filename}, optionally rebasing
7251 its segment addresses by @var{offset}.
7252 The image @var{type} may be one of
7253 @option{bin} (binary), @option{ihex} (Intel hex),
7254 @option{elf} (ELF file), @option{s19} (Motorola s19),
7255 @option{mem}, or @option{builder}.
7258 @anchor{xscalevectorcatch}
7259 @deffn Command {xscale vector_catch} [mask]
7260 @cindex vector_catch
7261 Display a bitmask showing the hardware vectors to catch.
7262 If the optional parameter is provided, first set the bitmask to that value.
7264 The mask bits correspond with bit 16..23 in the DCSR:
7267 0x02 Trap Undefined Instructions
7268 0x04 Trap Software Interrupt
7269 0x08 Trap Prefetch Abort
7270 0x10 Trap Data Abort
7277 @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
7278 @cindex vector_table
7280 Set an entry in the mini-IC vector table. There are two tables: one for
7281 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
7282 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
7283 points to the debug handler entry and can not be overwritten.
7284 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
7286 Without arguments, the current settings are displayed.
7290 @section ARMv6 Architecture
7293 @subsection ARM11 specific commands
7296 @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
7297 Displays the value of the memwrite burst-enable flag,
7298 which is enabled by default.
7299 If a boolean parameter is provided, first assigns that flag.
7300 Burst writes are only used for memory writes larger than 1 word.
7301 They improve performance by assuming that the CPU has read each data
7302 word over JTAG and completed its write before the next word arrives,
7303 instead of polling for a status flag to verify that completion.
7304 This is usually safe, because JTAG runs much slower than the CPU.
7307 @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
7308 Displays the value of the memwrite error_fatal flag,
7309 which is enabled by default.
7310 If a boolean parameter is provided, first assigns that flag.
7311 When set, certain memory write errors cause earlier transfer termination.
7314 @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
7315 Displays the value of the flag controlling whether
7316 IRQs are enabled during single stepping;
7317 they are disabled by default.
7318 If a boolean parameter is provided, first assigns that.
7321 @deffn Command {arm11 vcr} [value]
7322 @cindex vector_catch
7323 Displays the value of the @emph{Vector Catch Register (VCR)},
7324 coprocessor 14 register 7.
7325 If @var{value} is defined, first assigns that.
7327 Vector Catch hardware provides dedicated breakpoints
7328 for certain hardware events.
7329 The specific bit values are core-specific (as in fact is using
7330 coprocessor 14 register 7 itself) but all current ARM11
7331 cores @emph{except the ARM1176} use the same six bits.
7334 @section ARMv7 Architecture
7337 @subsection ARMv7 Debug Access Port (DAP) specific commands
7338 @cindex Debug Access Port
7340 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
7341 included on Cortex-M and Cortex-A systems.
7342 They are available in addition to other core-specific commands that may be available.
7344 @deffn Command {dap apid} [num]
7345 Displays ID register from AP @var{num},
7346 defaulting to the currently selected AP.
7349 @deffn Command {dap apsel} [num]
7350 Select AP @var{num}, defaulting to 0.
7353 @deffn Command {dap baseaddr} [num]
7354 Displays debug base address from MEM-AP @var{num},
7355 defaulting to the currently selected AP.
7358 @deffn Command {dap info} [num]
7359 Displays the ROM table for MEM-AP @var{num},
7360 defaulting to the currently selected AP.
7363 @deffn Command {dap memaccess} [value]
7364 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
7365 memory bus access [0-255], giving additional time to respond to reads.
7366 If @var{value} is defined, first assigns that.
7369 @deffn Command {dap apcsw} [0 / 1]
7370 fix CSW_SPROT from register AP_REG_CSW on selected dap.
7374 @subsection Cortex-M specific commands
7377 @deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
7378 Control masking (disabling) interrupts during target step/resume.
7380 The @option{auto} option handles interrupts during stepping a way they get
7381 served but don't disturb the program flow. The step command first allows
7382 pending interrupt handlers to execute, then disables interrupts and steps over
7383 the next instruction where the core was halted. After the step interrupts
7384 are enabled again. If the interrupt handlers don't complete within 500ms,
7385 the step command leaves with the core running.
7387 Note that a free breakpoint is required for the @option{auto} option. If no
7388 breakpoint is available at the time of the step, then the step is taken
7389 with interrupts enabled, i.e. the same way the @option{off} option does.
7391 Default is @option{auto}.
7394 @deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
7395 @cindex vector_catch
7396 Vector Catch hardware provides dedicated breakpoints
7397 for certain hardware events.
7399 Parameters request interception of
7400 @option{all} of these hardware event vectors,
7401 @option{none} of them,
7402 or one or more of the following:
7403 @option{hard_err} for a HardFault exception;
7404 @option{mm_err} for a MemManage exception;
7405 @option{bus_err} for a BusFault exception;
7408 @option{chk_err}, or
7409 @option{nocp_err} for various UsageFault exceptions; or
7411 If NVIC setup code does not enable them,
7412 MemManage, BusFault, and UsageFault exceptions
7413 are mapped to HardFault.
7414 UsageFault checks for
7415 divide-by-zero and unaligned access
7416 must also be explicitly enabled.
7418 This finishes by listing the current vector catch configuration.
7421 @deffn Command {cortex_m reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
7422 Control reset handling. The default @option{srst} is to use srst if fitted,
7423 otherwise fallback to @option{vectreset}.
7425 @item @option{srst} use hardware srst if fitted otherwise fallback to @option{vectreset}.
7426 @item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
7427 @item @option{vectreset} use NVIC VECTRESET to reset system.
7429 Using @option{vectreset} is a safe option for all current Cortex-M cores.
7430 This however has the disadvantage of only resetting the core, all peripherals
7431 are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
7433 @xref{targetevents,,Target Events}.
7436 @anchor{softwaredebugmessagesandtracing}
7437 @section Software Debug Messages and Tracing
7438 @cindex Linux-ARM DCC support
7442 OpenOCD can process certain requests from target software, when
7443 the target uses appropriate libraries.
7444 The most powerful mechanism is semihosting, but there is also
7445 a lighter weight mechanism using only the DCC channel.
7447 Currently @command{target_request debugmsgs}
7448 is supported only for @option{arm7_9} and @option{cortex_m} cores.
7449 These messages are received as part of target polling, so
7450 you need to have @command{poll on} active to receive them.
7451 They are intrusive in that they will affect program execution
7452 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
7454 See @file{libdcc} in the contrib dir for more details.
7455 In addition to sending strings, characters, and
7456 arrays of various size integers from the target,
7457 @file{libdcc} also exports a software trace point mechanism.
7458 The target being debugged may
7459 issue trace messages which include a 24-bit @dfn{trace point} number.
7460 Trace point support includes two distinct mechanisms,
7461 each supported by a command:
7464 @item @emph{History} ... A circular buffer of trace points
7465 can be set up, and then displayed at any time.
7466 This tracks where code has been, which can be invaluable in
7467 finding out how some fault was triggered.
7469 The buffer may overflow, since it collects records continuously.
7470 It may be useful to use some of the 24 bits to represent a
7471 particular event, and other bits to hold data.
7473 @item @emph{Counting} ... An array of counters can be set up,
7474 and then displayed at any time.
7475 This can help establish code coverage and identify hot spots.
7477 The array of counters is directly indexed by the trace point
7478 number, so trace points with higher numbers are not counted.
7481 Linux-ARM kernels have a ``Kernel low-level debugging
7482 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
7483 depends on CONFIG_DEBUG_LL) which uses this mechanism to
7484 deliver messages before a serial console can be activated.
7485 This is not the same format used by @file{libdcc}.
7486 Other software, such as the U-Boot boot loader, sometimes
7487 does the same thing.
7489 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
7490 Displays current handling of target DCC message requests.
7491 These messages may be sent to the debugger while the target is running.
7492 The optional @option{enable} and @option{charmsg} parameters
7493 both enable the messages, while @option{disable} disables them.
7495 With @option{charmsg} the DCC words each contain one character,
7496 as used by Linux with CONFIG_DEBUG_ICEDCC;
7497 otherwise the libdcc format is used.
7500 @deffn Command {trace history} [@option{clear}|count]
7501 With no parameter, displays all the trace points that have triggered
7502 in the order they triggered.
7503 With the parameter @option{clear}, erases all current trace history records.
7504 With a @var{count} parameter, allocates space for that many
7508 @deffn Command {trace point} [@option{clear}|identifier]
7509 With no parameter, displays all trace point identifiers and how many times
7510 they have been triggered.
7511 With the parameter @option{clear}, erases all current trace point counters.
7512 With a numeric @var{identifier} parameter, creates a new a trace point counter
7513 and associates it with that identifier.
7515 @emph{Important:} The identifier and the trace point number
7516 are not related except by this command.
7517 These trace point numbers always start at zero (from server startup,
7518 or after @command{trace point clear}) and count up from there.
7523 @chapter JTAG Commands
7524 @cindex JTAG Commands
7525 Most general purpose JTAG commands have been presented earlier.
7526 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
7527 Lower level JTAG commands, as presented here,
7528 may be needed to work with targets which require special
7529 attention during operations such as reset or initialization.
7531 To use these commands you will need to understand some
7532 of the basics of JTAG, including:
7535 @item A JTAG scan chain consists of a sequence of individual TAP
7536 devices such as a CPUs.
7537 @item Control operations involve moving each TAP through the same
7538 standard state machine (in parallel)
7539 using their shared TMS and clock signals.
7540 @item Data transfer involves shifting data through the chain of
7541 instruction or data registers of each TAP, writing new register values
7542 while the reading previous ones.
7543 @item Data register sizes are a function of the instruction active in
7544 a given TAP, while instruction register sizes are fixed for each TAP.
7545 All TAPs support a BYPASS instruction with a single bit data register.
7546 @item The way OpenOCD differentiates between TAP devices is by
7547 shifting different instructions into (and out of) their instruction
7551 @section Low Level JTAG Commands
7553 These commands are used by developers who need to access
7554 JTAG instruction or data registers, possibly controlling
7555 the order of TAP state transitions.
7556 If you're not debugging OpenOCD internals, or bringing up a
7557 new JTAG adapter or a new type of TAP device (like a CPU or
7558 JTAG router), you probably won't need to use these commands.
7559 In a debug session that doesn't use JTAG for its transport protocol,
7560 these commands are not available.
7562 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
7563 Loads the data register of @var{tap} with a series of bit fields
7564 that specify the entire register.
7565 Each field is @var{numbits} bits long with
7566 a numeric @var{value} (hexadecimal encouraged).
7567 The return value holds the original value of each
7570 For example, a 38 bit number might be specified as one
7571 field of 32 bits then one of 6 bits.
7572 @emph{For portability, never pass fields which are more
7573 than 32 bits long. Many OpenOCD implementations do not
7574 support 64-bit (or larger) integer values.}
7576 All TAPs other than @var{tap} must be in BYPASS mode.
7577 The single bit in their data registers does not matter.
7579 When @var{tap_state} is specified, the JTAG state machine is left
7581 For example @sc{drpause} might be specified, so that more
7582 instructions can be issued before re-entering the @sc{run/idle} state.
7583 If the end state is not specified, the @sc{run/idle} state is entered.
7586 OpenOCD does not record information about data register lengths,
7587 so @emph{it is important that you get the bit field lengths right}.
7588 Remember that different JTAG instructions refer to different
7589 data registers, which may have different lengths.
7590 Moreover, those lengths may not be fixed;
7591 the SCAN_N instruction can change the length of
7592 the register accessed by the INTEST instruction
7593 (by connecting a different scan chain).
7597 @deffn Command {flush_count}
7598 Returns the number of times the JTAG queue has been flushed.
7599 This may be used for performance tuning.
7601 For example, flushing a queue over USB involves a
7602 minimum latency, often several milliseconds, which does
7603 not change with the amount of data which is written.
7604 You may be able to identify performance problems by finding
7605 tasks which waste bandwidth by flushing small transfers too often,
7606 instead of batching them into larger operations.
7609 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
7610 For each @var{tap} listed, loads the instruction register
7611 with its associated numeric @var{instruction}.
7612 (The number of bits in that instruction may be displayed
7613 using the @command{scan_chain} command.)
7614 For other TAPs, a BYPASS instruction is loaded.
7616 When @var{tap_state} is specified, the JTAG state machine is left
7618 For example @sc{irpause} might be specified, so the data register
7619 can be loaded before re-entering the @sc{run/idle} state.
7620 If the end state is not specified, the @sc{run/idle} state is entered.
7623 OpenOCD currently supports only a single field for instruction
7624 register values, unlike data register values.
7625 For TAPs where the instruction register length is more than 32 bits,
7626 portable scripts currently must issue only BYPASS instructions.
7630 @deffn Command {jtag_reset} trst srst
7631 Set values of reset signals.
7632 The @var{trst} and @var{srst} parameter values may be
7633 @option{0}, indicating that reset is inactive (pulled or driven high),
7634 or @option{1}, indicating it is active (pulled or driven low).
7635 The @command{reset_config} command should already have been used
7636 to configure how the board and JTAG adapter treat these two
7637 signals, and to say if either signal is even present.
7638 @xref{Reset Configuration}.
7640 Note that TRST is specially handled.
7641 It actually signifies JTAG's @sc{reset} state.
7642 So if the board doesn't support the optional TRST signal,
7643 or it doesn't support it along with the specified SRST value,
7644 JTAG reset is triggered with TMS and TCK signals
7645 instead of the TRST signal.
7646 And no matter how that JTAG reset is triggered, once
7647 the scan chain enters @sc{reset} with TRST inactive,
7648 TAP @code{post-reset} events are delivered to all TAPs
7649 with handlers for that event.
7652 @deffn Command {pathmove} start_state [next_state ...]
7653 Start by moving to @var{start_state}, which
7654 must be one of the @emph{stable} states.
7655 Unless it is the only state given, this will often be the
7656 current state, so that no TCK transitions are needed.
7657 Then, in a series of single state transitions
7658 (conforming to the JTAG state machine) shift to
7659 each @var{next_state} in sequence, one per TCK cycle.
7660 The final state must also be stable.
7663 @deffn Command {runtest} @var{num_cycles}
7664 Move to the @sc{run/idle} state, and execute at least
7665 @var{num_cycles} of the JTAG clock (TCK).
7666 Instructions often need some time
7667 to execute before they take effect.
7670 @c tms_sequence (short|long)
7671 @c ... temporary, debug-only, other than USBprog bug workaround...
7673 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
7674 Verify values captured during @sc{ircapture} and returned
7675 during IR scans. Default is enabled, but this can be
7676 overridden by @command{verify_jtag}.
7677 This flag is ignored when validating JTAG chain configuration.
7680 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
7681 Enables verification of DR and IR scans, to help detect
7682 programming errors. For IR scans, @command{verify_ircapture}
7683 must also be enabled.
7687 @section TAP state names
7688 @cindex TAP state names
7690 The @var{tap_state} names used by OpenOCD in the @command{drscan},
7691 @command{irscan}, and @command{pathmove} commands are the same
7692 as those used in SVF boundary scan documents, except that
7693 SVF uses @sc{idle} instead of @sc{run/idle}.
7696 @item @b{RESET} ... @emph{stable} (with TMS high);
7697 acts as if TRST were pulsed
7698 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
7701 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
7702 through the data register
7704 @item @b{DRPAUSE} ... @emph{stable}; data register ready
7705 for update or more shifting
7710 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
7711 through the instruction register
7713 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
7714 for update or more shifting
7719 Note that only six of those states are fully ``stable'' in the
7720 face of TMS fixed (low except for @sc{reset})
7721 and a free-running JTAG clock. For all the
7722 others, the next TCK transition changes to a new state.
7725 @item From @sc{drshift} and @sc{irshift}, clock transitions will
7726 produce side effects by changing register contents. The values
7727 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
7728 may not be as expected.
7729 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
7730 choices after @command{drscan} or @command{irscan} commands,
7731 since they are free of JTAG side effects.
7732 @item @sc{run/idle} may have side effects that appear at non-JTAG
7733 levels, such as advancing the ARM9E-S instruction pipeline.
7734 Consult the documentation for the TAP(s) you are working with.
7737 @node Boundary Scan Commands
7738 @chapter Boundary Scan Commands
7740 One of the original purposes of JTAG was to support
7741 boundary scan based hardware testing.
7742 Although its primary focus is to support On-Chip Debugging,
7743 OpenOCD also includes some boundary scan commands.
7745 @section SVF: Serial Vector Format
7746 @cindex Serial Vector Format
7749 The Serial Vector Format, better known as @dfn{SVF}, is a
7750 way to represent JTAG test patterns in text files.
7751 In a debug session using JTAG for its transport protocol,
7752 OpenOCD supports running such test files.
7754 @deffn Command {svf} filename [@option{quiet}]
7755 This issues a JTAG reset (Test-Logic-Reset) and then
7756 runs the SVF script from @file{filename}.
7757 Unless the @option{quiet} option is specified,
7758 each command is logged before it is executed.
7761 @section XSVF: Xilinx Serial Vector Format
7762 @cindex Xilinx Serial Vector Format
7765 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
7766 binary representation of SVF which is optimized for use with
7768 In a debug session using JTAG for its transport protocol,
7769 OpenOCD supports running such test files.
7771 @quotation Important
7772 Not all XSVF commands are supported.
7775 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
7776 This issues a JTAG reset (Test-Logic-Reset) and then
7777 runs the XSVF script from @file{filename}.
7778 When a @var{tapname} is specified, the commands are directed at
7780 When @option{virt2} is specified, the @sc{xruntest} command counts
7781 are interpreted as TCK cycles instead of microseconds.
7782 Unless the @option{quiet} option is specified,
7783 messages are logged for comments and some retries.
7786 The OpenOCD sources also include two utility scripts
7787 for working with XSVF; they are not currently installed
7788 after building the software.
7789 You may find them useful:
7792 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
7793 syntax understood by the @command{xsvf} command; see notes below.
7794 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
7795 understands the OpenOCD extensions.
7798 The input format accepts a handful of non-standard extensions.
7799 These include three opcodes corresponding to SVF extensions
7800 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
7801 two opcodes supporting a more accurate translation of SVF
7802 (XTRST, XWAITSTATE).
7803 If @emph{xsvfdump} shows a file is using those opcodes, it
7804 probably will not be usable with other XSVF tools.
7810 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
7811 be used to access files on PCs (either the developer's PC or some other PC).
7813 The way this works on the ZY1000 is to prefix a filename by
7814 "/tftp/ip/" and append the TFTP path on the TFTP
7815 server (tftpd). For example,
7818 load_image /tftp/10.0.0.96/c:\temp\abc.elf
7821 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
7822 if the file was hosted on the embedded host.
7824 In order to achieve decent performance, you must choose a TFTP server
7825 that supports a packet size bigger than the default packet size (512 bytes). There
7826 are numerous TFTP servers out there (free and commercial) and you will have to do
7827 a bit of googling to find something that fits your requirements.
7829 @node GDB and OpenOCD
7830 @chapter GDB and OpenOCD
7832 OpenOCD complies with the remote gdbserver protocol, and as such can be used
7833 to debug remote targets.
7834 Setting up GDB to work with OpenOCD can involve several components:
7837 @item The OpenOCD server support for GDB may need to be configured.
7838 @xref{gdbconfiguration,,GDB Configuration}.
7839 @item GDB's support for OpenOCD may need configuration,
7840 as shown in this chapter.
7841 @item If you have a GUI environment like Eclipse,
7842 that also will probably need to be configured.
7845 Of course, the version of GDB you use will need to be one which has
7846 been built to know about the target CPU you're using. It's probably
7847 part of the tool chain you're using. For example, if you are doing
7848 cross-development for ARM on an x86 PC, instead of using the native
7849 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
7850 if that's the tool chain used to compile your code.
7852 @section Connecting to GDB
7853 @cindex Connecting to GDB
7854 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
7855 instance GDB 6.3 has a known bug that produces bogus memory access
7856 errors, which has since been fixed; see
7857 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
7859 OpenOCD can communicate with GDB in two ways:
7863 A socket (TCP/IP) connection is typically started as follows:
7865 target remote localhost:3333
7867 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
7869 It is also possible to use the GDB extended remote protocol as follows:
7871 target extended-remote localhost:3333
7874 A pipe connection is typically started as follows:
7876 target remote | openocd -c "gdb_port pipe; log_output openocd.log"
7878 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
7879 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
7880 session. log_output sends the log output to a file to ensure that the pipe is
7881 not saturated when using higher debug level outputs.
7884 To list the available OpenOCD commands type @command{monitor help} on the
7887 @section Sample GDB session startup
7889 With the remote protocol, GDB sessions start a little differently
7890 than they do when you're debugging locally.
7891 Here's an examples showing how to start a debug session with a
7893 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
7894 Most programs would be written into flash (address 0) and run from there.
7897 $ arm-none-eabi-gdb example.elf
7898 (gdb) target remote localhost:3333
7899 Remote debugging using localhost:3333
7901 (gdb) monitor reset halt
7904 Loading section .vectors, size 0x100 lma 0x20000000
7905 Loading section .text, size 0x5a0 lma 0x20000100
7906 Loading section .data, size 0x18 lma 0x200006a0
7907 Start address 0x2000061c, load size 1720
7908 Transfer rate: 22 KB/sec, 573 bytes/write.
7914 You could then interrupt the GDB session to make the program break,
7915 type @command{where} to show the stack, @command{list} to show the
7916 code around the program counter, @command{step} through code,
7917 set breakpoints or watchpoints, and so on.
7919 @section Configuring GDB for OpenOCD
7921 OpenOCD supports the gdb @option{qSupported} packet, this enables information
7922 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
7923 packet size and the device's memory map.
7924 You do not need to configure the packet size by hand,
7925 and the relevant parts of the memory map should be automatically
7926 set up when you declare (NOR) flash banks.
7928 However, there are other things which GDB can't currently query.
7929 You may need to set those up by hand.
7930 As OpenOCD starts up, you will often see a line reporting
7934 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
7937 You can pass that information to GDB with these commands:
7940 set remote hardware-breakpoint-limit 6
7941 set remote hardware-watchpoint-limit 4
7944 With that particular hardware (Cortex-M3) the hardware breakpoints
7945 only work for code running from flash memory. Most other ARM systems
7946 do not have such restrictions.
7948 Another example of useful GDB configuration came from a user who
7949 found that single stepping his Cortex-M3 didn't work well with IRQs
7950 and an RTOS until he told GDB to disable the IRQs while stepping:
7954 mon cortex_m maskisr on
7956 define hookpost-step
7957 mon cortex_m maskisr off
7961 Rather than typing such commands interactively, you may prefer to
7962 save them in a file and have GDB execute them as it starts, perhaps
7963 using a @file{.gdbinit} in your project directory or starting GDB
7964 using @command{gdb -x filename}.
7966 @section Programming using GDB
7967 @cindex Programming using GDB
7968 @anchor{programmingusinggdb}
7970 By default the target memory map is sent to GDB. This can be disabled by
7971 the following OpenOCD configuration option:
7973 gdb_memory_map disable
7975 For this to function correctly a valid flash configuration must also be set
7976 in OpenOCD. For faster performance you should also configure a valid
7979 Informing GDB of the memory map of the target will enable GDB to protect any
7980 flash areas of the target and use hardware breakpoints by default. This means
7981 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
7982 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
7984 To view the configured memory map in GDB, use the GDB command @option{info mem}
7985 All other unassigned addresses within GDB are treated as RAM.
7987 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
7988 This can be changed to the old behaviour by using the following GDB command
7990 set mem inaccessible-by-default off
7993 If @command{gdb_flash_program enable} is also used, GDB will be able to
7994 program any flash memory using the vFlash interface.
7996 GDB will look at the target memory map when a load command is given, if any
7997 areas to be programmed lie within the target flash area the vFlash packets
8000 If the target needs configuring before GDB programming, an event
8001 script can be executed:
8003 $_TARGETNAME configure -event EVENTNAME BODY
8006 To verify any flash programming the GDB command @option{compare-sections}
8008 @anchor{usingopenocdsmpwithgdb}
8009 @section Using OpenOCD SMP with GDB
8011 For SMP support following GDB serial protocol packet have been defined :
8013 @item j - smp status request
8014 @item J - smp set request
8017 OpenOCD implements :
8019 @item @option{jc} packet for reading core id displayed by
8020 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
8021 @option{E01} for target not smp.
8022 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
8023 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
8024 for target not smp or @option{OK} on success.
8027 Handling of this packet within GDB can be done :
8029 @item by the creation of an internal variable (i.e @option{_core}) by mean
8030 of function allocate_computed_value allowing following GDB command.
8033 #Jc01 packet is sent
8035 #jc packet is sent and result is affected in $
8038 @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
8039 core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
8042 # toggle0 : force display of coreid 0
8048 # toggle1 : force display of coreid 1
8058 @node Tcl Scripting API
8059 @chapter Tcl Scripting API
8060 @cindex Tcl Scripting API
8064 The commands are stateless. E.g. the telnet command line has a concept
8065 of currently active target, the Tcl API proc's take this sort of state
8066 information as an argument to each proc.
8068 There are three main types of return values: single value, name value
8069 pair list and lists.
8071 Name value pair. The proc 'foo' below returns a name/value pair
8077 > set foo(you) Oyvind
8078 > set foo(mouse) Micky
8079 > set foo(duck) Donald
8087 me Duane you Oyvind mouse Micky duck Donald
8089 Thus, to get the names of the associative array is easy:
8091 foreach { name value } [set foo] {
8092 puts "Name: $name, Value: $value"
8096 Lists returned must be relatively small. Otherwise a range
8097 should be passed in to the proc in question.
8099 @section Internal low-level Commands
8101 By low-level, the intent is a human would not directly use these commands.
8103 Low-level commands are (should be) prefixed with "ocd_", e.g.
8104 @command{ocd_flash_banks}
8105 is the low level API upon which @command{flash banks} is implemented.
8108 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
8110 Read memory and return as a Tcl array for script processing
8111 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
8113 Convert a Tcl array to memory locations and write the values
8114 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
8116 Return information about the flash banks
8119 OpenOCD commands can consist of two words, e.g. "flash banks". The
8120 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
8121 called "flash_banks".
8123 @section OpenOCD specific Global Variables
8125 Real Tcl has ::tcl_platform(), and platform::identify, and many other
8126 variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
8127 holds one of the following values:
8130 @item @b{cygwin} Running under Cygwin
8131 @item @b{darwin} Darwin (Mac-OS) is the underlying operating sytem.
8132 @item @b{freebsd} Running under FreeBSD
8133 @item @b{linux} Linux is the underlying operating sytem
8134 @item @b{mingw32} Running under MingW32
8135 @item @b{winxx} Built using Microsoft Visual Studio
8136 @item @b{other} Unknown, none of the above.
8139 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
8142 We should add support for a variable like Tcl variable
8143 @code{tcl_platform(platform)}, it should be called
8144 @code{jim_platform} (because it
8145 is jim, not real tcl).
8153 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
8155 @cindex adaptive clocking
8158 In digital circuit design it is often refered to as ``clock
8159 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
8160 operating at some speed, your CPU target is operating at another.
8161 The two clocks are not synchronised, they are ``asynchronous''
8163 In order for the two to work together they must be synchronised
8164 well enough to work; JTAG can't go ten times faster than the CPU,
8165 for example. There are 2 basic options:
8168 Use a special "adaptive clocking" circuit to change the JTAG
8169 clock rate to match what the CPU currently supports.
8171 The JTAG clock must be fixed at some speed that's enough slower than
8172 the CPU clock that all TMS and TDI transitions can be detected.
8175 @b{Does this really matter?} For some chips and some situations, this
8176 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
8177 the CPU has no difficulty keeping up with JTAG.
8178 Startup sequences are often problematic though, as are other
8179 situations where the CPU clock rate changes (perhaps to save
8182 For example, Atmel AT91SAM chips start operation from reset with
8183 a 32kHz system clock. Boot firmware may activate the main oscillator
8184 and PLL before switching to a faster clock (perhaps that 500 MHz
8186 If you're using JTAG to debug that startup sequence, you must slow
8187 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
8188 JTAG can use a faster clock.
8190 Consider also debugging a 500MHz ARM926 hand held battery powered
8191 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
8192 clock, between keystrokes unless it has work to do. When would
8193 that 5 MHz JTAG clock be usable?
8195 @b{Solution #1 - A special circuit}
8197 In order to make use of this,
8198 your CPU, board, and JTAG adapter must all support the RTCK
8199 feature. Not all of them support this; keep reading!
8201 The RTCK ("Return TCK") signal in some ARM chips is used to help with
8202 this problem. ARM has a good description of the problem described at
8203 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
8204 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
8205 work? / how does adaptive clocking work?''.
8207 The nice thing about adaptive clocking is that ``battery powered hand
8208 held device example'' - the adaptiveness works perfectly all the
8209 time. One can set a break point or halt the system in the deep power
8210 down code, slow step out until the system speeds up.
8212 Note that adaptive clocking may also need to work at the board level,
8213 when a board-level scan chain has multiple chips.
8214 Parallel clock voting schemes are good way to implement this,
8215 both within and between chips, and can easily be implemented
8217 It's not difficult to have logic fan a module's input TCK signal out
8218 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
8219 back with the right polarity before changing the output RTCK signal.
8220 Texas Instruments makes some clock voting logic available
8221 for free (with no support) in VHDL form; see
8222 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
8224 @b{Solution #2 - Always works - but may be slower}
8226 Often this is a perfectly acceptable solution.
8228 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
8229 the target clock speed. But what that ``magic division'' is varies
8230 depending on the chips on your board.
8231 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
8232 ARM11 cores use an 8:1 division.
8233 @b{Xilinx rule of thumb} is 1/12 the clock speed.
8235 Note: most full speed FT2232 based JTAG adapters are limited to a
8236 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
8237 often support faster clock rates (and adaptive clocking).
8239 You can still debug the 'low power' situations - you just need to
8240 either use a fixed and very slow JTAG clock rate ... or else
8241 manually adjust the clock speed at every step. (Adjusting is painful
8242 and tedious, and is not always practical.)
8244 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
8245 have a special debug mode in your application that does a ``high power
8246 sleep''. If you are careful - 98% of your problems can be debugged
8249 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
8250 operation in your idle loops even if you don't otherwise change the CPU
8252 That operation gates the CPU clock, and thus the JTAG clock; which
8253 prevents JTAG access. One consequence is not being able to @command{halt}
8254 cores which are executing that @emph{wait for interrupt} operation.
8256 To set the JTAG frequency use the command:
8264 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
8266 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
8267 around Windows filenames.
8280 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
8282 Make sure you have Cygwin installed, or at least a version of OpenOCD that
8283 claims to come with all the necessary DLLs. When using Cygwin, try launching
8284 OpenOCD from the Cygwin shell.
8286 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
8287 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
8288 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
8290 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
8291 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
8292 software breakpoints consume one of the two available hardware breakpoints.
8294 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
8296 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
8297 clock at the time you're programming the flash. If you've specified the crystal's
8298 frequency, make sure the PLL is disabled. If you've specified the full core speed
8299 (e.g. 60MHz), make sure the PLL is enabled.
8301 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
8302 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
8303 out while waiting for end of scan, rtck was disabled".
8305 Make sure your PC's parallel port operates in EPP mode. You might have to try several
8306 settings in your PC BIOS (ECP, EPP, and different versions of those).
8308 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
8309 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
8310 memory read caused data abort".
8312 The errors are non-fatal, and are the result of GDB trying to trace stack frames
8313 beyond the last valid frame. It might be possible to prevent this by setting up
8314 a proper "initial" stack frame, if you happen to know what exactly has to
8315 be done, feel free to add this here.
8317 @b{Simple:} In your startup code - push 8 registers of zeros onto the
8318 stack before calling main(). What GDB is doing is ``climbing'' the run
8319 time stack by reading various values on the stack using the standard
8320 call frame for the target. GDB keeps going - until one of 2 things
8321 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
8322 stackframes have been processed. By pushing zeros on the stack, GDB
8325 @b{Debugging Interrupt Service Routines} - In your ISR before you call
8326 your C code, do the same - artifically push some zeros onto the stack,
8327 remember to pop them off when the ISR is done.
8329 @b{Also note:} If you have a multi-threaded operating system, they
8330 often do not @b{in the intrest of saving memory} waste these few
8334 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
8335 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
8337 This warning doesn't indicate any serious problem, as long as you don't want to
8338 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
8339 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
8340 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
8341 independently. With this setup, it's not possible to halt the core right out of
8342 reset, everything else should work fine.
8344 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
8345 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
8346 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
8347 quit with an error message. Is there a stability issue with OpenOCD?
8349 No, this is not a stability issue concerning OpenOCD. Most users have solved
8350 this issue by simply using a self-powered USB hub, which they connect their
8351 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
8352 supply stable enough for the Amontec JTAGkey to be operated.
8354 @b{Laptops running on battery have this problem too...}
8356 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
8357 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
8358 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
8359 What does that mean and what might be the reason for this?
8361 First of all, the reason might be the USB power supply. Try using a self-powered
8362 hub instead of a direct connection to your computer. Secondly, the error code 4
8363 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
8364 chip ran into some sort of error - this points us to a USB problem.
8366 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
8367 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
8368 What does that mean and what might be the reason for this?
8370 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
8371 has closed the connection to OpenOCD. This might be a GDB issue.
8373 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
8374 are described, there is a parameter for specifying the clock frequency
8375 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
8376 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
8377 specified in kilohertz. However, I do have a quartz crystal of a
8378 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
8379 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
8382 No. The clock frequency specified here must be given as an integral number.
8383 However, this clock frequency is used by the In-Application-Programming (IAP)
8384 routines of the LPC2000 family only, which seems to be very tolerant concerning
8385 the given clock frequency, so a slight difference between the specified clock
8386 frequency and the actual clock frequency will not cause any trouble.
8388 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
8390 Well, yes and no. Commands can be given in arbitrary order, yet the
8391 devices listed for the JTAG scan chain must be given in the right
8392 order (jtag newdevice), with the device closest to the TDO-Pin being
8393 listed first. In general, whenever objects of the same type exist
8394 which require an index number, then these objects must be given in the
8395 right order (jtag newtap, targets and flash banks - a target
8396 references a jtag newtap and a flash bank references a target).
8398 You can use the ``scan_chain'' command to verify and display the tap order.
8400 Also, some commands can't execute until after @command{init} has been
8401 processed. Such commands include @command{nand probe} and everything
8402 else that needs to write to controller registers, perhaps for setting
8403 up DRAM and loading it with code.
8405 @anchor{faqtaporder}
8406 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
8409 Yes; whenever you have more than one, you must declare them in
8410 the same order used by the hardware.
8412 Many newer devices have multiple JTAG TAPs. For example: ST
8413 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
8414 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
8415 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
8416 connected to the boundary scan TAP, which then connects to the
8417 Cortex-M3 TAP, which then connects to the TDO pin.
8419 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
8420 (2) The boundary scan TAP. If your board includes an additional JTAG
8421 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
8422 place it before or after the STM32 chip in the chain. For example:
8425 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
8426 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
8427 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
8428 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
8429 @item Xilinx TDO Pin -> OpenOCD TDO (input)
8432 The ``jtag device'' commands would thus be in the order shown below. Note:
8435 @item jtag newtap Xilinx tap -irlen ...
8436 @item jtag newtap stm32 cpu -irlen ...
8437 @item jtag newtap stm32 bs -irlen ...
8438 @item # Create the debug target and say where it is
8439 @item target create stm32.cpu -chain-position stm32.cpu ...
8443 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
8444 log file, I can see these error messages: Error: arm7_9_common.c:561
8445 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
8451 @node Tcl Crash Course
8452 @chapter Tcl Crash Course
8455 Not everyone knows Tcl - this is not intended to be a replacement for
8456 learning Tcl, the intent of this chapter is to give you some idea of
8457 how the Tcl scripts work.
8459 This chapter is written with two audiences in mind. (1) OpenOCD users
8460 who need to understand a bit more of how Jim-Tcl works so they can do
8461 something useful, and (2) those that want to add a new command to
8464 @section Tcl Rule #1
8465 There is a famous joke, it goes like this:
8467 @item Rule #1: The wife is always correct
8468 @item Rule #2: If you think otherwise, See Rule #1
8471 The Tcl equal is this:
8474 @item Rule #1: Everything is a string
8475 @item Rule #2: If you think otherwise, See Rule #1
8478 As in the famous joke, the consequences of Rule #1 are profound. Once
8479 you understand Rule #1, you will understand Tcl.
8481 @section Tcl Rule #1b
8482 There is a second pair of rules.
8484 @item Rule #1: Control flow does not exist. Only commands
8485 @* For example: the classic FOR loop or IF statement is not a control
8486 flow item, they are commands, there is no such thing as control flow
8488 @item Rule #2: If you think otherwise, See Rule #1
8489 @* Actually what happens is this: There are commands that by
8490 convention, act like control flow key words in other languages. One of
8491 those commands is the word ``for'', another command is ``if''.
8494 @section Per Rule #1 - All Results are strings
8495 Every Tcl command results in a string. The word ``result'' is used
8496 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
8497 Everything is a string}
8499 @section Tcl Quoting Operators
8500 In life of a Tcl script, there are two important periods of time, the
8501 difference is subtle.
8504 @item Evaluation Time
8507 The two key items here are how ``quoted things'' work in Tcl. Tcl has
8508 three primary quoting constructs, the [square-brackets] the
8509 @{curly-braces@} and ``double-quotes''
8511 By now you should know $VARIABLES always start with a $DOLLAR
8512 sign. BTW: To set a variable, you actually use the command ``set'', as
8513 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
8514 = 1'' statement, but without the equal sign.
8517 @item @b{[square-brackets]}
8518 @* @b{[square-brackets]} are command substitutions. It operates much
8519 like Unix Shell `back-ticks`. The result of a [square-bracket]
8520 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
8521 string}. These two statements are roughly identical:
8525 echo "The Date is: $X"
8528 puts "The Date is: $X"
8530 @item @b{``double-quoted-things''}
8531 @* @b{``double-quoted-things''} are just simply quoted
8532 text. $VARIABLES and [square-brackets] are expanded in place - the
8533 result however is exactly 1 string. @i{Remember Rule #1 - Everything
8537 puts "It is now \"[date]\", $x is in 1 hour"
8539 @item @b{@{Curly-Braces@}}
8540 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
8541 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
8542 'single-quote' operators in BASH shell scripts, with the added
8543 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
8544 nested 3 times@}@}@} NOTE: [date] is a bad example;
8545 at this writing, Jim/OpenOCD does not have a date command.
8548 @section Consequences of Rule 1/2/3/4
8550 The consequences of Rule 1 are profound.
8552 @subsection Tokenisation & Execution.
8554 Of course, whitespace, blank lines and #comment lines are handled in
8557 As a script is parsed, each (multi) line in the script file is
8558 tokenised and according to the quoting rules. After tokenisation, that
8559 line is immedatly executed.
8561 Multi line statements end with one or more ``still-open''
8562 @{curly-braces@} which - eventually - closes a few lines later.
8564 @subsection Command Execution
8566 Remember earlier: There are no ``control flow''
8567 statements in Tcl. Instead there are COMMANDS that simply act like
8568 control flow operators.
8570 Commands are executed like this:
8573 @item Parse the next line into (argc) and (argv[]).
8574 @item Look up (argv[0]) in a table and call its function.
8575 @item Repeat until End Of File.
8578 It sort of works like this:
8581 ReadAndParse( &argc, &argv );
8583 cmdPtr = LookupCommand( argv[0] );
8585 (*cmdPtr->Execute)( argc, argv );
8589 When the command ``proc'' is parsed (which creates a procedure
8590 function) it gets 3 parameters on the command line. @b{1} the name of
8591 the proc (function), @b{2} the list of parameters, and @b{3} the body
8592 of the function. Not the choice of words: LIST and BODY. The PROC
8593 command stores these items in a table somewhere so it can be found by
8596 @subsection The FOR command
8598 The most interesting command to look at is the FOR command. In Tcl,
8599 the FOR command is normally implemented in C. Remember, FOR is a
8600 command just like any other command.
8602 When the ascii text containing the FOR command is parsed, the parser
8603 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
8607 @item The ascii text 'for'
8608 @item The start text
8609 @item The test expression
8614 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
8615 Remember @i{Rule #1 - Everything is a string.} The key point is this:
8616 Often many of those parameters are in @{curly-braces@} - thus the
8617 variables inside are not expanded or replaced until later.
8619 Remember that every Tcl command looks like the classic ``main( argc,
8620 argv )'' function in C. In JimTCL - they actually look like this:
8624 MyCommand( Jim_Interp *interp,
8626 Jim_Obj * const *argvs );
8629 Real Tcl is nearly identical. Although the newer versions have
8630 introduced a byte-code parser and intepreter, but at the core, it
8631 still operates in the same basic way.
8633 @subsection FOR command implementation
8635 To understand Tcl it is perhaps most helpful to see the FOR
8636 command. Remember, it is a COMMAND not a control flow structure.
8638 In Tcl there are two underlying C helper functions.
8640 Remember Rule #1 - You are a string.
8642 The @b{first} helper parses and executes commands found in an ascii
8643 string. Commands can be seperated by semicolons, or newlines. While
8644 parsing, variables are expanded via the quoting rules.
8646 The @b{second} helper evaluates an ascii string as a numerical
8647 expression and returns a value.
8649 Here is an example of how the @b{FOR} command could be
8650 implemented. The pseudo code below does not show error handling.
8652 void Execute_AsciiString( void *interp, const char *string );
8654 int Evaluate_AsciiExpression( void *interp, const char *string );
8657 MyForCommand( void *interp,
8662 SetResult( interp, "WRONG number of parameters");
8666 // argv[0] = the ascii string just like C
8668 // Execute the start statement.
8669 Execute_AsciiString( interp, argv[1] );
8673 i = Evaluate_AsciiExpression(interp, argv[2]);
8678 Execute_AsciiString( interp, argv[3] );
8680 // Execute the LOOP part
8681 Execute_AsciiString( interp, argv[4] );
8685 SetResult( interp, "" );
8690 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
8691 in the same basic way.
8693 @section OpenOCD Tcl Usage
8695 @subsection source and find commands
8696 @b{Where:} In many configuration files
8697 @* Example: @b{ source [find FILENAME] }
8698 @*Remember the parsing rules
8700 @item The @command{find} command is in square brackets,
8701 and is executed with the parameter FILENAME. It should find and return
8702 the full path to a file with that name; it uses an internal search path.
8703 The RESULT is a string, which is substituted into the command line in
8704 place of the bracketed @command{find} command.
8705 (Don't try to use a FILENAME which includes the "#" character.
8706 That character begins Tcl comments.)
8707 @item The @command{source} command is executed with the resulting filename;
8708 it reads a file and executes as a script.
8710 @subsection format command
8711 @b{Where:} Generally occurs in numerous places.
8712 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
8718 puts [format "The answer: %d" [expr $x * $y]]
8721 @item The SET command creates 2 variables, X and Y.
8722 @item The double [nested] EXPR command performs math
8723 @* The EXPR command produces numerical result as a string.
8725 @item The format command is executed, producing a single string
8726 @* Refer to Rule #1.
8727 @item The PUTS command outputs the text.
8729 @subsection Body or Inlined Text
8730 @b{Where:} Various TARGET scripts.
8733 proc someproc @{@} @{
8734 ... multiple lines of stuff ...
8736 $_TARGETNAME configure -event FOO someproc
8737 #2 Good - no variables
8738 $_TARGETNAME confgure -event foo "this ; that;"
8739 #3 Good Curly Braces
8740 $_TARGETNAME configure -event FOO @{
8743 #4 DANGER DANGER DANGER
8744 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
8747 @item The $_TARGETNAME is an OpenOCD variable convention.
8748 @*@b{$_TARGETNAME} represents the last target created, the value changes
8749 each time a new target is created. Remember the parsing rules. When
8750 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
8751 the name of the target which happens to be a TARGET (object)
8753 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
8754 @*There are 4 examples:
8756 @item The TCLBODY is a simple string that happens to be a proc name
8757 @item The TCLBODY is several simple commands seperated by semicolons
8758 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
8759 @item The TCLBODY is a string with variables that get expanded.
8762 In the end, when the target event FOO occurs the TCLBODY is
8763 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
8764 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
8766 Remember the parsing rules. In case #3, @{curly-braces@} mean the
8767 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
8768 and the text is evaluated. In case #4, they are replaced before the
8769 ``Target Object Command'' is executed. This occurs at the same time
8770 $_TARGETNAME is replaced. In case #4 the date will never
8771 change. @{BTW: [date] is a bad example; at this writing,
8772 Jim/OpenOCD does not have a date command@}
8774 @subsection Global Variables
8775 @b{Where:} You might discover this when writing your own procs @* In
8776 simple terms: Inside a PROC, if you need to access a global variable
8777 you must say so. See also ``upvar''. Example:
8779 proc myproc @{ @} @{
8780 set y 0 #Local variable Y
8781 global x #Global variable X
8782 puts [format "X=%d, Y=%d" $x $y]
8785 @section Other Tcl Hacks
8786 @b{Dynamic variable creation}
8788 # Dynamically create a bunch of variables.
8789 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
8791 set vn [format "BIT%d" $x]
8795 set $vn [expr (1 << $x)]
8798 @b{Dynamic proc/command creation}
8800 # One "X" function - 5 uart functions.
8801 foreach who @{A B C D E@}
8802 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
8808 @node OpenOCD Concept Index
8809 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
8810 @comment case issue with ``Index.html'' and ``index.html''
8811 @comment Occurs when creating ``--html --no-split'' output
8812 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
8813 @unnumbered OpenOCD Concept Index
8817 @node Command and Driver Index
8818 @unnumbered Command and Driver Index