1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
8 * OpenOCD: (openocd). Open On-Chip Debugger.
17 @item Copyright @copyright{} 2008 The OpenOCD Project
18 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
19 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
20 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
24 Permission is granted to copy, distribute and/or modify this document
25 under the terms of the GNU Free Documentation License, Version 1.2 or
26 any later version published by the Free Software Foundation; with no
27 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
28 Texts. A copy of the license is included in the section entitled ``GNU
29 Free Documentation License''.
34 @title Open On-Chip Debugger (OpenOCD)
35 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
36 @subtitle @value{UPDATED}
38 @vskip 0pt plus 1filll
45 @node Top, About, , (dir)
48 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
49 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
54 * About:: About OpenOCD
55 * Developers:: OpenOCD Developers
56 * Building OpenOCD:: Building OpenOCD From SVN
57 * JTAG Hardware Dongles:: JTAG Hardware Dongles
58 * Running:: Running OpenOCD
59 * Simple Configuration Files:: Simple Configuration Files
60 * Config File Guidelines:: Config File Guidelines
61 * About JIM-Tcl:: About JIM-Tcl
62 * Daemon Configuration:: Daemon Configuration
63 * Interface - Dongle Configuration:: Interface - Dongle Configuration
64 * Reset Configuration:: Reset Configuration
65 * Tap Creation:: Tap Creation
66 * Target Configuration:: Target Configuration
67 * Flash Configuration:: Flash Configuration
68 * NAND Flash Commands:: NAND Flash Commands
69 * General Commands:: General Commands
70 * JTAG Commands:: JTAG Commands
71 * Sample Scripts:: Sample Target Scripts
73 * GDB and OpenOCD:: Using GDB and OpenOCD
74 * Tcl Scripting API:: Tcl Scripting API
75 * Upgrading:: Deprecated/Removed Commands
76 * Target Library:: Target Library
77 * FAQ:: Frequently Asked Questions
78 * Tcl Crash Course:: Tcl Crash Course
79 * License:: GNU Free Documentation License
80 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
81 @comment case issue with ``Index.html'' and ``index.html''
82 @comment Occurs when creating ``--html --no-split'' output
83 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
84 * OpenOCD Concept Index:: Concept Index
85 * OpenOCD Command Index:: Command Index
92 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
93 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
94 Since that time, the project has grown into an active open-source project,
95 supported by a diverse community of software and hardware developers from
98 @section What is OpenOCD?
100 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
101 in-system programming and boundary-scan testing for embedded target
104 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
105 with the JTAG (IEEE 1149.1) compliant taps on your target board.
107 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
108 based, parallel port based, and other standalone boxes that run
109 OpenOCD internally. @xref{JTAG Hardware Dongles}.
111 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
112 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
113 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be
114 debugged via the GDB protocol.
116 @b{Flash Programing:} Flash writing is supported for external CFI
117 compatible NOR flashes (Intel and AMD/Spansion command set) and several
118 internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3, and
119 STM32x). Preliminary support for various NAND flash controllers
120 (LPC3180, Orion, S3C24xx, more) controller is included.
122 @section OpenOCD Web Site
124 The OpenOCD web site provides the latest public news from the community:
126 @uref{http://openocd.berlios.de/web/}
130 @chapter OpenOCD Developer Resources
133 If you are interested in improving the state of OpenOCD's debugging and
134 testing support, new contributions will be welcome. Motivated developers
135 can produce new target, flash or interface drivers, improve the
136 documentation, as well as more conventional bug fixes and enhancements.
138 The resources in this chapter are available for developers wishing to explore
139 or expand the OpenOCD source code.
141 @section OpenOCD Subversion Repository
143 The ``Building From Source'' section provides instructions to retrieve
144 and and build the latest version of the OpenOCD source code.
145 @xref{Building OpenOCD}.
147 Developers that want to contribute patches to the OpenOCD system are
148 @b{strongly} encouraged to base their work off of the most recent trunk
149 revision. Patches created against older versions may require additional
150 work from their submitter in order to be updated for newer releases.
152 @section Doxygen Developer Manual
154 During the development of the 0.2.0 release, the OpenOCD project began
155 providing a Doxygen reference manual. This document contains more
156 technical information about the software internals, development
157 processes, and similar documentation:
159 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
161 This document is a work-in-progress, but contributions would be welcome
162 to fill in the gaps. All of the source files are provided in-tree,
163 listed in the Doxyfile configuration in the top of the repository trunk.
165 @section OpenOCD Developer Mailing List
167 The OpenOCD Developer Mailing List provides the primary means of
168 communication between developers:
170 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
172 All drivers developers are enouraged to also subscribe to the list of
173 SVN commits to keep pace with the ongoing changes:
175 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
177 @node Building OpenOCD
178 @chapter Building OpenOCD
181 @section Pre-Built Tools
182 If you are interested in getting actual work done rather than building
183 OpenOCD, then check if your interface supplier provides binaries for
184 you. Chances are that that binary is from some SVN version that is more
185 stable than SVN trunk where bleeding edge development takes place.
187 @section Packagers Please Read!
189 You are a @b{PACKAGER} of OpenOCD if you
192 @item @b{Sell dongles} and include pre-built binaries
193 @item @b{Supply tools} i.e.: A complete development solution
194 @item @b{Supply IDEs} like Eclipse, or RHIDE, etc.
195 @item @b{Build packages} i.e.: RPM files, or DEB files for a Linux Distro
198 As a @b{PACKAGER}, you will experience first reports of most issues.
199 When you fix those problems for your users, your solution may help
200 prevent hundreds (if not thousands) of other questions from other users.
202 If something does not work for you, please work to inform the OpenOCD
203 developers know how to improve the system or documentation to avoid
204 future problems, and follow-up to help us ensure the issue will be fully
205 resolved in our future releases.
207 That said, the OpenOCD developers would also like you to follow a few
211 @item @b{Always build with printer ports enabled.}
212 @item @b{Try to use LIBFTDI + LIBUSB where possible. You cover more bases.}
216 @item @b{Why YES to LIBFTDI + LIBUSB?}
218 @item @b{LESS} work - libusb perhaps already there
219 @item @b{LESS} work - identical code, multiple platforms
220 @item @b{MORE} dongles are supported
221 @item @b{MORE} platforms are supported
222 @item @b{MORE} complete solution
224 @item @b{Why not LIBFTDI + LIBUSB} (i.e.: ftd2xx instead)?
226 @item @b{LESS} speed - some say it is slower
227 @item @b{LESS} complex to distribute (external dependencies)
231 @section Building From Source
233 You can download the current SVN version with an SVN client of your choice from the
234 following repositories:
236 @uref{svn://svn.berlios.de/openocd/trunk}
240 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
242 Using the SVN command line client, you can use the following command to fetch the
243 latest version (make sure there is no (non-svn) directory called "openocd" in the
247 svn checkout svn://svn.berlios.de/openocd/trunk openocd
250 Building OpenOCD requires a recent version of the GNU autotools (autoconf >= 2.59 and automake >= 1.9).
251 For building on Windows,
252 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
253 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
254 paths, resulting in obscure dependency errors (This is an observation I've gathered
255 from the logs of one user - correct me if I'm wrong).
257 You further need the appropriate driver files, if you want to build support for
258 a FTDI FT2232 based interface:
261 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
262 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
263 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
264 homepage (@uref{http://www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
267 libftdi is supported under Windows. Do not use versions earlier than 0.14.
269 In general, the D2XX driver provides superior performance (several times as fast),
270 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
271 a kernel module, only a user space library.
273 To build OpenOCD (on both Linux and Cygwin), use the following commands:
279 Bootstrap generates the configure script, and prepares building on your system.
282 ./configure [options, see below]
285 Configure generates the Makefiles used to build OpenOCD.
292 Make builds OpenOCD, and places the final executable in ./src/, the last step, ``make install'' is optional.
294 The configure script takes several options, specifying which JTAG interfaces
295 should be included (among other things):
299 @option{--enable-parport} - Enable building the PC parallel port driver.
301 @option{--enable-parport_ppdev} - Enable use of ppdev (/dev/parportN) for parport.
303 @option{--enable-parport_giveio} - Enable use of giveio for parport instead of ioperm.
305 @option{--enable-amtjtagaccel} - Enable building the Amontec JTAG-Accelerator driver.
307 @option{--enable-ecosboard} - Enable building support for eCosBoard based JTAG debugger.
309 @option{--enable-ioutil} - Enable ioutil functions - useful for standalone OpenOCD implementations.
311 @option{--enable-httpd} - Enable builtin httpd server - useful for standalone OpenOCD implementations.
313 @option{--enable-ep93xx} - Enable building support for EP93xx based SBCs.
315 @option{--enable-at91rm9200} - Enable building support for AT91RM9200 based SBCs.
317 @option{--enable-gw16012} - Enable building support for the Gateworks GW16012 JTAG programmer.
319 @option{--enable-ft2232_ftd2xx} - Numerous USB type ARM JTAG dongles use the FT2232C chip from this FTDICHIP.COM chip (closed source).
321 @option{--enable-ft2232_libftdi} - An open source (free) alternative to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin).
323 @option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c, point at the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
325 @option{--with-ftd2xx-linux-tardir=PATH} - Linux only. Equivalent of @option{--with-ftd2xx-win32-zipdir}, where you unpacked the TAR.GZ file.
327 @option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static. Specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note: 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}. The 'shared' value is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.
329 @option{--enable-presto_libftdi} - Enable building support for ASIX Presto programmer using the libftdi driver.
331 @option{--enable-presto_ftd2xx} - Enable building support for ASIX Presto programmer using the FTD2XX driver.
333 @option{--enable-usbprog} - Enable building support for the USBprog JTAG programmer.
335 @option{--enable-oocd_trace} - Enable building support for the OpenOCD+trace ETM capture device.
337 @option{--enable-jlink} - Enable building support for the Segger J-Link JTAG programmer.
339 @option{--enable-vsllink} - Enable building support for the Versaloon-Link JTAG programmer.
341 @option{--enable-rlink} - Enable building support for the Raisonance RLink JTAG programmer.
343 @option{--enable-arm-jtag-ew} - Enable building support for the Olimex ARM-JTAG-EW programmer.
345 @option{--enable-dummy} - Enable building the dummy port driver.
348 @section Parallel Port Dongles
350 If you want to access the parallel port using the PPDEV interface you have to specify
351 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
352 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
353 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
355 The same is true for the @option{--enable-parport_giveio} option, you have to
356 use both the @option{--enable-parport} AND the @option{--enable-parport_giveio} option if you want to use giveio instead of ioperm parallel port access method.
358 @section FT2232C Based USB Dongles
360 There are 2 methods of using the FTD2232, either (1) using the
361 FTDICHIP.COM closed source driver, or (2) the open (and free) driver
362 libftdi. Some claim the (closed) FTDICHIP.COM solution is faster.
364 The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux)
365 TAR.GZ file. You must unpack them ``some where'' convient. As of this
366 writing (12/26/2008) FTDICHIP does not supply means to install these
367 files ``in an appropriate place'' As a result, there are two
368 ``./configure'' options that help.
370 Below is an example build process:
372 1) Check out the latest version of ``openocd'' from SVN.
374 2) Download & unpack either the Windows or Linux FTD2xx drivers
375 (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
378 /home/duane/ftd2xx.win32 => the Cygwin/Win32 ZIP file contents.
379 /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents.
382 3) Configure with these options:
385 Cygwin FTDICHIP solution:
386 ./configure --prefix=/home/duane/mytools \
387 --enable-ft2232_ftd2xx \
388 --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
390 Linux FTDICHIP solution:
391 ./configure --prefix=/home/duane/mytools \
392 --enable-ft2232_ftd2xx \
393 --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
395 Cygwin/Linux LIBFTDI solution:
397 1a) For Windows: The Windows port of LIBUSB is in place.
398 1b) For Linux: libusb has been built/installed and is in place.
400 2) And libftdi has been built and installed
401 Note: libftdi - relies upon libusb.
403 ./configure --prefix=/home/duane/mytools \
404 --enable-ft2232_libftdi
408 4) Then just type ``make'', and perhaps ``make install''.
411 @section Miscellaneous Configure Options
415 @option{--disable-option-checking} - Ignore unrecognized @option{--enable} and @option{--with} options.
417 @option{--enable-gccwarnings} - Enable extra gcc warnings during build.
420 @option{--enable-release} - Enable building of an OpenOCD release, generally
421 this is for developers. It simply omits the svn version string when the
422 openocd @option{-v} is executed.
425 @node JTAG Hardware Dongles
426 @chapter JTAG Hardware Dongles
435 Defined: @b{dongle}: A small device that plugins into a computer and serves as
436 an adapter .... [snip]
438 In the OpenOCD case, this generally refers to @b{a small adapater} one
439 attaches to your computer via USB or the Parallel Printer Port. The
440 execption being the Zylin ZY1000 which is a small box you attach via
441 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
442 require any drivers to be installed on the developer PC. It also has
443 a built in web interface. It supports RTCK/RCLK or adaptive clocking
444 and has a built in relay to power cycle targets remotely.
447 @section Choosing a Dongle
449 There are three things you should keep in mind when choosing a dongle.
452 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
453 @item @b{Connection} Printer Ports - Does your computer have one?
454 @item @b{Connection} Is that long printer bit-bang cable practical?
455 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
458 @section Stand alone Systems
460 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
461 dongle, but a standalone box. The ZY1000 has the advantage that it does
462 not require any drivers installed on the developer PC. It also has
463 a built in web interface. It supports RTCK/RCLK or adaptive clocking
464 and has a built in relay to power cycle targets remotely.
466 @section USB FT2232 Based
468 There are many USB JTAG dongles on the market, many of them are based
469 on a chip from ``Future Technology Devices International'' (FTDI)
470 known as the FTDI FT2232.
472 See: @url{http://www.ftdichip.com} or @url{http://www.ftdichip.com/Products/FT2232H.htm}
474 As of 28/Nov/2008, the following are supported:
478 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
480 @* See: @url{http://www.amontec.com/jtagkey.shtml}
482 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
484 @* See: @url{http://www.signalyzer.com}
485 @item @b{evb_lm3s811}
486 @* See: @url{http://www.luminarymicro.com} - The Luminary Micro Stellaris LM3S811 eval board has an FTD2232C chip built in.
487 @item @b{olimex-jtag}
488 @* See: @url{http://www.olimex.com}
490 @* See: @url{http://www.tincantools.com}
491 @item @b{turtelizer2}
492 @* See: @url{http://www.ethernut.de}, or @url{http://www.ethernut.de/en/hardware/turtelizer/index.html}
494 @* Link: @url{http://www.hitex.com/index.php?id=383}
496 @* Link @url{http://www.hitex.com/stm32-stick}
497 @item @b{axm0432_jtag}
498 @* Axiom AXM-0432 Link @url{http://www.axman.com}
501 @section USB JLINK based
502 There are several OEM versions of the Segger @b{JLINK} adapter. It is
503 an example of a micro controller based JTAG adapter, it uses an
504 AT91SAM764 internally.
507 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
508 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
509 @item @b{SEGGER JLINK}
510 @* Link: @url{http://www.segger.com/jlink.html}
512 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
515 @section USB RLINK based
516 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
519 @item @b{Raisonance RLink}
520 @* Link: @url{http://www.raisonance.com/products/RLink.php}
521 @item @b{STM32 Primer}
522 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
523 @item @b{STM32 Primer2}
524 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
530 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
532 @item @b{USB - Presto}
533 @* Link: @url{http://tools.asix.net/prg_presto.htm}
535 @item @b{Versaloon-Link}
536 @* Link: @url{http://www.simonqian.com/en/Versaloon}
538 @item @b{ARM-JTAG-EW}
539 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
542 @section IBM PC Parallel Printer Port Based
544 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
545 and the MacGraigor Wiggler. There are many clones and variations of
550 @item @b{Wiggler} - There are many clones of this.
551 @* Link: @url{http://www.macraigor.com/wiggler.htm}
553 @item @b{DLC5} - From XILINX - There are many clones of this
554 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
555 produced, PDF schematics are easily found and it is easy to make.
557 @item @b{Amontec - JTAG Accelerator}
558 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
561 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
564 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
566 @item @b{Wiggler_ntrst_inverted}
567 @* Yet another variation - See the source code, src/jtag/parport.c
569 @item @b{old_amt_wiggler}
570 @* Unknown - probably not on the market today
573 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
576 @* Link: @url{http://www.amontec.com/chameleon.shtml}
582 @* ispDownload from Lattice Semiconductor @url{http://www.latticesemi.com/lit/docs/devtools/dlcable.pdf}
585 @* From ST Microsystems, link:
586 @url{http://www.st.com/stonline/products/literature/um/7889.pdf}
587 Title: FlashLINK JTAG programing cable for PSD and uPSD
595 @* An EP93xx based Linux machine using the GPIO pins directly.
598 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
604 @cindex running OpenOCD
606 @cindex --debug_level
610 The @option{--help} option shows:
614 --help | -h display this help
615 --version | -v display OpenOCD version
616 --file | -f use configuration file <name>
617 --search | -s dir to search for config files and scripts
618 --debug | -d set debug level <0-3>
619 --log_output | -l redirect log output to file <name>
620 --command | -c run <command>
621 --pipe | -p use pipes when talking to gdb
624 By default OpenOCD reads the file configuration file ``openocd.cfg''
625 in the current directory. To specify a different (or multiple)
626 configuration file, you can use the ``-f'' option. For example:
629 openocd -f config1.cfg -f config2.cfg -f config3.cfg
632 Once started, OpenOCD runs as a daemon, waiting for connections from
633 clients (Telnet, GDB, Other).
635 If you are having problems, you can enable internal debug messages via
638 Also it is possible to interleave commands w/config scripts using the
639 @option{-c} command line switch.
641 To enable debug output (when reporting problems or working on OpenOCD
642 itself), use the @option{-d} command line switch. This sets the
643 @option{debug_level} to "3", outputting the most information,
644 including debug messages. The default setting is "2", outputting only
645 informational messages, warnings and errors. You can also change this
646 setting from within a telnet or gdb session using @option{debug_level
647 <n>} @xref{debug_level}.
649 You can redirect all output from the daemon to a file using the
650 @option{-l <logfile>} switch.
652 Search paths for config/script files can be added to OpenOCD by using
653 the @option{-s <search>} switch. The current directory and the OpenOCD
654 target library is in the search path by default.
656 For details on the @option{-p} option. @xref{Connecting to GDB}.
658 Note! OpenOCD will launch the GDB & telnet server even if it can not
659 establish a connection with the target. In general, it is possible for
660 the JTAG controller to be unresponsive until the target is set up
661 correctly via e.g. GDB monitor commands in a GDB init script.
663 @node Simple Configuration Files
664 @chapter Simple Configuration Files
665 @cindex configuration
668 There are 4 basic ways of ``configurating'' OpenOCD to run, they are:
671 @item A small openocd.cfg file which ``sources'' other configuration files
672 @item A monolithic openocd.cfg file
673 @item Many -f filename options on the command line
674 @item Your Mixed Solution
677 @section Small configuration file method
679 This is the preferred method. It is simple and works well for many
680 people. The developers of OpenOCD would encourage you to use this
681 method. If you create a new configuration please email new
682 configurations to the development list.
684 Here is an example of an openocd.cfg file for an ATMEL at91sam7x256
687 source [find interface/signalyzer.cfg]
689 # GDB can also flash my flash!
690 gdb_memory_map enable
691 gdb_flash_program enable
693 source [find target/sam7x256.cfg]
696 There are many example configuration scripts you can work with. You
697 should look in the directory: @t{$(INSTALLDIR)/lib/openocd}. You
701 @item @b{board} - eval board level configurations
702 @item @b{interface} - specific dongle configurations
703 @item @b{target} - the target chips
704 @item @b{tcl} - helper scripts
705 @item @b{xscale} - things specific to the xscale.
708 Look first in the ``boards'' area, then the ``targets'' area. Often a board
709 configuration is a good example to work from.
711 @section Many -f filename options
712 Some believe this is a wonderful solution, others find it painful.
714 You can use a series of ``-f filename'' options on the command line,
715 OpenOCD will read each filename in sequence, for example:
718 openocd -f file1.cfg -f file2.cfg -f file2.cfg
721 You can also intermix various commands with the ``-c'' command line
724 @section Monolithic file
725 The ``Monolithic File'' dispenses with all ``source'' statements and
726 puts everything in one self contained (monolithic) file. This is not
729 Please try to ``source'' various files or use the multiple -f
732 @section Advice for you
733 Often, one uses a ``mixed approach''. Where possible, please try to
734 ``source'' common things, and if needed cut/paste parts of the
735 standard distribution configuration files as needed.
737 @b{REMEMBER:} The ``important parts'' of your configuration file are:
740 @item @b{Interface} - Defines the dongle
741 @item @b{Taps} - Defines the JTAG Taps
742 @item @b{GDB Targets} - What GDB talks to
743 @item @b{Flash Programing} - Very Helpful
746 Some key things you should look at and understand are:
749 @item The reset configuration of your debug environment as a whole
750 @item Is there a ``work area'' that OpenOCD can use?
751 @* For ARM - work areas mean up to 10x faster downloads.
752 @item For MMU/MPU based ARM chips (i.e.: ARM9 and later) will that work area still be available?
753 @item For complex targets (multiple chips) the JTAG SPEED becomes an issue.
758 @node Config File Guidelines
759 @chapter Config File Guidelines
761 This section/chapter is aimed at developers and integrators of
762 OpenOCD. These are guidelines for creating new boards and new target
763 configurations as of 28/Nov/2008.
765 However, you, the user of OpenOCD, should be somewhat familiar with
766 this section as it should help explain some of the internals of what
767 you might be looking at.
769 The user should find the following directories under @t{$(INSTALLDIR)/lib/openocd} :
773 @*Think JTAG Dongle. Files that configure the JTAG dongle go here.
775 @* Think Circuit Board, PWA, PCB, they go by many names. Board files
776 contain initialization items that are specific to a board - for
777 example: The SDRAM initialization sequence for the board, or the type
778 of external flash and what address it is found at. Any initialization
779 sequence to enable that external flash or SDRAM should be found in the
780 board file. Boards may also contain multiple targets, i.e.: Two CPUs, or
781 a CPU and an FPGA or CPLD.
783 @* Think chip. The ``target'' directory represents a JTAG tap (or
784 chip) OpenOCD should control, not a board. Two common types of targets
785 are ARM chips and FPGA or CPLD chips.
788 @b{If needed...} The user in their ``openocd.cfg'' file or the board
789 file might override a specific feature in any of the above files by
790 setting a variable or two before sourcing the target file. Or adding
791 various commands specific to their situation.
793 @section Interface Config Files
795 The user should be able to source one of these files via a command like this:
798 source [find interface/FOOBAR.cfg]
800 openocd -f interface/FOOBAR.cfg
803 A preconfigured interface file should exist for every interface in use
804 today, that said, perhaps some interfaces have only been used by the
805 sole developer who created it.
807 @b{FIXME/NOTE:} We need to add support for a variable like Tcl variable
808 tcl_platform(platform), it should be called jim_platform (because it
809 is jim, not real tcl) and it should contain 1 of 3 words: ``linux'',
810 ``cygwin'' or ``mingw''
812 Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
814 @section Board Config Files
816 @b{Note: BOARD directory NEW as of 28/nov/2008}
818 The user should be able to source one of these files via a command like this:
821 source [find board/FOOBAR.cfg]
823 openocd -f board/FOOBAR.cfg
827 The board file should contain one or more @t{source [find
828 target/FOO.cfg]} statements along with any board specific things.
830 In summary the board files should contain (if present)
833 @item External flash configuration (i.e.: NOR flash on CS0, two NANDs on CS2)
834 @item SDRAM configuration (size, speed, etc.
835 @item Board specific IO configuration (i.e.: GPIO pins might disable a 2nd flash)
836 @item Multiple TARGET source statements
837 @item All things that are not ``inside a chip''
838 @item Things inside a chip go in a 'target' file
841 @section Target Config Files
843 The user should be able to source one of these files via a command like this:
846 source [find target/FOOBAR.cfg]
848 openocd -f target/FOOBAR.cfg
851 In summary the target files should contain
856 @item Reset configuration
858 @item CPU/Chip/CPU-Core specific features
862 @subsection Important variable names
864 By default, the end user should never need to set these
865 variables. However, if the user needs to override a setting they only
866 need to set the variable in a simple way.
870 @* This gives a name to the overall chip, and is used as part of the
871 tap identifier dotted name.
873 @* By default little - unless the chip or board is not normally used that way.
875 @* When OpenOCD examines the JTAG chain, it will attempt to identify
876 every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
877 to verify the tap id number verses configuration file and may issue an
878 error or warning like this. The hope is that this will help to pinpoint
879 problems in OpenOCD configurations.
882 Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
883 Error: ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
884 Error: ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
885 Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
888 @item @b{_TARGETNAME}
889 @* By convention, this variable is created by the target configuration
890 script. The board configuration file may make use of this variable to
891 configure things like a ``reset init'' script, or other things
892 specific to that board and that target.
894 If the chip has 2 targets, use the names @b{_TARGETNAME0},
895 @b{_TARGETNAME1}, ... etc.
897 @b{Remember:} The ``board file'' may include multiple targets.
899 At no time should the name ``target0'' (the default target name if
900 none was specified) be used. The name ``target0'' is a hard coded name
901 - the next target on the board will be some other number.
902 In the same way, avoid using target numbers even when they are
903 permitted; use the right target name(s) for your board.
905 The user (or board file) should reasonably be able to:
908 source [find target/FOO.cfg]
909 $_TARGETNAME configure ... FOO specific parameters
911 source [find target/BAR.cfg]
912 $_TARGETNAME configure ... BAR specific parameters
917 @subsection Tcl Variables Guide Line
918 The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
920 Thus the rule we follow in OpenOCD is this: Variables that begin with
921 a leading underscore are temporary in nature, and can be modified and
922 used at will within a ?TARGET? configuration file.
924 @b{EXAMPLE:} The user should be able to do this:
928 # PXA270 #1 network side, big endian
929 # PXA270 #2 video side, little endian
933 source [find target/pxa270.cfg]
934 # variable: _TARGETNAME = network.cpu
935 # other commands can refer to the "network.cpu" tap.
936 $_TARGETNAME configure .... params for this CPU..
940 source [find target/pxa270.cfg]
941 # variable: _TARGETNAME = video.cpu
942 # other commands can refer to the "video.cpu" tap.
943 $_TARGETNAME configure .... params for this CPU..
947 source [find target/spartan3.cfg]
949 # Since $_TARGETNAME is temporal..
950 # these names still work!
951 network.cpu configure ... params
952 video.cpu configure ... params
956 @subsection Default Value Boiler Plate Code
958 All target configuration files should start with this (or a modified form)
962 if @{ [info exists CHIPNAME] @} @{
963 set _CHIPNAME $CHIPNAME
965 set _CHIPNAME sam7x256
968 if @{ [info exists ENDIAN] @} @{
974 if @{ [info exists CPUTAPID ] @} @{
975 set _CPUTAPID $CPUTAPID
977 set _CPUTAPID 0x3f0f0f0f
982 @subsection Creating Taps
983 After the ``defaults'' are choosen [see above] the taps are created.
985 @b{SIMPLE example:} such as an Atmel AT91SAM7X256
989 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
990 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
995 This is an SNIP/example for an STR912 - which has 3 internal taps. Key features shown:
998 @item @b{Unform tap names} - See: Tap Naming Convention
999 @item @b{_TARGETNAME} is created at the end where used.
1003 if @{ [info exists FLASHTAPID ] @} @{
1004 set _FLASHTAPID $FLASHTAPID
1006 set _FLASHTAPID 0x25966041
1008 jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
1010 if @{ [info exists CPUTAPID ] @} @{
1011 set _CPUTAPID $CPUTAPID
1013 set _CPUTAPID 0x25966041
1015 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
1018 if @{ [info exists BSTAPID ] @} @{
1019 set _BSTAPID $BSTAPID
1021 set _BSTAPID 0x1457f041
1023 jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
1025 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
1028 @b{Tap Naming Convention}
1030 See the command ``jtag newtap'' for detail, but in brief the names you should use are:
1039 @item @b{unknownN} - it happens :-(
1042 @subsection Reset Configuration
1044 Some chips have specific ways the TRST and SRST signals are
1045 managed. If these are @b{CHIP SPECIFIC} they go here, if they are
1046 @b{BOARD SPECIFIC} they go in the board file.
1048 @subsection Work Areas
1050 Work areas are small RAM areas used by OpenOCD to speed up downloads,
1051 and to download small snippets of code to program flash chips.
1053 If the chip includes a form of ``on-chip-ram'' - and many do - define
1054 a reasonable work area and use the ``backup'' option.
1056 @b{PROBLEMS:} On more complex chips, this ``work area'' may become
1057 inaccessible if/when the application code enables or disables the MMU.
1059 @subsection ARM Core Specific Hacks
1061 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1062 special high speed download features - enable it.
1064 If the chip has an ARM ``vector catch'' feature - by default enable
1065 it for Undefined Instructions, Data Abort, and Prefetch Abort, if the
1066 user is really writing a handler for those situations - they can
1067 easily disable it. Experiance has shown the ``vector catch'' is
1068 helpful - for common programing errors.
1070 If present, the MMU, the MPU and the CACHE should be disabled.
1072 Some ARM cores are equipped with trace support, which permits
1073 examination of the instruction and data bus activity. Trace
1074 activity is controlled through an ``Embedded Trace Module'' (ETM)
1075 on one of the core's scan chains. The ETM emits voluminous data
1076 through a ``trace port''. The trace port is accessed in one
1077 of two ways. When its signals are pinned out from the chip,
1078 boards may provide a special high speed debugging connector;
1079 software support for this is not configured by default, use
1080 the ``--enable-oocd_trace'' option. Alternatively, trace data
1081 may be stored an on-chip SRAM which is packaged as an ``Embedded
1082 Trace Buffer'' (ETB). An ETB has its own TAP, usually right after
1083 its associated ARM core. OpenOCD supports the ETM, and your
1084 target configuration should set it up with the relevant trace
1085 port: ``etb'' for chips which use that, else the board-specific
1086 option will be either ``oocd_trace'' or ``dummy''.
1089 etm config $_TARGETNAME 16 normal full etb
1090 etb config $_TARGETNAME $_CHIPNAME.etb
1093 @subsection Internal Flash Configuration
1095 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1097 @b{Never ever} in the ``target configuration file'' define any type of
1098 flash that is external to the chip. (For example a BOOT flash on
1099 Chip Select 0.) Such flash information goes in a board file - not
1100 the TARGET (chip) file.
1104 @item at91sam7x256 - has 256K flash YES enable it.
1105 @item str912 - has flash internal YES enable it.
1106 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1107 @item pxa270 - again - CS0 flash - it goes in the board file.
1111 @chapter About JIM-Tcl
1115 OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
1116 learn more about JIM here: @url{http://jim.berlios.de}
1119 @item @b{JIM vs. Tcl}
1120 @* JIM-TCL is a stripped down version of the well known Tcl language,
1121 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
1122 fewer features. JIM-Tcl is a single .C file and a single .H file and
1123 impliments the basic Tcl command set along. In contrast: Tcl 8.6 is a
1124 4.2 MB .zip file containing 1540 files.
1126 @item @b{Missing Features}
1127 @* Our practice has been: Add/clone the real Tcl feature if/when
1128 needed. We welcome JIM Tcl improvements, not bloat.
1131 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
1132 command interpreter today (28/nov/2008) is a mixture of (newer)
1133 JIM-Tcl commands, and (older) the orginal command interpreter.
1136 @* At the OpenOCD telnet command line (or via the GDB mon command) one
1137 can type a Tcl for() loop, set variables, etc.
1139 @item @b{Historical Note}
1140 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
1142 @item @b{Need a crash course in Tcl?}
1143 @* See: @xref{Tcl Crash Course}.
1147 @node Daemon Configuration
1148 @chapter Daemon Configuration
1149 @cindex initialization
1150 The commands here are commonly found in the openocd.cfg file and are
1151 used to specify what TCP/IP ports are used, and how GDB should be
1154 @section Configuration Stage
1155 @cindex configuration stage
1156 @cindex configuration command
1158 When the OpenOCD server process starts up, it enters a
1159 @emph{configuration stage} which is the only time that
1160 certain commands, @emph{configuration commands}, may be issued.
1161 Those configuration commands include declaration of TAPs
1162 and other basic setup.
1163 The server must leave the configuration stage before it
1164 may access or activate TAPs.
1165 After it leaves this stage, configuration commands may no
1168 @deffn {Config Command} init
1169 This command terminates the configuration stage and
1170 enters the normal command mode. This can be useful to add commands to
1171 the startup scripts and commands such as resetting the target,
1172 programming flash, etc. To reset the CPU upon startup, add "init" and
1173 "reset" at the end of the config script or at the end of the OpenOCD
1174 command line using the @option{-c} command line switch.
1176 If this command does not appear in any startup/configuration file
1177 OpenOCD executes the command for you after processing all
1178 configuration files and/or command line options.
1180 @b{NOTE:} This command normally occurs at or near the end of your
1181 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1182 targets ready. For example: If your openocd.cfg file needs to
1183 read/write memory on your target, @command{init} must occur before
1184 the memory read/write commands. This includes @command{nand probe}.
1187 @section TCP/IP Ports
1191 The OpenOCD server accepts remote commands in several syntaxes.
1192 Each syntax uses a different TCP/IP port, which you may specify
1193 only during configuration (before those ports are opened).
1195 @deffn {Command} gdb_port (number)
1197 Specify or query the first port used for incoming GDB connections.
1198 The GDB port for the
1199 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1200 When not specified during the configuration stage,
1201 the port @var{number} defaults to 3333.
1204 @deffn {Command} tcl_port (number)
1205 Specify or query the port used for a simplified RPC
1206 connection that can be used by clients to issue TCL commands and get the
1207 output from the Tcl engine.
1208 Intended as a machine interface.
1209 When not specified during the configuration stage,
1210 the port @var{number} defaults to 6666.
1213 @deffn {Command} telnet_port (number)
1214 Specify or query the
1215 port on which to listen for incoming telnet connections.
1216 This port is intended for interaction with one human through TCL commands.
1217 When not specified during the configuration stage,
1218 the port @var{number} defaults to 4444.
1221 @section GDB Configuration
1222 @anchor{GDB Configuration}
1224 @cindex GDB configuration
1225 You can reconfigure some GDB behaviors if needed.
1226 The ones listed here are static and global.
1227 @xref{Target Create}, about declaring individual targets.
1228 @xref{Target Events}, about configuring target-specific event handling.
1230 @deffn {Command} gdb_breakpoint_override <hard|soft|disable>
1231 @anchor{gdb_breakpoint_override}
1232 Force breakpoint type for gdb @command{break} commands.
1233 The raison d'etre for this option is to support GDB GUI's which don't
1234 distinguish hard versus soft breakpoints, if the default OpenOCD and
1235 GDB behaviour is not sufficient. GDB normally uses hardware
1236 breakpoints if the memory map has been set up for flash regions.
1238 This option replaces older arm7_9 target commands that addressed
1242 @deffn {Config command} gdb_detach <resume|reset|halt|nothing>
1243 Configures what OpenOCD will do when GDB detaches from the daemon.
1244 Default behaviour is @var{resume}.
1247 @deffn {Config command} gdb_flash_program <enable|disable>
1248 @anchor{gdb_flash_program}
1249 Set to @var{enable} to cause OpenOCD to program the flash memory when a
1250 vFlash packet is received.
1251 The default behaviour is @var{enable}.
1254 @deffn {Config command} gdb_memory_map <enable|disable>
1255 Set to @var{enable} to cause OpenOCD to send the memory configuration to GDB when
1256 requested. GDB will then know when to set hardware breakpoints, and program flash
1257 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1258 for flash programming to work.
1259 Default behaviour is @var{enable}.
1260 @xref{gdb_flash_program}.
1263 @deffn {Config command} gdb_report_data_abort <enable|disable>
1264 Specifies whether data aborts cause an error to be reported
1265 by GDB memory read packets.
1266 The default behaviour is @var{disable};
1267 use @var{enable} see these errors reported.
1270 @node Interface - Dongle Configuration
1271 @chapter Interface - Dongle Configuration
1272 Interface commands are normally found in an interface configuration
1273 file which is sourced by your openocd.cfg file. These commands tell
1274 OpenOCD what type of JTAG dongle you have and how to talk to it.
1275 @section Simple Complete Interface Examples
1276 @b{A Turtelizer FT2232 Based JTAG Dongle}
1280 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A"
1281 ft2232_layout turtelizer2
1282 ft2232_vid_pid 0x0403 0xbdc8
1289 @b{A Raisonance RLink}
1298 parport_cable wiggler
1303 interface arm-jtag-ew
1305 @section Interface Command
1307 The interface command tells OpenOCD what type of JTAG dongle you are
1308 using. Depending on the type of dongle, you may need to have one or
1309 more additional commands.
1313 @item @b{interface} <@var{name}>
1315 @*Use the interface driver <@var{name}> to connect to the
1316 target. Currently supported interfaces are
1321 @* PC parallel port bit-banging (Wigglers, PLD download cable, ...)
1323 @item @b{amt_jtagaccel}
1324 @* Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
1328 @* FTDI FT2232 (USB) based devices using either the open-source libftdi or the binary only
1329 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
1330 platform. The libftdi uses libusb, and should be portable to all systems that provide
1334 @*Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1337 @* ASIX PRESTO USB JTAG programmer.
1340 @* usbprog is a freely programmable USB adapter.
1343 @* Gateworks GW16012 JTAG programmer.
1346 @* Segger jlink USB adapter
1349 @* Raisonance RLink USB adapter
1352 @* vsllink is part of Versaloon which is a versatile USB programmer.
1354 @item @b{arm-jtag-ew}
1355 @* Olimex ARM-JTAG-EW USB adapter
1356 @comment - End parameters
1358 @comment - End Interface
1360 @subsection parport options
1363 @item @b{parport_port} <@var{number}>
1364 @cindex parport_port
1365 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1366 the @file{/dev/parport} device
1368 When using PPDEV to access the parallel port, use the number of the parallel port:
1369 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1370 you may encounter a problem.
1371 @item @b{parport_cable} <@var{name}>
1372 @cindex parport_cable
1373 @*The layout of the parallel port cable used to connect to the target.
1374 Currently supported cables are
1378 The original Wiggler layout, also supported by several clones, such
1379 as the Olimex ARM-JTAG
1382 Same as original wiggler except an led is fitted on D5.
1383 @item @b{wiggler_ntrst_inverted}
1384 @cindex wiggler_ntrst_inverted
1385 Same as original wiggler except TRST is inverted.
1386 @item @b{old_amt_wiggler}
1387 @cindex old_amt_wiggler
1388 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
1389 version available from the website uses the original Wiggler layout ('@var{wiggler}')
1392 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
1393 program the Chameleon itself, not a connected target.
1396 The Xilinx Parallel cable III.
1399 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
1400 This is also the layout used by the HollyGates design
1401 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1404 The ST Parallel cable.
1407 Same as original wiggler except SRST and TRST connections reversed and
1408 TRST is also inverted.
1411 Altium Universal JTAG cable.
1413 @item @b{parport_write_on_exit} <@var{on}|@var{off}>
1414 @cindex parport_write_on_exit
1415 @*This will configure the parallel driver to write a known value to the parallel
1416 interface on exiting OpenOCD
1419 @subsection amt_jtagaccel options
1421 @item @b{parport_port} <@var{number}>
1422 @cindex parport_port
1423 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
1424 @file{/dev/parport} device
1426 @subsection ft2232 options
1429 @item @b{ft2232_device_desc} <@var{description}>
1430 @cindex ft2232_device_desc
1431 @*The USB device description of the FTDI FT2232 device. If not
1432 specified, the FTDI default value is used. This setting is only valid
1433 if compiled with FTD2XX support.
1435 @b{TODO:} Confirm the following: On Windows the name needs to end with
1436 a ``space A''? Or not? It has to do with the FTD2xx driver. When must
1437 this be added and when must it not be added? Why can't the code in the
1438 interface or in OpenOCD automatically add this if needed? -- Duane.
1440 @item @b{ft2232_serial} <@var{serial-number}>
1441 @cindex ft2232_serial
1442 @*The serial number of the FTDI FT2232 device. If not specified, the FTDI default
1444 @item @b{ft2232_layout} <@var{name}>
1445 @cindex ft2232_layout
1446 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
1447 signals. Valid layouts are
1450 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
1452 Amontec JTAGkey and JTAGkey-Tiny
1453 @item @b{signalyzer}
1455 @item @b{olimex-jtag}
1458 American Microsystems M5960
1459 @item @b{evb_lm3s811}
1460 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
1461 SRST signals on external connector
1464 @item @b{stm32stick}
1465 Hitex STM32 Performance Stick
1466 @item @b{flyswatter}
1467 Tin Can Tools Flyswatter
1468 @item @b{turtelizer2}
1469 egnite Software turtelizer2
1472 @item @b{axm0432_jtag}
1476 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
1477 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1478 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, e.g.
1480 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1482 @item @b{ft2232_latency} <@var{ms}>
1483 @*On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1484 ft2232_read() fails to return the expected number of bytes. This can be caused by
1485 USB communication delays and has proved hard to reproduce and debug. Setting the
1486 FT2232 latency timer to a larger value increases delays for short USB packets but it
1487 also reduces the risk of timeouts before receiving the expected number of bytes.
1488 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1491 @subsection ep93xx options
1492 @cindex ep93xx options
1493 Currently, there are no options available for the ep93xx interface.
1497 @item @b{jtag_khz} <@var{reset speed kHz}>
1500 It is debatable if this command belongs here - or in a board
1501 configuration file. In fact, in some situations the JTAG speed is
1502 changed during the target initialisation process (i.e.: (1) slow at
1503 reset, (2) program the CPU clocks, (3) run fast)
1505 Speed 0 (khz) selects RTCK method. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1507 Not all interfaces support ``rtck''. If the interface device can not
1508 support the rate asked for, or can not translate from kHz to
1509 jtag_speed, then an error is returned.
1511 Make sure the JTAG clock is no more than @math{1/6th CPU-Clock}. This is
1512 especially true for synthesized cores (-S). Also see RTCK.
1514 @b{NOTE: Script writers} If the target chip requires/uses RTCK -
1515 please use the command: 'jtag_rclk FREQ'. This Tcl proc (in
1516 startup.tcl) attempts to enable RTCK, if that fails it falls back to
1517 the specified frequency.
1520 # Fall back to 3mhz if RCLK is not supported
1524 @item @b{DEPRECATED} @b{jtag_speed} - please use jtag_khz above.
1526 @*Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
1527 speed. The actual effect of this option depends on the JTAG interface used.
1529 The speed used during reset can be adjusted using setting jtag_speed during
1530 pre_reset and post_reset events.
1533 @item wiggler: maximum speed / @var{number}
1534 @item ft2232: 6MHz / (@var{number}+1)
1535 @item amt jtagaccel: 8 / 2**@var{number}
1536 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
1537 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
1538 @comment end speed list.
1541 @comment END command list
1544 @node Reset Configuration
1545 @chapter Reset Configuration
1546 @cindex Reset Configuration
1548 Every system configuration may require a different reset
1549 configuration. This can also be quite confusing. Please see the
1550 various board files for example.
1552 @section jtag_nsrst_delay <@var{ms}>
1553 @cindex jtag_nsrst_delay
1554 @*How long (in milliseconds) OpenOCD should wait after deasserting
1555 nSRST before starting new JTAG operations.
1557 @section jtag_ntrst_delay <@var{ms}>
1558 @cindex jtag_ntrst_delay
1559 @*Same @b{jtag_nsrst_delay}, but for nTRST
1561 The jtag_n[st]rst_delay options are useful if reset circuitry (like a
1562 big resistor/capacitor, reset supervisor, or on-chip features). This
1563 keeps the signal asserted for some time after the external reset got
1566 @section reset_config
1568 @b{Note:} To maintainers and integrators: Where exactly the
1569 ``reset configuration'' goes is a good question. It touches several
1570 things at once. In the end, if you have a board file - the board file
1571 should define it and assume 100% that the DONGLE supports
1572 anything. However, that does not mean the target should not also make
1573 not of something the silicon vendor has done inside the
1574 chip. @i{Grr.... nothing is every pretty.}
1578 @item Every JTAG Dongle is slightly different, some dongles implement reset differently.
1579 @item Every board is also slightly different; some boards tie TRST and SRST together.
1580 @item Every chip is slightly different; some chips internally tie the two signals together.
1581 @item Some may not implement all of the signals the same way.
1582 @item Some signals might be push-pull, others open-drain/collector.
1584 @b{Best Case:} OpenOCD can hold the SRST (push-button-reset), then
1585 reset the TAP via TRST and send commands through the JTAG tap to halt
1586 the CPU at the reset vector before the 1st instruction is executed,
1587 and finally release the SRST signal.
1588 @*Depending on your board vendor, chip vendor, etc., these
1589 signals may have slightly different names.
1591 OpenOCD defines these signals in these terms:
1593 @item @b{TRST} - is Tap Reset - and should reset only the TAP.
1594 @item @b{SRST} - is System Reset - typically equal to a reset push button.
1600 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
1601 @cindex reset_config
1602 @* The @t{reset_config} command tells OpenOCD the reset configuration
1603 of your combination of Dongle, Board, and Chips.
1604 If the JTAG interface provides SRST, but the target doesn't connect
1605 that signal properly, then OpenOCD can't use it. <@var{signals}> can
1606 be @option{none}, @option{trst_only}, @option{srst_only} or
1607 @option{trst_and_srst}.
1609 [@var{combination}] is an optional value specifying broken reset
1610 signal implementations. @option{srst_pulls_trst} states that the
1611 test logic is reset together with the reset of the system (e.g. Philips
1612 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
1613 the system is reset together with the test logic (only hypothetical, I
1614 haven't seen hardware with such a bug, and can be worked around).
1615 @option{combined} implies both @option{srst_pulls_trst} and
1616 @option{trst_pulls_srst}. The default behaviour if no option given is
1619 The [@var{trst_type}] and [@var{srst_type}] parameters allow the
1620 driver type of the reset lines to be specified. Possible values are
1621 @option{trst_push_pull} (default) and @option{trst_open_drain} for the
1622 test reset signal, and @option{srst_open_drain} (default) and
1623 @option{srst_push_pull} for the system reset. These values only affect
1624 JTAG interfaces with support for different drivers, like the Amontec
1625 JTAGkey and JTAGAccelerator.
1627 @comment - end command
1633 @chapter Tap Creation
1634 @cindex tap creation
1635 @cindex tap configuration
1637 In order for OpenOCD to control a target, a JTAG tap must be
1640 Commands to create taps are normally found in a configuration file and
1641 are not normally typed by a human.
1643 When a tap is created a @b{dotted.name} is created for the tap. Other
1644 commands use that dotted.name to manipulate or refer to the tap.
1648 @item @b{Debug Target} A tap can be used by a GDB debug target
1649 @item @b{Flash Programing} Some chips program the flash directly via JTAG,
1650 instead of indirectly by making a CPU do it.
1651 @item @b{Boundry Scan} Some chips support boundary scan.
1655 @section jtag newtap
1656 @b{@t{jtag newtap CHIPNAME TAPNAME configparams ....}}
1661 @cindex tap geometry
1663 @comment START options
1666 @* is a symbolic name of the chip.
1668 @* is a symbol name of a tap present on the chip.
1669 @item @b{Required configparams}
1670 @* Every tap has 3 required configparams, and several ``optional
1671 parameters'', the required parameters are:
1672 @comment START REQUIRED
1674 @item @b{-irlen NUMBER} - the length in bits of the instruction register, mostly 4 or 5 bits.
1675 @item @b{-ircapture NUMBER} - the IDCODE capture command, usually 0x01.
1676 @item @b{-irmask NUMBER} - the corresponding mask for the IR register. For
1677 some devices, there are bits in the IR that aren't used. This lets you mask
1678 them off when doing comparisons. In general, this should just be all ones for
1680 @comment END REQUIRED
1682 An example of a FOOBAR Tap
1684 jtag newtap foobar tap -irlen 7 -ircapture 0x42 -irmask 0x55
1686 Creates the tap ``foobar.tap'' with the instruction register (IR) is 7
1687 bits long, during Capture-IR 0x42 is loaded into the IR, and bits
1688 [6,4,2,0] are checked.
1690 @item @b{Optional configparams}
1691 @comment START Optional
1693 @item @b{-expected-id NUMBER}
1694 @* By default it is zero. If non-zero represents the
1695 expected tap ID used when the JTAG chain is examined. Repeat
1696 the option as many times as required if multiple id's can be
1697 expected. See below.
1700 @* By default not specified the tap is enabled. Some chips have a
1701 JTAG route controller (JRC) that is used to enable and/or disable
1702 specific JTAG taps. You can later enable or disable any JTAG tap via
1703 the command @b{jtag tapenable DOTTED.NAME} or @b{jtag tapdisable
1705 @comment END Optional
1708 @comment END OPTIONS
1711 @comment START NOTES
1713 @item @b{Technically}
1714 @* newtap is a sub command of the ``jtag'' command
1715 @item @b{Big Picture Background}
1716 @*GDB Talks to OpenOCD using the GDB protocol via
1717 TCP/IP. OpenOCD then uses the JTAG interface (the dongle) to
1718 control the JTAG chain on your board. Your board has one or more chips
1719 in a @i{daisy chain configuration}. Each chip may have one or more
1720 JTAG taps. GDB ends up talking via OpenOCD to one of the taps.
1721 @item @b{NAME Rules}
1722 @*Names follow ``C'' symbol name rules (start with alpha ...)
1723 @item @b{TAPNAME - Conventions}
1725 @item @b{tap} - should be used only FPGA or CPLD like devices with a single tap.
1726 @item @b{cpu} - the main CPU of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
1727 @item @b{flash} - if the chip has a flash tap, example: str912.flash
1728 @item @b{bs} - for boundary scan if this is a seperate tap.
1729 @item @b{etb} - for an embedded trace buffer (example: an ARM ETB11)
1730 @item @b{jrc} - for JTAG route controller (example: OMAP3530 found on Beagleboards)
1731 @item @b{unknownN} - where N is a number if you have no idea what the tap is for
1732 @item @b{Other names} - Freescale IMX31 has a SDMA (smart dma) with a JTAG tap, that tap should be called the ``sdma'' tap.
1733 @item @b{When in doubt} - use the chip maker's name in their data sheet.
1735 @item @b{DOTTED.NAME}
1736 @* @b{CHIPNAME}.@b{TAPNAME} creates the tap name, aka: the
1737 @b{Dotted.Name} is the @b{CHIPNAME} and @b{TAPNAME} combined with a
1738 dot (period); for example: @b{xilinx.tap}, @b{str912.flash},
1739 @b{omap3530.jrc}, or @b{stm32.cpu} The @b{dotted.name} is used in
1740 numerous other places to refer to various taps.
1742 @* The order this command appears via the config files is
1744 @item @b{Multi Tap Example}
1745 @* This example is based on the ST Microsystems STR912. See the ST
1746 document titled: @b{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
1747 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
1749 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}
1750 @*@b{checked: 28/nov/2008}
1752 The diagram shows that the TDO pin connects to the flash tap, flash TDI
1753 connects to the CPU debug tap, CPU TDI connects to the boundary scan
1754 tap which then connects to the TDI pin.
1758 # create tap: 'str912.flash'
1759 jtag newtap str912 flash ... params ...
1760 # create tap: 'str912.cpu'
1761 jtag newtap str912 cpu ... params ...
1762 # create tap: 'str912.bs'
1763 jtag newtap str912 bs ... params ...
1766 @item @b{Note: Deprecated} - Index Numbers
1767 @* Prior to 28/nov/2008, JTAG taps where numbered from 0..N this
1768 feature is still present, however its use is highly discouraged and
1769 should not be counted upon. Update all of your scripts to use
1770 TAP names rather than numbers.
1771 @item @b{Multiple chips}
1772 @* If your board has multiple chips, you should be
1773 able to @b{source} two configuration files, in the proper order, and
1774 have the taps created in the proper order.
1777 @comment at command level
1778 @comment DOCUMENT old command
1779 @section jtag_device - REMOVED
1781 @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
1785 @* @b{Removed: 28/nov/2008} This command has been removed and replaced
1786 by the ``jtag newtap'' command. The documentation remains here so that
1787 one can easily convert the old syntax to the new syntax. About the old
1788 syntax: The old syntax is positional, i.e.: The 3rd parameter is the
1789 ``irmask''. The new syntax requires named prefixes, and supports
1790 additional options, for example ``-expected-id 0x3f0f0f0f''. Please refer to the
1791 @b{jtag newtap} command for details.
1793 OLD: jtag_device 8 0x01 0xe3 0xfe
1794 NEW: jtag newtap CHIPNAME TAPNAME -irlen 8 -ircapture 0x01 -irmask 0xe3
1797 @section Enable/Disable Taps
1798 @b{Note:} These commands are intended to be used as a machine/script
1799 interface. Humans might find the ``scan_chain'' command more helpful
1800 when querying the state of the JTAG taps.
1802 @b{By default, all taps are enabled}
1805 @item @b{jtag tapenable} @var{DOTTED.NAME}
1806 @item @b{jtag tapdisable} @var{DOTTED.NAME}
1807 @item @b{jtag tapisenabled} @var{DOTTED.NAME}
1812 @cindex route controller
1814 These commands are used when your target has a JTAG route controller
1815 that effectively adds or removes a tap from the JTAG chain in a
1818 The ``standard way'' to remove a tap would be to place the tap in
1819 bypass mode. But with the advent of modern chips, this is not always a
1820 good solution. Some taps operate slowly, others operate fast, and
1821 there are other JTAG clock synchronisation problems one must face. To
1822 solve that problem, the JTAG route controller was introduced. Rather
1823 than ``bypass'' the tap, the tap is completely removed from the
1824 circuit and skipped.
1827 From OpenOCD's point of view, a JTAG tap is in one of 3 states:
1830 @item @b{Enabled - Not In ByPass} and has a variable bit length
1831 @item @b{Enabled - In ByPass} and has a length of exactly 1 bit.
1832 @item @b{Disabled} and has a length of ZERO and is removed from the circuit.
1835 The IEEE JTAG definition has no concept of a ``disabled'' tap.
1836 @b{Historical note:} this feature was added 28/nov/2008
1838 @b{jtag tapisenabled DOTTED.NAME}
1840 This command returns 1 if the named tap is currently enabled, 0 if not.
1841 This command exists so that scripts that manipulate a JRC (like the
1842 OMAP3530 has) can determine if OpenOCD thinks a tap is presently
1843 enabled or disabled.
1846 @node Target Configuration
1847 @chapter Target Configuration
1850 This chapter discusses how to create a GDB debug target. Before
1851 creating a ``target'' a JTAG tap DOTTED.NAME must exist first.
1853 @section targets [NAME]
1854 @b{Note:} This command name is PLURAL - not singular.
1856 With NO parameter, this plural @b{targets} command lists all known
1857 targets in a human friendly form.
1859 With a parameter, this plural @b{targets} command sets the current
1860 target to the given name. (i.e.: If there are multiple debug targets)
1865 CmdName Type Endian ChainPos State
1866 -- ---------- ---------- ---------- -------- ----------
1867 0: target0 arm7tdmi little 0 halted
1870 @section target COMMANDS
1871 @b{Note:} This command name is SINGULAR - not plural. It is used to
1872 manipulate specific targets, to create targets and other things.
1874 Once a target is created, a TARGETNAME (object) command is created;
1875 see below for details.
1877 The TARGET command accepts these sub-commands:
1879 @item @b{create} .. parameters ..
1880 @* creates a new target, see below for details.
1882 @* Lists all supported target types (perhaps some are not yet in this document).
1884 @* Lists all current debug target names, for example: 'str912.cpu' or 'pxa27.cpu' example usage:
1886 foreach t [target names] {
1887 puts [format "Target: %s\n" $t]
1891 @* Returns the current target. OpenOCD always has, or refers to the ``current target'' in some way.
1892 By default, commands like: ``mww'' (used to write memory) operate on the current target.
1893 @item @b{number} @b{NUMBER}
1894 @* Internally OpenOCD maintains a list of targets - in numerical index
1895 (0..N-1) this command returns the name of the target at index N.
1898 set thename [target number $x]
1899 puts [format "Target %d is: %s\n" $x $thename]
1902 @* Returns the number of targets known to OpenOCD (see number above)
1905 set c [target count]
1906 for { set x 0 } { $x < $c } { incr x } {
1907 # Assuming you have created this function
1908 print_target_details $x
1914 @section TARGETNAME (object) commands
1915 @b{Use:} Once a target is created, an ``object name'' that represents the
1916 target is created. By convention, the target name is identical to the
1917 tap name. In a multiple target system, one can preceed many common
1918 commands with a specific target name and effect only that target.
1920 str912.cpu mww 0x1234 0x42
1921 omap3530.cpu mww 0x5555 123
1924 @b{Model:} The Tcl/Tk language has the concept of object commands. A
1925 good example is a on screen button, once a button is created a button
1926 has a name (a path in Tk terms) and that name is useable as a 1st
1927 class command. For example in Tk, one can create a button and later
1928 configure it like this:
1932 button .foobar -background red -command @{ foo @}
1934 .foobar configure -foreground blue
1936 set x [.foobar cget -background]
1938 puts [format "The button is %s" $x]
1941 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
1942 button. Commands available as a ``target object'' are:
1944 @comment START targetobj commands.
1946 @item @b{configure} - configure the target; see Target Config/Cget Options below
1947 @item @b{cget} - query the target configuration; see Target Config/Cget Options below
1948 @item @b{curstate} - current target state (running, halt, etc.
1950 @* Intended for a human to see/read the currently configure target events.
1951 @item @b{Various Memory Commands} See the ``mww'' command elsewhere.
1952 @comment start memory
1962 @item @b{Memory To Array, Array To Memory}
1963 @* These are aimed at a machine interface to memory
1965 @item @b{mem2array ARRAYNAME WIDTH ADDRESS COUNT}
1966 @item @b{array2mem ARRAYNAME WIDTH ADDRESS COUNT}
1968 @* @b{ARRAYNAME} is the name of an array variable
1969 @* @b{WIDTH} is 8/16/32 - indicating the memory access size
1970 @* @b{ADDRESS} is the target memory address
1971 @* @b{COUNT} is the number of elements to process
1973 @item @b{Used during ``reset''}
1974 @* These commands are used internally by the OpenOCD scripts to deal
1975 with odd reset situations and are not documented here.
1977 @item @b{arp_examine}
1981 @item @b{arp_waitstate}
1983 @item @b{invoke-event} @b{EVENT-NAME}
1984 @* Invokes the specific event manually for the target
1987 @section Target Events
1989 @anchor{Target Events}
1990 At various times, certain things can happen, or you want them to happen.
1994 @item What should happen when GDB connects? Should your target reset?
1995 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
1996 @item During reset, do you need to write to certain memory location to reconfigure the SDRAM?
1999 All of the above items are handled by target events.
2001 To specify an event action, either during target creation, or later
2002 via ``$_TARGETNAME configure'' see this example.
2004 Syntactially, the option is: ``-event NAME BODY'' where NAME is a
2005 target event name, and BODY is a Tcl procedure or string of commands
2008 The programmers model is the ``-command'' option used in Tcl/Tk
2009 buttons and events. Below are two identical examples, the first
2010 creates and invokes small procedure. The second inlines the procedure.
2013 proc my_attach_proc @{ @} @{
2017 mychip.cpu configure -event gdb-attach my_attach_proc
2018 mychip.cpu configure -event gdb-attach @{ puts "Reset..." ; reset halt @}
2021 @section Current Events
2022 The following events are available:
2024 @item @b{debug-halted}
2025 @* The target has halted for debug reasons (i.e.: breakpoint)
2026 @item @b{debug-resumed}
2027 @* The target has resumed (i.e.: gdb said run)
2028 @item @b{early-halted}
2029 @* Occurs early in the halt process
2030 @item @b{examine-end}
2031 @* Currently not used (goal: when JTAG examine completes)
2032 @item @b{examine-start}
2033 @* Currently not used (goal: when JTAG examine starts)
2034 @item @b{gdb-attach}
2035 @* When GDB connects
2036 @item @b{gdb-detach}
2037 @* When GDB disconnects
2039 @* When the taret has halted and GDB is not doing anything (see early halt)
2040 @item @b{gdb-flash-erase-start}
2041 @* Before the GDB flash process tries to erase the flash
2042 @item @b{gdb-flash-erase-end}
2043 @* After the GDB flash process has finished erasing the flash
2044 @item @b{gdb-flash-write-start}
2045 @* Before GDB writes to the flash
2046 @item @b{gdb-flash-write-end}
2047 @* After GDB writes to the flash
2049 @* Before the taret steps, gdb is trying to start/resume the target
2051 @* The target has halted
2052 @item @b{old-gdb_program_config}
2053 @* DO NOT USE THIS: Used internally
2054 @item @b{old-pre_resume}
2055 @* DO NOT USE THIS: Used internally
2056 @item @b{reset-assert-pre}
2057 @* Before reset is asserted on the tap.
2058 @item @b{reset-assert-post}
2059 @* Reset is now asserted on the tap.
2060 @item @b{reset-deassert-pre}
2061 @* Reset is about to be released on the tap
2062 @item @b{reset-deassert-post}
2063 @* Reset has been released on the tap
2065 @* Currently not used.
2066 @item @b{reset-halt-post}
2067 @* Currently not usd
2068 @item @b{reset-halt-pre}
2069 @* Currently not used
2070 @item @b{reset-init}
2071 @* Used by @b{reset init} command for board-specific initialization.
2072 This is where you would configure PLLs and clocking, set up DRAM so
2073 you can download programs that don't fit in on-chip SRAM, set up pin
2074 multiplexing, and so on.
2075 @item @b{reset-start}
2076 @* Currently not used
2077 @item @b{reset-wait-pos}
2078 @* Currently not used
2079 @item @b{reset-wait-pre}
2080 @* Currently not used
2081 @item @b{resume-start}
2082 @* Before any target is resumed
2083 @item @b{resume-end}
2084 @* After all targets have resumed
2088 @* Target has resumed
2089 @item @b{tap-enable}
2090 @* Executed by @b{jtag tapenable DOTTED.NAME} command. Example:
2092 jtag configure DOTTED.NAME -event tap-enable @{
2097 @item @b{tap-disable}
2098 @*Executed by @b{jtag tapdisable DOTTED.NAME} command. Example:
2100 jtag configure DOTTED.NAME -event tap-disable @{
2101 puts "Disabling CPU"
2107 @section Target Create
2108 @anchor{Target Create}
2110 @cindex target creation
2113 @b{target} @b{create} <@var{NAME}> <@var{TYPE}> <@var{PARAMS ...}>
2115 @*This command creates a GDB debug target that refers to a specific JTAG tap.
2116 @comment START params
2119 @* Is the name of the debug target. By convention it should be the tap
2120 DOTTED.NAME. This name is also used to create the target object
2121 command, and in other places the target needs to be identified.
2123 @* Specifies the target type, i.e.: ARM7TDMI, or Cortex-M3. Currently supported targets are:
2124 @comment START types
2141 @*PARAMs are various target configuration parameters. The following ones are mandatory:
2142 @comment START mandatory
2144 @item @b{-endian big|little}
2145 @item @b{-chain-position DOTTED.NAME}
2146 @comment end MANDATORY
2151 @section Target Config/Cget Options
2152 These options can be specified when the target is created, or later
2153 via the configure option or to query the target via cget.
2155 You should specify a working area if you can; typically it uses some
2156 on-chip SRAM. Such a working area can speed up many things, including bulk
2157 writes to target memory; flash operations like checking to see if memory needs
2158 to be erased; GDB memory checksumming; and may help perform otherwise
2159 unavailable operations (like some coprocessor operations on ARM7/9 systems).
2161 @item @b{-type} - returns the target type
2162 @item @b{-event NAME BODY} see Target events
2163 @item @b{-work-area-virt [ADDRESS]} specify/set the work area base address
2164 which will be used when an MMU is active.
2165 @item @b{-work-area-phys [ADDRESS]} specify/set the work area base address
2166 which will be used when an MMU is inactive.
2167 @item @b{-work-area-size [ADDRESS]} specify/set the work area
2168 @item @b{-work-area-backup [0|1]} does the work area get backed up;
2169 by default, it doesn't. When possible, use a working_area that doesn't
2170 need to be backed up, since performing a backup slows down operations.
2171 @item @b{-endian [big|little]}
2172 @item @b{-variant [NAME]} some chips have variants OpenOCD needs to know about
2173 @item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
2177 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
2178 set name [target number $x]
2179 set y [$name cget -endian]
2180 set z [$name cget -type]
2181 puts [format "Chip %d is %s, Endian: %s, type: %s" $x $y $z]
2185 @section Target Variants
2188 @* Unknown (please write me)
2190 @* Unknown (please write me) (similar to arm7tdmi)
2192 @* Variants: @option{arm920t}, @option{arm922t} and @option{arm940t}
2193 This enables the hardware single-stepping support found on these
2198 @* None (this is also used as the ARM946)
2200 @* use variant <@var{-variant lm3s}> when debugging Luminary lm3s targets. This will cause
2201 OpenOCD to use a software reset rather than asserting SRST to avoid a issue with clearing
2202 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
2203 be detected and the normal reset behaviour used.
2205 @* Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},@option{pxa250}, @option{pxa255}, @option{pxa26x}.
2207 @* Supported variants are @option{arm1136}, @option{arm1156}, @option{arm1176}
2209 @* Use variant @option{ejtag_srst} when debugging targets that do not
2210 provide a functional SRST line on the EJTAG connector. This causes
2211 OpenOCD to instead use an EJTAG software reset command to reset the
2212 processor. You still need to enable @option{srst} on the reset
2213 configuration command to enable OpenOCD hardware reset functionality.
2214 @comment END variants
2216 @section working_area - Command Removed
2217 @cindex working_area
2218 @*@b{Please use the ``$_TARGETNAME configure -work-area-... parameters instead}
2219 @* This documentation remains because there are existing scripts that
2220 still use this that need to be converted.
2222 working_area target# address size backup| [virtualaddress]
2224 @* The target# is a the 0 based target numerical index.
2226 @node Flash Configuration
2227 @chapter Flash programming
2228 @cindex Flash Configuration
2230 OpenOCD has different commands for NOR and NAND flash;
2231 the ``flash'' command works with NOR flash, while
2232 the ``nand'' command works with NAND flash.
2233 This partially reflects different hardware technologies:
2234 NOR flash usually supports direct CPU instruction and data bus access,
2235 while data from a NAND flash must be copied to memory before it can be
2236 used. (SPI flash must also be copied to memory before use.)
2237 However, the documentation also uses ``flash'' as a generic term;
2238 for example, ``Put flash configuration in board-specific files''.
2240 @b{Note:} As of 28/nov/2008 OpenOCD does not know how to program a SPI
2241 flash that a micro may boot from. Perhaps you, the reader, would like to
2242 contribute support for this.
2246 @item Configure via the command @b{flash bank}
2247 @* Normally this is done in a configuration file.
2248 @item Operate on the flash via @b{flash SOMECOMMAND}
2249 @* Often commands to manipulate the flash are typed by a human, or run
2250 via a script in some automated way. For example: To program the boot
2251 flash on your board.
2253 @* Flashing via GDB requires the flash be configured via ``flash
2254 bank'', and the GDB flash features be enabled.
2255 @xref{GDB Configuration}.
2258 @section Flash commands
2259 @cindex Flash commands
2260 @subsection flash banks
2263 @*List configured flash banks
2264 @*@b{NOTE:} the singular form: 'flash bank' is used to configure the flash banks.
2265 @subsection flash info
2266 @b{flash info} <@var{num}>
2268 @*Print info about flash bank <@option{num}>
2269 @subsection flash probe
2270 @b{flash probe} <@var{num}>
2272 @*Identify the flash, or validate the parameters of the configured flash. Operation
2273 depends on the flash type.
2274 @subsection flash erase_check
2275 @b{flash erase_check} <@var{num}>
2276 @cindex flash erase_check
2277 @*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
2278 updates the erase state information displayed by @option{flash info}. That means you have
2279 to issue an @option{erase_check} command after erasing or programming the device to get
2280 updated information.
2281 @subsection flash protect_check
2282 @b{flash protect_check} <@var{num}>
2283 @cindex flash protect_check
2284 @*Check protection state of sectors in flash bank <num>.
2285 @option{flash erase_sector} using the same syntax.
2286 @subsection flash erase_sector
2287 @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
2288 @cindex flash erase_sector
2289 @anchor{flash erase_sector}
2290 @*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
2291 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
2292 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
2294 @subsection flash erase_address
2295 @b{flash erase_address} <@var{address}> <@var{length}>
2296 @cindex flash erase_address
2297 @*Erase sectors starting at <@var{address}> for <@var{length}> bytes
2298 @subsection flash write_bank
2299 @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
2300 @cindex flash write_bank
2301 @anchor{flash write_bank}
2302 @*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
2303 <@option{offset}> bytes from the beginning of the bank.
2304 @subsection flash write_image
2305 @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
2306 @cindex flash write_image
2307 @anchor{flash write_image}
2308 @*Write the image <@var{file}> to the current target's flash bank(s). A relocation
2309 [@var{offset}] can be specified and the file [@var{type}] can be specified
2310 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
2311 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
2312 if the @option{erase} parameter is given.
2313 @subsection flash protect
2314 @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
2315 @cindex flash protect
2316 @*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
2317 <@var{last}> of @option{flash bank} <@var{num}>.
2319 @subsection mFlash commands
2320 @cindex mFlash commands
2322 @item @b{mflash probe}
2323 @cindex mflash probe
2325 @item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
2326 @cindex mflash write
2327 Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
2328 <@var{offset}> bytes from the beginning of the bank.
2329 @item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
2331 Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
2335 @section flash bank command
2336 The @b{flash bank} command is used to configure one or more flash chips (or banks in OpenOCD terms)
2339 @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
2340 <@var{bus_width}> <@var{target}> [@var{driver_options ...}]
2343 @*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
2344 and <@var{bus_width}> bytes using the selected flash <driver>.
2346 @subsection External Flash - cfi options
2348 CFI flashes are external flash chips - often they are connected to a
2349 specific chip select on the CPU. By default, at hard reset, most
2350 CPUs have the ablity to ``boot'' from some flash chip - typically
2351 attached to the CPU's CS0 pin.
2353 For other chip selects: OpenOCD does not know how to configure, or
2354 access a specific chip select. Instead you, the human, might need to
2355 configure additional chip selects via other commands (like: mww) , or
2356 perhaps configure a GPIO pin that controls the ``write protect'' pin
2359 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
2360 <@var{target}> [@var{jedec_probe}|@var{x16_as_x8}]
2361 @*CFI flashes require the name or number of the target they're connected to
2363 argument. The CFI driver makes use of a working area (specified for the target)
2364 to significantly speed up operation.
2366 @var{chip_width} and @var{bus_width} are specified in bytes.
2368 The @var{jedec_probe} option is used to detect certain non-CFI flash ROMs, like AM29LV010 and similar types.
2372 @subsection Internal Flash (Microcontrollers)
2373 @subsubsection lpc2000 options
2374 @cindex lpc2000 options
2376 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
2377 <@var{clock}> [@var{calc_checksum}]
2378 @*LPC flashes don't require the chip and bus width to be specified. Additional
2379 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
2380 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx),
2381 the name or number of the target this flash belongs to (first is 0),
2382 the frequency at which the core
2383 is currently running (in kHz - must be an integral number), and the optional keyword
2384 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
2388 @subsubsection at91sam7 options
2389 @cindex at91sam7 options
2391 @b{flash bank at91sam7} 0 0 0 0 <@var{target}>
2392 @*AT91SAM7 flashes only require the @var{target}, all other values are looked up after
2393 reading the chip-id and type.
2395 @subsubsection str7 options
2396 @cindex str7 options
2398 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
2399 @*variant can be either STR71x, STR73x or STR75x.
2401 @subsubsection str9 options
2402 @cindex str9 options
2404 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target}>
2405 @*The str9 needs the flash controller to be configured prior to Flash programming, e.g.
2407 str9x flash_config 0 4 2 0 0x80000
2409 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
2411 @subsubsection str9 options (str9xpec driver)
2413 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target}>
2414 @*Before using the flash commands the turbo mode must be enabled using str9xpec
2415 @option{enable_turbo} <@var{num>.}
2417 Only use this driver for locking/unlocking the device or configuring the option bytes.
2418 Use the standard str9 driver for programming. @xref{STR9 specific commands}.
2420 @subsubsection Stellaris (LM3Sxxx) options
2421 @cindex Stellaris (LM3Sxxx) options
2423 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target}>
2424 @*Stellaris flash plugin only require the @var{target}.
2426 @subsubsection stm32x options
2427 @cindex stm32x options
2429 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target}>
2430 @*stm32x flash plugin only require the @var{target}.
2432 @subsubsection aduc702x options
2433 @cindex aduc702x options
2435 @b{flash bank aduc702x} 0 0 0 0 <@var{target}>
2436 @*The aduc702x flash plugin works with Analog Devices model numbers ADUC7019 through ADUC7028. The setup command only requires the @var{target} argument (all devices in this family have the same memory layout).
2438 @subsection mFlash Configuration
2439 @cindex mFlash Configuration
2440 @b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
2441 <@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target}>
2443 @*Configures a mflash for <@var{soc}> host bank at
2444 <@var{base}>. <@var{chip_width}> and <@var{bus_width}> are bytes
2445 order. Pin number format is dependent on host GPIO calling convention.
2446 If WP or DPD pin was not used, write -1. Currently, mflash bank
2447 support s3c2440 and pxa270.
2449 (ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1, <@var{WP pin}> and <@var{DPD pin}> are not used.
2451 mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0
2453 (ex. of pxa270) mflash <@var{RST pin}> is GPIO 43, <@var{DPD pin}> is not used and <@var{DPD pin}> is GPIO 51.
2455 mflash bank pxa270 0x08000000 2 2 43 -1 51 0
2458 @section Microcontroller specific Flash Commands
2460 @subsection AT91SAM7 specific commands
2461 @cindex AT91SAM7 specific commands
2462 The flash configuration is deduced from the chip identification register. The flash
2463 controller handles erases automatically on a page (128/265 byte) basis, so erase is
2464 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
2465 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
2466 that can be erased separatly. Only an EraseAll command is supported by the controller
2467 for each flash plane and this is called with
2469 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
2470 @*bulk erase flash planes first_plane to last_plane.
2471 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
2472 @cindex at91sam7 gpnvm
2473 @*set or clear a gpnvm bit for the processor
2476 @subsection STR9 specific commands
2477 @cindex STR9 specific commands
2478 @anchor{STR9 specific commands}
2479 These are flash specific commands when using the str9xpec driver.
2481 @item @b{str9xpec enable_turbo} <@var{num}>
2482 @cindex str9xpec enable_turbo
2483 @*enable turbo mode, will simply remove the str9 from the chain and talk
2484 directly to the embedded flash controller.
2485 @item @b{str9xpec disable_turbo} <@var{num}>
2486 @cindex str9xpec disable_turbo
2487 @*restore the str9 into JTAG chain.
2488 @item @b{str9xpec lock} <@var{num}>
2489 @cindex str9xpec lock
2490 @*lock str9 device. The str9 will only respond to an unlock command that will
2492 @item @b{str9xpec unlock} <@var{num}>
2493 @cindex str9xpec unlock
2494 @*unlock str9 device.
2495 @item @b{str9xpec options_read} <@var{num}>
2496 @cindex str9xpec options_read
2497 @*read str9 option bytes.
2498 @item @b{str9xpec options_write} <@var{num}>
2499 @cindex str9xpec options_write
2500 @*write str9 option bytes.
2503 Note: Before using the str9xpec driver here is some background info to help
2504 you better understand how the drivers works. OpenOCD has two flash drivers for
2508 Standard driver @option{str9x} programmed via the str9 core. Normally used for
2509 flash programming as it is faster than the @option{str9xpec} driver.
2511 Direct programming @option{str9xpec} using the flash controller. This is an
2512 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
2513 core does not need to be running to program using this flash driver. Typical use
2514 for this driver is locking/unlocking the target and programming the option bytes.
2517 Before we run any commands using the @option{str9xpec} driver we must first disable
2518 the str9 core. This example assumes the @option{str9xpec} driver has been
2519 configured for flash bank 0.
2521 # assert srst, we do not want core running
2522 # while accessing str9xpec flash driver
2524 # turn off target polling
2527 str9xpec enable_turbo 0
2529 str9xpec options_read 0
2530 # re-enable str9 core
2531 str9xpec disable_turbo 0
2535 The above example will read the str9 option bytes.
2536 When performing a unlock remember that you will not be able to halt the str9 - it
2537 has been locked. Halting the core is not required for the @option{str9xpec} driver
2538 as mentioned above, just issue the commands above manually or from a telnet prompt.
2540 @subsection STR9 configuration
2541 @cindex STR9 configuration
2543 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
2544 <@var{BBADR}> <@var{NBBADR}>
2545 @cindex str9x flash_config
2546 @*Configure str9 flash controller.
2548 e.g. str9x flash_config 0 4 2 0 0x80000
2550 BBSR - Boot Bank Size register
2551 NBBSR - Non Boot Bank Size register
2552 BBADR - Boot Bank Start Address register
2553 NBBADR - Boot Bank Start Address register
2557 @subsection STR9 option byte configuration
2558 @cindex STR9 option byte configuration
2560 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
2561 @cindex str9xpec options_cmap
2562 @*configure str9 boot bank.
2563 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
2564 @cindex str9xpec options_lvdthd
2565 @*configure str9 lvd threshold.
2566 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
2567 @cindex str9xpec options_lvdsel
2568 @*configure str9 lvd source.
2569 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
2570 @cindex str9xpec options_lvdwarn
2571 @*configure str9 lvd reset warning source.
2574 @subsection STM32x specific commands
2575 @cindex STM32x specific commands
2577 These are flash specific commands when using the stm32x driver.
2579 @item @b{stm32x lock} <@var{num}>
2581 @*lock stm32 device.
2582 @item @b{stm32x unlock} <@var{num}>
2583 @cindex stm32x unlock
2584 @*unlock stm32 device.
2585 @item @b{stm32x options_read} <@var{num}>
2586 @cindex stm32x options_read
2587 @*read stm32 option bytes.
2588 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
2589 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
2590 @cindex stm32x options_write
2591 @*write stm32 option bytes.
2592 @item @b{stm32x mass_erase} <@var{num}>
2593 @cindex stm32x mass_erase
2594 @*mass erase flash memory.
2597 @subsection Stellaris specific commands
2598 @cindex Stellaris specific commands
2600 These are flash specific commands when using the Stellaris driver.
2602 @item @b{stellaris mass_erase} <@var{num}>
2603 @cindex stellaris mass_erase
2604 @*mass erase flash memory.
2607 @node NAND Flash Commands
2608 @chapter NAND Flash Commands
2611 Compared to NOR or SPI flash, NAND devices are inexpensive
2612 and high density. Today's NAND chips, and multi-chip modules,
2613 commonly hold multiple GigaBytes of data.
2615 NAND chips consist of a number of ``erase blocks'' of a given
2616 size (such as 128 KBytes), each of which is divided into a
2617 number of pages (of perhaps 512 or 2048 bytes each). Each
2618 page of a NAND flash has an ``out of band'' (OOB) area to hold
2619 Error Correcting Code (ECC) and other metadata, usually 16 bytes
2620 of OOB for every 512 bytes of page data.
2622 One key characteristic of NAND flash is that its error rate
2623 is higher than that of NOR flash. In normal operation, that
2624 ECC is used to correct and detect errors. However, NAND
2625 blocks can also wear out and become unusable; those blocks
2626 are then marked "bad". NAND chips are even shipped from the
2627 manufacturer with a few bad blocks. The highest density chips
2628 use a technology (MLC) that wears out more quickly, so ECC
2629 support is increasingly important as a way to detect blocks
2630 that have begun to fail, and help to preserve data integrity
2631 with techniques such as wear leveling.
2633 Software is used to manage the ECC. Some controllers don't
2634 support ECC directly; in those cases, software ECC is used.
2635 Other controllers speed up the ECC calculations with hardware.
2636 Single-bit error correction hardware is routine. Controllers
2637 geared for newer MLC chips may correct 4 or more errors for
2638 every 512 bytes of data.
2640 You will need to make sure that any data you write using
2641 OpenOCD includes the apppropriate kind of ECC. For example,
2642 that may mean passing the @code{oob_softecc} flag when
2643 writing NAND data, or ensuring that the correct hardware
2646 The basic steps for using NAND devices include:
2648 @item Declare via the command @command{nand device}
2649 @* Do this in a board-specific configuration file,
2650 passing parameters as needed by the controller.
2651 @item Configure each device using @command{nand probe}.
2652 @* Do this only after the associated target is set up,
2653 such as in its reset-init script or in procures defined
2654 to access that device.
2655 @item Operate on the flash via @command{nand subcommand}
2656 @* Often commands to manipulate the flash are typed by a human, or run
2657 via a script in some automated way. Common task include writing a
2658 boot loader, operating system, or other data needed to initialize or
2662 @b{NOTE:} At the time this text was written, the largest NAND
2663 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
2664 This is because the variables used to hold offsets and lengths
2665 are only 32 bits wide.
2666 (Larger chips may work in some cases, unless an offset or length
2667 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
2668 Some larger devices will work, since they are actually multi-chip
2669 modules with two smaller chips and individual chipselect lines.
2671 @section NAND Configuration Commands
2672 @cindex NAND configuration
2674 NAND chips must be declared in configuration scripts,
2675 plus some additional configuration that's done after
2676 OpenOCD has initialized.
2678 @deffn {Config Command} {nand device} controller target [configparams...]
2679 Declares a NAND device, which can be read and written to
2680 after it has been configured through @command{nand probe}.
2681 In OpenOCD, devices are single chips; this is unlike some
2682 operating systems, which may manage multiple chips as if
2683 they were a single (larger) device.
2684 In some cases, configuring a device will activate extra
2685 commands; see the controller-specific documentation.
2687 @b{NOTE:} This command is not available after OpenOCD
2688 initialization has completed. Use it in board specific
2689 configuration files, not interactively.
2692 @item @var{controller} ... identifies a the controller driver
2693 associated with the NAND device being declared.
2694 @xref{NAND Driver List}.
2695 @item @var{target} ... names the target used when issuing
2696 commands to the NAND controller.
2697 @comment Actually, it's currently a controller-specific parameter...
2698 @item @var{configparams} ... controllers may support, or require,
2699 additional parameters. See the controller-specific documentation
2700 for more information.
2704 @deffn Command {nand list}
2705 Prints a one-line summary of each device declared
2706 using @command{nand device}, numbered from zero.
2707 Note that un-probed devices show no details.
2710 @deffn Command {nand probe} num
2711 Probes the specified device to determine key characteristics
2712 like its page and block sizes, and how many blocks it has.
2713 The @var{num} parameter is the value shown by @command{nand list}.
2714 You must (successfully) probe a device before you can use
2715 it with most other NAND commands.
2718 @section Erasing, Reading, Writing to NAND Flash
2720 @deffn Command {nand dump} num filename offset length [oob_option]
2721 @cindex NAND reading
2722 Reads binary data from the NAND device and writes it to the file,
2723 starting at the specified offset.
2724 The @var{num} parameter is the value shown by @command{nand list}.
2726 Use a complete path name for @var{filename}, so you don't depend
2727 on the directory used to start the OpenOCD server.
2729 The @var{offset} and @var{length} must be exact multiples of the
2730 device's page size. They describe a data region; the OOB data
2731 associated with each such page may also be accessed.
2733 @b{NOTE:} At the time this text was written, no error correction
2734 was done on the data that's read, unless raw access was disabled
2735 and the underlying NAND controller driver had a @code{read_page}
2736 method which handled that error correction.
2738 By default, only page data is saved to the specified file.
2739 Use an @var{oob_option} parameter to save OOB data:
2741 @item no oob_* parameter
2742 @*Output file holds only page data; OOB is discarded.
2743 @item @code{oob_raw}
2744 @*Output file interleaves page data and OOB data;
2745 the file will be longer than "length" by the size of the
2746 spare areas associated with each data page.
2747 Note that this kind of "raw" access is different from
2748 what's implied by @command{nand raw_access}, which just
2749 controls whether a hardware-aware access method is used.
2750 @item @code{oob_only}
2751 @*Output file has only raw OOB data, and will
2752 be smaller than "length" since it will contain only the
2753 spare areas associated with each data page.
2757 @deffn Command {nand erase} num offset length
2758 @cindex NAND erasing
2759 Erases blocks on the specified NAND device, starting at the
2760 specified @var{offset} and continuing for @var{length} bytes.
2761 Both of those values must be exact multiples of the device's
2762 block size, and the region they specify must fit entirely in the chip.
2763 The @var{num} parameter is the value shown by @command{nand list}.
2765 @b{NOTE:} This command will try to erase bad blocks, when told
2766 to do so, which will probably invalidate the manufacturer's bad
2768 For the remainder of the current server session, @command{nand info}
2769 will still report that the block ``is'' bad.
2772 @deffn Command {nand write} num filename offset [option...]
2773 @cindex NAND writing
2774 Writes binary data from the file into the specified NAND device,
2775 starting at the specified offset. Those pages should already
2776 have been erased; you can't change zero bits to one bits.
2777 The @var{num} parameter is the value shown by @command{nand list}.
2779 Use a complete path name for @var{filename}, so you don't depend
2780 on the directory used to start the OpenOCD server.
2782 The @var{offset} must be an exact multiple of the device's page size.
2783 All data in the file will be written, assuming it doesn't run
2784 past the end of the device.
2785 Only full pages are written, and any extra space in the last
2786 page will be filled with 0xff bytes. (That includes OOB data,
2787 if that's being written.)
2789 @b{NOTE:} At the time this text was written, bad blocks are
2790 ignored. That is, this routine will not skip bad blocks,
2791 but will instead try to write them. This can cause problems.
2793 Provide at most one @var{option} parameter. With some
2794 NAND drivers, the meanings of these parameters may change
2795 if @command{nand raw_access} was used to disable hardware ECC.
2797 @item no oob_* parameter
2798 @*File has only page data, which is written.
2799 If raw acccess is in use, the OOB area will not be written.
2800 Otherwise, if the underlying NAND controller driver has
2801 a @code{write_page} routine, that routine may write the OOB
2802 with hardware-computed ECC data.
2803 @item @code{oob_only}
2804 @*File has only raw OOB data, which is written to the OOB area.
2805 Each page's data area stays untouched. @i{This can be a dangerous
2806 option}, since it can invalidate the ECC data.
2807 You may need to force raw access to use this mode.
2808 @item @code{oob_raw}
2809 @*File interleaves data and OOB data, both of which are written
2810 If raw access is enabled, the data is written first, then the
2812 Otherwise, if the underlying NAND controller driver has
2813 a @code{write_page} routine, that routine may modify the OOB
2814 before it's written, to include hardware-computed ECC data.
2815 @item @code{oob_softecc}
2816 @*File has only page data, which is written.
2817 The OOB area is filled with 0xff, except for a standard 1-bit
2818 software ECC code stored in conventional locations.
2819 You might need to force raw access to use this mode, to prevent
2820 the underlying driver from applying hardware ECC.
2821 @item @code{oob_softecc_kw}
2822 @*File has only page data, which is written.
2823 The OOB area is filled with 0xff, except for a 4-bit software ECC
2824 specific to the boot ROM in Marvell Kirkwood SoCs.
2825 You might need to force raw access to use this mode, to prevent
2826 the underlying driver from applying hardware ECC.
2830 @section Other NAND commands
2831 @cindex NAND other commands
2833 @deffn Command {nand check_bad_blocks} [offset length]
2834 Checks for manufacturer bad block markers on the specified NAND
2835 device. If no parameters are provided, checks the whole
2836 device; otherwise, starts at the specified @var{offset} and
2837 continues for @var{length} bytes.
2838 Both of those values must be exact multiples of the device's
2839 block size, and the region they specify must fit entirely in the chip.
2840 The @var{num} parameter is the value shown by @command{nand list}.
2842 @b{NOTE:} Before using this command you should force raw access
2843 with @command{nand raw_access enable} to ensure that the underlying
2844 driver will not try to apply hardware ECC.
2847 @deffn Command {nand info} num
2848 The @var{num} parameter is the value shown by @command{nand list}.
2849 This prints the one-line summary from "nand list", plus for
2850 devices which have been probed this also prints any known
2851 status for each block.
2854 @deffn Command {nand raw_access} num <enable|disable>
2855 Sets or clears an flag affecting how page I/O is done.
2856 The @var{num} parameter is the value shown by @command{nand list}.
2858 This flag is cleared (disabled) by default, but changing that
2859 value won't affect all NAND devices. The key factor is whether
2860 the underlying driver provides @code{read_page} or @code{write_page}
2861 methods. If it doesn't provide those methods, the setting of
2862 this flag is irrelevant; all access is effectively ``raw''.
2864 When those methods exist, they are normally used when reading
2865 data (@command{nand dump} or reading bad block markers) or
2866 writing it (@command{nand write}). However, enabling
2867 raw access (setting the flag) prevents use of those methods,
2868 bypassing hardware ECC logic.
2869 @i{This can be a dangerous option}, since writing blocks
2870 with the wrong ECC data can cause them to be marked as bad.
2873 @section NAND Drivers; Driver-specific Options and Commands
2874 @anchor{NAND Driver List}
2875 As noted above, the @command{nand device} command allows
2876 driver-specific options and behaviors.
2877 Some controllers also activate controller-specific commands.
2879 @deffn {NAND Driver} davinci
2880 This driver handles the NAND controllers found on DaVinci family
2881 chips from Texas Instruments.
2882 It takes three extra parameters:
2883 address of the NAND chip;
2884 hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
2885 address of the AEMIF controller on this processor.
2887 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
2889 All DaVinci processors support the single-bit ECC hardware,
2890 and newer ones also support the four-bit ECC hardware.
2891 The @code{write_page} and @code{read_page} methods are used
2892 to implement those ECC modes, unless they are disabled using
2893 the @command{nand raw_access} command.
2896 @deffn {NAND Driver} lpc3180
2897 These controllers require an extra @command{nand device}
2898 parameter: the clock rate used by the controller.
2899 @deffn Command {nand lpc3180 select} num [mlc|slc]
2900 Configures use of the MLC or SLC controller mode.
2901 MLC implies use of hardware ECC.
2902 The @var{num} parameter is the value shown by @command{nand list}.
2905 At this writing, this driver includes @code{write_page}
2906 and @code{read_page} methods. Using @command{nand raw_access}
2907 to disable those methods will prevent use of hardware ECC
2908 in the MLC controller mode, but won't change SLC behavior.
2910 @comment current lpc3180 code won't issue 5-byte address cycles
2912 @deffn {NAND Driver} orion
2913 These controllers require an extra @command{nand device}
2914 parameter: the address of the controller.
2916 nand device orion 0xd8000000
2918 These controllers don't define any specialized commands.
2919 At this writing, their drivers don't include @code{write_page}
2920 or @code{read_page} methods, so @command{nand raw_access} won't
2921 change any behavior.
2924 @deffn {NAND Driver} {s3c2410, s3c2412, s3c2440, s3c2443}
2925 These S3C24xx family controllers don't have any special
2926 @command{nand device} options, and don't define any
2927 specialized commands.
2928 At this writing, their drivers don't include @code{write_page}
2929 or @code{read_page} methods, so @command{nand raw_access} won't
2930 change any behavior.
2933 @node General Commands
2934 @chapter General Commands
2937 The commands documented in this chapter here are common commands that
2938 you, as a human, may want to type and see the output of. Configuration type
2939 commands are documented elsewhere.
2943 @item @b{Source Of Commands}
2944 @* OpenOCD commands can occur in a configuration script (discussed
2945 elsewhere) or typed manually by a human or supplied programatically,
2946 or via one of several TCP/IP Ports.
2948 @item @b{From the human}
2949 @* A human should interact with the telnet interface (default port: 4444)
2950 or via GDB (default port 3333).
2952 To issue commands from within a GDB session, use the @option{monitor}
2953 command, e.g. use @option{monitor poll} to issue the @option{poll}
2954 command. All output is relayed through the GDB session.
2956 @item @b{Machine Interface}
2957 The Tcl interface's intent is to be a machine interface. The default Tcl
2962 @section Daemon Commands
2964 @subsection sleep [@var{msec}]
2966 @*Wait for n milliseconds before resuming. Useful in connection with script files
2967 (@var{script} command and @var{target_script} configuration).
2969 @subsection shutdown
2971 @*Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
2973 @subsection debug_level [@var{n}]
2975 @anchor{debug_level}
2976 @*Display or adjust debug level to n<0-3>
2978 @subsection fast [@var{enable|disable}]
2980 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
2981 downloads and fast memory access will work if the JTAG interface isn't too fast and
2982 the core doesn't run at a too low frequency. Note that this option only changes the default
2983 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
2986 The target specific "dangerous" optimisation tweaking options may come and go
2987 as more robust and user friendly ways are found to ensure maximum throughput
2988 and robustness with a minimum of configuration.
2990 Typically the "fast enable" is specified first on the command line:
2993 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
2996 @subsection echo <@var{message}>
2998 @*Output message to stdio. e.g. echo "Programming - please wait"
3000 @subsection log_output <@var{file}>
3002 @*Redirect logging to <file> (default: stderr)
3004 @subsection script <@var{file}>
3006 @*Execute commands from <file>
3007 See also: ``source [find FILENAME]''
3009 @section Target state handling
3010 @subsection power <@var{on}|@var{off}>
3012 @*Turn power switch to target on/off.
3013 No arguments: print status.
3014 Not all interfaces support this.
3016 @subsection reg [@option{#}|@option{name}] [value]
3018 @*Access a single register by its number[@option{#}] or by its [@option{name}].
3019 No arguments: list all available registers for the current target.
3020 Number or name argument: display a register.
3021 Number or name and value arguments: set register value.
3023 @subsection poll [@option{on}|@option{off}]
3025 @*Poll the target for its current state. If the target is in debug mode, architecture
3026 specific information about the current state is printed. An optional parameter
3027 allows continuous polling to be enabled and disabled.
3029 @subsection halt [@option{ms}]
3031 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
3032 Default [@option{ms}] is 5 seconds if no arg given.
3033 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
3034 will stop OpenOCD from waiting.
3036 @subsection wait_halt [@option{ms}]
3038 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
3039 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
3042 @subsection resume [@var{address}]
3044 @*Resume the target at its current code position, or at an optional address.
3045 OpenOCD will wait 5 seconds for the target to resume.
3047 @subsection step [@var{address}]
3049 @*Single-step the target at its current code position, or at an optional address.
3051 @subsection reset [@option{run}|@option{halt}|@option{init}]
3053 @*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
3055 With no arguments a "reset run" is executed
3059 @*Let the target run.
3062 @*Immediately halt the target (works only with certain configurations).
3065 @*Immediately halt the target, and execute the reset script (works only with certain
3069 @subsection soft_reset_halt
3071 @*Requesting target halt and executing a soft reset. This is often used
3072 when a target cannot be reset and halted. The target, after reset is
3073 released begins to execute code. OpenOCD attempts to stop the CPU and
3074 then sets the program counter back to the reset vector. Unfortunately
3075 the code that was executed may have left the hardware in an unknown
3079 @section Memory access commands
3081 display available RAM memory.
3082 @subsection Memory peek/poke type commands
3083 These commands allow accesses of a specific size to the memory
3084 system. Often these are used to configure the current target in some
3085 special way. For example - one may need to write certian values to the
3086 SDRAM controller to enable SDRAM.
3089 @item To change the current target see the ``targets'' (plural) command
3090 @item In system level scripts these commands are deprecated, please use the TARGET object versions.
3094 @item @b{mdw} <@var{addr}> [@var{count}]
3096 @*display memory words (32bit)
3097 @item @b{mdh} <@var{addr}> [@var{count}]
3099 @*display memory half-words (16bit)
3100 @item @b{mdb} <@var{addr}> [@var{count}]
3102 @*display memory bytes (8bit)
3103 @item @b{mww} <@var{addr}> <@var{value}>
3105 @*write memory word (32bit)
3106 @item @b{mwh} <@var{addr}> <@var{value}>
3108 @*write memory half-word (16bit)
3109 @item @b{mwb} <@var{addr}> <@var{value}>
3111 @*write memory byte (8bit)
3114 @section Image loading commands
3115 @subsection load_image
3116 @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3119 @*Load image <@var{file}> to target memory at <@var{address}>
3120 @subsection fast_load_image
3121 @b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3122 @cindex fast_load_image
3123 @anchor{fast_load_image}
3124 @*Normally you should be using @b{load_image} or GDB load. However, for
3125 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
3126 host), storing the image in memory and uploading the image to the target
3127 can be a way to upload e.g. multiple debug sessions when the binary does not change.
3128 Arguments are the same as @b{load_image}, but the image is stored in OpenOCD host
3129 memory, i.e. does not affect target. This approach is also useful when profiling
3130 target programming performance as I/O and target programming can easily be profiled
3132 @subsection fast_load
3136 @*Loads an image stored in memory by @b{fast_load_image} to the current target. Must be preceeded by fast_load_image.
3137 @subsection dump_image
3138 @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
3141 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
3142 (binary) <@var{file}>.
3143 @subsection verify_image
3144 @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3145 @cindex verify_image
3146 @*Verify <@var{file}> against target memory starting at <@var{address}>.
3147 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
3150 @section Breakpoint commands
3151 @cindex Breakpoint commands
3153 @item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
3155 @*set breakpoint <address> <length> [hw]
3156 @item @b{rbp} <@var{addr}>
3158 @*remove breakpoint <adress>
3159 @item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
3161 @*set watchpoint <address> <length> <r/w/a> [value] [mask]
3162 @item @b{rwp} <@var{addr}>
3164 @*remove watchpoint <adress>
3167 @section Misc Commands
3168 @cindex Other Target Commands
3170 @item @b{profile} <@var{seconds}> <@var{gmon.out}>
3172 Profiling samples the CPU's program counter as quickly as possible, which is useful for non-intrusive stochastic profiling.
3176 @section Target Specific Commands
3177 @cindex Target Specific Commands
3181 @section Architecture Specific Commands
3182 @cindex Architecture Specific Commands
3184 @subsection ARMV4/5 specific commands
3185 @cindex ARMV4/5 specific commands
3187 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
3188 or Intel XScale (XScale isn't supported yet).
3190 @item @b{armv4_5 reg}
3192 @*Display a list of all banked core registers, fetching the current value from every
3193 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
3195 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
3196 @cindex armv4_5 core_mode
3197 @*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
3198 The target is resumed in the currently set @option{core_mode}.
3201 @subsection ARM7/9 specific commands
3202 @cindex ARM7/9 specific commands
3204 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
3205 ARM920T or ARM926EJ-S.
3207 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
3208 @cindex arm7_9 dbgrq
3209 @*Enable use of the DBGRQ bit to force entry into debug mode. This should be
3210 safe for all but ARM7TDMI--S cores (like Philips LPC).
3211 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
3212 @cindex arm7_9 fast_memory_access
3213 @anchor{arm7_9 fast_memory_access}
3214 @*Allow OpenOCD to read and write memory without checking completion of
3215 the operation. This provides a huge speed increase, especially with USB JTAG
3216 cables (FT2232), but might be unsafe if used with targets running at very low
3217 speeds, like the 32kHz startup clock of an AT91RM9200.
3218 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
3219 @cindex arm7_9 dcc_downloads
3220 @*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
3221 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
3222 unsafe, especially with targets running at very low speeds. This command was introduced
3223 with OpenOCD rev. 60, and requires a few bytes of working area.
3226 @subsection ARM720T specific commands
3227 @cindex ARM720T specific commands
3230 @item @b{arm720t cp15} <@var{num}> [@var{value}]
3231 @cindex arm720t cp15
3232 @*display/modify cp15 register <@option{num}> [@option{value}].
3233 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
3234 @cindex arm720t md<bhw>_phys
3235 @*Display memory at physical address addr.
3236 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
3237 @cindex arm720t mw<bhw>_phys
3238 @*Write memory at physical address addr.
3239 @item @b{arm720t virt2phys} <@var{va}>
3240 @cindex arm720t virt2phys
3241 @*Translate a virtual address to a physical address.
3244 @subsection ARM9TDMI specific commands
3245 @cindex ARM9TDMI specific commands
3248 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
3249 @cindex arm9tdmi vector_catch
3250 @*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
3251 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
3252 @option{irq} @option{fiq}.
3254 Can also be used on other ARM9 based cores such as ARM966, ARM920T and ARM926EJ-S.
3257 @subsection ARM966E specific commands
3258 @cindex ARM966E specific commands
3261 @item @b{arm966e cp15} <@var{num}> [@var{value}]
3262 @cindex arm966e cp15
3263 @*display/modify cp15 register <@option{num}> [@option{value}].
3266 @subsection ARM920T specific commands
3267 @cindex ARM920T specific commands
3270 @item @b{arm920t cp15} <@var{num}> [@var{value}]
3271 @cindex arm920t cp15
3272 @*display/modify cp15 register <@option{num}> [@option{value}].
3273 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
3274 @cindex arm920t cp15i
3275 @*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
3276 @item @b{arm920t cache_info}
3277 @cindex arm920t cache_info
3278 @*Print information about the caches found. This allows to see whether your target
3279 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
3280 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
3281 @cindex arm920t md<bhw>_phys
3282 @*Display memory at physical address addr.
3283 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
3284 @cindex arm920t mw<bhw>_phys
3285 @*Write memory at physical address addr.
3286 @item @b{arm920t read_cache} <@var{filename}>
3287 @cindex arm920t read_cache
3288 @*Dump the content of ICache and DCache to a file.
3289 @item @b{arm920t read_mmu} <@var{filename}>
3290 @cindex arm920t read_mmu
3291 @*Dump the content of the ITLB and DTLB to a file.
3292 @item @b{arm920t virt2phys} <@var{va}>
3293 @cindex arm920t virt2phys
3294 @*Translate a virtual address to a physical address.
3297 @subsection ARM926EJ-S specific commands
3298 @cindex ARM926EJ-S specific commands
3301 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
3302 @cindex arm926ejs cp15
3303 @*display/modify cp15 register <@option{num}> [@option{value}].
3304 @item @b{arm926ejs cache_info}
3305 @cindex arm926ejs cache_info
3306 @*Print information about the caches found.
3307 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
3308 @cindex arm926ejs md<bhw>_phys
3309 @*Display memory at physical address addr.
3310 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
3311 @cindex arm926ejs mw<bhw>_phys
3312 @*Write memory at physical address addr.
3313 @item @b{arm926ejs virt2phys} <@var{va}>
3314 @cindex arm926ejs virt2phys
3315 @*Translate a virtual address to a physical address.
3318 @subsection CORTEX_M3 specific commands
3319 @cindex CORTEX_M3 specific commands
3322 @item @b{cortex_m3 maskisr} <@var{on}|@var{off}>
3323 @cindex cortex_m3 maskisr
3324 @*Enable masking (disabling) interrupts during target step/resume.
3328 @section Debug commands
3329 @cindex Debug commands
3330 The following commands give direct access to the core, and are most likely
3331 only useful while debugging OpenOCD.
3333 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
3334 @cindex arm7_9 write_xpsr
3335 @*Immediately write either the current program status register (CPSR) or the saved
3336 program status register (SPSR), without changing the register cache (as displayed
3337 by the @option{reg} and @option{armv4_5 reg} commands).
3338 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
3339 <@var{0=cpsr},@var{1=spsr}>
3340 @cindex arm7_9 write_xpsr_im8
3341 @*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
3342 operation (similar to @option{write_xpsr}).
3343 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
3344 @cindex arm7_9 write_core_reg
3345 @*Write a core register, without changing the register cache (as displayed by the
3346 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
3347 encoding of the [M4:M0] bits of the PSR.
3350 @section Target Requests
3351 @cindex Target Requests
3352 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
3353 See libdcc in the contrib dir for more details.
3355 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}|@var{charmsg}>
3356 @cindex target_request debugmsgs
3357 @*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running. @var{charmsg} receives messages if Linux kernel ``Kernel low-level debugging via EmbeddedICE DCC channel'' option is enabled.
3361 @chapter JTAG Commands
3362 @cindex JTAG Commands
3363 Generally most people will not use the bulk of these commands. They
3364 are mostly used by the OpenOCD developers or those who need to
3365 directly manipulate the JTAG taps.
3367 In general these commands control JTAG taps at a very low level. For
3368 example if you need to control a JTAG Route Controller (i.e.: the
3369 OMAP3530 on the Beagle Board has one) you might use these commands in
3370 a script or an event procedure.
3374 @item @b{scan_chain}
3376 @*Print current scan chain configuration.
3377 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
3379 @*Toggle reset lines.
3380 @item @b{endstate} <@var{tap_state}>
3382 @*Finish JTAG operations in <@var{tap_state}>.
3383 @item @b{runtest} <@var{num_cycles}>
3385 @*Move to Run-Test/Idle, and execute <@var{num_cycles}>
3386 @item @b{statemove} [@var{tap_state}]
3388 @*Move to current endstate or [@var{tap_state}]
3389 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
3391 @*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
3392 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
3394 @*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
3395 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
3396 @cindex verify_ircapture
3397 @*Verify value captured during Capture-IR. Default is enabled.
3398 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
3400 @*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
3401 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
3403 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
3408 Available tap_states are:
3448 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
3449 be used to access files on PCs (either the developer's PC or some other PC).
3451 The way this works on the ZY1000 is to prefix a filename by
3452 "/tftp/ip/" and append the TFTP path on the TFTP
3453 server (tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf" will
3454 load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
3455 if the file was hosted on the embedded host.
3457 In order to achieve decent performance, you must choose a TFTP server
3458 that supports a packet size bigger than the default packet size (512 bytes). There
3459 are numerous TFTP servers out there (free and commercial) and you will have to do
3460 a bit of googling to find something that fits your requirements.
3462 @node Sample Scripts
3463 @chapter Sample Scripts
3466 This page shows how to use the Target Library.
3468 The configuration script can be divided into the following sections:
3470 @item Daemon configuration
3472 @item JTAG scan chain
3473 @item Target configuration
3474 @item Flash configuration
3477 Detailed information about each section can be found at OpenOCD configuration.
3479 @section AT91R40008 example
3480 @cindex AT91R40008 example
3481 To start OpenOCD with a target script for the AT91R40008 CPU and reset
3482 the CPU upon startup of the OpenOCD daemon.
3484 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
3488 @node GDB and OpenOCD
3489 @chapter GDB and OpenOCD
3491 OpenOCD complies with the remote gdbserver protocol, and as such can be used
3492 to debug remote targets.
3494 @section Connecting to GDB
3495 @cindex Connecting to GDB
3496 @anchor{Connecting to GDB}
3497 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
3498 instance GDB 6.3 has a known bug that produces bogus memory access
3499 errors, which has since been fixed: look up 1836 in
3500 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
3502 @*OpenOCD can communicate with GDB in two ways:
3505 A socket (TCP/IP) connection is typically started as follows:
3507 target remote localhost:3333
3509 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
3511 A pipe connection is typically started as follows:
3513 target remote | openocd --pipe
3515 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
3516 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
3520 @*To see a list of available OpenOCD commands type @option{monitor help} on the
3523 OpenOCD supports the gdb @option{qSupported} packet, this enables information
3524 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
3525 packet size and the device's memory map.
3527 Previous versions of OpenOCD required the following GDB options to increase
3528 the packet size and speed up GDB communication:
3530 set remote memory-write-packet-size 1024
3531 set remote memory-write-packet-size fixed
3532 set remote memory-read-packet-size 1024
3533 set remote memory-read-packet-size fixed
3535 This is now handled in the @option{qSupported} PacketSize and should not be required.
3537 @section Programming using GDB
3538 @cindex Programming using GDB
3540 By default the target memory map is sent to GDB. This can be disabled by
3541 the following OpenOCD configuration option:
3543 gdb_memory_map disable
3545 For this to function correctly a valid flash configuration must also be set
3546 in OpenOCD. For faster performance you should also configure a valid
3549 Informing GDB of the memory map of the target will enable GDB to protect any
3550 flash areas of the target and use hardware breakpoints by default. This means
3551 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
3552 using a memory map. @xref{gdb_breakpoint_override}.
3554 To view the configured memory map in GDB, use the GDB command @option{info mem}
3555 All other unassigned addresses within GDB are treated as RAM.
3557 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
3558 This can be changed to the old behaviour by using the following GDB command
3560 set mem inaccessible-by-default off
3563 If @command{gdb_flash_program enable} is also used, GDB will be able to
3564 program any flash memory using the vFlash interface.
3566 GDB will look at the target memory map when a load command is given, if any
3567 areas to be programmed lie within the target flash area the vFlash packets
3570 If the target needs configuring before GDB programming, an event
3571 script can be executed:
3573 $_TARGETNAME configure -event EVENTNAME BODY
3576 To verify any flash programming the GDB command @option{compare-sections}
3579 @node Tcl Scripting API
3580 @chapter Tcl Scripting API
3581 @cindex Tcl Scripting API
3585 The commands are stateless. E.g. the telnet command line has a concept
3586 of currently active target, the Tcl API proc's take this sort of state
3587 information as an argument to each proc.
3589 There are three main types of return values: single value, name value
3590 pair list and lists.
3592 Name value pair. The proc 'foo' below returns a name/value pair
3598 > set foo(you) Oyvind
3599 > set foo(mouse) Micky
3600 > set foo(duck) Donald
3608 me Duane you Oyvind mouse Micky duck Donald
3610 Thus, to get the names of the associative array is easy:
3612 foreach { name value } [set foo] {
3613 puts "Name: $name, Value: $value"
3617 Lists returned must be relatively small. Otherwise a range
3618 should be passed in to the proc in question.
3620 @section Internal low-level Commands
3622 By low-level, the intent is a human would not directly use these commands.
3624 Low-level commands are (should be) prefixed with "openocd_", e.g. openocd_flash_banks
3625 is the low level API upon which "flash banks" is implemented.
3628 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
3630 Read memory and return as a Tcl array for script processing
3631 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
3633 Convert a Tcl array to memory locations and write the values
3634 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
3636 Return information about the flash banks
3639 OpenOCD commands can consist of two words, e.g. "flash banks". The
3640 startup.tcl "unknown" proc will translate this into a Tcl proc
3641 called "flash_banks".
3643 @section OpenOCD specific Global Variables
3647 Real Tcl has ::tcl_platform(), and platform::identify, and many other
3648 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
3649 holds one of the following values:
3652 @item @b{winxx} Built using Microsoft Visual Studio
3653 @item @b{linux} Linux is the underlying operating sytem
3654 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
3655 @item @b{cygwin} Running under Cygwin
3656 @item @b{mingw32} Running under MingW32
3657 @item @b{other} Unknown, none of the above.
3660 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
3663 @chapter Deprecated/Removed Commands
3664 @cindex Deprecated/Removed Commands
3665 Certain OpenOCD commands have been deprecated/removed during the various revisions.
3668 @item @b{arm7_9 fast_writes}
3669 @cindex arm7_9 fast_writes
3670 @*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}.
3671 @item @b{arm7_9 force_hw_bkpts}
3672 @cindex arm7_9 force_hw_bkpts
3673 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
3674 for flash if the GDB memory map has been set up(default when flash is declared in
3675 target configuration). @xref{gdb_breakpoint_override}.
3676 @item @b{arm7_9 sw_bkpts}
3677 @cindex arm7_9 sw_bkpts
3678 @*On by default. @xref{gdb_breakpoint_override}.
3679 @item @b{daemon_startup}
3680 @cindex daemon_startup
3681 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
3682 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
3683 and @option{target cortex_m3 little reset_halt 0}.
3684 @item @b{dump_binary}
3686 @*use @option{dump_image} command with same args. @xref{dump_image}.
3687 @item @b{flash erase}
3689 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
3690 @item @b{flash write}
3692 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
3693 @item @b{flash write_binary}
3694 @cindex flash write_binary
3695 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
3696 @item @b{flash auto_erase}
3697 @cindex flash auto_erase
3698 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
3699 @item @b{load_binary}
3701 @*use @option{load_image} command with same args. @xref{load_image}.
3702 @item @b{run_and_halt_time}
3703 @cindex run_and_halt_time
3704 @*This command has been removed for simpler reset behaviour, it can be simulated with the
3711 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
3713 @*use the create subcommand of @option{target}.
3714 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
3715 @cindex target_script
3716 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
3717 @item @b{working_area}
3718 @cindex working_area
3719 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
3726 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
3728 @cindex adaptive clocking
3731 In digital circuit design it is often refered to as ``clock
3732 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
3733 operating at some speed, your target is operating at another. The two
3734 clocks are not synchronised, they are ``asynchronous''
3736 In order for the two to work together they must be synchronised. Otherwise
3737 the two systems will get out of sync with each other and nothing will
3738 work. There are 2 basic options:
3741 Use a special circuit.
3743 One clock must be some multiple slower than the other.
3746 @b{Does this really matter?} For some chips and some situations, this
3747 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
3748 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
3749 program/enable the oscillators and eventually the main clock. It is in
3750 those critical times you must slow the JTAG clock to sometimes 1 to
3753 Imagine debugging a 500MHz ARM926 hand held battery powered device
3754 that ``deep sleeps'' at 32kHz between every keystroke. It can be
3757 @b{Solution #1 - A special circuit}
3759 In order to make use of this, your JTAG dongle must support the RTCK
3760 feature. Not all dongles support this - keep reading!
3762 The RTCK signal often found in some ARM chips is used to help with
3763 this problem. ARM has a good description of the problem described at
3764 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
3765 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
3766 work? / how does adaptive clocking work?''.
3768 The nice thing about adaptive clocking is that ``battery powered hand
3769 held device example'' - the adaptiveness works perfectly all the
3770 time. One can set a break point or halt the system in the deep power
3771 down code, slow step out until the system speeds up.
3773 @b{Solution #2 - Always works - but may be slower}
3775 Often this is a perfectly acceptable solution.
3777 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
3778 the target clock speed. But what that ``magic division'' is varies
3779 depending on the chips on your board. @b{ARM rule of thumb} Most ARM
3780 based systems require an 8:1 division. @b{Xilinx rule of thumb} is
3781 1/12 the clock speed.
3783 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
3785 You can still debug the 'low power' situations - you just need to
3786 manually adjust the clock speed at every step. While painful and
3787 tedious, it is not always practical.
3789 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
3790 have a special debug mode in your application that does a ``high power
3791 sleep''. If you are careful - 98% of your problems can be debugged
3794 To set the JTAG frequency use the command:
3802 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
3804 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
3805 around Windows filenames.
3818 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
3820 Make sure you have Cygwin installed, or at least a version of OpenOCD that
3821 claims to come with all the necessary DLLs. When using Cygwin, try launching
3822 OpenOCD from the Cygwin shell.
3824 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
3825 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
3826 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
3828 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
3829 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
3830 software breakpoints consume one of the two available hardware breakpoints.
3832 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
3834 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
3835 clock at the time you're programming the flash. If you've specified the crystal's
3836 frequency, make sure the PLL is disabled. If you've specified the full core speed
3837 (e.g. 60MHz), make sure the PLL is enabled.
3839 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
3840 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
3841 out while waiting for end of scan, rtck was disabled".
3843 Make sure your PC's parallel port operates in EPP mode. You might have to try several
3844 settings in your PC BIOS (ECP, EPP, and different versions of those).
3846 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
3847 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
3848 memory read caused data abort".
3850 The errors are non-fatal, and are the result of GDB trying to trace stack frames
3851 beyond the last valid frame. It might be possible to prevent this by setting up
3852 a proper "initial" stack frame, if you happen to know what exactly has to
3853 be done, feel free to add this here.
3855 @b{Simple:} In your startup code - push 8 registers of zeros onto the
3856 stack before calling main(). What GDB is doing is ``climbing'' the run
3857 time stack by reading various values on the stack using the standard
3858 call frame for the target. GDB keeps going - until one of 2 things
3859 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
3860 stackframes have been processed. By pushing zeros on the stack, GDB
3863 @b{Debugging Interrupt Service Routines} - In your ISR before you call
3864 your C code, do the same - artifically push some zeros onto the stack,
3865 remember to pop them off when the ISR is done.
3867 @b{Also note:} If you have a multi-threaded operating system, they
3868 often do not @b{in the intrest of saving memory} waste these few
3872 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
3873 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
3875 This warning doesn't indicate any serious problem, as long as you don't want to
3876 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
3877 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
3878 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
3879 independently. With this setup, it's not possible to halt the core right out of
3880 reset, everything else should work fine.
3882 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
3883 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
3884 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
3885 quit with an error message. Is there a stability issue with OpenOCD?
3887 No, this is not a stability issue concerning OpenOCD. Most users have solved
3888 this issue by simply using a self-powered USB hub, which they connect their
3889 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
3890 supply stable enough for the Amontec JTAGkey to be operated.
3892 @b{Laptops running on battery have this problem too...}
3894 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
3895 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
3896 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
3897 What does that mean and what might be the reason for this?
3899 First of all, the reason might be the USB power supply. Try using a self-powered
3900 hub instead of a direct connection to your computer. Secondly, the error code 4
3901 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
3902 chip ran into some sort of error - this points us to a USB problem.
3904 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
3905 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
3906 What does that mean and what might be the reason for this?
3908 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
3909 has closed the connection to OpenOCD. This might be a GDB issue.
3911 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
3912 are described, there is a parameter for specifying the clock frequency
3913 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
3914 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
3915 specified in kilohertz. However, I do have a quartz crystal of a
3916 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
3917 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
3920 No. The clock frequency specified here must be given as an integral number.
3921 However, this clock frequency is used by the In-Application-Programming (IAP)
3922 routines of the LPC2000 family only, which seems to be very tolerant concerning
3923 the given clock frequency, so a slight difference between the specified clock
3924 frequency and the actual clock frequency will not cause any trouble.
3926 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
3928 Well, yes and no. Commands can be given in arbitrary order, yet the
3929 devices listed for the JTAG scan chain must be given in the right
3930 order (jtag newdevice), with the device closest to the TDO-Pin being
3931 listed first. In general, whenever objects of the same type exist
3932 which require an index number, then these objects must be given in the
3933 right order (jtag newtap, targets and flash banks - a target
3934 references a jtag newtap and a flash bank references a target).
3936 You can use the ``scan_chain'' command to verify and display the tap order.
3938 Also, some commands can't execute until after @command{init} has been
3939 processed. Such commands include @command{nand probe} and everything
3940 else that needs to write to controller registers, perhaps for setting
3941 up DRAM and loading it with code.
3943 @item @b{JTAG Tap Order} JTAG tap order - command order
3945 Many newer devices have multiple JTAG taps. For example: ST
3946 Microsystems STM32 chips have two taps, a ``boundary scan tap'' and
3947 ``Cortex-M3'' tap. Example: The STM32 reference manual, Document ID:
3948 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
3949 connected to the boundary scan tap, which then connects to the
3950 Cortex-M3 tap, which then connects to the TDO pin.
3952 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
3953 (2) The boundary scan tap. If your board includes an additional JTAG
3954 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
3955 place it before or after the STM32 chip in the chain. For example:
3958 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
3959 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
3960 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
3961 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
3962 @item Xilinx TDO Pin -> OpenOCD TDO (input)
3965 The ``jtag device'' commands would thus be in the order shown below. Note:
3968 @item jtag newtap Xilinx tap -irlen ...
3969 @item jtag newtap stm32 cpu -irlen ...
3970 @item jtag newtap stm32 bs -irlen ...
3971 @item # Create the debug target and say where it is
3972 @item target create stm32.cpu -chain-position stm32.cpu ...
3976 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
3977 log file, I can see these error messages: Error: arm7_9_common.c:561
3978 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
3984 @node Tcl Crash Course
3985 @chapter Tcl Crash Course
3988 Not everyone knows Tcl - this is not intended to be a replacement for
3989 learning Tcl, the intent of this chapter is to give you some idea of
3990 how the Tcl scripts work.
3992 This chapter is written with two audiences in mind. (1) OpenOCD users
3993 who need to understand a bit more of how JIM-Tcl works so they can do
3994 something useful, and (2) those that want to add a new command to
3997 @section Tcl Rule #1
3998 There is a famous joke, it goes like this:
4000 @item Rule #1: The wife is always correct
4001 @item Rule #2: If you think otherwise, See Rule #1
4004 The Tcl equal is this:
4007 @item Rule #1: Everything is a string
4008 @item Rule #2: If you think otherwise, See Rule #1
4011 As in the famous joke, the consequences of Rule #1 are profound. Once
4012 you understand Rule #1, you will understand Tcl.
4014 @section Tcl Rule #1b
4015 There is a second pair of rules.
4017 @item Rule #1: Control flow does not exist. Only commands
4018 @* For example: the classic FOR loop or IF statement is not a control
4019 flow item, they are commands, there is no such thing as control flow
4021 @item Rule #2: If you think otherwise, See Rule #1
4022 @* Actually what happens is this: There are commands that by
4023 convention, act like control flow key words in other languages. One of
4024 those commands is the word ``for'', another command is ``if''.
4027 @section Per Rule #1 - All Results are strings
4028 Every Tcl command results in a string. The word ``result'' is used
4029 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
4030 Everything is a string}
4032 @section Tcl Quoting Operators
4033 In life of a Tcl script, there are two important periods of time, the
4034 difference is subtle.
4037 @item Evaluation Time
4040 The two key items here are how ``quoted things'' work in Tcl. Tcl has
4041 three primary quoting constructs, the [square-brackets] the
4042 @{curly-braces@} and ``double-quotes''
4044 By now you should know $VARIABLES always start with a $DOLLAR
4045 sign. BTW: To set a variable, you actually use the command ``set'', as
4046 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
4047 = 1'' statement, but without the equal sign.
4050 @item @b{[square-brackets]}
4051 @* @b{[square-brackets]} are command substitutions. It operates much
4052 like Unix Shell `back-ticks`. The result of a [square-bracket]
4053 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
4054 string}. These two statements are roughly identical:
4058 echo "The Date is: $X"
4061 puts "The Date is: $X"
4063 @item @b{``double-quoted-things''}
4064 @* @b{``double-quoted-things''} are just simply quoted
4065 text. $VARIABLES and [square-brackets] are expanded in place - the
4066 result however is exactly 1 string. @i{Remember Rule #1 - Everything
4070 puts "It is now \"[date]\", $x is in 1 hour"
4072 @item @b{@{Curly-Braces@}}
4073 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
4074 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
4075 'single-quote' operators in BASH shell scripts, with the added
4076 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
4077 nested 3 times@}@}@} NOTE: [date] is perhaps a bad example, as of
4078 28/nov/2008, Jim/OpenOCD does not have a date command.
4081 @section Consequences of Rule 1/2/3/4
4083 The consequences of Rule 1 are profound.
4085 @subsection Tokenisation & Execution.
4087 Of course, whitespace, blank lines and #comment lines are handled in
4090 As a script is parsed, each (multi) line in the script file is
4091 tokenised and according to the quoting rules. After tokenisation, that
4092 line is immedatly executed.
4094 Multi line statements end with one or more ``still-open''
4095 @{curly-braces@} which - eventually - closes a few lines later.
4097 @subsection Command Execution
4099 Remember earlier: There are no ``control flow''
4100 statements in Tcl. Instead there are COMMANDS that simply act like
4101 control flow operators.
4103 Commands are executed like this:
4106 @item Parse the next line into (argc) and (argv[]).
4107 @item Look up (argv[0]) in a table and call its function.
4108 @item Repeat until End Of File.
4111 It sort of works like this:
4114 ReadAndParse( &argc, &argv );
4116 cmdPtr = LookupCommand( argv[0] );
4118 (*cmdPtr->Execute)( argc, argv );
4122 When the command ``proc'' is parsed (which creates a procedure
4123 function) it gets 3 parameters on the command line. @b{1} the name of
4124 the proc (function), @b{2} the list of parameters, and @b{3} the body
4125 of the function. Not the choice of words: LIST and BODY. The PROC
4126 command stores these items in a table somewhere so it can be found by
4129 @subsection The FOR command
4131 The most interesting command to look at is the FOR command. In Tcl,
4132 the FOR command is normally implemented in C. Remember, FOR is a
4133 command just like any other command.
4135 When the ascii text containing the FOR command is parsed, the parser
4136 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
4140 @item The ascii text 'for'
4141 @item The start text
4142 @item The test expression
4147 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
4148 Remember @i{Rule #1 - Everything is a string.} The key point is this:
4149 Often many of those parameters are in @{curly-braces@} - thus the
4150 variables inside are not expanded or replaced until later.
4152 Remember that every Tcl command looks like the classic ``main( argc,
4153 argv )'' function in C. In JimTCL - they actually look like this:
4157 MyCommand( Jim_Interp *interp,
4159 Jim_Obj * const *argvs );
4162 Real Tcl is nearly identical. Although the newer versions have
4163 introduced a byte-code parser and intepreter, but at the core, it
4164 still operates in the same basic way.
4166 @subsection FOR command implementation
4168 To understand Tcl it is perhaps most helpful to see the FOR
4169 command. Remember, it is a COMMAND not a control flow structure.
4171 In Tcl there are two underlying C helper functions.
4173 Remember Rule #1 - You are a string.
4175 The @b{first} helper parses and executes commands found in an ascii
4176 string. Commands can be seperated by semicolons, or newlines. While
4177 parsing, variables are expanded via the quoting rules.
4179 The @b{second} helper evaluates an ascii string as a numerical
4180 expression and returns a value.
4182 Here is an example of how the @b{FOR} command could be
4183 implemented. The pseudo code below does not show error handling.
4185 void Execute_AsciiString( void *interp, const char *string );
4187 int Evaluate_AsciiExpression( void *interp, const char *string );
4190 MyForCommand( void *interp,
4195 SetResult( interp, "WRONG number of parameters");
4199 // argv[0] = the ascii string just like C
4201 // Execute the start statement.
4202 Execute_AsciiString( interp, argv[1] );
4206 i = Evaluate_AsciiExpression(interp, argv[2]);
4211 Execute_AsciiString( interp, argv[3] );
4213 // Execute the LOOP part
4214 Execute_AsciiString( interp, argv[4] );
4218 SetResult( interp, "" );
4223 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
4224 in the same basic way.
4226 @section OpenOCD Tcl Usage
4228 @subsection source and find commands
4229 @b{Where:} In many configuration files
4230 @* Example: @b{ source [find FILENAME] }
4231 @*Remember the parsing rules
4233 @item The FIND command is in square brackets.
4234 @* The FIND command is executed with the parameter FILENAME. It should
4235 find the full path to the named file. The RESULT is a string, which is
4236 substituted on the orginal command line.
4237 @item The command source is executed with the resulting filename.
4238 @* SOURCE reads a file and executes as a script.
4240 @subsection format command
4241 @b{Where:} Generally occurs in numerous places.
4242 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
4248 puts [format "The answer: %d" [expr $x * $y]]
4251 @item The SET command creates 2 variables, X and Y.
4252 @item The double [nested] EXPR command performs math
4253 @* The EXPR command produces numerical result as a string.
4255 @item The format command is executed, producing a single string
4256 @* Refer to Rule #1.
4257 @item The PUTS command outputs the text.
4259 @subsection Body or Inlined Text
4260 @b{Where:} Various TARGET scripts.
4263 proc someproc @{@} @{
4264 ... multiple lines of stuff ...
4266 $_TARGETNAME configure -event FOO someproc
4267 #2 Good - no variables
4268 $_TARGETNAME confgure -event foo "this ; that;"
4269 #3 Good Curly Braces
4270 $_TARGETNAME configure -event FOO @{
4273 #4 DANGER DANGER DANGER
4274 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
4277 @item The $_TARGETNAME is an OpenOCD variable convention.
4278 @*@b{$_TARGETNAME} represents the last target created, the value changes
4279 each time a new target is created. Remember the parsing rules. When
4280 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
4281 the name of the target which happens to be a TARGET (object)
4283 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
4284 @*There are 4 examples:
4286 @item The TCLBODY is a simple string that happens to be a proc name
4287 @item The TCLBODY is several simple commands seperated by semicolons
4288 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
4289 @item The TCLBODY is a string with variables that get expanded.
4292 In the end, when the target event FOO occurs the TCLBODY is
4293 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
4294 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
4296 Remember the parsing rules. In case #3, @{curly-braces@} mean the
4297 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
4298 and the text is evaluated. In case #4, they are replaced before the
4299 ``Target Object Command'' is executed. This occurs at the same time
4300 $_TARGETNAME is replaced. In case #4 the date will never
4301 change. @{BTW: [date] is perhaps a bad example, as of 28/nov/2008,
4302 Jim/OpenOCD does not have a date command@}
4304 @subsection Global Variables
4305 @b{Where:} You might discover this when writing your own procs @* In
4306 simple terms: Inside a PROC, if you need to access a global variable
4307 you must say so. See also ``upvar''. Example:
4309 proc myproc @{ @} @{
4310 set y 0 #Local variable Y
4311 global x #Global variable X
4312 puts [format "X=%d, Y=%d" $x $y]
4315 @section Other Tcl Hacks
4316 @b{Dynamic variable creation}
4318 # Dynamically create a bunch of variables.
4319 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
4321 set vn [format "BIT%d" $x]
4325 set $vn [expr (1 << $x)]
4328 @b{Dynamic proc/command creation}
4330 # One "X" function - 5 uart functions.
4331 foreach who @{A B C D E@}
4332 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
4336 @node Target Library
4337 @chapter Target Library
4338 @cindex Target Library
4340 OpenOCD comes with a target configuration script library. These scripts can be
4341 used as-is or serve as a starting point.
4343 The target library is published together with the OpenOCD executable and
4344 the path to the target library is in the OpenOCD script search path.
4345 Similarly there are example scripts for configuring the JTAG interface.
4347 The command line below uses the example parport configuration script
4348 that ship with OpenOCD, then configures the str710.cfg target and
4349 finally issues the init and reset commands. The communication speed
4350 is set to 10kHz for reset and 8MHz for post reset.
4353 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
4356 To list the target scripts available:
4359 $ ls /usr/local/lib/openocd/target
4361 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
4362 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
4363 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
4364 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
4369 @node OpenOCD Concept Index
4370 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
4371 @comment case issue with ``Index.html'' and ``index.html''
4372 @comment Occurs when creating ``--html --no-split'' output
4373 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
4374 @unnumbered OpenOCD Concept Index
4378 @node OpenOCD Command Index
4379 @unnumbered OpenOCD Command Index