1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
8 * OpenOCD: (openocd). Open On-Chip Debugger.
17 @item Copyright @copyright{} 2008 The OpenOCD Project
18 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
19 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
20 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
24 Permission is granted to copy, distribute and/or modify this document
25 under the terms of the GNU Free Documentation License, Version 1.2 or
26 any later version published by the Free Software Foundation; with no
27 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
28 Texts. A copy of the license is included in the section entitled ``GNU
29 Free Documentation License''.
34 @title Open On-Chip Debugger (OpenOCD)
35 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
36 @subtitle @value{UPDATED}
38 @vskip 0pt plus 1filll
45 @node Top, About, , (dir)
48 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
49 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
54 * About:: About OpenOCD
55 * Developers:: OpenOCD Developers
56 * Building:: Building OpenOCD
57 * JTAG Hardware Dongles:: JTAG Hardware Dongles
58 * Running:: Running OpenOCD
59 * Simple Configuration Files:: Simple Configuration Files
60 * Config File Guidelines:: Config File Guidelines
61 * About JIM-Tcl:: About JIM-Tcl
62 * Daemon Configuration:: Daemon Configuration
63 * Interface - Dongle Configuration:: Interface - Dongle Configuration
64 * Reset Configuration:: Reset Configuration
65 * Tap Creation:: Tap Creation
66 * Target Configuration:: Target Configuration
67 * Flash Configuration:: Flash Configuration
68 * NAND Flash Commands:: NAND Flash Commands
69 * General Commands:: General Commands
70 * JTAG Commands:: JTAG Commands
71 * Sample Scripts:: Sample Target Scripts
73 * GDB and OpenOCD:: Using GDB and OpenOCD
74 * Tcl Scripting API:: Tcl Scripting API
75 * Upgrading:: Deprecated/Removed Commands
76 * Target Library:: Target Library
77 * FAQ:: Frequently Asked Questions
78 * Tcl Crash Course:: Tcl Crash Course
79 * License:: GNU Free Documentation License
80 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
81 @comment case issue with ``Index.html'' and ``index.html''
82 @comment Occurs when creating ``--html --no-split'' output
83 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
84 * OpenOCD Concept Index:: Concept Index
85 * OpenOCD Command Index:: Command Index
92 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
93 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
94 Since that time, the project has grown into an active open-source project,
95 supported by a diverse community of software and hardware developers from
98 @section What is OpenOCD?
100 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
101 in-system programming and boundary-scan testing for embedded target
104 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
105 with the JTAG (IEEE 1149.1) compliant taps on your target board.
107 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
108 based, parallel port based, and other standalone boxes that run
109 OpenOCD internally. @xref{JTAG Hardware Dongles}.
111 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
112 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
113 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be
114 debugged via the GDB protocol.
116 @b{Flash Programing:} Flash writing is supported for external CFI
117 compatible NOR flashes (Intel and AMD/Spansion command set) and several
118 internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3, and
119 STM32x). Preliminary support for various NAND flash controllers
120 (LPC3180, Orion, S3C24xx, more) controller is included.
122 @section OpenOCD Web Site
124 The OpenOCD web site provides the latest public news from the community:
126 @uref{http://openocd.berlios.de/web/}
130 @chapter OpenOCD Developer Resources
133 If you are interested in improving the state of OpenOCD's debugging and
134 testing support, new contributions will be welcome. Motivated developers
135 can produce new target, flash or interface drivers, improve the
136 documentation, as well as more conventional bug fixes and enhancements.
138 The resources in this chapter are available for developers wishing to explore
139 or expand the OpenOCD source code.
141 @section OpenOCD Subversion Repository
143 The ``Building From Source'' section (@xref{Building}) provides
144 instructions to retrieve and and build the latest version of the OpenOCD
147 Developers that want to contribute patches to the OpenOCD system are
148 @b{strongly} encouraged to base their work off of the most recent trunk
149 revision. Patches created against older versions may require additional
150 work from their submitter in order to be updated for newer releases.
152 @section Doxygen Developer Manual
154 During the development of the 0.2.0 release, the OpenOCD project began
155 providing a Doxygen reference manual. This document contains more
156 technical information about the software internals, development
157 processes, and similar documentation:
159 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
161 This document is a work-in-progress, but contributions would be welcome
162 to fill in the gaps. All of the source files are provided in-tree,
163 listed in the Doxyfile configuration in the top of the repository trunk.
165 @section OpenOCD Developer Mailing List
167 The OpenOCD Developer Mailing List provides the primary means of
168 communication between developers:
170 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
172 All drivers developers are enouraged to also subscribe to the list of
173 SVN commits to keep pace with the ongoing changes:
175 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
178 @chapter Building OpenOCD
181 @section Pre-Built Tools
182 If you are interested in getting actual work done rather than building
183 OpenOCD, then check if your interface supplier provides binaries for
184 you. Chances are that that binary is from some SVN version that is more
185 stable than SVN trunk where bleeding edge development takes place.
187 @section Packagers Please Read!
189 You are a @b{PACKAGER} of OpenOCD if you
192 @item @b{Sell dongles} and include pre-built binaries
193 @item @b{Supply tools} i.e.: A complete development solution
194 @item @b{Supply IDEs} like Eclipse, or RHIDE, etc.
195 @item @b{Build packages} i.e.: RPM files, or DEB files for a Linux Distro
198 As a @b{PACKAGER}, you will experience first reports of most issues.
199 When you fix those problems for your users, your solution may help
200 prevent hundreds (if not thousands) of other questions from other users.
202 If something does not work for you, please work to inform the OpenOCD
203 developers know how to improve the system or documentation to avoid
204 future problems, and follow-up to help us ensure the issue will be fully
205 resolved in our future releases.
207 That said, the OpenOCD developers would also like you to follow a few
211 @item @b{Always build with printer ports enabled.}
212 @item @b{Try to use LIBFTDI + LIBUSB where possible. You cover more bases.}
216 @item @b{Why YES to LIBFTDI + LIBUSB?}
218 @item @b{LESS} work - libusb perhaps already there
219 @item @b{LESS} work - identical code, multiple platforms
220 @item @b{MORE} dongles are supported
221 @item @b{MORE} platforms are supported
222 @item @b{MORE} complete solution
224 @item @b{Why not LIBFTDI + LIBUSB} (i.e.: ftd2xx instead)?
226 @item @b{LESS} speed - some say it is slower
227 @item @b{LESS} complex to distribute (external dependencies)
231 @section Building From Source
233 You can download the current SVN version with an SVN client of your choice from the
234 following repositories:
236 @uref{svn://svn.berlios.de/openocd/trunk}
240 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
242 Using the SVN command line client, you can use the following command to fetch the
243 latest version (make sure there is no (non-svn) directory called "openocd" in the
247 svn checkout svn://svn.berlios.de/openocd/trunk openocd
250 Building OpenOCD requires a recent version of the GNU autotools (autoconf >= 2.59 and automake >= 1.9).
251 For building on Windows,
252 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
253 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
254 paths, resulting in obscure dependency errors (This is an observation I've gathered
255 from the logs of one user - correct me if I'm wrong).
257 You further need the appropriate driver files, if you want to build support for
258 a FTDI FT2232 based interface:
261 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
262 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
263 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
264 homepage (@uref{http://www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
267 libftdi is supported under Windows. Do not use versions earlier than 0.14.
269 In general, the D2XX driver provides superior performance (several times as fast),
270 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
271 a kernel module, only a user space library.
273 To build OpenOCD (on both Linux and Cygwin), use the following commands:
279 Bootstrap generates the configure script, and prepares building on your system.
282 ./configure [options, see below]
285 Configure generates the Makefiles used to build OpenOCD.
292 Make builds OpenOCD, and places the final executable in ./src/, the last step, ``make install'' is optional.
294 The configure script takes several options, specifying which JTAG interfaces
295 should be included (among other things):
299 @option{--enable-parport} - Enable building the PC parallel port driver.
301 @option{--enable-parport_ppdev} - Enable use of ppdev (/dev/parportN) for parport.
303 @option{--enable-parport_giveio} - Enable use of giveio for parport instead of ioperm.
305 @option{--enable-amtjtagaccel} - Enable building the Amontec JTAG-Accelerator driver.
307 @option{--enable-ecosboard} - Enable building support for eCosBoard based JTAG debugger.
309 @option{--enable-ioutil} - Enable ioutil functions - useful for standalone OpenOCD implementations.
311 @option{--enable-httpd} - Enable builtin httpd server - useful for standalone OpenOCD implementations.
313 @option{--enable-ep93xx} - Enable building support for EP93xx based SBCs.
315 @option{--enable-at91rm9200} - Enable building support for AT91RM9200 based SBCs.
317 @option{--enable-gw16012} - Enable building support for the Gateworks GW16012 JTAG programmer.
319 @option{--enable-ft2232_ftd2xx} - Numerous USB type ARM JTAG dongles use the FT2232C chip from this FTDICHIP.COM chip (closed source).
321 @option{--enable-ft2232_libftdi} - An open source (free) alternative to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin).
323 @option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c, point at the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
325 @option{--with-ftd2xx-linux-tardir=PATH} - Linux only. Equivalent of @option{--with-ftd2xx-win32-zipdir}, where you unpacked the TAR.GZ file.
327 @option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static. Specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note: 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}. The 'shared' value is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.
329 @option{--enable-presto_libftdi} - Enable building support for ASIX Presto programmer using the libftdi driver.
331 @option{--enable-presto_ftd2xx} - Enable building support for ASIX Presto programmer using the FTD2XX driver.
333 @option{--enable-usbprog} - Enable building support for the USBprog JTAG programmer.
335 @option{--enable-oocd_trace} - Enable building support for the OpenOCD+trace ETM capture device.
337 @option{--enable-jlink} - Enable building support for the Segger J-Link JTAG programmer.
339 @option{--enable-vsllink} - Enable building support for the Versaloon-Link JTAG programmer.
341 @option{--enable-rlink} - Enable building support for the Raisonance RLink JTAG programmer.
343 @option{--enable-arm-jtag-ew} - Enable building support for the Olimex ARM-JTAG-EW programmer.
345 @option{--enable-dummy} - Enable building the dummy port driver.
348 @section Parallel Port Dongles
350 If you want to access the parallel port using the PPDEV interface you have to specify
351 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
352 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
353 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
355 The same is true for the @option{--enable-parport_giveio} option, you have to
356 use both the @option{--enable-parport} AND the @option{--enable-parport_giveio} option if you want to use giveio instead of ioperm parallel port access method.
358 @section FT2232C Based USB Dongles
360 There are 2 methods of using the FTD2232, either (1) using the
361 FTDICHIP.COM closed source driver, or (2) the open (and free) driver
362 libftdi. Some claim the (closed) FTDICHIP.COM solution is faster.
364 The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux)
365 TAR.GZ file. You must unpack them ``some where'' convient. As of this
366 writing (12/26/2008) FTDICHIP does not supply means to install these
367 files ``in an appropriate place'' As a result, there are two
368 ``./configure'' options that help.
370 Below is an example build process:
372 1) Check out the latest version of ``openocd'' from SVN.
374 2) Download & unpack either the Windows or Linux FTD2xx drivers
375 (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
378 /home/duane/ftd2xx.win32 => the Cygwin/Win32 ZIP file contents.
379 /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents.
382 3) Configure with these options:
385 Cygwin FTDICHIP solution:
386 ./configure --prefix=/home/duane/mytools \
387 --enable-ft2232_ftd2xx \
388 --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
390 Linux FTDICHIP solution:
391 ./configure --prefix=/home/duane/mytools \
392 --enable-ft2232_ftd2xx \
393 --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
395 Cygwin/Linux LIBFTDI solution:
397 1a) For Windows: The Windows port of LIBUSB is in place.
398 1b) For Linux: libusb has been built/installed and is in place.
400 2) And libftdi has been built and installed
401 Note: libftdi - relies upon libusb.
403 ./configure --prefix=/home/duane/mytools \
404 --enable-ft2232_libftdi
408 4) Then just type ``make'', and perhaps ``make install''.
411 @section Miscellaneous Configure Options
415 @option{--disable-option-checking} - Ignore unrecognized @option{--enable} and @option{--with} options.
417 @option{--enable-gccwarnings} - Enable extra gcc warnings during build.
420 @option{--enable-release} - Enable building of an OpenOCD release, generally
421 this is for developers. It simply omits the svn version string when the
422 openocd @option{-v} is executed.
425 @node JTAG Hardware Dongles
426 @chapter JTAG Hardware Dongles
435 Defined: @b{dongle}: A small device that plugins into a computer and serves as
436 an adapter .... [snip]
438 In the OpenOCD case, this generally refers to @b{a small adapater} one
439 attaches to your computer via USB or the Parallel Printer Port. The
440 execption being the Zylin ZY1000 which is a small box you attach via
441 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
442 require any drivers to be installed on the developer PC. It also has
443 a built in web interface. It supports RTCK/RCLK or adaptive clocking
444 and has a built in relay to power cycle targets remotely.
447 @section Choosing a Dongle
449 There are three things you should keep in mind when choosing a dongle.
452 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
453 @item @b{Connection} Printer Ports - Does your computer have one?
454 @item @b{Connection} Is that long printer bit-bang cable practical?
455 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
458 @section Stand alone Systems
460 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
461 dongle, but a standalone box. The ZY1000 has the advantage that it does
462 not require any drivers installed on the developer PC. It also has
463 a built in web interface. It supports RTCK/RCLK or adaptive clocking
464 and has a built in relay to power cycle targets remotely.
466 @section USB FT2232 Based
468 There are many USB JTAG dongles on the market, many of them are based
469 on a chip from ``Future Technology Devices International'' (FTDI)
470 known as the FTDI FT2232.
472 See: @url{http://www.ftdichip.com} or @url{http://www.ftdichip.com/Products/FT2232H.htm}
474 As of 28/Nov/2008, the following are supported:
478 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
480 @* See: @url{http://www.amontec.com/jtagkey.shtml}
482 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
484 @* See: @url{http://www.signalyzer.com}
485 @item @b{evb_lm3s811}
486 @* See: @url{http://www.luminarymicro.com} - The Luminary Micro Stellaris LM3S811 eval board has an FTD2232C chip built in.
487 @item @b{olimex-jtag}
488 @* See: @url{http://www.olimex.com}
490 @* See: @url{http://www.tincantools.com}
491 @item @b{turtelizer2}
492 @* See: @url{http://www.ethernut.de}, or @url{http://www.ethernut.de/en/hardware/turtelizer/index.html}
494 @* Link: @url{http://www.hitex.com/index.php?id=383}
496 @* Link @url{http://www.hitex.com/stm32-stick}
497 @item @b{axm0432_jtag}
498 @* Axiom AXM-0432 Link @url{http://www.axman.com}
501 @section USB JLINK based
502 There are several OEM versions of the Segger @b{JLINK} adapter. It is
503 an example of a micro controller based JTAG adapter, it uses an
504 AT91SAM764 internally.
507 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
508 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
509 @item @b{SEGGER JLINK}
510 @* Link: @url{http://www.segger.com/jlink.html}
512 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
515 @section USB RLINK based
516 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
519 @item @b{Raisonance RLink}
520 @* Link: @url{http://www.raisonance.com/products/RLink.php}
521 @item @b{STM32 Primer}
522 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
523 @item @b{STM32 Primer2}
524 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
530 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
532 @item @b{USB - Presto}
533 @* Link: @url{http://tools.asix.net/prg_presto.htm}
535 @item @b{Versaloon-Link}
536 @* Link: @url{http://www.simonqian.com/en/Versaloon}
538 @item @b{ARM-JTAG-EW}
539 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
542 @section IBM PC Parallel Printer Port Based
544 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
545 and the MacGraigor Wiggler. There are many clones and variations of
550 @item @b{Wiggler} - There are many clones of this.
551 @* Link: @url{http://www.macraigor.com/wiggler.htm}
553 @item @b{DLC5} - From XILINX - There are many clones of this
554 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
555 produced, PDF schematics are easily found and it is easy to make.
557 @item @b{Amontec - JTAG Accelerator}
558 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
561 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
564 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
566 @item @b{Wiggler_ntrst_inverted}
567 @* Yet another variation - See the source code, src/jtag/parport.c
569 @item @b{old_amt_wiggler}
570 @* Unknown - probably not on the market today
573 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
576 @* Link: @url{http://www.amontec.com/chameleon.shtml}
582 @* ispDownload from Lattice Semiconductor @url{http://www.latticesemi.com/lit/docs/devtools/dlcable.pdf}
585 @* From ST Microsystems, link:
586 @url{http://www.st.com/stonline/products/literature/um/7889.pdf}
587 Title: FlashLINK JTAG programing cable for PSD and uPSD
595 @* An EP93xx based Linux machine using the GPIO pins directly.
598 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
604 @cindex running OpenOCD
606 @cindex --debug_level
610 The @option{--help} option shows:
614 --help | -h display this help
615 --version | -v display OpenOCD version
616 --file | -f use configuration file <name>
617 --search | -s dir to search for config files and scripts
618 --debug | -d set debug level <0-3>
619 --log_output | -l redirect log output to file <name>
620 --command | -c run <command>
621 --pipe | -p use pipes when talking to gdb
624 By default OpenOCD reads the file configuration file ``openocd.cfg''
625 in the current directory. To specify a different (or multiple)
626 configuration file, you can use the ``-f'' option. For example:
629 openocd -f config1.cfg -f config2.cfg -f config3.cfg
632 Once started, OpenOCD runs as a daemon, waiting for connections from
633 clients (Telnet, GDB, Other).
635 If you are having problems, you can enable internal debug messages via
638 Also it is possible to interleave commands w/config scripts using the
639 @option{-c} command line switch.
641 To enable debug output (when reporting problems or working on OpenOCD
642 itself), use the @option{-d} command line switch. This sets the
643 @option{debug_level} to "3", outputting the most information,
644 including debug messages. The default setting is "2", outputting only
645 informational messages, warnings and errors. You can also change this
646 setting from within a telnet or gdb session using @option{debug_level
647 <n>} @xref{debug_level}.
649 You can redirect all output from the daemon to a file using the
650 @option{-l <logfile>} switch.
652 Search paths for config/script files can be added to OpenOCD by using
653 the @option{-s <search>} switch. The current directory and the OpenOCD
654 target library is in the search path by default.
656 For details on the @option{-p} option. @xref{Connecting to GDB}.
658 Note! OpenOCD will launch the GDB & telnet server even if it can not
659 establish a connection with the target. In general, it is possible for
660 the JTAG controller to be unresponsive until the target is set up
661 correctly via e.g. GDB monitor commands in a GDB init script.
663 @node Simple Configuration Files
664 @chapter Simple Configuration Files
665 @cindex configuration
668 There are 4 basic ways of ``configurating'' OpenOCD to run, they are:
671 @item A small openocd.cfg file which ``sources'' other configuration files
672 @item A monolithic openocd.cfg file
673 @item Many -f filename options on the command line
674 @item Your Mixed Solution
677 @section Small configuration file method
679 This is the preferred method. It is simple and works well for many
680 people. The developers of OpenOCD would encourage you to use this
681 method. If you create a new configuration please email new
682 configurations to the development list.
684 Here is an example of an openocd.cfg file for an ATMEL at91sam7x256
687 source [find interface/signalyzer.cfg]
689 # Change the default telnet port...
693 # GDB can also flash my flash!
694 gdb_memory_map enable
695 gdb_flash_program enable
697 source [find target/sam7x256.cfg]
700 There are many example configuration scripts you can work with. You
701 should look in the directory: @t{$(INSTALLDIR)/lib/openocd}. You
705 @item @b{board} - eval board level configurations
706 @item @b{interface} - specific dongle configurations
707 @item @b{target} - the target chips
708 @item @b{tcl} - helper scripts
709 @item @b{xscale} - things specific to the xscale.
712 Look first in the ``boards'' area, then the ``targets'' area. Often a board
713 configuration is a good example to work from.
715 @section Many -f filename options
716 Some believe this is a wonderful solution, others find it painful.
718 You can use a series of ``-f filename'' options on the command line,
719 OpenOCD will read each filename in sequence, for example:
722 openocd -f file1.cfg -f file2.cfg -f file2.cfg
725 You can also intermix various commands with the ``-c'' command line
728 @section Monolithic file
729 The ``Monolithic File'' dispenses with all ``source'' statements and
730 puts everything in one self contained (monolithic) file. This is not
733 Please try to ``source'' various files or use the multiple -f
736 @section Advice for you
737 Often, one uses a ``mixed approach''. Where possible, please try to
738 ``source'' common things, and if needed cut/paste parts of the
739 standard distribution configuration files as needed.
741 @b{REMEMBER:} The ``important parts'' of your configuration file are:
744 @item @b{Interface} - Defines the dongle
745 @item @b{Taps} - Defines the JTAG Taps
746 @item @b{GDB Targets} - What GDB talks to
747 @item @b{Flash Programing} - Very Helpful
750 Some key things you should look at and understand are:
753 @item The reset configuration of your debug environment as a whole
754 @item Is there a ``work area'' that OpenOCD can use?
755 @* For ARM - work areas mean up to 10x faster downloads.
756 @item For MMU/MPU based ARM chips (i.e.: ARM9 and later) will that work area still be available?
757 @item For complex targets (multiple chips) the JTAG SPEED becomes an issue.
762 @node Config File Guidelines
763 @chapter Config File Guidelines
765 This section/chapter is aimed at developers and integrators of
766 OpenOCD. These are guidelines for creating new boards and new target
767 configurations as of 28/Nov/2008.
769 However, you, the user of OpenOCD, should be somewhat familiar with
770 this section as it should help explain some of the internals of what
771 you might be looking at.
773 The user should find the following directories under @t{$(INSTALLDIR)/lib/openocd} :
777 @*Think JTAG Dongle. Files that configure the JTAG dongle go here.
779 @* Think Circuit Board, PWA, PCB, they go by many names. Board files
780 contain initialization items that are specific to a board - for
781 example: The SDRAM initialization sequence for the board, or the type
782 of external flash and what address it is found at. Any initialization
783 sequence to enable that external flash or SDRAM should be found in the
784 board file. Boards may also contain multiple targets, i.e.: Two CPUs, or
785 a CPU and an FPGA or CPLD.
787 @* Think chip. The ``target'' directory represents a JTAG tap (or
788 chip) OpenOCD should control, not a board. Two common types of targets
789 are ARM chips and FPGA or CPLD chips.
792 @b{If needed...} The user in their ``openocd.cfg'' file or the board
793 file might override a specific feature in any of the above files by
794 setting a variable or two before sourcing the target file. Or adding
795 various commands specific to their situation.
797 @section Interface Config Files
799 The user should be able to source one of these files via a command like this:
802 source [find interface/FOOBAR.cfg]
804 openocd -f interface/FOOBAR.cfg
807 A preconfigured interface file should exist for every interface in use
808 today, that said, perhaps some interfaces have only been used by the
809 sole developer who created it.
811 @b{FIXME/NOTE:} We need to add support for a variable like Tcl variable
812 tcl_platform(platform), it should be called jim_platform (because it
813 is jim, not real tcl) and it should contain 1 of 3 words: ``linux'',
814 ``cygwin'' or ``mingw''
816 Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
818 @section Board Config Files
820 @b{Note: BOARD directory NEW as of 28/nov/2008}
822 The user should be able to source one of these files via a command like this:
825 source [find board/FOOBAR.cfg]
827 openocd -f board/FOOBAR.cfg
831 The board file should contain one or more @t{source [find
832 target/FOO.cfg]} statements along with any board specific things.
834 In summary the board files should contain (if present)
837 @item External flash configuration (i.e.: NOR flash on CS0, two NANDs on CS2)
838 @item SDRAM configuration (size, speed, etc.
839 @item Board specific IO configuration (i.e.: GPIO pins might disable a 2nd flash)
840 @item Multiple TARGET source statements
841 @item All things that are not ``inside a chip''
842 @item Things inside a chip go in a 'target' file
845 @section Target Config Files
847 The user should be able to source one of these files via a command like this:
850 source [find target/FOOBAR.cfg]
852 openocd -f target/FOOBAR.cfg
855 In summary the target files should contain
860 @item Reset configuration
862 @item CPU/Chip/CPU-Core specific features
866 @subsection Important variable names
868 By default, the end user should never need to set these
869 variables. However, if the user needs to override a setting they only
870 need to set the variable in a simple way.
874 @* This gives a name to the overall chip, and is used as part of the
875 tap identifier dotted name.
877 @* By default little - unless the chip or board is not normally used that way.
879 @* When OpenOCD examines the JTAG chain, it will attempt to identify
880 every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
881 to verify the tap id number verses configuration file and may issue an
882 error or warning like this. The hope is that this will help to pinpoint
883 problems in OpenOCD configurations.
886 Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
887 Error: ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
888 Error: ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
889 Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
892 @item @b{_TARGETNAME}
893 @* By convention, this variable is created by the target configuration
894 script. The board configuration file may make use of this variable to
895 configure things like a ``reset init'' script, or other things
896 specific to that board and that target.
898 If the chip has 2 targets, use the names @b{_TARGETNAME0},
899 @b{_TARGETNAME1}, ... etc.
901 @b{Remember:} The ``board file'' may include multiple targets.
903 At no time should the name ``target0'' (the default target name if
904 none was specified) be used. The name ``target0'' is a hard coded name
905 - the next target on the board will be some other number.
906 In the same way, avoid using target numbers even when they are
907 permitted; use the right target name(s) for your board.
909 The user (or board file) should reasonably be able to:
912 source [find target/FOO.cfg]
913 $_TARGETNAME configure ... FOO specific parameters
915 source [find target/BAR.cfg]
916 $_TARGETNAME configure ... BAR specific parameters
921 @subsection Tcl Variables Guide Line
922 The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
924 Thus the rule we follow in OpenOCD is this: Variables that begin with
925 a leading underscore are temporary in nature, and can be modified and
926 used at will within a ?TARGET? configuration file.
928 @b{EXAMPLE:} The user should be able to do this:
932 # PXA270 #1 network side, big endian
933 # PXA270 #2 video side, little endian
937 source [find target/pxa270.cfg]
938 # variable: _TARGETNAME = network.cpu
939 # other commands can refer to the "network.cpu" tap.
940 $_TARGETNAME configure .... params for this CPU..
944 source [find target/pxa270.cfg]
945 # variable: _TARGETNAME = video.cpu
946 # other commands can refer to the "video.cpu" tap.
947 $_TARGETNAME configure .... params for this CPU..
951 source [find target/spartan3.cfg]
953 # Since $_TARGETNAME is temporal..
954 # these names still work!
955 network.cpu configure ... params
956 video.cpu configure ... params
960 @subsection Default Value Boiler Plate Code
962 All target configuration files should start with this (or a modified form)
966 if @{ [info exists CHIPNAME] @} @{
967 set _CHIPNAME $CHIPNAME
969 set _CHIPNAME sam7x256
972 if @{ [info exists ENDIAN] @} @{
978 if @{ [info exists CPUTAPID ] @} @{
979 set _CPUTAPID $CPUTAPID
981 set _CPUTAPID 0x3f0f0f0f
986 @subsection Creating Taps
987 After the ``defaults'' are choosen [see above] the taps are created.
989 @b{SIMPLE example:} such as an Atmel AT91SAM7X256
993 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
994 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
999 This is an SNIP/example for an STR912 - which has 3 internal taps. Key features shown:
1002 @item @b{Unform tap names} - See: Tap Naming Convention
1003 @item @b{_TARGETNAME} is created at the end where used.
1007 if @{ [info exists FLASHTAPID ] @} @{
1008 set _FLASHTAPID $FLASHTAPID
1010 set _FLASHTAPID 0x25966041
1012 jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
1014 if @{ [info exists CPUTAPID ] @} @{
1015 set _CPUTAPID $CPUTAPID
1017 set _CPUTAPID 0x25966041
1019 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
1022 if @{ [info exists BSTAPID ] @} @{
1023 set _BSTAPID $BSTAPID
1025 set _BSTAPID 0x1457f041
1027 jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
1029 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
1032 @b{Tap Naming Convention}
1034 See the command ``jtag newtap'' for detail, but in brief the names you should use are:
1043 @item @b{unknownN} - it happens :-(
1046 @subsection Reset Configuration
1048 Some chips have specific ways the TRST and SRST signals are
1049 managed. If these are @b{CHIP SPECIFIC} they go here, if they are
1050 @b{BOARD SPECIFIC} they go in the board file.
1052 @subsection Work Areas
1054 Work areas are small RAM areas used by OpenOCD to speed up downloads,
1055 and to download small snippets of code to program flash chips.
1057 If the chip includes a form of ``on-chip-ram'' - and many do - define
1058 a reasonable work area and use the ``backup'' option.
1060 @b{PROBLEMS:} On more complex chips, this ``work area'' may become
1061 inaccessible if/when the application code enables or disables the MMU.
1063 @subsection ARM Core Specific Hacks
1065 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1066 special high speed download features - enable it.
1068 If the chip has an ARM ``vector catch'' feature - by default enable
1069 it for Undefined Instructions, Data Abort, and Prefetch Abort, if the
1070 user is really writing a handler for those situations - they can
1071 easily disable it. Experiance has shown the ``vector catch'' is
1072 helpful - for common programing errors.
1074 If present, the MMU, the MPU and the CACHE should be disabled.
1076 Some ARM cores are equipped with trace support, which permits
1077 examination of the instruction and data bus activity. Trace
1078 activity is controlled through an ``Embedded Trace Module'' (ETM)
1079 on one of the core's scan chains. The ETM emits voluminous data
1080 through a ``trace port''. The trace port is accessed in one
1081 of two ways. When its signals are pinned out from the chip,
1082 boards may provide a special high speed debugging connector;
1083 software support for this is not configured by default, use
1084 the ``--enable-oocd_trace'' option. Alternatively, trace data
1085 may be stored an on-chip SRAM which is packaged as an ``Embedded
1086 Trace Buffer'' (ETB). An ETB has its own TAP, usually right after
1087 its associated ARM core. OpenOCD supports the ETM, and your
1088 target configuration should set it up with the relevant trace
1089 port: ``etb'' for chips which use that, else the board-specific
1090 option will be either ``oocd_trace'' or ``dummy''.
1093 etm config $_TARGETNAME 16 normal full etb
1094 etb config $_TARGETNAME $_CHIPNAME.etb
1097 @subsection Internal Flash Configuration
1099 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1101 @b{Never ever} in the ``target configuration file'' define any type of
1102 flash that is external to the chip. (For example a BOOT flash on
1103 Chip Select 0.) Such flash information goes in a board file - not
1104 the TARGET (chip) file.
1108 @item at91sam7x256 - has 256K flash YES enable it.
1109 @item str912 - has flash internal YES enable it.
1110 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1111 @item pxa270 - again - CS0 flash - it goes in the board file.
1115 @chapter About JIM-Tcl
1119 OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
1120 learn more about JIM here: @url{http://jim.berlios.de}
1123 @item @b{JIM vs. Tcl}
1124 @* JIM-TCL is a stripped down version of the well known Tcl language,
1125 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
1126 fewer features. JIM-Tcl is a single .C file and a single .H file and
1127 impliments the basic Tcl command set along. In contrast: Tcl 8.6 is a
1128 4.2 MB .zip file containing 1540 files.
1130 @item @b{Missing Features}
1131 @* Our practice has been: Add/clone the real Tcl feature if/when
1132 needed. We welcome JIM Tcl improvements, not bloat.
1135 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
1136 command interpreter today (28/nov/2008) is a mixture of (newer)
1137 JIM-Tcl commands, and (older) the orginal command interpreter.
1140 @* At the OpenOCD telnet command line (or via the GDB mon command) one
1141 can type a Tcl for() loop, set variables, etc.
1143 @item @b{Historical Note}
1144 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
1146 @item @b{Need a crash course in Tcl?}
1147 @* See: @xref{Tcl Crash Course}.
1151 @node Daemon Configuration
1152 @chapter Daemon Configuration
1153 The commands here are commonly found in the openocd.cfg file and are
1154 used to specify what TCP/IP ports are used, and how GDB should be
1158 This command terminates the configuration stage and
1159 enters the normal command mode. This can be useful to add commands to
1160 the startup scripts and commands such as resetting the target,
1161 programming flash, etc. To reset the CPU upon startup, add "init" and
1162 "reset" at the end of the config script or at the end of the OpenOCD
1163 command line using the @option{-c} command line switch.
1165 If this command does not appear in any startup/configuration file
1166 OpenOCD executes the command for you after processing all
1167 configuration files and/or command line options.
1169 @b{NOTE:} This command normally occurs at or near the end of your
1170 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1171 targets ready. For example: If your openocd.cfg file needs to
1172 read/write memory on your target - the init command must occur before
1173 the memory read/write commands. This includes @command{nand probe}.
1175 @section TCP/IP Ports
1177 @item @b{telnet_port} <@var{number}>
1179 @*Intended for a human. Port on which to listen for incoming telnet connections.
1181 @item @b{tcl_port} <@var{number}>
1183 @*Intended as a machine interface. Port on which to listen for
1184 incoming Tcl syntax. This port is intended as a simplified RPC
1185 connection that can be used by clients to issue commands and get the
1186 output from the Tcl engine.
1188 @item @b{gdb_port} <@var{number}>
1190 @*First port on which to listen for incoming GDB connections. The GDB port for the
1191 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1196 @item @b{gdb_breakpoint_override} <@var{hard|soft|disable}>
1197 @cindex gdb_breakpoint_override
1198 @anchor{gdb_breakpoint_override}
1199 @*Force breakpoint type for gdb 'break' commands.
1200 The raison d'etre for this option is to support GDB GUI's without
1201 a hard/soft breakpoint concept where the default OpenOCD and
1202 GDB behaviour is not sufficient. Note that GDB will use hardware
1203 breakpoints if the memory map has been set up for flash regions.
1205 This option replaces older arm7_9 target commands that addressed
1208 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
1210 @*Configures what OpenOCD will do when GDB detaches from the daemon.
1211 Default behaviour is <@var{resume}>
1213 @item @b{gdb_memory_map} <@var{enable|disable}>
1214 @cindex gdb_memory_map
1215 @*Set to <@var{enable}> to cause OpenOCD to send the memory configuration to GDB when
1216 requested. GDB will then know when to set hardware breakpoints, and program flash
1217 using the GDB load command. @option{gdb_flash_program enable} must also be enabled
1218 for flash programming to work.
1219 Default behaviour is <@var{enable}>
1220 @xref{gdb_flash_program}.
1222 @item @b{gdb_flash_program} <@var{enable|disable}>
1223 @cindex gdb_flash_program
1224 @anchor{gdb_flash_program}
1225 @*Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
1226 vFlash packet is received.
1227 Default behaviour is <@var{enable}>
1228 @comment END GDB Items
1231 @node Interface - Dongle Configuration
1232 @chapter Interface - Dongle Configuration
1233 Interface commands are normally found in an interface configuration
1234 file which is sourced by your openocd.cfg file. These commands tell
1235 OpenOCD what type of JTAG dongle you have and how to talk to it.
1236 @section Simple Complete Interface Examples
1237 @b{A Turtelizer FT2232 Based JTAG Dongle}
1241 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A"
1242 ft2232_layout turtelizer2
1243 ft2232_vid_pid 0x0403 0xbdc8
1250 @b{A Raisonance RLink}
1259 parport_cable wiggler
1264 interface arm-jtag-ew
1266 @section Interface Command
1268 The interface command tells OpenOCD what type of JTAG dongle you are
1269 using. Depending on the type of dongle, you may need to have one or
1270 more additional commands.
1274 @item @b{interface} <@var{name}>
1276 @*Use the interface driver <@var{name}> to connect to the
1277 target. Currently supported interfaces are
1282 @* PC parallel port bit-banging (Wigglers, PLD download cable, ...)
1284 @item @b{amt_jtagaccel}
1285 @* Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
1289 @* FTDI FT2232 (USB) based devices using either the open-source libftdi or the binary only
1290 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
1291 platform. The libftdi uses libusb, and should be portable to all systems that provide
1295 @*Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1298 @* ASIX PRESTO USB JTAG programmer.
1301 @* usbprog is a freely programmable USB adapter.
1304 @* Gateworks GW16012 JTAG programmer.
1307 @* Segger jlink USB adapter
1310 @* Raisonance RLink USB adapter
1313 @* vsllink is part of Versaloon which is a versatile USB programmer.
1315 @item @b{arm-jtag-ew}
1316 @* Olimex ARM-JTAG-EW USB adapter
1317 @comment - End parameters
1319 @comment - End Interface
1321 @subsection parport options
1324 @item @b{parport_port} <@var{number}>
1325 @cindex parport_port
1326 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1327 the @file{/dev/parport} device
1329 When using PPDEV to access the parallel port, use the number of the parallel port:
1330 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1331 you may encounter a problem.
1332 @item @b{parport_cable} <@var{name}>
1333 @cindex parport_cable
1334 @*The layout of the parallel port cable used to connect to the target.
1335 Currently supported cables are
1339 The original Wiggler layout, also supported by several clones, such
1340 as the Olimex ARM-JTAG
1343 Same as original wiggler except an led is fitted on D5.
1344 @item @b{wiggler_ntrst_inverted}
1345 @cindex wiggler_ntrst_inverted
1346 Same as original wiggler except TRST is inverted.
1347 @item @b{old_amt_wiggler}
1348 @cindex old_amt_wiggler
1349 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
1350 version available from the website uses the original Wiggler layout ('@var{wiggler}')
1353 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
1354 program the Chameleon itself, not a connected target.
1357 The Xilinx Parallel cable III.
1360 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
1361 This is also the layout used by the HollyGates design
1362 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1365 The ST Parallel cable.
1368 Same as original wiggler except SRST and TRST connections reversed and
1369 TRST is also inverted.
1372 Altium Universal JTAG cable.
1374 @item @b{parport_write_on_exit} <@var{on}|@var{off}>
1375 @cindex parport_write_on_exit
1376 @*This will configure the parallel driver to write a known value to the parallel
1377 interface on exiting OpenOCD
1380 @subsection amt_jtagaccel options
1382 @item @b{parport_port} <@var{number}>
1383 @cindex parport_port
1384 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
1385 @file{/dev/parport} device
1387 @subsection ft2232 options
1390 @item @b{ft2232_device_desc} <@var{description}>
1391 @cindex ft2232_device_desc
1392 @*The USB device description of the FTDI FT2232 device. If not
1393 specified, the FTDI default value is used. This setting is only valid
1394 if compiled with FTD2XX support.
1396 @b{TODO:} Confirm the following: On Windows the name needs to end with
1397 a ``space A''? Or not? It has to do with the FTD2xx driver. When must
1398 this be added and when must it not be added? Why can't the code in the
1399 interface or in OpenOCD automatically add this if needed? -- Duane.
1401 @item @b{ft2232_serial} <@var{serial-number}>
1402 @cindex ft2232_serial
1403 @*The serial number of the FTDI FT2232 device. If not specified, the FTDI default
1405 @item @b{ft2232_layout} <@var{name}>
1406 @cindex ft2232_layout
1407 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
1408 signals. Valid layouts are
1411 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
1413 Amontec JTAGkey and JTAGkey-Tiny
1414 @item @b{signalyzer}
1416 @item @b{olimex-jtag}
1419 American Microsystems M5960
1420 @item @b{evb_lm3s811}
1421 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
1422 SRST signals on external connector
1425 @item @b{stm32stick}
1426 Hitex STM32 Performance Stick
1427 @item @b{flyswatter}
1428 Tin Can Tools Flyswatter
1429 @item @b{turtelizer2}
1430 egnite Software turtelizer2
1433 @item @b{axm0432_jtag}
1437 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
1438 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1439 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, e.g.
1441 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1443 @item @b{ft2232_latency} <@var{ms}>
1444 @*On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1445 ft2232_read() fails to return the expected number of bytes. This can be caused by
1446 USB communication delays and has proved hard to reproduce and debug. Setting the
1447 FT2232 latency timer to a larger value increases delays for short USB packets but it
1448 also reduces the risk of timeouts before receiving the expected number of bytes.
1449 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1452 @subsection ep93xx options
1453 @cindex ep93xx options
1454 Currently, there are no options available for the ep93xx interface.
1458 @item @b{jtag_khz} <@var{reset speed kHz}>
1461 It is debatable if this command belongs here - or in a board
1462 configuration file. In fact, in some situations the JTAG speed is
1463 changed during the target initialisation process (i.e.: (1) slow at
1464 reset, (2) program the CPU clocks, (3) run fast)
1466 Speed 0 (khz) selects RTCK method. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1468 Not all interfaces support ``rtck''. If the interface device can not
1469 support the rate asked for, or can not translate from kHz to
1470 jtag_speed, then an error is returned.
1472 Make sure the JTAG clock is no more than @math{1/6th CPU-Clock}. This is
1473 especially true for synthesized cores (-S). Also see RTCK.
1475 @b{NOTE: Script writers} If the target chip requires/uses RTCK -
1476 please use the command: 'jtag_rclk FREQ'. This Tcl proc (in
1477 startup.tcl) attempts to enable RTCK, if that fails it falls back to
1478 the specified frequency.
1481 # Fall back to 3mhz if RCLK is not supported
1485 @item @b{DEPRECATED} @b{jtag_speed} - please use jtag_khz above.
1487 @*Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
1488 speed. The actual effect of this option depends on the JTAG interface used.
1490 The speed used during reset can be adjusted using setting jtag_speed during
1491 pre_reset and post_reset events.
1494 @item wiggler: maximum speed / @var{number}
1495 @item ft2232: 6MHz / (@var{number}+1)
1496 @item amt jtagaccel: 8 / 2**@var{number}
1497 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
1498 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
1499 @comment end speed list.
1502 @comment END command list
1505 @node Reset Configuration
1506 @chapter Reset Configuration
1507 @cindex Reset Configuration
1509 Every system configuration may require a different reset
1510 configuration. This can also be quite confusing. Please see the
1511 various board files for example.
1513 @section jtag_nsrst_delay <@var{ms}>
1514 @cindex jtag_nsrst_delay
1515 @*How long (in milliseconds) OpenOCD should wait after deasserting
1516 nSRST before starting new JTAG operations.
1518 @section jtag_ntrst_delay <@var{ms}>
1519 @cindex jtag_ntrst_delay
1520 @*Same @b{jtag_nsrst_delay}, but for nTRST
1522 The jtag_n[st]rst_delay options are useful if reset circuitry (like a
1523 big resistor/capacitor, reset supervisor, or on-chip features). This
1524 keeps the signal asserted for some time after the external reset got
1527 @section reset_config
1529 @b{Note:} To maintainers and integrators: Where exactly the
1530 ``reset configuration'' goes is a good question. It touches several
1531 things at once. In the end, if you have a board file - the board file
1532 should define it and assume 100% that the DONGLE supports
1533 anything. However, that does not mean the target should not also make
1534 not of something the silicon vendor has done inside the
1535 chip. @i{Grr.... nothing is every pretty.}
1539 @item Every JTAG Dongle is slightly different, some dongles implement reset differently.
1540 @item Every board is also slightly different; some boards tie TRST and SRST together.
1541 @item Every chip is slightly different; some chips internally tie the two signals together.
1542 @item Some may not implement all of the signals the same way.
1543 @item Some signals might be push-pull, others open-drain/collector.
1545 @b{Best Case:} OpenOCD can hold the SRST (push-button-reset), then
1546 reset the TAP via TRST and send commands through the JTAG tap to halt
1547 the CPU at the reset vector before the 1st instruction is executed,
1548 and finally release the SRST signal.
1549 @*Depending on your board vendor, chip vendor, etc., these
1550 signals may have slightly different names.
1552 OpenOCD defines these signals in these terms:
1554 @item @b{TRST} - is Tap Reset - and should reset only the TAP.
1555 @item @b{SRST} - is System Reset - typically equal to a reset push button.
1561 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
1562 @cindex reset_config
1563 @* The @t{reset_config} command tells OpenOCD the reset configuration
1564 of your combination of Dongle, Board, and Chips.
1565 If the JTAG interface provides SRST, but the target doesn't connect
1566 that signal properly, then OpenOCD can't use it. <@var{signals}> can
1567 be @option{none}, @option{trst_only}, @option{srst_only} or
1568 @option{trst_and_srst}.
1570 [@var{combination}] is an optional value specifying broken reset
1571 signal implementations. @option{srst_pulls_trst} states that the
1572 test logic is reset together with the reset of the system (e.g. Philips
1573 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
1574 the system is reset together with the test logic (only hypothetical, I
1575 haven't seen hardware with such a bug, and can be worked around).
1576 @option{combined} implies both @option{srst_pulls_trst} and
1577 @option{trst_pulls_srst}. The default behaviour if no option given is
1580 The [@var{trst_type}] and [@var{srst_type}] parameters allow the
1581 driver type of the reset lines to be specified. Possible values are
1582 @option{trst_push_pull} (default) and @option{trst_open_drain} for the
1583 test reset signal, and @option{srst_open_drain} (default) and
1584 @option{srst_push_pull} for the system reset. These values only affect
1585 JTAG interfaces with support for different drivers, like the Amontec
1586 JTAGkey and JTAGAccelerator.
1588 @comment - end command
1594 @chapter Tap Creation
1595 @cindex tap creation
1596 @cindex tap configuration
1598 In order for OpenOCD to control a target, a JTAG tap must be
1601 Commands to create taps are normally found in a configuration file and
1602 are not normally typed by a human.
1604 When a tap is created a @b{dotted.name} is created for the tap. Other
1605 commands use that dotted.name to manipulate or refer to the tap.
1609 @item @b{Debug Target} A tap can be used by a GDB debug target
1610 @item @b{Flash Programing} Some chips program the flash directly via JTAG,
1611 instead of indirectly by making a CPU do it.
1612 @item @b{Boundry Scan} Some chips support boundary scan.
1616 @section jtag newtap
1617 @b{@t{jtag newtap CHIPNAME TAPNAME configparams ....}}
1622 @cindex tap geometry
1624 @comment START options
1627 @* is a symbolic name of the chip.
1629 @* is a symbol name of a tap present on the chip.
1630 @item @b{Required configparams}
1631 @* Every tap has 3 required configparams, and several ``optional
1632 parameters'', the required parameters are:
1633 @comment START REQUIRED
1635 @item @b{-irlen NUMBER} - the length in bits of the instruction register, mostly 4 or 5 bits.
1636 @item @b{-ircapture NUMBER} - the IDCODE capture command, usually 0x01.
1637 @item @b{-irmask NUMBER} - the corresponding mask for the IR register. For
1638 some devices, there are bits in the IR that aren't used. This lets you mask
1639 them off when doing comparisons. In general, this should just be all ones for
1641 @comment END REQUIRED
1643 An example of a FOOBAR Tap
1645 jtag newtap foobar tap -irlen 7 -ircapture 0x42 -irmask 0x55
1647 Creates the tap ``foobar.tap'' with the instruction register (IR) is 7
1648 bits long, during Capture-IR 0x42 is loaded into the IR, and bits
1649 [6,4,2,0] are checked.
1651 @item @b{Optional configparams}
1652 @comment START Optional
1654 @item @b{-expected-id NUMBER}
1655 @* By default it is zero. If non-zero represents the
1656 expected tap ID used when the JTAG chain is examined. Repeat
1657 the option as many times as required if multiple id's can be
1658 expected. See below.
1661 @* By default not specified the tap is enabled. Some chips have a
1662 JTAG route controller (JRC) that is used to enable and/or disable
1663 specific JTAG taps. You can later enable or disable any JTAG tap via
1664 the command @b{jtag tapenable DOTTED.NAME} or @b{jtag tapdisable
1666 @comment END Optional
1669 @comment END OPTIONS
1672 @comment START NOTES
1674 @item @b{Technically}
1675 @* newtap is a sub command of the ``jtag'' command
1676 @item @b{Big Picture Background}
1677 @*GDB Talks to OpenOCD using the GDB protocol via
1678 TCP/IP. OpenOCD then uses the JTAG interface (the dongle) to
1679 control the JTAG chain on your board. Your board has one or more chips
1680 in a @i{daisy chain configuration}. Each chip may have one or more
1681 JTAG taps. GDB ends up talking via OpenOCD to one of the taps.
1682 @item @b{NAME Rules}
1683 @*Names follow ``C'' symbol name rules (start with alpha ...)
1684 @item @b{TAPNAME - Conventions}
1686 @item @b{tap} - should be used only FPGA or CPLD like devices with a single tap.
1687 @item @b{cpu} - the main CPU of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
1688 @item @b{flash} - if the chip has a flash tap, example: str912.flash
1689 @item @b{bs} - for boundary scan if this is a seperate tap.
1690 @item @b{etb} - for an embedded trace buffer (example: an ARM ETB11)
1691 @item @b{jrc} - for JTAG route controller (example: OMAP3530 found on Beagleboards)
1692 @item @b{unknownN} - where N is a number if you have no idea what the tap is for
1693 @item @b{Other names} - Freescale IMX31 has a SDMA (smart dma) with a JTAG tap, that tap should be called the ``sdma'' tap.
1694 @item @b{When in doubt} - use the chip maker's name in their data sheet.
1696 @item @b{DOTTED.NAME}
1697 @* @b{CHIPNAME}.@b{TAPNAME} creates the tap name, aka: the
1698 @b{Dotted.Name} is the @b{CHIPNAME} and @b{TAPNAME} combined with a
1699 dot (period); for example: @b{xilinx.tap}, @b{str912.flash},
1700 @b{omap3530.jrc}, or @b{stm32.cpu} The @b{dotted.name} is used in
1701 numerous other places to refer to various taps.
1703 @* The order this command appears via the config files is
1705 @item @b{Multi Tap Example}
1706 @* This example is based on the ST Microsystems STR912. See the ST
1707 document titled: @b{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
1708 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
1710 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}
1711 @*@b{checked: 28/nov/2008}
1713 The diagram shows that the TDO pin connects to the flash tap, flash TDI
1714 connects to the CPU debug tap, CPU TDI connects to the boundary scan
1715 tap which then connects to the TDI pin.
1719 # create tap: 'str912.flash'
1720 jtag newtap str912 flash ... params ...
1721 # create tap: 'str912.cpu'
1722 jtag newtap str912 cpu ... params ...
1723 # create tap: 'str912.bs'
1724 jtag newtap str912 bs ... params ...
1727 @item @b{Note: Deprecated} - Index Numbers
1728 @* Prior to 28/nov/2008, JTAG taps where numbered from 0..N this
1729 feature is still present, however its use is highly discouraged and
1730 should not be counted upon. Update all of your scripts to use
1731 TAP names rather than numbers.
1732 @item @b{Multiple chips}
1733 @* If your board has multiple chips, you should be
1734 able to @b{source} two configuration files, in the proper order, and
1735 have the taps created in the proper order.
1738 @comment at command level
1739 @comment DOCUMENT old command
1740 @section jtag_device - REMOVED
1742 @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
1746 @* @b{Removed: 28/nov/2008} This command has been removed and replaced
1747 by the ``jtag newtap'' command. The documentation remains here so that
1748 one can easily convert the old syntax to the new syntax. About the old
1749 syntax: The old syntax is positional, i.e.: The 3rd parameter is the
1750 ``irmask''. The new syntax requires named prefixes, and supports
1751 additional options, for example ``-expected-id 0x3f0f0f0f''. Please refer to the
1752 @b{jtag newtap} command for details.
1754 OLD: jtag_device 8 0x01 0xe3 0xfe
1755 NEW: jtag newtap CHIPNAME TAPNAME -irlen 8 -ircapture 0x01 -irmask 0xe3
1758 @section Enable/Disable Taps
1759 @b{Note:} These commands are intended to be used as a machine/script
1760 interface. Humans might find the ``scan_chain'' command more helpful
1761 when querying the state of the JTAG taps.
1763 @b{By default, all taps are enabled}
1766 @item @b{jtag tapenable} @var{DOTTED.NAME}
1767 @item @b{jtag tapdisable} @var{DOTTED.NAME}
1768 @item @b{jtag tapisenabled} @var{DOTTED.NAME}
1773 @cindex route controller
1775 These commands are used when your target has a JTAG route controller
1776 that effectively adds or removes a tap from the JTAG chain in a
1779 The ``standard way'' to remove a tap would be to place the tap in
1780 bypass mode. But with the advent of modern chips, this is not always a
1781 good solution. Some taps operate slowly, others operate fast, and
1782 there are other JTAG clock synchronisation problems one must face. To
1783 solve that problem, the JTAG route controller was introduced. Rather
1784 than ``bypass'' the tap, the tap is completely removed from the
1785 circuit and skipped.
1788 From OpenOCD's point of view, a JTAG tap is in one of 3 states:
1791 @item @b{Enabled - Not In ByPass} and has a variable bit length
1792 @item @b{Enabled - In ByPass} and has a length of exactly 1 bit.
1793 @item @b{Disabled} and has a length of ZERO and is removed from the circuit.
1796 The IEEE JTAG definition has no concept of a ``disabled'' tap.
1797 @b{Historical note:} this feature was added 28/nov/2008
1799 @b{jtag tapisenabled DOTTED.NAME}
1801 This command returns 1 if the named tap is currently enabled, 0 if not.
1802 This command exists so that scripts that manipulate a JRC (like the
1803 OMAP3530 has) can determine if OpenOCD thinks a tap is presently
1804 enabled or disabled.
1807 @node Target Configuration
1808 @chapter Target Configuration
1810 This chapter discusses how to create a GDB debug target. Before
1811 creating a ``target'' a JTAG tap DOTTED.NAME must exist first.
1813 @section targets [NAME]
1814 @b{Note:} This command name is PLURAL - not singular.
1816 With NO parameter, this plural @b{targets} command lists all known
1817 targets in a human friendly form.
1819 With a parameter, this plural @b{targets} command sets the current
1820 target to the given name. (i.e.: If there are multiple debug targets)
1825 CmdName Type Endian ChainPos State
1826 -- ---------- ---------- ---------- -------- ----------
1827 0: target0 arm7tdmi little 0 halted
1830 @section target COMMANDS
1831 @b{Note:} This command name is SINGULAR - not plural. It is used to
1832 manipulate specific targets, to create targets and other things.
1834 Once a target is created, a TARGETNAME (object) command is created;
1835 see below for details.
1837 The TARGET command accepts these sub-commands:
1839 @item @b{create} .. parameters ..
1840 @* creates a new target, see below for details.
1842 @* Lists all supported target types (perhaps some are not yet in this document).
1844 @* Lists all current debug target names, for example: 'str912.cpu' or 'pxa27.cpu' example usage:
1846 foreach t [target names] {
1847 puts [format "Target: %s\n" $t]
1851 @* Returns the current target. OpenOCD always has, or refers to the ``current target'' in some way.
1852 By default, commands like: ``mww'' (used to write memory) operate on the current target.
1853 @item @b{number} @b{NUMBER}
1854 @* Internally OpenOCD maintains a list of targets - in numerical index
1855 (0..N-1) this command returns the name of the target at index N.
1858 set thename [target number $x]
1859 puts [format "Target %d is: %s\n" $x $thename]
1862 @* Returns the number of targets known to OpenOCD (see number above)
1865 set c [target count]
1866 for { set x 0 } { $x < $c } { incr x } {
1867 # Assuming you have created this function
1868 print_target_details $x
1874 @section TARGETNAME (object) commands
1875 @b{Use:} Once a target is created, an ``object name'' that represents the
1876 target is created. By convention, the target name is identical to the
1877 tap name. In a multiple target system, one can preceed many common
1878 commands with a specific target name and effect only that target.
1880 str912.cpu mww 0x1234 0x42
1881 omap3530.cpu mww 0x5555 123
1884 @b{Model:} The Tcl/Tk language has the concept of object commands. A
1885 good example is a on screen button, once a button is created a button
1886 has a name (a path in Tk terms) and that name is useable as a 1st
1887 class command. For example in Tk, one can create a button and later
1888 configure it like this:
1892 button .foobar -background red -command @{ foo @}
1894 .foobar configure -foreground blue
1896 set x [.foobar cget -background]
1898 puts [format "The button is %s" $x]
1901 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
1902 button. Commands available as a ``target object'' are:
1904 @comment START targetobj commands.
1906 @item @b{configure} - configure the target; see Target Config/Cget Options below
1907 @item @b{cget} - query the target configuration; see Target Config/Cget Options below
1908 @item @b{curstate} - current target state (running, halt, etc.
1910 @* Intended for a human to see/read the currently configure target events.
1911 @item @b{Various Memory Commands} See the ``mww'' command elsewhere.
1912 @comment start memory
1922 @item @b{Memory To Array, Array To Memory}
1923 @* These are aimed at a machine interface to memory
1925 @item @b{mem2array ARRAYNAME WIDTH ADDRESS COUNT}
1926 @item @b{array2mem ARRAYNAME WIDTH ADDRESS COUNT}
1928 @* @b{ARRAYNAME} is the name of an array variable
1929 @* @b{WIDTH} is 8/16/32 - indicating the memory access size
1930 @* @b{ADDRESS} is the target memory address
1931 @* @b{COUNT} is the number of elements to process
1933 @item @b{Used during ``reset''}
1934 @* These commands are used internally by the OpenOCD scripts to deal
1935 with odd reset situations and are not documented here.
1937 @item @b{arp_examine}
1941 @item @b{arp_waitstate}
1943 @item @b{invoke-event} @b{EVENT-NAME}
1944 @* Invokes the specific event manually for the target
1947 @section Target Events
1948 At various times, certain things can happen, or you want them to happen.
1952 @item What should happen when GDB connects? Should your target reset?
1953 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
1954 @item During reset, do you need to write to certain memory location to reconfigure the SDRAM?
1957 All of the above items are handled by target events.
1959 To specify an event action, either during target creation, or later
1960 via ``$_TARGETNAME configure'' see this example.
1962 Syntactially, the option is: ``-event NAME BODY'' where NAME is a
1963 target event name, and BODY is a Tcl procedure or string of commands
1966 The programmers model is the ``-command'' option used in Tcl/Tk
1967 buttons and events. Below are two identical examples, the first
1968 creates and invokes small procedure. The second inlines the procedure.
1971 proc my_attach_proc @{ @} @{
1975 mychip.cpu configure -event gdb-attach my_attach_proc
1976 mychip.cpu configure -event gdb-attach @{ puts "Reset..." ; reset halt @}
1979 @section Current Events
1980 The following events are available:
1982 @item @b{debug-halted}
1983 @* The target has halted for debug reasons (i.e.: breakpoint)
1984 @item @b{debug-resumed}
1985 @* The target has resumed (i.e.: gdb said run)
1986 @item @b{early-halted}
1987 @* Occurs early in the halt process
1988 @item @b{examine-end}
1989 @* Currently not used (goal: when JTAG examine completes)
1990 @item @b{examine-start}
1991 @* Currently not used (goal: when JTAG examine starts)
1992 @item @b{gdb-attach}
1993 @* When GDB connects
1994 @item @b{gdb-detach}
1995 @* When GDB disconnects
1997 @* When the taret has halted and GDB is not doing anything (see early halt)
1998 @item @b{gdb-flash-erase-start}
1999 @* Before the GDB flash process tries to erase the flash
2000 @item @b{gdb-flash-erase-end}
2001 @* After the GDB flash process has finished erasing the flash
2002 @item @b{gdb-flash-write-start}
2003 @* Before GDB writes to the flash
2004 @item @b{gdb-flash-write-end}
2005 @* After GDB writes to the flash
2007 @* Before the taret steps, gdb is trying to start/resume the target
2009 @* The target has halted
2010 @item @b{old-gdb_program_config}
2011 @* DO NOT USE THIS: Used internally
2012 @item @b{old-pre_resume}
2013 @* DO NOT USE THIS: Used internally
2014 @item @b{reset-assert-pre}
2015 @* Before reset is asserted on the tap.
2016 @item @b{reset-assert-post}
2017 @* Reset is now asserted on the tap.
2018 @item @b{reset-deassert-pre}
2019 @* Reset is about to be released on the tap
2020 @item @b{reset-deassert-post}
2021 @* Reset has been released on the tap
2023 @* Currently not used.
2024 @item @b{reset-halt-post}
2025 @* Currently not usd
2026 @item @b{reset-halt-pre}
2027 @* Currently not used
2028 @item @b{reset-init}
2029 @* Used by @b{reset init} command for board-specific initialization.
2030 This is where you would configure PLLs and clocking, set up DRAM so
2031 you can download programs that don't fit in on-chip SRAM, set up pin
2032 multiplexing, and so on.
2033 @item @b{reset-start}
2034 @* Currently not used
2035 @item @b{reset-wait-pos}
2036 @* Currently not used
2037 @item @b{reset-wait-pre}
2038 @* Currently not used
2039 @item @b{resume-start}
2040 @* Before any target is resumed
2041 @item @b{resume-end}
2042 @* After all targets have resumed
2046 @* Target has resumed
2047 @item @b{tap-enable}
2048 @* Executed by @b{jtag tapenable DOTTED.NAME} command. Example:
2050 jtag configure DOTTED.NAME -event tap-enable @{
2055 @item @b{tap-disable}
2056 @*Executed by @b{jtag tapdisable DOTTED.NAME} command. Example:
2058 jtag configure DOTTED.NAME -event tap-disable @{
2059 puts "Disabling CPU"
2065 @section target create
2067 @cindex target creation
2070 @b{target} @b{create} <@var{NAME}> <@var{TYPE}> <@var{PARAMS ...}>
2072 @*This command creates a GDB debug target that refers to a specific JTAG tap.
2073 @comment START params
2076 @* Is the name of the debug target. By convention it should be the tap
2077 DOTTED.NAME. This name is also used to create the target object
2078 command, and in other places the target needs to be identified.
2080 @* Specifies the target type, i.e.: ARM7TDMI, or Cortex-M3. Currently supported targets are:
2081 @comment START types
2098 @*PARAMs are various target configuration parameters. The following ones are mandatory:
2099 @comment START mandatory
2101 @item @b{-endian big|little}
2102 @item @b{-chain-position DOTTED.NAME}
2103 @comment end MANDATORY
2108 @section Target Config/Cget Options
2109 These options can be specified when the target is created, or later
2110 via the configure option or to query the target via cget.
2112 You should specify a working area if you can; typically it uses some
2113 on-chip SRAM. Such a working area can speed up many things, including bulk
2114 writes to target memory; flash operations like checking to see if memory needs
2115 to be erased; GDB memory checksumming; and may help perform otherwise
2116 unavailable operations (like some coprocessor operations on ARM7/9 systems).
2118 @item @b{-type} - returns the target type
2119 @item @b{-event NAME BODY} see Target events
2120 @item @b{-work-area-virt [ADDRESS]} specify/set the work area base address
2121 which will be used when an MMU is active.
2122 @item @b{-work-area-phys [ADDRESS]} specify/set the work area base address
2123 which will be used when an MMU is inactive.
2124 @item @b{-work-area-size [ADDRESS]} specify/set the work area
2125 @item @b{-work-area-backup [0|1]} does the work area get backed up;
2126 by default, it doesn't. When possible, use a working_area that doesn't
2127 need to be backed up, since performing a backup slows down operations.
2128 @item @b{-endian [big|little]}
2129 @item @b{-variant [NAME]} some chips have variants OpenOCD needs to know about
2130 @item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
2134 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
2135 set name [target number $x]
2136 set y [$name cget -endian]
2137 set z [$name cget -type]
2138 puts [format "Chip %d is %s, Endian: %s, type: %s" $x $y $z]
2142 @section Target Variants
2145 @* Unknown (please write me)
2147 @* Unknown (please write me) (similar to arm7tdmi)
2149 @* Variants: @option{arm920t}, @option{arm922t} and @option{arm940t}
2150 This enables the hardware single-stepping support found on these
2155 @* None (this is also used as the ARM946)
2157 @* use variant <@var{-variant lm3s}> when debugging Luminary lm3s targets. This will cause
2158 OpenOCD to use a software reset rather than asserting SRST to avoid a issue with clearing
2159 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
2160 be detected and the normal reset behaviour used.
2162 @* Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},@option{pxa250}, @option{pxa255}, @option{pxa26x}.
2164 @* Supported variants are @option{arm1136}, @option{arm1156}, @option{arm1176}
2166 @* Use variant @option{ejtag_srst} when debugging targets that do not
2167 provide a functional SRST line on the EJTAG connector. This causes
2168 OpenOCD to instead use an EJTAG software reset command to reset the
2169 processor. You still need to enable @option{srst} on the reset
2170 configuration command to enable OpenOCD hardware reset functionality.
2171 @comment END variants
2173 @section working_area - Command Removed
2174 @cindex working_area
2175 @*@b{Please use the ``$_TARGETNAME configure -work-area-... parameters instead}
2176 @* This documentation remains because there are existing scripts that
2177 still use this that need to be converted.
2179 working_area target# address size backup| [virtualaddress]
2181 @* The target# is a the 0 based target numerical index.
2183 @node Flash Configuration
2184 @chapter Flash programming
2185 @cindex Flash Configuration
2187 OpenOCD has different commands for NOR and NAND flash;
2188 the ``flash'' command works with NOR flash, while
2189 the ``nand'' command works with NAND flash.
2190 This partially reflects different hardware technologies:
2191 NOR flash usually supports direct CPU instruction and data bus access,
2192 while data from a NAND flash must be copied to memory before it can be
2193 used. (SPI flash must also be copied to memory before use.)
2194 However, the documentation also uses ``flash'' as a generic term;
2195 for example, ``Put flash configuration in board-specific files''.
2197 @b{Note:} As of 28/nov/2008 OpenOCD does not know how to program a SPI
2198 flash that a micro may boot from. Perhaps you, the reader, would like to
2199 contribute support for this.
2203 @item Configure via the command @b{flash bank}
2204 @* Normally this is done in a configuration file.
2205 @item Operate on the flash via @b{flash SOMECOMMAND}
2206 @* Often commands to manipulate the flash are typed by a human, or run
2207 via a script in some automated way. For example: To program the boot
2208 flash on your board.
2210 @* Flashing via GDB requires the flash be configured via ``flash
2211 bank'', and the GDB flash features be enabled. See the daemon
2212 configuration section for more details.
2215 @section Flash commands
2216 @cindex Flash commands
2217 @subsection flash banks
2220 @*List configured flash banks
2221 @*@b{NOTE:} the singular form: 'flash bank' is used to configure the flash banks.
2222 @subsection flash info
2223 @b{flash info} <@var{num}>
2225 @*Print info about flash bank <@option{num}>
2226 @subsection flash probe
2227 @b{flash probe} <@var{num}>
2229 @*Identify the flash, or validate the parameters of the configured flash. Operation
2230 depends on the flash type.
2231 @subsection flash erase_check
2232 @b{flash erase_check} <@var{num}>
2233 @cindex flash erase_check
2234 @*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
2235 updates the erase state information displayed by @option{flash info}. That means you have
2236 to issue an @option{erase_check} command after erasing or programming the device to get
2237 updated information.
2238 @subsection flash protect_check
2239 @b{flash protect_check} <@var{num}>
2240 @cindex flash protect_check
2241 @*Check protection state of sectors in flash bank <num>.
2242 @option{flash erase_sector} using the same syntax.
2243 @subsection flash erase_sector
2244 @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
2245 @cindex flash erase_sector
2246 @anchor{flash erase_sector}
2247 @*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
2248 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
2249 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
2251 @subsection flash erase_address
2252 @b{flash erase_address} <@var{address}> <@var{length}>
2253 @cindex flash erase_address
2254 @*Erase sectors starting at <@var{address}> for <@var{length}> bytes
2255 @subsection flash write_bank
2256 @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
2257 @cindex flash write_bank
2258 @anchor{flash write_bank}
2259 @*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
2260 <@option{offset}> bytes from the beginning of the bank.
2261 @subsection flash write_image
2262 @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
2263 @cindex flash write_image
2264 @anchor{flash write_image}
2265 @*Write the image <@var{file}> to the current target's flash bank(s). A relocation
2266 [@var{offset}] can be specified and the file [@var{type}] can be specified
2267 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
2268 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
2269 if the @option{erase} parameter is given.
2270 @subsection flash protect
2271 @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
2272 @cindex flash protect
2273 @*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
2274 <@var{last}> of @option{flash bank} <@var{num}>.
2276 @subsection mFlash commands
2277 @cindex mFlash commands
2279 @item @b{mflash probe}
2280 @cindex mflash probe
2282 @item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
2283 @cindex mflash write
2284 Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
2285 <@var{offset}> bytes from the beginning of the bank.
2286 @item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
2288 Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
2292 @section flash bank command
2293 The @b{flash bank} command is used to configure one or more flash chips (or banks in OpenOCD terms)
2296 @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
2297 <@var{bus_width}> <@var{target}> [@var{driver_options ...}]
2300 @*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
2301 and <@var{bus_width}> bytes using the selected flash <driver>.
2303 @subsection External Flash - cfi options
2305 CFI flashes are external flash chips - often they are connected to a
2306 specific chip select on the CPU. By default, at hard reset, most
2307 CPUs have the ablity to ``boot'' from some flash chip - typically
2308 attached to the CPU's CS0 pin.
2310 For other chip selects: OpenOCD does not know how to configure, or
2311 access a specific chip select. Instead you, the human, might need to
2312 configure additional chip selects via other commands (like: mww) , or
2313 perhaps configure a GPIO pin that controls the ``write protect'' pin
2316 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
2317 <@var{target}> [@var{jedec_probe}|@var{x16_as_x8}]
2318 @*CFI flashes require the name or number of the target they're connected to
2320 argument. The CFI driver makes use of a working area (specified for the target)
2321 to significantly speed up operation.
2323 @var{chip_width} and @var{bus_width} are specified in bytes.
2325 The @var{jedec_probe} option is used to detect certain non-CFI flash ROMs, like AM29LV010 and similar types.
2329 @subsection Internal Flash (Microcontrollers)
2330 @subsubsection lpc2000 options
2331 @cindex lpc2000 options
2333 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
2334 <@var{clock}> [@var{calc_checksum}]
2335 @*LPC flashes don't require the chip and bus width to be specified. Additional
2336 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
2337 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx),
2338 the name or number of the target this flash belongs to (first is 0),
2339 the frequency at which the core
2340 is currently running (in kHz - must be an integral number), and the optional keyword
2341 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
2345 @subsubsection at91sam7 options
2346 @cindex at91sam7 options
2348 @b{flash bank at91sam7} 0 0 0 0 <@var{target}>
2349 @*AT91SAM7 flashes only require the @var{target}, all other values are looked up after
2350 reading the chip-id and type.
2352 @subsubsection str7 options
2353 @cindex str7 options
2355 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
2356 @*variant can be either STR71x, STR73x or STR75x.
2358 @subsubsection str9 options
2359 @cindex str9 options
2361 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target}>
2362 @*The str9 needs the flash controller to be configured prior to Flash programming, e.g.
2364 str9x flash_config 0 4 2 0 0x80000
2366 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
2368 @subsubsection str9 options (str9xpec driver)
2370 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target}>
2371 @*Before using the flash commands the turbo mode must be enabled using str9xpec
2372 @option{enable_turbo} <@var{num>.}
2374 Only use this driver for locking/unlocking the device or configuring the option bytes.
2375 Use the standard str9 driver for programming. @xref{STR9 specific commands}.
2377 @subsubsection Stellaris (LM3Sxxx) options
2378 @cindex Stellaris (LM3Sxxx) options
2380 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target}>
2381 @*Stellaris flash plugin only require the @var{target}.
2383 @subsubsection stm32x options
2384 @cindex stm32x options
2386 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target}>
2387 @*stm32x flash plugin only require the @var{target}.
2389 @subsubsection aduc702x options
2390 @cindex aduc702x options
2392 @b{flash bank aduc702x} 0 0 0 0 <@var{target}>
2393 @*The aduc702x flash plugin works with Analog Devices model numbers ADUC7019 through ADUC7028. The setup command only requires the @var{target} argument (all devices in this family have the same memory layout).
2395 @subsection mFlash Configuration
2396 @cindex mFlash Configuration
2397 @b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
2398 <@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target}>
2400 @*Configures a mflash for <@var{soc}> host bank at
2401 <@var{base}>. <@var{chip_width}> and <@var{bus_width}> are bytes
2402 order. Pin number format is dependent on host GPIO calling convention.
2403 If WP or DPD pin was not used, write -1. Currently, mflash bank
2404 support s3c2440 and pxa270.
2406 (ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1, <@var{WP pin}> and <@var{DPD pin}> are not used.
2408 mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0
2410 (ex. of pxa270) mflash <@var{RST pin}> is GPIO 43, <@var{DPD pin}> is not used and <@var{DPD pin}> is GPIO 51.
2412 mflash bank pxa270 0x08000000 2 2 43 -1 51 0
2415 @section Microcontroller specific Flash Commands
2417 @subsection AT91SAM7 specific commands
2418 @cindex AT91SAM7 specific commands
2419 The flash configuration is deduced from the chip identification register. The flash
2420 controller handles erases automatically on a page (128/265 byte) basis, so erase is
2421 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
2422 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
2423 that can be erased separatly. Only an EraseAll command is supported by the controller
2424 for each flash plane and this is called with
2426 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
2427 @*bulk erase flash planes first_plane to last_plane.
2428 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
2429 @cindex at91sam7 gpnvm
2430 @*set or clear a gpnvm bit for the processor
2433 @subsection STR9 specific commands
2434 @cindex STR9 specific commands
2435 @anchor{STR9 specific commands}
2436 These are flash specific commands when using the str9xpec driver.
2438 @item @b{str9xpec enable_turbo} <@var{num}>
2439 @cindex str9xpec enable_turbo
2440 @*enable turbo mode, will simply remove the str9 from the chain and talk
2441 directly to the embedded flash controller.
2442 @item @b{str9xpec disable_turbo} <@var{num}>
2443 @cindex str9xpec disable_turbo
2444 @*restore the str9 into JTAG chain.
2445 @item @b{str9xpec lock} <@var{num}>
2446 @cindex str9xpec lock
2447 @*lock str9 device. The str9 will only respond to an unlock command that will
2449 @item @b{str9xpec unlock} <@var{num}>
2450 @cindex str9xpec unlock
2451 @*unlock str9 device.
2452 @item @b{str9xpec options_read} <@var{num}>
2453 @cindex str9xpec options_read
2454 @*read str9 option bytes.
2455 @item @b{str9xpec options_write} <@var{num}>
2456 @cindex str9xpec options_write
2457 @*write str9 option bytes.
2460 Note: Before using the str9xpec driver here is some background info to help
2461 you better understand how the drivers works. OpenOCD has two flash drivers for
2465 Standard driver @option{str9x} programmed via the str9 core. Normally used for
2466 flash programming as it is faster than the @option{str9xpec} driver.
2468 Direct programming @option{str9xpec} using the flash controller. This is an
2469 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
2470 core does not need to be running to program using this flash driver. Typical use
2471 for this driver is locking/unlocking the target and programming the option bytes.
2474 Before we run any commands using the @option{str9xpec} driver we must first disable
2475 the str9 core. This example assumes the @option{str9xpec} driver has been
2476 configured for flash bank 0.
2478 # assert srst, we do not want core running
2479 # while accessing str9xpec flash driver
2481 # turn off target polling
2484 str9xpec enable_turbo 0
2486 str9xpec options_read 0
2487 # re-enable str9 core
2488 str9xpec disable_turbo 0
2492 The above example will read the str9 option bytes.
2493 When performing a unlock remember that you will not be able to halt the str9 - it
2494 has been locked. Halting the core is not required for the @option{str9xpec} driver
2495 as mentioned above, just issue the commands above manually or from a telnet prompt.
2497 @subsection STR9 configuration
2498 @cindex STR9 configuration
2500 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
2501 <@var{BBADR}> <@var{NBBADR}>
2502 @cindex str9x flash_config
2503 @*Configure str9 flash controller.
2505 e.g. str9x flash_config 0 4 2 0 0x80000
2507 BBSR - Boot Bank Size register
2508 NBBSR - Non Boot Bank Size register
2509 BBADR - Boot Bank Start Address register
2510 NBBADR - Boot Bank Start Address register
2514 @subsection STR9 option byte configuration
2515 @cindex STR9 option byte configuration
2517 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
2518 @cindex str9xpec options_cmap
2519 @*configure str9 boot bank.
2520 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
2521 @cindex str9xpec options_lvdthd
2522 @*configure str9 lvd threshold.
2523 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
2524 @cindex str9xpec options_lvdsel
2525 @*configure str9 lvd source.
2526 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
2527 @cindex str9xpec options_lvdwarn
2528 @*configure str9 lvd reset warning source.
2531 @subsection STM32x specific commands
2532 @cindex STM32x specific commands
2534 These are flash specific commands when using the stm32x driver.
2536 @item @b{stm32x lock} <@var{num}>
2538 @*lock stm32 device.
2539 @item @b{stm32x unlock} <@var{num}>
2540 @cindex stm32x unlock
2541 @*unlock stm32 device.
2542 @item @b{stm32x options_read} <@var{num}>
2543 @cindex stm32x options_read
2544 @*read stm32 option bytes.
2545 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
2546 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
2547 @cindex stm32x options_write
2548 @*write stm32 option bytes.
2549 @item @b{stm32x mass_erase} <@var{num}>
2550 @cindex stm32x mass_erase
2551 @*mass erase flash memory.
2554 @subsection Stellaris specific commands
2555 @cindex Stellaris specific commands
2557 These are flash specific commands when using the Stellaris driver.
2559 @item @b{stellaris mass_erase} <@var{num}>
2560 @cindex stellaris mass_erase
2561 @*mass erase flash memory.
2564 @node NAND Flash Commands
2565 @chapter NAND Flash Commands
2568 Compared to NOR or SPI flash, NAND devices are inexpensive
2569 and high density. Today's NAND chips, and multi-chip modules,
2570 commonly hold multiple GigaBytes of data.
2572 NAND chips consist of a number of ``erase blocks'' of a given
2573 size (such as 128 KBytes), each of which is divided into a
2574 number of pages (of perhaps 512 or 2048 bytes each). Each
2575 page of a NAND flash has an ``out of band'' (OOB) area to hold
2576 Error Correcting Code (ECC) and other metadata, usually 16 bytes
2577 of OOB for every 512 bytes of page data.
2579 One key characteristic of NAND flash is that its error rate
2580 is higher than that of NOR flash. In normal operation, that
2581 ECC is used to correct and detect errors. However, NAND
2582 blocks can also wear out and become unusable; those blocks
2583 are then marked "bad". NAND chips are even shipped from the
2584 manufacturer with a few bad blocks. The highest density chips
2585 use a technology (MLC) that wears out more quickly, so ECC
2586 support is increasingly important as a way to detect blocks
2587 that have begun to fail, and help to preserve data integrity
2588 with techniques such as wear leveling.
2590 Software is used to manage the ECC. Some controllers don't
2591 support ECC directly; in those cases, software ECC is used.
2592 Other controllers speed up the ECC calculations with hardware.
2593 Single-bit error correction hardware is routine. Controllers
2594 geared for newer MLC chips may correct 4 or more errors for
2595 every 512 bytes of data.
2597 You will need to make sure that any data you write using
2598 OpenOCD includes the apppropriate kind of ECC. For example,
2599 that may mean passing the @code{oob_softecc} flag when
2600 writing NAND data, or ensuring that the correct hardware
2603 The basic steps for using NAND devices include:
2605 @item Declare via the command @command{nand device}
2606 @* Do this in a board-specific configuration file,
2607 passing parameters as needed by the controller.
2608 @item Configure each device using @command{nand probe}.
2609 @* Do this only after the associated target is set up,
2610 such as in its reset-init script or in procures defined
2611 to access that device.
2612 @item Operate on the flash via @command{nand subcommand}
2613 @* Often commands to manipulate the flash are typed by a human, or run
2614 via a script in some automated way. Common task include writing a
2615 boot loader, operating system, or other data needed to initialize or
2619 @section NAND Configuration Commands
2620 @cindex NAND configuration
2622 NAND chips must be declared in configuration scripts,
2623 plus some additional configuration that's done after
2624 OpenOCD has initialized.
2626 @deffn {Config Command} {nand device} controller target [configparams...]
2627 Declares a NAND device, which can be read and written to
2628 after it has been configured through @command{nand probe}.
2629 In OpenOCD, devices are single chips; this is unlike some
2630 operating systems, which may manage multiple chips as if
2631 they were a single (larger) device.
2632 In some cases, configuring a device will activate extra
2633 commands; see the controller-specific documentation.
2635 @b{NOTE:} This command is not available after OpenOCD
2636 initialization has completed. Use it in board specific
2637 configuration files, not interactively.
2640 @item @var{controller} ... identifies a the controller driver
2641 associated with the NAND device being declared.
2642 @xref{NAND Driver List}.
2643 @item @var{target} ... names the target used when issuing
2644 commands to the NAND controller.
2645 @comment Actually, it's currently a controller-specific parameter...
2646 @item @var{configparams} ... controllers may support, or require,
2647 additional parameters. See the controller-specific documentation
2648 for more information.
2652 @deffn Command {nand list}
2653 Prints a one-line summary of each device declared
2654 using @command{nand device}, numbered from zero.
2655 Note that un-probed devices show no details.
2658 @deffn Command {nand probe} num
2659 Probes the specified device to determine key characteristics
2660 like its page and block sizes, and how many blocks it has.
2661 The @var{num} parameter is the value shown by @command{nand list}.
2662 You must (successfully) probe a device before you can use
2663 it with most other NAND commands.
2666 @section Erasing, Reading, Writing to NAND Flash
2668 @deffn Command {nand dump} num filename offset length [oob_option]
2669 @cindex NAND reading
2670 Reads binary data from the NAND device and writes it to the file,
2671 starting at the specified offset.
2672 The @var{num} parameter is the value shown by @command{nand list}.
2674 Use a complete path name for @var{filename}, so you don't depend
2675 on the directory used to start the OpenOCD server.
2677 The @var{offset} and @var{length} must be exact multiples of the
2678 device's page size. They describe a data region; the OOB data
2679 associated with each such page may also be accessed.
2681 @b{NOTE:} At the time this text was written, no error correction
2682 was done on the data that's read, unless raw access was disabled
2683 and the underlying NAND controller driver had a @code{read_page}
2684 method which handled that error correction.
2686 By default, only page data is saved to the specified file.
2687 Use an @var{oob_option} parameter to save OOB data:
2689 @item no oob_* parameter
2690 @*Output file holds only page data; OOB is discarded.
2691 @item @code{oob_raw}
2692 @*Output file interleaves page data and OOB data;
2693 the file will be longer than "length" by the size of the
2694 spare areas associated with each data page.
2695 Note that this kind of "raw" access is different from
2696 what's implied by @command{nand raw_access}, which just
2697 controls whether a hardware-aware access method is used.
2698 @item @code{oob_only}
2699 @*Output file has only raw OOB data, and will
2700 be smaller than "length" since it will contain only the
2701 spare areas associated with each data page.
2705 @deffn Command {nand erase} num ...
2706 @cindex NAND erasing
2707 @b{NOTE:} Syntax is in flux.
2710 @deffn Command {nand write} num filename offset [option...]
2711 @cindex NAND writing
2712 Writes binary data from the file into the specified NAND device,
2713 starting at the specified offset. Those pages should already
2714 have been erased; you can't change zero bits to one bits.
2715 The @var{num} parameter is the value shown by @command{nand list}.
2717 Use a complete path name for @var{filename}, so you don't depend
2718 on the directory used to start the OpenOCD server.
2720 The @var{offset} must be an exact multiple of the device's page size.
2721 All data in the file will be written, assuming it doesn't run
2722 past the end of the device.
2723 Only full pages are written, and any extra space in the last
2724 page will be filled with 0xff bytes. (That includes OOB data,
2725 if that's being written.)
2727 @b{NOTE:} At the time this text was written, bad blocks are
2728 ignored. That is, this routine will not skip bad blocks,
2729 but will instead try to write them. This can cause problems.
2731 Provide at most one @var{option} parameter. With some
2732 NAND drivers, the meanings of these parameters may change
2733 if @command{nand raw_access} was used to disable hardware ECC.
2735 @item no oob_* parameter
2736 @*File has only page data, which is written.
2737 If raw acccess is in use, the OOB area will not be written.
2738 Otherwise, if the underlying NAND controller driver has
2739 a @code{write_page} routine, that routine may write the OOB
2740 with hardware-computed ECC data.
2741 @item @code{oob_only}
2742 @*File has only raw OOB data, which is written to the OOB area.
2743 Each page's data area stays untouched. @i{This can be a dangerous
2744 option}, since it can invalidate the ECC data.
2745 You may need to force raw access to use this mode.
2746 @item @code{oob_raw}
2747 @*File interleaves data and OOB data, both of which are written
2748 If raw access is enabled, the data is written first, then the
2750 Otherwise, if the underlying NAND controller driver has
2751 a @code{write_page} routine, that routine may modify the OOB
2752 before it's written, to include hardware-computed ECC data.
2753 @item @code{oob_softecc}
2754 @*File has only page data, which is written.
2755 The OOB area is filled with 0xff, except for a standard 1-bit
2756 software ECC code stored in conventional locations.
2757 You might need to force raw access to use this mode, to prevent
2758 the underlying driver from applying hardware ECC.
2759 @item @code{oob_softecc_kw}
2760 @*File has only page data, which is written.
2761 The OOB area is filled with 0xff, except for a 4-bit software ECC
2762 specific to the boot ROM in Marvell Kirkwood SoCs.
2763 You might need to force raw access to use this mode, to prevent
2764 the underlying driver from applying hardware ECC.
2768 @section Other NAND commands
2769 @cindex NAND other commands
2771 @deffn Command {nand check_bad} num ...
2772 @b{NOTE:} Syntax is in flux.
2775 @deffn Command {nand info} num
2776 The @var{num} parameter is the value shown by @command{nand list}.
2777 This prints the one-line summary from "nand list", plus for
2778 devices which have been probed this also prints any known
2779 status for each block.
2782 @deffn Command {nand raw_access} num <enable|disable>
2783 Sets or clears an flag affecting how page I/O is done.
2784 The @var{num} parameter is the value shown by @command{nand list}.
2786 This flag is cleared (disabled) by default, but changing that
2787 value won't affect all NAND devices. The key factor is whether
2788 the underlying driver provides @code{read_page} or @code{write_page}
2789 methods. If it doesn't provide those methods, the setting of
2790 this flag is irrelevant; all access is effectively ``raw''.
2792 When those methods exist, they are normally used when reading
2793 data (@command{nand dump} or reading bad block markers) or
2794 writing it (@command{nand write}). However, enabling
2795 raw access (setting the flag) prevents use of those methods,
2796 bypassing hardware ECC logic.
2797 @i{This can be a dangerous option}, since writing blocks
2798 with the wrong ECC data can cause them to be marked as bad.
2801 @section NAND Drivers; Driver-specific Options and Commands
2802 @anchor{NAND Driver List}
2803 As noted above, the @command{nand device} command allows
2804 driver-specific options and behaviors.
2805 Some controllers also activate controller-specific commands.
2807 @deffn {NAND Driver} lpc3180
2808 These controllers require an extra @command{nand device}
2809 parameter: the clock rate used by the controller.
2810 @deffn Command {nand lpc3180 select} num [mlc|slc]
2811 Configures use of the MLC or SLC controller mode.
2812 MLC implies use of hardware ECC.
2813 The @var{num} parameter is the value shown by @command{nand list}.
2816 At this writing, this driver includes @code{write_page}
2817 and @code{read_page} methods. Using @command{nand raw_access}
2818 to disable those methods will prevent use of hardware ECC
2819 in the MLC controller mode, but won't change SLC behavior.
2821 @comment current lpc3180 code won't issue 5-byte address cycles
2823 @deffn {NAND Driver} orion
2824 These controllers require an extra @command{nand device}
2825 parameter: the address of the controller.
2827 nand device orion 0xd8000000
2829 These controllers don't define any specialized commands.
2830 At this writing, their drivers don't include @code{write_page}
2831 or @code{read_page} methods, so @command{nand raw_access} won't
2832 change any behavior.
2835 @deffn {NAND Driver} {s3c2410, s3c2412, s3c2440, s3c2443}
2836 These S3C24xx family controllers don't have any special
2837 @command{nand device} options, and don't define any
2838 specialized commands.
2839 At this writing, their drivers don't include @code{write_page}
2840 or @code{read_page} methods, so @command{nand raw_access} won't
2841 change any behavior.
2844 @node General Commands
2845 @chapter General Commands
2848 The commands documented in this chapter here are common commands that
2849 you, as a human, may want to type and see the output of. Configuration type
2850 commands are documented elsewhere.
2854 @item @b{Source Of Commands}
2855 @* OpenOCD commands can occur in a configuration script (discussed
2856 elsewhere) or typed manually by a human or supplied programatically,
2857 or via one of several TCP/IP Ports.
2859 @item @b{From the human}
2860 @* A human should interact with the telnet interface (default port: 4444,
2861 or via GDB, default port 3333)
2863 To issue commands from within a GDB session, use the @option{monitor}
2864 command, e.g. use @option{monitor poll} to issue the @option{poll}
2865 command. All output is relayed through the GDB session.
2867 @item @b{Machine Interface}
2868 The Tcl interface's intent is to be a machine interface. The default Tcl
2873 @section Daemon Commands
2875 @subsection sleep [@var{msec}]
2877 @*Wait for n milliseconds before resuming. Useful in connection with script files
2878 (@var{script} command and @var{target_script} configuration).
2880 @subsection shutdown
2882 @*Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
2884 @subsection debug_level [@var{n}]
2886 @anchor{debug_level}
2887 @*Display or adjust debug level to n<0-3>
2889 @subsection fast [@var{enable|disable}]
2891 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
2892 downloads and fast memory access will work if the JTAG interface isn't too fast and
2893 the core doesn't run at a too low frequency. Note that this option only changes the default
2894 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
2897 The target specific "dangerous" optimisation tweaking options may come and go
2898 as more robust and user friendly ways are found to ensure maximum throughput
2899 and robustness with a minimum of configuration.
2901 Typically the "fast enable" is specified first on the command line:
2904 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
2907 @subsection echo <@var{message}>
2909 @*Output message to stdio. e.g. echo "Programming - please wait"
2911 @subsection log_output <@var{file}>
2913 @*Redirect logging to <file> (default: stderr)
2915 @subsection script <@var{file}>
2917 @*Execute commands from <file>
2918 See also: ``source [find FILENAME]''
2920 @section Target state handling
2921 @subsection power <@var{on}|@var{off}>
2923 @*Turn power switch to target on/off.
2924 No arguments: print status.
2925 Not all interfaces support this.
2927 @subsection reg [@option{#}|@option{name}] [value]
2929 @*Access a single register by its number[@option{#}] or by its [@option{name}].
2930 No arguments: list all available registers for the current target.
2931 Number or name argument: display a register.
2932 Number or name and value arguments: set register value.
2934 @subsection poll [@option{on}|@option{off}]
2936 @*Poll the target for its current state. If the target is in debug mode, architecture
2937 specific information about the current state is printed. An optional parameter
2938 allows continuous polling to be enabled and disabled.
2940 @subsection halt [@option{ms}]
2942 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
2943 Default [@option{ms}] is 5 seconds if no arg given.
2944 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
2945 will stop OpenOCD from waiting.
2947 @subsection wait_halt [@option{ms}]
2949 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
2950 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
2953 @subsection resume [@var{address}]
2955 @*Resume the target at its current code position, or at an optional address.
2956 OpenOCD will wait 5 seconds for the target to resume.
2958 @subsection step [@var{address}]
2960 @*Single-step the target at its current code position, or at an optional address.
2962 @subsection reset [@option{run}|@option{halt}|@option{init}]
2964 @*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
2966 With no arguments a "reset run" is executed
2970 @*Let the target run.
2973 @*Immediately halt the target (works only with certain configurations).
2976 @*Immediately halt the target, and execute the reset script (works only with certain
2980 @subsection soft_reset_halt
2982 @*Requesting target halt and executing a soft reset. This is often used
2983 when a target cannot be reset and halted. The target, after reset is
2984 released begins to execute code. OpenOCD attempts to stop the CPU and
2985 then sets the program counter back to the reset vector. Unfortunately
2986 the code that was executed may have left the hardware in an unknown
2990 @section Memory access commands
2992 display available RAM memory.
2993 @subsection Memory peek/poke type commands
2994 These commands allow accesses of a specific size to the memory
2995 system. Often these are used to configure the current target in some
2996 special way. For example - one may need to write certian values to the
2997 SDRAM controller to enable SDRAM.
3000 @item To change the current target see the ``targets'' (plural) command
3001 @item In system level scripts these commands are deprecated, please use the TARGET object versions.
3005 @item @b{mdw} <@var{addr}> [@var{count}]
3007 @*display memory words (32bit)
3008 @item @b{mdh} <@var{addr}> [@var{count}]
3010 @*display memory half-words (16bit)
3011 @item @b{mdb} <@var{addr}> [@var{count}]
3013 @*display memory bytes (8bit)
3014 @item @b{mww} <@var{addr}> <@var{value}>
3016 @*write memory word (32bit)
3017 @item @b{mwh} <@var{addr}> <@var{value}>
3019 @*write memory half-word (16bit)
3020 @item @b{mwb} <@var{addr}> <@var{value}>
3022 @*write memory byte (8bit)
3025 @section Image loading commands
3026 @subsection load_image
3027 @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3030 @*Load image <@var{file}> to target memory at <@var{address}>
3031 @subsection fast_load_image
3032 @b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3033 @cindex fast_load_image
3034 @anchor{fast_load_image}
3035 @*Normally you should be using @b{load_image} or GDB load. However, for
3036 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
3037 host), storing the image in memory and uploading the image to the target
3038 can be a way to upload e.g. multiple debug sessions when the binary does not change.
3039 Arguments are the same as @b{load_image}, but the image is stored in OpenOCD host
3040 memory, i.e. does not affect target. This approach is also useful when profiling
3041 target programming performance as I/O and target programming can easily be profiled
3043 @subsection fast_load
3047 @*Loads an image stored in memory by @b{fast_load_image} to the current target. Must be preceeded by fast_load_image.
3048 @subsection dump_image
3049 @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
3052 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
3053 (binary) <@var{file}>.
3054 @subsection verify_image
3055 @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3056 @cindex verify_image
3057 @*Verify <@var{file}> against target memory starting at <@var{address}>.
3058 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
3061 @section Breakpoint commands
3062 @cindex Breakpoint commands
3064 @item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
3066 @*set breakpoint <address> <length> [hw]
3067 @item @b{rbp} <@var{addr}>
3069 @*remove breakpoint <adress>
3070 @item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
3072 @*set watchpoint <address> <length> <r/w/a> [value] [mask]
3073 @item @b{rwp} <@var{addr}>
3075 @*remove watchpoint <adress>
3078 @section Misc Commands
3079 @cindex Other Target Commands
3081 @item @b{profile} <@var{seconds}> <@var{gmon.out}>
3083 Profiling samples the CPU's program counter as quickly as possible, which is useful for non-intrusive stochastic profiling.
3087 @section Target Specific Commands
3088 @cindex Target Specific Commands
3092 @section Architecture Specific Commands
3093 @cindex Architecture Specific Commands
3095 @subsection ARMV4/5 specific commands
3096 @cindex ARMV4/5 specific commands
3098 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
3099 or Intel XScale (XScale isn't supported yet).
3101 @item @b{armv4_5 reg}
3103 @*Display a list of all banked core registers, fetching the current value from every
3104 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
3106 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
3107 @cindex armv4_5 core_mode
3108 @*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
3109 The target is resumed in the currently set @option{core_mode}.
3112 @subsection ARM7/9 specific commands
3113 @cindex ARM7/9 specific commands
3115 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
3116 ARM920T or ARM926EJ-S.
3118 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
3119 @cindex arm7_9 dbgrq
3120 @*Enable use of the DBGRQ bit to force entry into debug mode. This should be
3121 safe for all but ARM7TDMI--S cores (like Philips LPC).
3122 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
3123 @cindex arm7_9 fast_memory_access
3124 @anchor{arm7_9 fast_memory_access}
3125 @*Allow OpenOCD to read and write memory without checking completion of
3126 the operation. This provides a huge speed increase, especially with USB JTAG
3127 cables (FT2232), but might be unsafe if used with targets running at very low
3128 speeds, like the 32kHz startup clock of an AT91RM9200.
3129 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
3130 @cindex arm7_9 dcc_downloads
3131 @*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
3132 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
3133 unsafe, especially with targets running at very low speeds. This command was introduced
3134 with OpenOCD rev. 60, and requires a few bytes of working area.
3137 @subsection ARM720T specific commands
3138 @cindex ARM720T specific commands
3141 @item @b{arm720t cp15} <@var{num}> [@var{value}]
3142 @cindex arm720t cp15
3143 @*display/modify cp15 register <@option{num}> [@option{value}].
3144 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
3145 @cindex arm720t md<bhw>_phys
3146 @*Display memory at physical address addr.
3147 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
3148 @cindex arm720t mw<bhw>_phys
3149 @*Write memory at physical address addr.
3150 @item @b{arm720t virt2phys} <@var{va}>
3151 @cindex arm720t virt2phys
3152 @*Translate a virtual address to a physical address.
3155 @subsection ARM9TDMI specific commands
3156 @cindex ARM9TDMI specific commands
3159 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
3160 @cindex arm9tdmi vector_catch
3161 @*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
3162 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
3163 @option{irq} @option{fiq}.
3165 Can also be used on other ARM9 based cores such as ARM966, ARM920T and ARM926EJ-S.
3168 @subsection ARM966E specific commands
3169 @cindex ARM966E specific commands
3172 @item @b{arm966e cp15} <@var{num}> [@var{value}]
3173 @cindex arm966e cp15
3174 @*display/modify cp15 register <@option{num}> [@option{value}].
3177 @subsection ARM920T specific commands
3178 @cindex ARM920T specific commands
3181 @item @b{arm920t cp15} <@var{num}> [@var{value}]
3182 @cindex arm920t cp15
3183 @*display/modify cp15 register <@option{num}> [@option{value}].
3184 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
3185 @cindex arm920t cp15i
3186 @*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
3187 @item @b{arm920t cache_info}
3188 @cindex arm920t cache_info
3189 @*Print information about the caches found. This allows to see whether your target
3190 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
3191 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
3192 @cindex arm920t md<bhw>_phys
3193 @*Display memory at physical address addr.
3194 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
3195 @cindex arm920t mw<bhw>_phys
3196 @*Write memory at physical address addr.
3197 @item @b{arm920t read_cache} <@var{filename}>
3198 @cindex arm920t read_cache
3199 @*Dump the content of ICache and DCache to a file.
3200 @item @b{arm920t read_mmu} <@var{filename}>
3201 @cindex arm920t read_mmu
3202 @*Dump the content of the ITLB and DTLB to a file.
3203 @item @b{arm920t virt2phys} <@var{va}>
3204 @cindex arm920t virt2phys
3205 @*Translate a virtual address to a physical address.
3208 @subsection ARM926EJ-S specific commands
3209 @cindex ARM926EJ-S specific commands
3212 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
3213 @cindex arm926ejs cp15
3214 @*display/modify cp15 register <@option{num}> [@option{value}].
3215 @item @b{arm926ejs cache_info}
3216 @cindex arm926ejs cache_info
3217 @*Print information about the caches found.
3218 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
3219 @cindex arm926ejs md<bhw>_phys
3220 @*Display memory at physical address addr.
3221 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
3222 @cindex arm926ejs mw<bhw>_phys
3223 @*Write memory at physical address addr.
3224 @item @b{arm926ejs virt2phys} <@var{va}>
3225 @cindex arm926ejs virt2phys
3226 @*Translate a virtual address to a physical address.
3229 @subsection CORTEX_M3 specific commands
3230 @cindex CORTEX_M3 specific commands
3233 @item @b{cortex_m3 maskisr} <@var{on}|@var{off}>
3234 @cindex cortex_m3 maskisr
3235 @*Enable masking (disabling) interrupts during target step/resume.
3239 @section Debug commands
3240 @cindex Debug commands
3241 The following commands give direct access to the core, and are most likely
3242 only useful while debugging OpenOCD.
3244 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
3245 @cindex arm7_9 write_xpsr
3246 @*Immediately write either the current program status register (CPSR) or the saved
3247 program status register (SPSR), without changing the register cache (as displayed
3248 by the @option{reg} and @option{armv4_5 reg} commands).
3249 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
3250 <@var{0=cpsr},@var{1=spsr}>
3251 @cindex arm7_9 write_xpsr_im8
3252 @*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
3253 operation (similar to @option{write_xpsr}).
3254 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
3255 @cindex arm7_9 write_core_reg
3256 @*Write a core register, without changing the register cache (as displayed by the
3257 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
3258 encoding of the [M4:M0] bits of the PSR.
3261 @section Target Requests
3262 @cindex Target Requests
3263 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
3264 See libdcc in the contrib dir for more details.
3266 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}|@var{charmsg}>
3267 @cindex target_request debugmsgs
3268 @*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running. @var{charmsg} receives messages if Linux kernel ``Kernel low-level debugging via EmbeddedICE DCC channel'' option is enabled.
3272 @chapter JTAG Commands
3273 @cindex JTAG Commands
3274 Generally most people will not use the bulk of these commands. They
3275 are mostly used by the OpenOCD developers or those who need to
3276 directly manipulate the JTAG taps.
3278 In general these commands control JTAG taps at a very low level. For
3279 example if you need to control a JTAG Route Controller (i.e.: the
3280 OMAP3530 on the Beagle Board has one) you might use these commands in
3281 a script or an event procedure.
3285 @item @b{scan_chain}
3287 @*Print current scan chain configuration.
3288 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
3290 @*Toggle reset lines.
3291 @item @b{endstate} <@var{tap_state}>
3293 @*Finish JTAG operations in <@var{tap_state}>.
3294 @item @b{runtest} <@var{num_cycles}>
3296 @*Move to Run-Test/Idle, and execute <@var{num_cycles}>
3297 @item @b{statemove} [@var{tap_state}]
3299 @*Move to current endstate or [@var{tap_state}]
3300 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
3302 @*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
3303 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
3305 @*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
3306 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
3307 @cindex verify_ircapture
3308 @*Verify value captured during Capture-IR. Default is enabled.
3309 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
3311 @*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
3312 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
3314 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
3319 Available tap_states are:
3359 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
3360 be used to access files on PCs (either the developer's PC or some other PC).
3362 The way this works on the ZY1000 is to prefix a filename by
3363 "/tftp/ip/" and append the TFTP path on the TFTP
3364 server (tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf" will
3365 load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
3366 if the file was hosted on the embedded host.
3368 In order to achieve decent performance, you must choose a TFTP server
3369 that supports a packet size bigger than the default packet size (512 bytes). There
3370 are numerous TFTP servers out there (free and commercial) and you will have to do
3371 a bit of googling to find something that fits your requirements.
3373 @node Sample Scripts
3374 @chapter Sample Scripts
3377 This page shows how to use the Target Library.
3379 The configuration script can be divided into the following sections:
3381 @item Daemon configuration
3383 @item JTAG scan chain
3384 @item Target configuration
3385 @item Flash configuration
3388 Detailed information about each section can be found at OpenOCD configuration.
3390 @section AT91R40008 example
3391 @cindex AT91R40008 example
3392 To start OpenOCD with a target script for the AT91R40008 CPU and reset
3393 the CPU upon startup of the OpenOCD daemon.
3395 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
3399 @node GDB and OpenOCD
3400 @chapter GDB and OpenOCD
3401 @cindex GDB and OpenOCD
3402 OpenOCD complies with the remote gdbserver protocol, and as such can be used
3403 to debug remote targets.
3405 @section Connecting to GDB
3406 @cindex Connecting to GDB
3407 @anchor{Connecting to GDB}
3408 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
3409 instance GDB 6.3 has a known bug that produces bogus memory access
3410 errors, which has since been fixed: look up 1836 in
3411 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
3413 @*OpenOCD can communicate with GDB in two ways:
3416 A socket (TCP/IP) connection is typically started as follows:
3418 target remote localhost:3333
3420 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
3422 A pipe connection is typically started as follows:
3424 target remote | openocd --pipe
3426 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
3427 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
3431 @*To see a list of available OpenOCD commands type @option{monitor help} on the
3434 OpenOCD supports the gdb @option{qSupported} packet, this enables information
3435 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
3436 packet size and the device's memory map.
3438 Previous versions of OpenOCD required the following GDB options to increase
3439 the packet size and speed up GDB communication:
3441 set remote memory-write-packet-size 1024
3442 set remote memory-write-packet-size fixed
3443 set remote memory-read-packet-size 1024
3444 set remote memory-read-packet-size fixed
3446 This is now handled in the @option{qSupported} PacketSize and should not be required.
3448 @section Programming using GDB
3449 @cindex Programming using GDB
3451 By default the target memory map is sent to GDB. This can be disabled by
3452 the following OpenOCD configuration option:
3454 gdb_memory_map disable
3456 For this to function correctly a valid flash configuration must also be set
3457 in OpenOCD. For faster performance you should also configure a valid
3460 Informing GDB of the memory map of the target will enable GDB to protect any
3461 flash areas of the target and use hardware breakpoints by default. This means
3462 that the OpenOCD option @option{gdb_breakpoint_override} is not required when
3463 using a memory map. @xref{gdb_breakpoint_override}.
3465 To view the configured memory map in GDB, use the GDB command @option{info mem}
3466 All other unassigned addresses within GDB are treated as RAM.
3468 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
3469 This can be changed to the old behaviour by using the following GDB command
3471 set mem inaccessible-by-default off
3474 If @option{gdb_flash_program enable} is also used, GDB will be able to
3475 program any flash memory using the vFlash interface.
3477 GDB will look at the target memory map when a load command is given, if any
3478 areas to be programmed lie within the target flash area the vFlash packets
3481 If the target needs configuring before GDB programming, an event
3482 script can be executed:
3484 $_TARGETNAME configure -event EVENTNAME BODY
3487 To verify any flash programming the GDB command @option{compare-sections}
3490 @node Tcl Scripting API
3491 @chapter Tcl Scripting API
3492 @cindex Tcl Scripting API
3496 The commands are stateless. E.g. the telnet command line has a concept
3497 of currently active target, the Tcl API proc's take this sort of state
3498 information as an argument to each proc.
3500 There are three main types of return values: single value, name value
3501 pair list and lists.
3503 Name value pair. The proc 'foo' below returns a name/value pair
3509 > set foo(you) Oyvind
3510 > set foo(mouse) Micky
3511 > set foo(duck) Donald
3519 me Duane you Oyvind mouse Micky duck Donald
3521 Thus, to get the names of the associative array is easy:
3523 foreach { name value } [set foo] {
3524 puts "Name: $name, Value: $value"
3528 Lists returned must be relatively small. Otherwise a range
3529 should be passed in to the proc in question.
3531 @section Internal low-level Commands
3533 By low-level, the intent is a human would not directly use these commands.
3535 Low-level commands are (should be) prefixed with "openocd_", e.g. openocd_flash_banks
3536 is the low level API upon which "flash banks" is implemented.
3539 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
3541 Read memory and return as a Tcl array for script processing
3542 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
3544 Convert a Tcl array to memory locations and write the values
3545 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
3547 Return information about the flash banks
3550 OpenOCD commands can consist of two words, e.g. "flash banks". The
3551 startup.tcl "unknown" proc will translate this into a Tcl proc
3552 called "flash_banks".
3554 @section OpenOCD specific Global Variables
3558 Real Tcl has ::tcl_platform(), and platform::identify, and many other
3559 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
3560 holds one of the following values:
3563 @item @b{winxx} Built using Microsoft Visual Studio
3564 @item @b{linux} Linux is the underlying operating sytem
3565 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
3566 @item @b{cygwin} Running under Cygwin
3567 @item @b{mingw32} Running under MingW32
3568 @item @b{other} Unknown, none of the above.
3571 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
3574 @chapter Deprecated/Removed Commands
3575 @cindex Deprecated/Removed Commands
3576 Certain OpenOCD commands have been deprecated/removed during the various revisions.
3579 @item @b{arm7_9 fast_writes}
3580 @cindex arm7_9 fast_writes
3581 @*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}.
3582 @item @b{arm7_9 force_hw_bkpts}
3583 @cindex arm7_9 force_hw_bkpts
3584 @*Use @option{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
3585 for flash if the GDB memory map has been set up(default when flash is declared in
3586 target configuration). @xref{gdb_breakpoint_override}.
3587 @item @b{arm7_9 sw_bkpts}
3588 @cindex arm7_9 sw_bkpts
3589 @*On by default. See also @option{gdb_breakpoint_override}. @xref{gdb_breakpoint_override}.
3590 @item @b{daemon_startup}
3591 @cindex daemon_startup
3592 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
3593 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
3594 and @option{target cortex_m3 little reset_halt 0}.
3595 @item @b{dump_binary}
3597 @*use @option{dump_image} command with same args. @xref{dump_image}.
3598 @item @b{flash erase}
3600 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
3601 @item @b{flash write}
3603 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
3604 @item @b{flash write_binary}
3605 @cindex flash write_binary
3606 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
3607 @item @b{flash auto_erase}
3608 @cindex flash auto_erase
3609 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
3610 @item @b{load_binary}
3612 @*use @option{load_image} command with same args. @xref{load_image}.
3613 @item @b{run_and_halt_time}
3614 @cindex run_and_halt_time
3615 @*This command has been removed for simpler reset behaviour, it can be simulated with the
3622 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
3624 @*use the create subcommand of @option{target}.
3625 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
3626 @cindex target_script
3627 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
3628 @item @b{working_area}
3629 @cindex working_area
3630 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
3637 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
3639 @cindex adaptive clocking
3642 In digital circuit design it is often refered to as ``clock
3643 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
3644 operating at some speed, your target is operating at another. The two
3645 clocks are not synchronised, they are ``asynchronous''
3647 In order for the two to work together they must be synchronised. Otherwise
3648 the two systems will get out of sync with each other and nothing will
3649 work. There are 2 basic options:
3652 Use a special circuit.
3654 One clock must be some multiple slower than the other.
3657 @b{Does this really matter?} For some chips and some situations, this
3658 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
3659 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
3660 program/enable the oscillators and eventually the main clock. It is in
3661 those critical times you must slow the JTAG clock to sometimes 1 to
3664 Imagine debugging a 500MHz ARM926 hand held battery powered device
3665 that ``deep sleeps'' at 32kHz between every keystroke. It can be
3668 @b{Solution #1 - A special circuit}
3670 In order to make use of this, your JTAG dongle must support the RTCK
3671 feature. Not all dongles support this - keep reading!
3673 The RTCK signal often found in some ARM chips is used to help with
3674 this problem. ARM has a good description of the problem described at
3675 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
3676 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
3677 work? / how does adaptive clocking work?''.
3679 The nice thing about adaptive clocking is that ``battery powered hand
3680 held device example'' - the adaptiveness works perfectly all the
3681 time. One can set a break point or halt the system in the deep power
3682 down code, slow step out until the system speeds up.
3684 @b{Solution #2 - Always works - but may be slower}
3686 Often this is a perfectly acceptable solution.
3688 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
3689 the target clock speed. But what that ``magic division'' is varies
3690 depending on the chips on your board. @b{ARM rule of thumb} Most ARM
3691 based systems require an 8:1 division. @b{Xilinx rule of thumb} is
3692 1/12 the clock speed.
3694 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
3696 You can still debug the 'low power' situations - you just need to
3697 manually adjust the clock speed at every step. While painful and
3698 tedious, it is not always practical.
3700 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
3701 have a special debug mode in your application that does a ``high power
3702 sleep''. If you are careful - 98% of your problems can be debugged
3705 To set the JTAG frequency use the command:
3713 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
3715 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
3716 around Windows filenames.
3729 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
3731 Make sure you have Cygwin installed, or at least a version of OpenOCD that
3732 claims to come with all the necessary DLLs. When using Cygwin, try launching
3733 OpenOCD from the Cygwin shell.
3735 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
3736 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
3737 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
3739 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
3740 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
3741 software breakpoints consume one of the two available hardware breakpoints.
3743 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
3745 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
3746 clock at the time you're programming the flash. If you've specified the crystal's
3747 frequency, make sure the PLL is disabled. If you've specified the full core speed
3748 (e.g. 60MHz), make sure the PLL is enabled.
3750 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
3751 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
3752 out while waiting for end of scan, rtck was disabled".
3754 Make sure your PC's parallel port operates in EPP mode. You might have to try several
3755 settings in your PC BIOS (ECP, EPP, and different versions of those).
3757 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
3758 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
3759 memory read caused data abort".
3761 The errors are non-fatal, and are the result of GDB trying to trace stack frames
3762 beyond the last valid frame. It might be possible to prevent this by setting up
3763 a proper "initial" stack frame, if you happen to know what exactly has to
3764 be done, feel free to add this here.
3766 @b{Simple:} In your startup code - push 8 registers of zeros onto the
3767 stack before calling main(). What GDB is doing is ``climbing'' the run
3768 time stack by reading various values on the stack using the standard
3769 call frame for the target. GDB keeps going - until one of 2 things
3770 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
3771 stackframes have been processed. By pushing zeros on the stack, GDB
3774 @b{Debugging Interrupt Service Routines} - In your ISR before you call
3775 your C code, do the same - artifically push some zeros onto the stack,
3776 remember to pop them off when the ISR is done.
3778 @b{Also note:} If you have a multi-threaded operating system, they
3779 often do not @b{in the intrest of saving memory} waste these few
3783 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
3784 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
3786 This warning doesn't indicate any serious problem, as long as you don't want to
3787 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
3788 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
3789 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
3790 independently. With this setup, it's not possible to halt the core right out of
3791 reset, everything else should work fine.
3793 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
3794 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
3795 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
3796 quit with an error message. Is there a stability issue with OpenOCD?
3798 No, this is not a stability issue concerning OpenOCD. Most users have solved
3799 this issue by simply using a self-powered USB hub, which they connect their
3800 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
3801 supply stable enough for the Amontec JTAGkey to be operated.
3803 @b{Laptops running on battery have this problem too...}
3805 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
3806 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
3807 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
3808 What does that mean and what might be the reason for this?
3810 First of all, the reason might be the USB power supply. Try using a self-powered
3811 hub instead of a direct connection to your computer. Secondly, the error code 4
3812 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
3813 chip ran into some sort of error - this points us to a USB problem.
3815 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
3816 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
3817 What does that mean and what might be the reason for this?
3819 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
3820 has closed the connection to OpenOCD. This might be a GDB issue.
3822 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
3823 are described, there is a parameter for specifying the clock frequency
3824 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
3825 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
3826 specified in kilohertz. However, I do have a quartz crystal of a
3827 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
3828 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
3831 No. The clock frequency specified here must be given as an integral number.
3832 However, this clock frequency is used by the In-Application-Programming (IAP)
3833 routines of the LPC2000 family only, which seems to be very tolerant concerning
3834 the given clock frequency, so a slight difference between the specified clock
3835 frequency and the actual clock frequency will not cause any trouble.
3837 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
3839 Well, yes and no. Commands can be given in arbitrary order, yet the
3840 devices listed for the JTAG scan chain must be given in the right
3841 order (jtag newdevice), with the device closest to the TDO-Pin being
3842 listed first. In general, whenever objects of the same type exist
3843 which require an index number, then these objects must be given in the
3844 right order (jtag newtap, targets and flash banks - a target
3845 references a jtag newtap and a flash bank references a target).
3847 You can use the ``scan_chain'' command to verify and display the tap order.
3849 Also, some commands can't execute until after @command{init} has been
3850 processed. Such commands include @command{nand probe} and everything
3851 else that needs to write to controller registers, perhaps for setting
3852 up DRAM and loading it with code.
3854 @item @b{JTAG Tap Order} JTAG tap order - command order
3856 Many newer devices have multiple JTAG taps. For example: ST
3857 Microsystems STM32 chips have two taps, a ``boundary scan tap'' and
3858 ``Cortex-M3'' tap. Example: The STM32 reference manual, Document ID:
3859 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
3860 connected to the boundary scan tap, which then connects to the
3861 Cortex-M3 tap, which then connects to the TDO pin.
3863 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
3864 (2) The boundary scan tap. If your board includes an additional JTAG
3865 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
3866 place it before or after the STM32 chip in the chain. For example:
3869 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
3870 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
3871 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
3872 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
3873 @item Xilinx TDO Pin -> OpenOCD TDO (input)
3876 The ``jtag device'' commands would thus be in the order shown below. Note:
3879 @item jtag newtap Xilinx tap -irlen ...
3880 @item jtag newtap stm32 cpu -irlen ...
3881 @item jtag newtap stm32 bs -irlen ...
3882 @item # Create the debug target and say where it is
3883 @item target create stm32.cpu -chain-position stm32.cpu ...
3887 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
3888 log file, I can see these error messages: Error: arm7_9_common.c:561
3889 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
3895 @node Tcl Crash Course
3896 @chapter Tcl Crash Course
3899 Not everyone knows Tcl - this is not intended to be a replacement for
3900 learning Tcl, the intent of this chapter is to give you some idea of
3901 how the Tcl scripts work.
3903 This chapter is written with two audiences in mind. (1) OpenOCD users
3904 who need to understand a bit more of how JIM-Tcl works so they can do
3905 something useful, and (2) those that want to add a new command to
3908 @section Tcl Rule #1
3909 There is a famous joke, it goes like this:
3911 @item Rule #1: The wife is always correct
3912 @item Rule #2: If you think otherwise, See Rule #1
3915 The Tcl equal is this:
3918 @item Rule #1: Everything is a string
3919 @item Rule #2: If you think otherwise, See Rule #1
3922 As in the famous joke, the consequences of Rule #1 are profound. Once
3923 you understand Rule #1, you will understand Tcl.
3925 @section Tcl Rule #1b
3926 There is a second pair of rules.
3928 @item Rule #1: Control flow does not exist. Only commands
3929 @* For example: the classic FOR loop or IF statement is not a control
3930 flow item, they are commands, there is no such thing as control flow
3932 @item Rule #2: If you think otherwise, See Rule #1
3933 @* Actually what happens is this: There are commands that by
3934 convention, act like control flow key words in other languages. One of
3935 those commands is the word ``for'', another command is ``if''.
3938 @section Per Rule #1 - All Results are strings
3939 Every Tcl command results in a string. The word ``result'' is used
3940 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
3941 Everything is a string}
3943 @section Tcl Quoting Operators
3944 In life of a Tcl script, there are two important periods of time, the
3945 difference is subtle.
3948 @item Evaluation Time
3951 The two key items here are how ``quoted things'' work in Tcl. Tcl has
3952 three primary quoting constructs, the [square-brackets] the
3953 @{curly-braces@} and ``double-quotes''
3955 By now you should know $VARIABLES always start with a $DOLLAR
3956 sign. BTW: To set a variable, you actually use the command ``set'', as
3957 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
3958 = 1'' statement, but without the equal sign.
3961 @item @b{[square-brackets]}
3962 @* @b{[square-brackets]} are command substitutions. It operates much
3963 like Unix Shell `back-ticks`. The result of a [square-bracket]
3964 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
3965 string}. These two statements are roughly identical:
3969 echo "The Date is: $X"
3972 puts "The Date is: $X"
3974 @item @b{``double-quoted-things''}
3975 @* @b{``double-quoted-things''} are just simply quoted
3976 text. $VARIABLES and [square-brackets] are expanded in place - the
3977 result however is exactly 1 string. @i{Remember Rule #1 - Everything
3981 puts "It is now \"[date]\", $x is in 1 hour"
3983 @item @b{@{Curly-Braces@}}
3984 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
3985 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
3986 'single-quote' operators in BASH shell scripts, with the added
3987 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
3988 nested 3 times@}@}@} NOTE: [date] is perhaps a bad example, as of
3989 28/nov/2008, Jim/OpenOCD does not have a date command.
3992 @section Consequences of Rule 1/2/3/4
3994 The consequences of Rule 1 are profound.
3996 @subsection Tokenisation & Execution.
3998 Of course, whitespace, blank lines and #comment lines are handled in
4001 As a script is parsed, each (multi) line in the script file is
4002 tokenised and according to the quoting rules. After tokenisation, that
4003 line is immedatly executed.
4005 Multi line statements end with one or more ``still-open''
4006 @{curly-braces@} which - eventually - closes a few lines later.
4008 @subsection Command Execution
4010 Remember earlier: There are no ``control flow''
4011 statements in Tcl. Instead there are COMMANDS that simply act like
4012 control flow operators.
4014 Commands are executed like this:
4017 @item Parse the next line into (argc) and (argv[]).
4018 @item Look up (argv[0]) in a table and call its function.
4019 @item Repeat until End Of File.
4022 It sort of works like this:
4025 ReadAndParse( &argc, &argv );
4027 cmdPtr = LookupCommand( argv[0] );
4029 (*cmdPtr->Execute)( argc, argv );
4033 When the command ``proc'' is parsed (which creates a procedure
4034 function) it gets 3 parameters on the command line. @b{1} the name of
4035 the proc (function), @b{2} the list of parameters, and @b{3} the body
4036 of the function. Not the choice of words: LIST and BODY. The PROC
4037 command stores these items in a table somewhere so it can be found by
4040 @subsection The FOR command
4042 The most interesting command to look at is the FOR command. In Tcl,
4043 the FOR command is normally implemented in C. Remember, FOR is a
4044 command just like any other command.
4046 When the ascii text containing the FOR command is parsed, the parser
4047 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
4051 @item The ascii text 'for'
4052 @item The start text
4053 @item The test expression
4058 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
4059 Remember @i{Rule #1 - Everything is a string.} The key point is this:
4060 Often many of those parameters are in @{curly-braces@} - thus the
4061 variables inside are not expanded or replaced until later.
4063 Remember that every Tcl command looks like the classic ``main( argc,
4064 argv )'' function in C. In JimTCL - they actually look like this:
4068 MyCommand( Jim_Interp *interp,
4070 Jim_Obj * const *argvs );
4073 Real Tcl is nearly identical. Although the newer versions have
4074 introduced a byte-code parser and intepreter, but at the core, it
4075 still operates in the same basic way.
4077 @subsection FOR command implementation
4079 To understand Tcl it is perhaps most helpful to see the FOR
4080 command. Remember, it is a COMMAND not a control flow structure.
4082 In Tcl there are two underlying C helper functions.
4084 Remember Rule #1 - You are a string.
4086 The @b{first} helper parses and executes commands found in an ascii
4087 string. Commands can be seperated by semicolons, or newlines. While
4088 parsing, variables are expanded via the quoting rules.
4090 The @b{second} helper evaluates an ascii string as a numerical
4091 expression and returns a value.
4093 Here is an example of how the @b{FOR} command could be
4094 implemented. The pseudo code below does not show error handling.
4096 void Execute_AsciiString( void *interp, const char *string );
4098 int Evaluate_AsciiExpression( void *interp, const char *string );
4101 MyForCommand( void *interp,
4106 SetResult( interp, "WRONG number of parameters");
4110 // argv[0] = the ascii string just like C
4112 // Execute the start statement.
4113 Execute_AsciiString( interp, argv[1] );
4117 i = Evaluate_AsciiExpression(interp, argv[2]);
4122 Execute_AsciiString( interp, argv[3] );
4124 // Execute the LOOP part
4125 Execute_AsciiString( interp, argv[4] );
4129 SetResult( interp, "" );
4134 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
4135 in the same basic way.
4137 @section OpenOCD Tcl Usage
4139 @subsection source and find commands
4140 @b{Where:} In many configuration files
4141 @* Example: @b{ source [find FILENAME] }
4142 @*Remember the parsing rules
4144 @item The FIND command is in square brackets.
4145 @* The FIND command is executed with the parameter FILENAME. It should
4146 find the full path to the named file. The RESULT is a string, which is
4147 substituted on the orginal command line.
4148 @item The command source is executed with the resulting filename.
4149 @* SOURCE reads a file and executes as a script.
4151 @subsection format command
4152 @b{Where:} Generally occurs in numerous places.
4153 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
4159 puts [format "The answer: %d" [expr $x * $y]]
4162 @item The SET command creates 2 variables, X and Y.
4163 @item The double [nested] EXPR command performs math
4164 @* The EXPR command produces numerical result as a string.
4166 @item The format command is executed, producing a single string
4167 @* Refer to Rule #1.
4168 @item The PUTS command outputs the text.
4170 @subsection Body or Inlined Text
4171 @b{Where:} Various TARGET scripts.
4174 proc someproc @{@} @{
4175 ... multiple lines of stuff ...
4177 $_TARGETNAME configure -event FOO someproc
4178 #2 Good - no variables
4179 $_TARGETNAME confgure -event foo "this ; that;"
4180 #3 Good Curly Braces
4181 $_TARGETNAME configure -event FOO @{
4184 #4 DANGER DANGER DANGER
4185 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
4188 @item The $_TARGETNAME is an OpenOCD variable convention.
4189 @*@b{$_TARGETNAME} represents the last target created, the value changes
4190 each time a new target is created. Remember the parsing rules. When
4191 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
4192 the name of the target which happens to be a TARGET (object)
4194 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
4195 @*There are 4 examples:
4197 @item The TCLBODY is a simple string that happens to be a proc name
4198 @item The TCLBODY is several simple commands seperated by semicolons
4199 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
4200 @item The TCLBODY is a string with variables that get expanded.
4203 In the end, when the target event FOO occurs the TCLBODY is
4204 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
4205 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
4207 Remember the parsing rules. In case #3, @{curly-braces@} mean the
4208 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
4209 and the text is evaluated. In case #4, they are replaced before the
4210 ``Target Object Command'' is executed. This occurs at the same time
4211 $_TARGETNAME is replaced. In case #4 the date will never
4212 change. @{BTW: [date] is perhaps a bad example, as of 28/nov/2008,
4213 Jim/OpenOCD does not have a date command@}
4215 @subsection Global Variables
4216 @b{Where:} You might discover this when writing your own procs @* In
4217 simple terms: Inside a PROC, if you need to access a global variable
4218 you must say so. See also ``upvar''. Example:
4220 proc myproc @{ @} @{
4221 set y 0 #Local variable Y
4222 global x #Global variable X
4223 puts [format "X=%d, Y=%d" $x $y]
4226 @section Other Tcl Hacks
4227 @b{Dynamic variable creation}
4229 # Dynamically create a bunch of variables.
4230 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
4232 set vn [format "BIT%d" $x]
4236 set $vn [expr (1 << $x)]
4239 @b{Dynamic proc/command creation}
4241 # One "X" function - 5 uart functions.
4242 foreach who @{A B C D E@}
4243 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
4247 @node Target Library
4248 @chapter Target Library
4249 @cindex Target Library
4251 OpenOCD comes with a target configuration script library. These scripts can be
4252 used as-is or serve as a starting point.
4254 The target library is published together with the OpenOCD executable and
4255 the path to the target library is in the OpenOCD script search path.
4256 Similarly there are example scripts for configuring the JTAG interface.
4258 The command line below uses the example parport configuration script
4259 that ship with OpenOCD, then configures the str710.cfg target and
4260 finally issues the init and reset commands. The communication speed
4261 is set to 10kHz for reset and 8MHz for post reset.
4264 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
4267 To list the target scripts available:
4270 $ ls /usr/local/lib/openocd/target
4272 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
4273 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
4274 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
4275 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
4280 @node OpenOCD Concept Index
4281 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
4282 @comment case issue with ``Index.html'' and ``index.html''
4283 @comment Occurs when creating ``--html --no-split'' output
4284 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
4285 @unnumbered OpenOCD Concept Index
4289 @node OpenOCD Command Index
4290 @unnumbered OpenOCD Command Index