1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
29 Permission is granted to copy, distribute and/or modify this document
30 under the terms of the GNU Free Documentation License, Version 1.2 or
31 any later version published by the Free Software Foundation; with no
32 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
33 Texts. A copy of the license is included in the section entitled ``GNU
34 Free Documentation License''.
39 @titlefont{@emph{Open On-Chip Debugger:}}
41 @title OpenOCD User's Guide
42 @subtitle for release @value{VERSION}
43 @subtitle @value{UPDATED}
46 @vskip 0pt plus 1filll
55 @top OpenOCD User's Guide
61 * About:: About OpenOCD
62 * Developers:: OpenOCD Developers
63 * Building OpenOCD:: Building OpenOCD From SVN
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * Running:: Running OpenOCD
66 * Simple Configuration Files:: Simple Configuration Files
67 * Config File Guidelines:: Config File Guidelines
68 * About JIM-Tcl:: About JIM-Tcl
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * Tap Creation:: Tap Creation
73 * Target Configuration:: Target Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * General Commands:: General Commands
77 * JTAG Commands:: JTAG Commands
78 * Sample Scripts:: Sample Target Scripts
80 * GDB and OpenOCD:: Using GDB and OpenOCD
81 * Tcl Scripting API:: Tcl Scripting API
82 * Upgrading:: Deprecated/Removed Commands
83 * Target Library:: Target Library
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
100 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
101 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
106 @section What is OpenOCD?
108 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
109 in-system programming and boundary-scan testing for embedded target
112 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
113 with the JTAG (IEEE 1149.1) compliant taps on your target board.
115 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
116 based, parallel port based, and other standalone boxes that run
117 OpenOCD internally. @xref{JTAG Hardware Dongles}.
119 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
120 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
121 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
122 debugged via the GDB protocol.
124 @b{Flash Programing:} Flash writing is supported for external CFI
125 compatible NOR flashes (Intel and AMD/Spansion command set) and several
126 internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3, and
127 STM32x). Preliminary support for various NAND flash controllers
128 (LPC3180, Orion, S3C24xx, more) controller is included.
130 @section OpenOCD Web Site
132 The OpenOCD web site provides the latest public news from the community:
134 @uref{http://openocd.berlios.de/web/}
136 @section Latest User's Guide:
138 The user's guide you are now reading may not be the latest one
139 available. A version for more recent code may be available.
140 Its HTML form is published irregularly at:
142 @uref{http://openocd.berlios.de/doc/}
144 PDF form is likewise published at:
146 @uref{http://openocd.berlios.de/doc/pdf/}
148 @section OpenOCD User's Forum
150 There is an OpenOCD forum (phpBB) hosted by SparkFun:
152 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
156 @chapter OpenOCD Developer Resources
159 If you are interested in improving the state of OpenOCD's debugging and
160 testing support, new contributions will be welcome. Motivated developers
161 can produce new target, flash or interface drivers, improve the
162 documentation, as well as more conventional bug fixes and enhancements.
164 The resources in this chapter are available for developers wishing to explore
165 or expand the OpenOCD source code.
167 @section OpenOCD Subversion Repository
169 The ``Building From Source'' section provides instructions to retrieve
170 and and build the latest version of the OpenOCD source code.
171 @xref{Building OpenOCD}.
173 Developers that want to contribute patches to the OpenOCD system are
174 @b{strongly} encouraged to base their work off of the most recent trunk
175 revision. Patches created against older versions may require additional
176 work from their submitter in order to be updated for newer releases.
178 @section Doxygen Developer Manual
180 During the development of the 0.2.0 release, the OpenOCD project began
181 providing a Doxygen reference manual. This document contains more
182 technical information about the software internals, development
183 processes, and similar documentation:
185 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
187 This document is a work-in-progress, but contributions would be welcome
188 to fill in the gaps. All of the source files are provided in-tree,
189 listed in the Doxyfile configuration in the top of the repository trunk.
191 @section OpenOCD Developer Mailing List
193 The OpenOCD Developer Mailing List provides the primary means of
194 communication between developers:
196 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
198 All drivers developers are enouraged to also subscribe to the list of
199 SVN commits to keep pace with the ongoing changes:
201 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
204 @node Building OpenOCD
205 @chapter Building OpenOCD
208 @section Pre-Built Tools
209 If you are interested in getting actual work done rather than building
210 OpenOCD, then check if your interface supplier provides binaries for
211 you. Chances are that that binary is from some SVN version that is more
212 stable than SVN trunk where bleeding edge development takes place.
214 @section Packagers Please Read!
216 You are a @b{PACKAGER} of OpenOCD if you
219 @item @b{Sell dongles} and include pre-built binaries
220 @item @b{Supply tools} i.e.: A complete development solution
221 @item @b{Supply IDEs} like Eclipse, or RHIDE, etc.
222 @item @b{Build packages} i.e.: RPM files, or DEB files for a Linux Distro
225 As a @b{PACKAGER}, you will experience first reports of most issues.
226 When you fix those problems for your users, your solution may help
227 prevent hundreds (if not thousands) of other questions from other users.
229 If something does not work for you, please work to inform the OpenOCD
230 developers know how to improve the system or documentation to avoid
231 future problems, and follow-up to help us ensure the issue will be fully
232 resolved in our future releases.
234 That said, the OpenOCD developers would also like you to follow a few
238 @item @b{Always build with printer ports enabled.}
239 @item @b{Try to use LIBFTDI + LIBUSB where possible. You cover more bases.}
243 @item @b{Why YES to LIBFTDI + LIBUSB?}
245 @item @b{LESS} work - libusb perhaps already there
246 @item @b{LESS} work - identical code, multiple platforms
247 @item @b{MORE} dongles are supported
248 @item @b{MORE} platforms are supported
249 @item @b{MORE} complete solution
251 @item @b{Why not LIBFTDI + LIBUSB} (i.e.: ftd2xx instead)?
253 @item @b{LESS} speed - some say it is slower
254 @item @b{LESS} complex to distribute (external dependencies)
258 @section Building From Source
260 You can download the current SVN version with an SVN client of your choice from the
261 following repositories:
263 @uref{svn://svn.berlios.de/openocd/trunk}
267 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
269 Using the SVN command line client, you can use the following command to fetch the
270 latest version (make sure there is no (non-svn) directory called "openocd" in the
274 svn checkout svn://svn.berlios.de/openocd/trunk openocd
277 If you prefer GIT based tools, the @command{git-svn} package works too:
280 git svn clone -s svn://svn.berlios.de/openocd
283 Building OpenOCD from a repository requires a recent version of the
284 GNU autotools (autoconf >= 2.59 and automake >= 1.9).
285 For building on Windows,
286 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
287 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
288 paths, resulting in obscure dependency errors (This is an observation I've gathered
289 from the logs of one user - correct me if I'm wrong).
291 You further need the appropriate driver files, if you want to build support for
292 a FTDI FT2232 based interface:
295 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
296 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
297 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
298 homepage (@uref{http://www.amontec.com}). The JTAGkey uses a non-standard VID/PID.
301 libftdi is supported under Windows. Do not use versions earlier than 0.14.
303 In general, the D2XX driver provides superior performance (several times as fast),
304 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
305 a kernel module, only a user space library.
307 To build OpenOCD (on both Linux and Cygwin), use the following commands:
313 Bootstrap generates the configure script, and prepares building on your system.
316 ./configure [options, see below]
319 Configure generates the Makefiles used to build OpenOCD.
326 Make builds OpenOCD, and places the final executable in ./src/, the last step, ``make install'' is optional.
328 The configure script takes several options, specifying which JTAG interfaces
329 should be included (among other things):
333 @option{--enable-parport} - Enable building the PC parallel port driver.
335 @option{--enable-parport_ppdev} - Enable use of ppdev (/dev/parportN) for parport.
337 @option{--enable-parport_giveio} - Enable use of giveio for parport instead of ioperm.
339 @option{--enable-amtjtagaccel} - Enable building the Amontec JTAG-Accelerator driver.
341 @option{--enable-ecosboard} - Enable building support for eCosBoard based JTAG debugger.
343 @option{--enable-ioutil} - Enable ioutil functions - useful for standalone OpenOCD implementations.
345 @option{--enable-httpd} - Enable builtin httpd server - useful for standalone OpenOCD implementations.
347 @option{--enable-ep93xx} - Enable building support for EP93xx based SBCs.
349 @option{--enable-at91rm9200} - Enable building support for AT91RM9200 based SBCs.
351 @option{--enable-gw16012} - Enable building support for the Gateworks GW16012 JTAG programmer.
353 @option{--enable-ft2232_ftd2xx} - Numerous USB type ARM JTAG dongles use the FT2232C chip from this FTDICHIP.COM chip (closed source).
355 @option{--enable-ft2232_libftdi} - An open source (free) alternative to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin).
357 @option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c driver,
358 give the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
360 @option{--with-ftd2xx-linux-tardir=PATH} - If using FTDICHIP.COM ft2232c driver
361 on Linux, give the directory where the Linux driver's TAR.GZ file was unpacked.
363 @option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static. Specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note: 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}. The 'shared' value is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.
365 @option{--enable-presto_libftdi} - Enable building support for ASIX Presto programmer using the libftdi driver.
367 @option{--enable-presto_ftd2xx} - Enable building support for ASIX Presto programmer using the FTD2XX driver.
369 @option{--enable-usbprog} - Enable building support for the USBprog JTAG programmer.
371 @option{--enable-oocd_trace} - Enable building support for the OpenOCD+trace ETM capture device.
373 @option{--enable-jlink} - Enable building support for the Segger J-Link JTAG programmer.
375 @option{--enable-vsllink} - Enable building support for the Versaloon-Link JTAG programmer.
377 @option{--enable-rlink} - Enable building support for the Raisonance RLink JTAG programmer.
379 @option{--enable-arm-jtag-ew} - Enable building support for the Olimex ARM-JTAG-EW programmer.
381 @option{--enable-dummy} - Enable building the dummy port driver.
384 @section Parallel Port Dongles
386 If you want to access the parallel port using the PPDEV interface you have to specify
387 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
388 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
389 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
391 The same is true for the @option{--enable-parport_giveio} option, you have to
392 use both the @option{--enable-parport} AND the @option{--enable-parport_giveio} option if you want to use giveio instead of ioperm parallel port access method.
394 @section FT2232C Based USB Dongles
396 There are 2 methods of using the FTD2232, either (1) using the
397 FTDICHIP.COM closed source driver, or (2) the open (and free) driver
398 libftdi. Some claim the (closed) FTDICHIP.COM solution is faster.
400 The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux)
401 TAR.GZ file. You must unpack them ``some where'' convient. As of this
402 writing (12/26/2008) FTDICHIP does not supply means to install these
403 files ``in an appropriate place'' As a result, there are two
404 ``./configure'' options that help.
406 Below is an example build process:
409 @item Check out the latest version of ``openocd'' from SVN.
411 @item If you are using the FTDICHIP.COM driver, download
412 and unpack the Windows or Linux FTD2xx drivers
413 (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
414 If you are using the libftdi driver, install that package
415 (e.g. @command{apt-get install libftdi} on systems with APT).
418 /home/duane/ftd2xx.win32 => the Cygwin/Win32 ZIP file contents
419 /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents
422 @item Configure with options resembling the following.
425 @item Cygwin FTDICHIP solution:
427 ./configure --prefix=/home/duane/mytools \
428 --enable-ft2232_ftd2xx \
429 --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
432 @item Linux FTDICHIP solution:
434 ./configure --prefix=/home/duane/mytools \
435 --enable-ft2232_ftd2xx \
436 --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
439 @item Cygwin/Linux LIBFTDI solution ... assuming that
441 @item For Windows -- that the Windows port of LIBUSB is in place.
442 @item For Linux -- that libusb has been built/installed and is in place.
443 @item That libftdi has been built and installed (relies on libusb).
446 Then configure the libftdi solution like this:
449 ./configure --prefix=/home/duane/mytools \
450 --enable-ft2232_libftdi
454 @item Then just type ``make'', and perhaps ``make install''.
458 @section Miscellaneous Configure Options
462 @option{--disable-option-checking} - Ignore unrecognized @option{--enable} and @option{--with} options.
464 @option{--enable-gccwarnings} - Enable extra gcc warnings during build.
467 @option{--enable-release} - Enable building of an OpenOCD release, generally
468 this is for developers. It simply omits the svn version string when the
469 openocd @option{-v} is executed.
472 @node JTAG Hardware Dongles
473 @chapter JTAG Hardware Dongles
482 Defined: @b{dongle}: A small device that plugins into a computer and serves as
483 an adapter .... [snip]
485 In the OpenOCD case, this generally refers to @b{a small adapater} one
486 attaches to your computer via USB or the Parallel Printer Port. The
487 execption being the Zylin ZY1000 which is a small box you attach via
488 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
489 require any drivers to be installed on the developer PC. It also has
490 a built in web interface. It supports RTCK/RCLK or adaptive clocking
491 and has a built in relay to power cycle targets remotely.
494 @section Choosing a Dongle
496 There are three things you should keep in mind when choosing a dongle.
499 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
500 @item @b{Connection} Printer Ports - Does your computer have one?
501 @item @b{Connection} Is that long printer bit-bang cable practical?
502 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
505 @section Stand alone Systems
507 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
508 dongle, but a standalone box. The ZY1000 has the advantage that it does
509 not require any drivers installed on the developer PC. It also has
510 a built in web interface. It supports RTCK/RCLK or adaptive clocking
511 and has a built in relay to power cycle targets remotely.
513 @section USB FT2232 Based
515 There are many USB JTAG dongles on the market, many of them are based
516 on a chip from ``Future Technology Devices International'' (FTDI)
517 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
518 See: @url{http://www.ftdichip.com} for more information.
519 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
520 chips are starting to become available in JTAG adapters.
522 As of 28/Nov/2008, the following are supported:
526 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
528 @* See: @url{http://www.amontec.com/jtagkey.shtml}
530 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
532 @* See: @url{http://www.signalyzer.com}
533 @item @b{evb_lm3s811}
534 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
535 @item @b{olimex-jtag}
536 @* See: @url{http://www.olimex.com}
538 @* See: @url{http://www.tincantools.com}
539 @item @b{turtelizer2}
541 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
542 @url{http://www.ethernut.de}
544 @* Link: @url{http://www.hitex.com/index.php?id=383}
546 @* Link @url{http://www.hitex.com/stm32-stick}
547 @item @b{axm0432_jtag}
548 @* Axiom AXM-0432 Link @url{http://www.axman.com}
550 @* Link @url{http://www.hitex.com/index.php?id=cortino}
553 @section USB JLINK based
554 There are several OEM versions of the Segger @b{JLINK} adapter. It is
555 an example of a micro controller based JTAG adapter, it uses an
556 AT91SAM764 internally.
559 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
560 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
561 @item @b{SEGGER JLINK}
562 @* Link: @url{http://www.segger.com/jlink.html}
564 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
567 @section USB RLINK based
568 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
571 @item @b{Raisonance RLink}
572 @* Link: @url{http://www.raisonance.com/products/RLink.php}
573 @item @b{STM32 Primer}
574 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
575 @item @b{STM32 Primer2}
576 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
582 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
584 @item @b{USB - Presto}
585 @* Link: @url{http://tools.asix.net/prg_presto.htm}
587 @item @b{Versaloon-Link}
588 @* Link: @url{http://www.simonqian.com/en/Versaloon}
590 @item @b{ARM-JTAG-EW}
591 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
594 @section IBM PC Parallel Printer Port Based
596 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
597 and the MacGraigor Wiggler. There are many clones and variations of
602 @item @b{Wiggler} - There are many clones of this.
603 @* Link: @url{http://www.macraigor.com/wiggler.htm}
605 @item @b{DLC5} - From XILINX - There are many clones of this
606 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
607 produced, PDF schematics are easily found and it is easy to make.
609 @item @b{Amontec - JTAG Accelerator}
610 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
613 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
616 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
617 Improved parallel-port wiggler-style JTAG adapter}
619 @item @b{Wiggler_ntrst_inverted}
620 @* Yet another variation - See the source code, src/jtag/parport.c
622 @item @b{old_amt_wiggler}
623 @* Unknown - probably not on the market today
626 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
629 @* Link: @url{http://www.amontec.com/chameleon.shtml}
635 @* ispDownload from Lattice Semiconductor
636 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
639 @* From ST Microsystems;
640 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
641 FlashLINK JTAG programing cable for PSD and uPSD}
649 @* An EP93xx based Linux machine using the GPIO pins directly.
652 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
658 @cindex running OpenOCD
660 @cindex --debug_level
664 The @option{--help} option shows:
668 --help | -h display this help
669 --version | -v display OpenOCD version
670 --file | -f use configuration file <name>
671 --search | -s dir to search for config files and scripts
672 --debug | -d set debug level <0-3>
673 --log_output | -l redirect log output to file <name>
674 --command | -c run <command>
675 --pipe | -p use pipes when talking to gdb
678 By default OpenOCD reads the file configuration file ``openocd.cfg''
679 in the current directory. To specify a different (or multiple)
680 configuration file, you can use the ``-f'' option. For example:
683 openocd -f config1.cfg -f config2.cfg -f config3.cfg
686 Once started, OpenOCD runs as a daemon, waiting for connections from
687 clients (Telnet, GDB, Other).
689 If you are having problems, you can enable internal debug messages via
692 Also it is possible to interleave commands w/config scripts using the
693 @option{-c} command line switch.
695 To enable debug output (when reporting problems or working on OpenOCD
696 itself), use the @option{-d} command line switch. This sets the
697 @option{debug_level} to "3", outputting the most information,
698 including debug messages. The default setting is "2", outputting only
699 informational messages, warnings and errors. You can also change this
700 setting from within a telnet or gdb session using @option{debug_level
701 <n>} @xref{debug_level}.
703 You can redirect all output from the daemon to a file using the
704 @option{-l <logfile>} switch.
706 Search paths for config/script files can be added to OpenOCD by using
707 the @option{-s <search>} switch. The current directory and the OpenOCD
708 target library is in the search path by default.
710 For details on the @option{-p} option. @xref{Connecting to GDB}.
712 Note! OpenOCD will launch the GDB & telnet server even if it can not
713 establish a connection with the target. In general, it is possible for
714 the JTAG controller to be unresponsive until the target is set up
715 correctly via e.g. GDB monitor commands in a GDB init script.
717 @node Simple Configuration Files
718 @chapter Simple Configuration Files
719 @cindex configuration
722 There are 4 basic ways of ``configurating'' OpenOCD to run, they are:
725 @item A small openocd.cfg file which ``sources'' other configuration files
726 @item A monolithic openocd.cfg file
727 @item Many -f filename options on the command line
728 @item Your Mixed Solution
731 @section Small configuration file method
733 This is the preferred method. It is simple and works well for many
734 people. The developers of OpenOCD would encourage you to use this
735 method. If you create a new configuration please email new
736 configurations to the development list.
738 Here is an example of an openocd.cfg file for an ATMEL at91sam7x256
741 source [find interface/signalyzer.cfg]
743 # GDB can also flash my flash!
744 gdb_memory_map enable
745 gdb_flash_program enable
747 source [find target/sam7x256.cfg]
750 There are many example configuration scripts you can work with. You
751 should look in the directory: @t{$(INSTALLDIR)/lib/openocd}. You
755 @item @b{board} - eval board level configurations
756 @item @b{interface} - specific dongle configurations
757 @item @b{target} - the target chips
758 @item @b{tcl} - helper scripts
759 @item @b{xscale} - things specific to the xscale.
762 Look first in the ``boards'' area, then the ``targets'' area. Often a board
763 configuration is a good example to work from.
765 @section Many -f filename options
766 Some believe this is a wonderful solution, others find it painful.
768 You can use a series of ``-f filename'' options on the command line,
769 OpenOCD will read each filename in sequence, for example:
772 openocd -f file1.cfg -f file2.cfg -f file2.cfg
775 You can also intermix various commands with the ``-c'' command line
778 @section Monolithic file
779 The ``Monolithic File'' dispenses with all ``source'' statements and
780 puts everything in one self contained (monolithic) file. This is not
783 Please try to ``source'' various files or use the multiple -f
786 @section Advice for you
787 Often, one uses a ``mixed approach''. Where possible, please try to
788 ``source'' common things, and if needed cut/paste parts of the
789 standard distribution configuration files as needed.
791 @b{REMEMBER:} The ``important parts'' of your configuration file are:
794 @item @b{Interface} - Defines the dongle
795 @item @b{Taps} - Defines the JTAG Taps
796 @item @b{GDB Targets} - What GDB talks to
797 @item @b{Flash Programing} - Very Helpful
800 Some key things you should look at and understand are:
803 @item The reset configuration of your debug environment as a whole
804 @item Is there a ``work area'' that OpenOCD can use?
805 @* For ARM - work areas mean up to 10x faster downloads.
806 @item For MMU/MPU based ARM chips (i.e.: ARM9 and later) will that work area still be available?
807 @item For complex targets (multiple chips) the JTAG SPEED becomes an issue.
812 @node Config File Guidelines
813 @chapter Config File Guidelines
815 This section/chapter is aimed at developers and integrators of
816 OpenOCD. These are guidelines for creating new boards and new target
817 configurations as of 28/Nov/2008.
819 However, you, the user of OpenOCD, should be somewhat familiar with
820 this section as it should help explain some of the internals of what
821 you might be looking at.
823 The user should find the following directories under @t{$(INSTALLDIR)/lib/openocd} :
827 @*Think JTAG Dongle. Files that configure the JTAG dongle go here.
829 @* Think Circuit Board, PWA, PCB, they go by many names. Board files
830 contain initialization items that are specific to a board - for
831 example: The SDRAM initialization sequence for the board, or the type
832 of external flash and what address it is found at. Any initialization
833 sequence to enable that external flash or SDRAM should be found in the
834 board file. Boards may also contain multiple targets, i.e.: Two CPUs, or
835 a CPU and an FPGA or CPLD.
837 @* Think chip. The ``target'' directory represents a JTAG tap (or
838 chip) OpenOCD should control, not a board. Two common types of targets
839 are ARM chips and FPGA or CPLD chips.
842 @b{If needed...} The user in their ``openocd.cfg'' file or the board
843 file might override a specific feature in any of the above files by
844 setting a variable or two before sourcing the target file. Or adding
845 various commands specific to their situation.
847 @section Interface Config Files
849 The user should be able to source one of these files via a command like this:
852 source [find interface/FOOBAR.cfg]
854 openocd -f interface/FOOBAR.cfg
857 A preconfigured interface file should exist for every interface in use
858 today, that said, perhaps some interfaces have only been used by the
859 sole developer who created it.
861 Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
863 @section Board Config Files
865 @b{Note: BOARD directory NEW as of 28/nov/2008}
867 The user should be able to source one of these files via a command like this:
870 source [find board/FOOBAR.cfg]
872 openocd -f board/FOOBAR.cfg
876 The board file should contain one or more @t{source [find
877 target/FOO.cfg]} statements along with any board specific things.
879 In summary the board files should contain (if present)
882 @item External flash configuration (i.e.: NOR flash on CS0, two NANDs on CS2)
883 @item SDRAM configuration (size, speed, etc.
884 @item Board specific IO configuration (i.e.: GPIO pins might disable a 2nd flash)
885 @item Multiple TARGET source statements
886 @item All things that are not ``inside a chip''
887 @item Things inside a chip go in a 'target' file
890 @section Target Config Files
892 The user should be able to source one of these files via a command like this:
895 source [find target/FOOBAR.cfg]
897 openocd -f target/FOOBAR.cfg
900 In summary the target files should contain
905 @item Reset configuration
907 @item CPU/Chip/CPU-Core specific features
911 @subsection Important variable names
913 By default, the end user should never need to set these
914 variables. However, if the user needs to override a setting they only
915 need to set the variable in a simple way.
919 @* This gives a name to the overall chip, and is used as part of the
920 tap identifier dotted name.
922 @* By default little - unless the chip or board is not normally used that way.
924 @* When OpenOCD examines the JTAG chain, it will attempt to identify
925 every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
926 to verify the tap id number verses configuration file and may issue an
927 error or warning like this. The hope is that this will help to pinpoint
928 problems in OpenOCD configurations.
931 Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
932 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
933 Error: ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678,
935 Error: ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
936 Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
939 @item @b{_TARGETNAME}
940 @* By convention, this variable is created by the target configuration
941 script. The board configuration file may make use of this variable to
942 configure things like a ``reset init'' script, or other things
943 specific to that board and that target.
945 If the chip has 2 targets, use the names @b{_TARGETNAME0},
946 @b{_TARGETNAME1}, ... etc.
948 @b{Remember:} The ``board file'' may include multiple targets.
950 At no time should the name ``target0'' (the default target name if
951 none was specified) be used. The name ``target0'' is a hard coded name
952 - the next target on the board will be some other number.
953 In the same way, avoid using target numbers even when they are
954 permitted; use the right target name(s) for your board.
956 The user (or board file) should reasonably be able to:
959 source [find target/FOO.cfg]
960 $_TARGETNAME configure ... FOO specific parameters
962 source [find target/BAR.cfg]
963 $_TARGETNAME configure ... BAR specific parameters
968 @subsection Tcl Variables Guide Line
969 The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
971 Thus the rule we follow in OpenOCD is this: Variables that begin with
972 a leading underscore are temporary in nature, and can be modified and
973 used at will within a ?TARGET? configuration file.
975 @b{EXAMPLE:} The user should be able to do this:
979 # PXA270 #1 network side, big endian
980 # PXA270 #2 video side, little endian
984 source [find target/pxa270.cfg]
985 # variable: _TARGETNAME = network.cpu
986 # other commands can refer to the "network.cpu" tap.
987 $_TARGETNAME configure .... params for this CPU..
991 source [find target/pxa270.cfg]
992 # variable: _TARGETNAME = video.cpu
993 # other commands can refer to the "video.cpu" tap.
994 $_TARGETNAME configure .... params for this CPU..
998 source [find target/spartan3.cfg]
1000 # Since $_TARGETNAME is temporal..
1001 # these names still work!
1002 network.cpu configure ... params
1003 video.cpu configure ... params
1007 @subsection Default Value Boiler Plate Code
1009 All target configuration files should start with this (or a modified form)
1013 if @{ [info exists CHIPNAME] @} @{
1014 set _CHIPNAME $CHIPNAME
1016 set _CHIPNAME sam7x256
1019 if @{ [info exists ENDIAN] @} @{
1025 if @{ [info exists CPUTAPID ] @} @{
1026 set _CPUTAPID $CPUTAPID
1028 set _CPUTAPID 0x3f0f0f0f
1033 @subsection Creating Taps
1034 After the ``defaults'' are choosen [see above] the taps are created.
1036 @b{SIMPLE example:} such as an Atmel AT91SAM7X256
1040 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
1041 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1042 -expected-id $_CPUTAPID
1045 @b{COMPLEX example:}
1047 This is an SNIP/example for an STR912 - which has 3 internal taps. Key features shown:
1050 @item @b{Unform tap names} - See: Tap Naming Convention
1051 @item @b{_TARGETNAME} is created at the end where used.
1055 if @{ [info exists FLASHTAPID ] @} @{
1056 set _FLASHTAPID $FLASHTAPID
1058 set _FLASHTAPID 0x25966041
1060 jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 \
1061 -expected-id $_FLASHTAPID
1063 if @{ [info exists CPUTAPID ] @} @{
1064 set _CPUTAPID $CPUTAPID
1066 set _CPUTAPID 0x25966041
1068 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe \
1069 -expected-id $_CPUTAPID
1072 if @{ [info exists BSTAPID ] @} @{
1073 set _BSTAPID $BSTAPID
1075 set _BSTAPID 0x1457f041
1077 jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 \
1078 -expected-id $_BSTAPID
1080 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
1083 @b{Tap Naming Convention}
1085 See the command ``jtag newtap'' for detail, but in brief the names you should use are:
1094 @item @b{unknownN} - it happens :-(
1097 @subsection Reset Configuration
1099 Some chips have specific ways the TRST and SRST signals are
1100 managed. If these are @b{CHIP SPECIFIC} they go here, if they are
1101 @b{BOARD SPECIFIC} they go in the board file.
1103 @subsection Work Areas
1105 Work areas are small RAM areas used by OpenOCD to speed up downloads,
1106 and to download small snippets of code to program flash chips.
1108 If the chip includes a form of ``on-chip-ram'' - and many do - define
1109 a reasonable work area and use the ``backup'' option.
1111 @b{PROBLEMS:} On more complex chips, this ``work area'' may become
1112 inaccessible if/when the application code enables or disables the MMU.
1114 @subsection ARM Core Specific Hacks
1116 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1117 special high speed download features - enable it.
1119 If the chip has an ARM ``vector catch'' feature - by default enable
1120 it for Undefined Instructions, Data Abort, and Prefetch Abort, if the
1121 user is really writing a handler for those situations - they can
1122 easily disable it. Experiance has shown the ``vector catch'' is
1123 helpful - for common programing errors.
1125 If present, the MMU, the MPU and the CACHE should be disabled.
1127 Some ARM cores are equipped with trace support, which permits
1128 examination of the instruction and data bus activity. Trace
1129 activity is controlled through an ``Embedded Trace Module'' (ETM)
1130 on one of the core's scan chains. The ETM emits voluminous data
1131 through a ``trace port''. (@xref{ARM Tracing}.)
1132 If you are using an external trace port,
1133 configure it in your board config file.
1134 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1135 configure it in your target config file.
1138 etm config $_TARGETNAME 16 normal full etb
1139 etb config $_TARGETNAME $_CHIPNAME.etb
1142 @subsection Internal Flash Configuration
1144 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1146 @b{Never ever} in the ``target configuration file'' define any type of
1147 flash that is external to the chip. (For example a BOOT flash on
1148 Chip Select 0.) Such flash information goes in a board file - not
1149 the TARGET (chip) file.
1153 @item at91sam7x256 - has 256K flash YES enable it.
1154 @item str912 - has flash internal YES enable it.
1155 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1156 @item pxa270 - again - CS0 flash - it goes in the board file.
1160 @chapter About JIM-Tcl
1164 OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
1165 learn more about JIM here: @url{http://jim.berlios.de}
1168 @item @b{JIM vs. Tcl}
1169 @* JIM-TCL is a stripped down version of the well known Tcl language,
1170 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
1171 fewer features. JIM-Tcl is a single .C file and a single .H file and
1172 impliments the basic Tcl command set along. In contrast: Tcl 8.6 is a
1173 4.2 MB .zip file containing 1540 files.
1175 @item @b{Missing Features}
1176 @* Our practice has been: Add/clone the real Tcl feature if/when
1177 needed. We welcome JIM Tcl improvements, not bloat.
1180 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
1181 command interpreter today (28/nov/2008) is a mixture of (newer)
1182 JIM-Tcl commands, and (older) the orginal command interpreter.
1185 @* At the OpenOCD telnet command line (or via the GDB mon command) one
1186 can type a Tcl for() loop, set variables, etc.
1188 @item @b{Historical Note}
1189 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
1191 @item @b{Need a crash course in Tcl?}
1192 @*@xref{Tcl Crash Course}.
1195 @node Daemon Configuration
1196 @chapter Daemon Configuration
1197 @cindex initialization
1198 The commands here are commonly found in the openocd.cfg file and are
1199 used to specify what TCP/IP ports are used, and how GDB should be
1202 @section Configuration Stage
1203 @cindex configuration stage
1204 @cindex configuration command
1206 When the OpenOCD server process starts up, it enters a
1207 @emph{configuration stage} which is the only time that
1208 certain commands, @emph{configuration commands}, may be issued.
1209 Those configuration commands include declaration of TAPs
1210 and other basic setup.
1211 The server must leave the configuration stage before it
1212 may access or activate TAPs.
1213 After it leaves this stage, configuration commands may no
1216 @deffn {Config Command} init
1217 This command terminates the configuration stage and
1218 enters the normal command mode. This can be useful to add commands to
1219 the startup scripts and commands such as resetting the target,
1220 programming flash, etc. To reset the CPU upon startup, add "init" and
1221 "reset" at the end of the config script or at the end of the OpenOCD
1222 command line using the @option{-c} command line switch.
1224 If this command does not appear in any startup/configuration file
1225 OpenOCD executes the command for you after processing all
1226 configuration files and/or command line options.
1228 @b{NOTE:} This command normally occurs at or near the end of your
1229 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1230 targets ready. For example: If your openocd.cfg file needs to
1231 read/write memory on your target, @command{init} must occur before
1232 the memory read/write commands. This includes @command{nand probe}.
1235 @section TCP/IP Ports
1239 The OpenOCD server accepts remote commands in several syntaxes.
1240 Each syntax uses a different TCP/IP port, which you may specify
1241 only during configuration (before those ports are opened).
1243 @deffn {Command} gdb_port (number)
1245 Specify or query the first port used for incoming GDB connections.
1246 The GDB port for the
1247 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1248 When not specified during the configuration stage,
1249 the port @var{number} defaults to 3333.
1252 @deffn {Command} tcl_port (number)
1253 Specify or query the port used for a simplified RPC
1254 connection that can be used by clients to issue TCL commands and get the
1255 output from the Tcl engine.
1256 Intended as a machine interface.
1257 When not specified during the configuration stage,
1258 the port @var{number} defaults to 6666.
1261 @deffn {Command} telnet_port (number)
1262 Specify or query the
1263 port on which to listen for incoming telnet connections.
1264 This port is intended for interaction with one human through TCL commands.
1265 When not specified during the configuration stage,
1266 the port @var{number} defaults to 4444.
1269 @anchor{GDB Configuration}
1270 @section GDB Configuration
1272 @cindex GDB configuration
1273 You can reconfigure some GDB behaviors if needed.
1274 The ones listed here are static and global.
1275 @xref{Target Create}, about declaring individual targets.
1276 @xref{Target Events}, about configuring target-specific event handling.
1278 @anchor{gdb_breakpoint_override}
1279 @deffn {Command} gdb_breakpoint_override <hard|soft|disable>
1280 Force breakpoint type for gdb @command{break} commands.
1281 The raison d'etre for this option is to support GDB GUI's which don't
1282 distinguish hard versus soft breakpoints, if the default OpenOCD and
1283 GDB behaviour is not sufficient. GDB normally uses hardware
1284 breakpoints if the memory map has been set up for flash regions.
1286 This option replaces older arm7_9 target commands that addressed
1290 @deffn {Config command} gdb_detach <resume|reset|halt|nothing>
1291 Configures what OpenOCD will do when GDB detaches from the daemon.
1292 Default behaviour is @var{resume}.
1295 @anchor{gdb_flash_program}
1296 @deffn {Config command} gdb_flash_program <enable|disable>
1297 Set to @var{enable} to cause OpenOCD to program the flash memory when a
1298 vFlash packet is received.
1299 The default behaviour is @var{enable}.
1302 @deffn {Config command} gdb_memory_map <enable|disable>
1303 Set to @var{enable} to cause OpenOCD to send the memory configuration to GDB when
1304 requested. GDB will then know when to set hardware breakpoints, and program flash
1305 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1306 for flash programming to work.
1307 Default behaviour is @var{enable}.
1308 @xref{gdb_flash_program}.
1311 @deffn {Config command} gdb_report_data_abort <enable|disable>
1312 Specifies whether data aborts cause an error to be reported
1313 by GDB memory read packets.
1314 The default behaviour is @var{disable};
1315 use @var{enable} see these errors reported.
1318 @node Interface - Dongle Configuration
1319 @chapter Interface - Dongle Configuration
1320 Interface commands are normally found in an interface configuration
1321 file which is sourced by your openocd.cfg file. These commands tell
1322 OpenOCD what type of JTAG dongle you have and how to talk to it.
1323 @section Simple Complete Interface Examples
1324 @b{A Turtelizer FT2232 Based JTAG Dongle}
1328 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A"
1329 ft2232_layout turtelizer2
1330 ft2232_vid_pid 0x0403 0xbdc8
1337 @b{A Raisonance RLink}
1346 parport_cable wiggler
1351 interface arm-jtag-ew
1353 @section Interface Command
1355 The interface command tells OpenOCD what type of JTAG dongle you are
1356 using. Depending on the type of dongle, you may need to have one or
1357 more additional commands.
1361 @item @b{interface} <@var{name}>
1363 @*Use the interface driver <@var{name}> to connect to the
1364 target. Currently supported interfaces are
1369 @* PC parallel port bit-banging (Wigglers, PLD download cable, ...)
1371 @item @b{amt_jtagaccel}
1372 @* Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
1376 @* FTDI FT2232 (USB) based devices using either the open-source libftdi or the binary only
1377 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
1378 platform. The libftdi uses libusb, and should be portable to all systems that provide
1382 @*Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1385 @* ASIX PRESTO USB JTAG programmer.
1388 @* usbprog is a freely programmable USB adapter.
1391 @* Gateworks GW16012 JTAG programmer.
1394 @* Segger jlink USB adapter
1397 @* Raisonance RLink USB adapter
1400 @* vsllink is part of Versaloon which is a versatile USB programmer.
1402 @item @b{arm-jtag-ew}
1403 @* Olimex ARM-JTAG-EW USB adapter
1404 @comment - End parameters
1406 @comment - End Interface
1408 @subsection parport options
1411 @item @b{parport_port} <@var{number}>
1412 @cindex parport_port
1413 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1414 the @file{/dev/parport} device
1416 When using PPDEV to access the parallel port, use the number of the parallel port:
1417 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1418 you may encounter a problem.
1419 @item @b{parport_cable} <@var{name}>
1420 @cindex parport_cable
1421 @*The layout of the parallel port cable used to connect to the target.
1422 Currently supported cables are
1426 The original Wiggler layout, also supported by several clones, such
1427 as the Olimex ARM-JTAG
1430 Same as original wiggler except an led is fitted on D5.
1431 @item @b{wiggler_ntrst_inverted}
1432 @cindex wiggler_ntrst_inverted
1433 Same as original wiggler except TRST is inverted.
1434 @item @b{old_amt_wiggler}
1435 @cindex old_amt_wiggler
1436 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
1437 version available from the website uses the original Wiggler layout ('@var{wiggler}')
1440 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
1441 program the Chameleon itself, not a connected target.
1444 The Xilinx Parallel cable III.
1447 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
1448 This is also the layout used by the HollyGates design
1449 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1452 The ST Parallel cable.
1455 Same as original wiggler except SRST and TRST connections reversed and
1456 TRST is also inverted.
1459 Altium Universal JTAG cable.
1461 @item @b{parport_write_on_exit} <@var{on}|@var{off}>
1462 @cindex parport_write_on_exit
1463 @*This will configure the parallel driver to write a known value to the parallel
1464 interface on exiting OpenOCD
1467 @subsection amt_jtagaccel options
1469 @item @b{parport_port} <@var{number}>
1470 @cindex parport_port
1471 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
1472 @file{/dev/parport} device
1474 @subsection ft2232 options
1477 @item @b{ft2232_device_desc} <@var{description}>
1478 @cindex ft2232_device_desc
1479 @*The USB device description of the FTDI FT2232 device. If not
1480 specified, the FTDI default value is used. This setting is only valid
1481 if compiled with FTD2XX support.
1483 @b{TODO:} Confirm the following: On Windows the name needs to end with
1484 a ``space A''? Or not? It has to do with the FTD2xx driver. When must
1485 this be added and when must it not be added? Why can't the code in the
1486 interface or in OpenOCD automatically add this if needed? -- Duane.
1488 @item @b{ft2232_serial} <@var{serial-number}>
1489 @cindex ft2232_serial
1490 @*The serial number of the FTDI FT2232 device. If not specified, the FTDI default
1492 @item @b{ft2232_layout} <@var{name}>
1493 @cindex ft2232_layout
1494 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
1495 signals. Valid layouts are
1498 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
1500 Amontec JTAGkey and JTAGkey-Tiny
1501 @item @b{signalyzer}
1503 @item @b{olimex-jtag}
1506 American Microsystems M5960
1507 @item @b{evb_lm3s811}
1508 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
1509 SRST signals on external connector
1512 @item @b{stm32stick}
1513 Hitex STM32 Performance Stick
1514 @item @b{flyswatter}
1515 Tin Can Tools Flyswatter
1516 @item @b{turtelizer2}
1517 egnite Software turtelizer2
1520 @item @b{axm0432_jtag}
1523 Hitex Cortino JTAG interface
1526 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
1527 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1528 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, e.g.
1530 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1532 @item @b{ft2232_latency} <@var{ms}>
1533 @*On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1534 ft2232_read() fails to return the expected number of bytes. This can be caused by
1535 USB communication delays and has proved hard to reproduce and debug. Setting the
1536 FT2232 latency timer to a larger value increases delays for short USB packets but it
1537 also reduces the risk of timeouts before receiving the expected number of bytes.
1538 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1541 @subsection ep93xx options
1542 @cindex ep93xx options
1543 Currently, there are no options available for the ep93xx interface.
1547 JTAG clock setup is part of system setup.
1548 It @emph{does not belong with interface setup} since any interface
1549 only knows a few of the constraints for the JTAG clock speed.
1550 Sometimes the JTAG speed is
1551 changed during the target initialization process: (1) slow at
1552 reset, (2) program the CPU clocks, (3) run fast.
1553 Both the "slow" and "fast" clock rates are functions of the
1554 oscillators used, the chip, the board design, and sometimes
1555 power management software that may be active.
1557 The speed used during reset can be adjusted using pre_reset
1558 and post_reset event handlers.
1559 @xref{Target Events}.
1561 If your system supports adaptive clocking (RTCK), configuring
1562 JTAG to use that is probably the most robust approach.
1563 However, it introduces delays to synchronize clocks; so it
1564 may not be the fastest solution.
1566 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1567 instead of @command{jtag_khz}.
1569 @deffn {Command} jtag_khz max_speed_kHz
1570 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1571 JTAG interfaces usually support a limited number of
1572 speeds. The speed actually used won't be faster
1573 than the speed specified.
1575 As a rule of thumb, if you specify a clock rate make
1576 sure the JTAG clock is no more than @math{1/6th CPU-Clock}.
1577 This is especially true for synthesized cores (ARMxxx-S).
1579 Speed 0 (khz) selects RTCK method.
1581 If your system uses RTCK, you won't need to change the
1582 JTAG clocking after setup.
1583 Not all interfaces, boards, or targets support ``rtck''.
1584 If the interface device can not
1585 support it, an error is returned when you try to use RTCK.
1588 @defun jtag_rclk fallback_speed_kHz
1590 This Tcl proc (defined in startup.tcl) attempts to enable RTCK/RCLK.
1591 If that fails (maybe the interface, board, or target doesn't
1592 support it), falls back to the specified frequency.
1594 # Fall back to 3mhz if RTCK is not supported
1599 @node Reset Configuration
1600 @chapter Reset Configuration
1601 @cindex Reset Configuration
1603 Every system configuration may require a different reset
1604 configuration. This can also be quite confusing.
1605 Resets also interact with @var{reset-init} event handlers,
1606 which do things like setting up clocks and DRAM, and
1607 JTAG clock rates. (@xref{JTAG Speed}.)
1608 Please see the various board files for examples.
1611 To maintainers and integrators:
1612 Reset configuration touches several things at once.
1613 Normally the board configuration file
1614 should define it and assume that the JTAG adapter supports
1615 everything that's wired up to the board's JTAG connector.
1616 However, the target configuration file could also make note
1617 of something the silicon vendor has done inside the chip,
1618 which will be true for most (or all) boards using that chip.
1619 And when the JTAG adapter doesn't support everything, the
1620 system configuration file will need to override parts of
1621 the reset configuration provided by other files.
1624 @section Types of Reset
1626 There are many kinds of reset possible through JTAG, but
1627 they may not all work with a given board and adapter.
1628 That's part of why reset configuration can be error prone.
1632 @emph{System Reset} ... the @emph{SRST} hardware signal
1633 resets all chips connected to the JTAG adapter, such as processors,
1634 power management chips, and I/O controllers. Normally resets triggered
1635 with this signal behave exactly like pressing a RESET button.
1637 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
1638 just the TAP controllers connected to the JTAG adapter.
1639 Such resets should not be visible to the rest of the system; resetting a
1640 device's the TAP controller just puts that controller into a known state.
1642 @emph{Emulation Reset} ... many devices can be reset through JTAG
1643 commands. These resets are often distinguishable from system
1644 resets, either explicitly (a "reset reason" register says so)
1645 or implicitly (not all parts of the chip get reset).
1647 @emph{Other Resets} ... system-on-chip devices often support
1648 several other types of reset.
1649 You may need to arrange that a watchdog timer stops
1650 while debugging, preventing a watchdog reset.
1651 There may be individual module resets.
1654 In the best case, OpenOCD can hold SRST, then reset
1655 the TAPs via TRST and send commands through JTAG to halt the
1656 CPU at the reset vector before the 1st instruction is executed.
1657 Then when it finally releases the SRST signal, the system is
1658 halted under debugger control before any code has executed.
1659 This is the behavior required to support the @command{reset halt}
1660 and @command{reset init} commands; after @command{reset init} a
1661 board-specific script might do things like setting up DRAM.
1662 (@xref{Reset Command}.)
1664 @section SRST and TRST Signal Issues
1666 Because SRST and TRST are hardware signals, they can have a
1667 variety of system-specific constraints. Some of the most
1672 @item @emph{Signal not available} ... Some boards don't wire
1673 SRST or TRST to the JTAG connector. Some JTAG adapters don't
1674 support such signals even if they are wired up.
1675 Use the @command{reset_config} @var{signals} options to say
1676 when one of those signals is not connected.
1677 When SRST is not available, your code might not be able to rely
1678 on controllers having been fully reset during code startup.
1680 @item @emph{Signals shorted} ... Sometimes a chip, board, or
1681 adapter will connect SRST to TRST, instead of keeping them separate.
1682 Use the @command{reset_config} @var{combination} options to say
1683 when those signals aren't properly independent.
1685 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
1686 delay circuit, reset supervisor, or on-chip features can extend
1687 the effect of a JTAG adapter's reset for some time after the adapter
1688 stops issuing the reset. For example, there may be chip or board
1689 requirements that all reset pulses last for at least a
1690 certain amount of time; and reset buttons commonly have
1691 hardware debouncing.
1692 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
1693 commands to say when extra delays are needed.
1695 @item @emph{Drive type} ... Reset lines often have a pullup
1696 resistor, letting the JTAG interface treat them as open-drain
1697 signals. But that's not a requirement, so the adapter may need
1698 to use push/pull output drivers.
1699 Also, with weak pullups it may be advisable to drive
1700 signals to both levels (push/pull) to minimize rise times.
1701 Use the @command{reset_config} @var{trst_type} and
1702 @var{srst_type} parameters to say how to drive reset signals.
1705 There can also be other issues.
1706 Some devices don't fully conform to the JTAG specifications.
1707 Trivial system-specific differences are common, such as
1708 SRST and TRST using slightly different names.
1709 There are also vendors who distribute key JTAG documentation for
1710 their chips only to developers who have signed a Non-Disclosure
1713 Sometimes there are chip-specific extensions like a requirement to use
1714 the normally-optional TRST signal (precluding use of JTAG adapters which
1715 don't pass TRST through), or needing extra steps to complete a TAP reset.
1717 In short, SRST and especially TRST handling may be very finicky,
1718 needing to cope with both architecture and board specific constraints.
1720 @section Commands for Handling Resets
1722 @deffn {Command} jtag_nsrst_delay milliseconds
1723 How long (in milliseconds) OpenOCD should wait after deasserting
1724 nSRST (active-low system reset) before starting new JTAG operations.
1725 When a board has a reset button connected to SRST line it will
1726 probably have hardware debouncing, implying you should use this.
1729 @deffn {Command} jtag_ntrst_delay milliseconds
1730 How long (in milliseconds) OpenOCD should wait after deasserting
1731 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
1734 @deffn {Command} reset_config mode_flag ...
1735 This command tells OpenOCD the reset configuration
1736 of your combination of JTAG board and target in target
1737 configuration scripts.
1739 If you have an interface that does not support SRST and
1740 TRST(unlikely), then you may be able to work around that
1741 problem by using a reset_config command to override any
1742 settings in the target configuration script.
1744 SRST and TRST has a fairly well understood definition and
1745 behaviour in the JTAG specification, but vendors take
1746 liberties to achieve various more or less clearly understood
1747 goals. Sometimes documentation is available, other times it
1748 is not. OpenOCD has the reset_config command to allow OpenOCD
1749 to deal with the various common cases.
1751 The @var{mode_flag} options can be specified in any order, but only one
1752 of each type -- @var{signals}, @var{combination}, @var{trst_type},
1753 and @var{srst_type} -- may be specified at a time.
1754 If you don't provide a new value for a given type, its previous
1755 value (perhaps the default) is unchanged.
1756 For example, this means that you don't need to say anything at all about
1757 TRST just to declare that if the JTAG adapter should want to drive SRST,
1758 it must explicitly be driven high (@option{srst_push_pull}).
1760 @var{signals} can specify which of the reset signals are connected.
1761 For example, If the JTAG interface provides SRST, but the board doesn't
1762 connect that signal properly, then OpenOCD can't use it.
1763 Possible values are @option{none} (the default), @option{trst_only},
1764 @option{srst_only} and @option{trst_and_srst}.
1767 If your board provides SRST or TRST through the JTAG connector,
1768 you must declare that or else those signals will not be used.
1771 The @var{combination} is an optional value specifying broken reset
1772 signal implementations.
1773 The default behaviour if no option given is @option{separate},
1774 indicating everything behaves normally.
1775 @option{srst_pulls_trst} states that the
1776 test logic is reset together with the reset of the system (e.g. Philips
1777 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
1778 the system is reset together with the test logic (only hypothetical, I
1779 haven't seen hardware with such a bug, and can be worked around).
1780 @option{combined} implies both @option{srst_pulls_trst} and
1781 @option{trst_pulls_srst}.
1783 The optional @var{trst_type} and @var{srst_type} parameters allow the
1784 driver mode of each reset line to be specified. These values only affect
1785 JTAG interfaces with support for different driver modes, like the Amontec
1786 JTAGkey and JTAGAccelerator. Also, they are necessarily ignored if the
1787 relevant signal (TRST or SRST) is not connected.
1789 Possible @var{trst_type} driver modes for the test reset signal (TRST)
1790 are @option{trst_push_pull} (default) and @option{trst_open_drain}.
1791 Most boards connect this signal to a pulldown, so the JTAG TAPs
1792 never leave reset unless they are hooked up to a JTAG adapter.
1794 Possible @var{srst_type} driver modes for the system reset signal (SRST)
1795 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
1796 Most boards connect this signal to a pullup, and allow the
1797 signal to be pulled low by various events including system
1798 powerup and pressing a reset button.
1803 @chapter Tap Creation
1804 @cindex tap creation
1805 @cindex tap configuration
1807 In order for OpenOCD to control a target, a JTAG tap must be
1810 Commands to create taps are normally found in a configuration file and
1811 are not normally typed by a human.
1813 When a tap is created a @b{dotted.name} is created for the tap. Other
1814 commands use that dotted.name to manipulate or refer to the tap.
1818 @item @b{Debug Target} A tap can be used by a GDB debug target
1819 @item @b{Flash Programing} Some chips program the flash directly via JTAG,
1820 instead of indirectly by making a CPU do it.
1821 @item @b{Boundry Scan} Some chips support boundary scan.
1825 @section jtag newtap
1826 @b{@t{jtag newtap CHIPNAME TAPNAME configparams ....}}
1831 @cindex tap geometry
1833 @comment START options
1836 @* is a symbolic name of the chip.
1838 @* is a symbol name of a tap present on the chip.
1839 @item @b{Required configparams}
1840 @* Every tap has 3 required configparams, and several ``optional
1841 parameters'', the required parameters are:
1842 @comment START REQUIRED
1844 @item @b{-irlen NUMBER} - the length in bits of the instruction register, mostly 4 or 5 bits.
1845 @item @b{-ircapture NUMBER} - the IDCODE capture command, usually 0x01.
1846 @item @b{-irmask NUMBER} - the corresponding mask for the IR register. For
1847 some devices, there are bits in the IR that aren't used. This lets you mask
1848 them off when doing comparisons. In general, this should just be all ones for
1850 @comment END REQUIRED
1852 An example of a FOOBAR Tap
1854 jtag newtap foobar tap -irlen 7 -ircapture 0x42 -irmask 0x55
1856 Creates the tap ``foobar.tap'' with the instruction register (IR) is 7
1857 bits long, during Capture-IR 0x42 is loaded into the IR, and bits
1858 [6,4,2,0] are checked.
1860 @item @b{Optional configparams}
1861 @comment START Optional
1863 @item @b{-expected-id NUMBER}
1864 @* By default it is zero. If non-zero represents the
1865 expected tap ID used when the JTAG chain is examined. Repeat
1866 the option as many times as required if multiple id's can be
1867 expected. See below.
1870 @* By default not specified the tap is enabled. Some chips have a
1871 JTAG route controller (JRC) that is used to enable and/or disable
1872 specific JTAG taps. You can later enable or disable any JTAG tap via
1873 the command @b{jtag tapenable DOTTED.NAME} or @b{jtag tapdisable
1875 @comment END Optional
1878 @comment END OPTIONS
1881 @comment START NOTES
1883 @item @b{Technically}
1884 @* newtap is a sub command of the ``jtag'' command
1885 @item @b{Big Picture Background}
1886 @*GDB Talks to OpenOCD using the GDB protocol via
1887 TCP/IP. OpenOCD then uses the JTAG interface (the dongle) to
1888 control the JTAG chain on your board. Your board has one or more chips
1889 in a @i{daisy chain configuration}. Each chip may have one or more
1890 JTAG taps. GDB ends up talking via OpenOCD to one of the taps.
1891 @item @b{NAME Rules}
1892 @*Names follow ``C'' symbol name rules (start with alpha ...)
1893 @item @b{TAPNAME - Conventions}
1895 @item @b{tap} - should be used only FPGA or CPLD like devices with a single tap.
1896 @item @b{cpu} - the main CPU of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
1897 @item @b{flash} - if the chip has a flash tap, example: str912.flash
1898 @item @b{bs} - for boundary scan if this is a seperate tap.
1899 @item @b{etb} - for an embedded trace buffer (example: an ARM ETB11)
1900 @item @b{jrc} - for JTAG route controller (example: OMAP3530 found on Beagleboards)
1901 @item @b{unknownN} - where N is a number if you have no idea what the tap is for
1902 @item @b{Other names} - Freescale IMX31 has a SDMA (smart dma) with a JTAG tap, that tap should be called the ``sdma'' tap.
1903 @item @b{When in doubt} - use the chip maker's name in their data sheet.
1905 @item @b{DOTTED.NAME}
1906 @* @b{CHIPNAME}.@b{TAPNAME} creates the tap name, aka: the
1907 @b{Dotted.Name} is the @b{CHIPNAME} and @b{TAPNAME} combined with a
1908 dot (period); for example: @b{xilinx.tap}, @b{str912.flash},
1909 @b{omap3530.jrc}, or @b{stm32.cpu} The @b{dotted.name} is used in
1910 numerous other places to refer to various taps.
1912 @* The order this command appears via the config files is
1914 @item @b{Multi Tap Example}
1915 @* This example is based on the ST Microsystems STR912. See the ST
1916 document titled: @b{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
1917 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
1919 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}
1920 @*@b{checked: 28/nov/2008}
1922 The diagram shows that the TDO pin connects to the flash tap, flash TDI
1923 connects to the CPU debug tap, CPU TDI connects to the boundary scan
1924 tap which then connects to the TDI pin.
1928 # create tap: 'str912.flash'
1929 jtag newtap str912 flash ... params ...
1930 # create tap: 'str912.cpu'
1931 jtag newtap str912 cpu ... params ...
1932 # create tap: 'str912.bs'
1933 jtag newtap str912 bs ... params ...
1936 @item @b{Note: Deprecated} - Index Numbers
1937 @* Prior to 28/nov/2008, JTAG taps where numbered from 0..N this
1938 feature is still present, however its use is highly discouraged and
1939 should not be counted upon. Update all of your scripts to use
1940 TAP names rather than numbers.
1941 @item @b{Multiple chips}
1942 @* If your board has multiple chips, you should be
1943 able to @b{source} two configuration files, in the proper order, and
1944 have the taps created in the proper order.
1947 @comment at command level
1948 @comment DOCUMENT old command
1949 @section jtag_device - REMOVED
1951 @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
1955 @* @b{Removed: 28/nov/2008} This command has been removed and replaced
1956 by the ``jtag newtap'' command. The documentation remains here so that
1957 one can easily convert the old syntax to the new syntax. About the old
1958 syntax: The old syntax is positional, i.e.: The 3rd parameter is the
1959 ``irmask''. The new syntax requires named prefixes, and supports
1960 additional options, for example ``-expected-id 0x3f0f0f0f''. Please refer to the
1961 @b{jtag newtap} command for details.
1963 OLD: jtag_device 8 0x01 0xe3 0xfe
1964 NEW: jtag newtap CHIPNAME TAPNAME -irlen 8 -ircapture 0x01 -irmask 0xe3
1967 @section Enable/Disable Taps
1968 @b{Note:} These commands are intended to be used as a machine/script
1969 interface. Humans might find the ``scan_chain'' command more helpful
1970 when querying the state of the JTAG taps.
1972 @b{By default, all taps are enabled}
1975 @item @b{jtag tapenable} @var{DOTTED.NAME}
1976 @item @b{jtag tapdisable} @var{DOTTED.NAME}
1977 @item @b{jtag tapisenabled} @var{DOTTED.NAME}
1982 @cindex route controller
1984 These commands are used when your target has a JTAG route controller
1985 that effectively adds or removes a tap from the JTAG chain in a
1988 The ``standard way'' to remove a tap would be to place the tap in
1989 bypass mode. But with the advent of modern chips, this is not always a
1990 good solution. Some taps operate slowly, others operate fast, and
1991 there are other JTAG clock synchronisation problems one must face. To
1992 solve that problem, the JTAG route controller was introduced. Rather
1993 than ``bypass'' the tap, the tap is completely removed from the
1994 circuit and skipped.
1997 From OpenOCD's point of view, a JTAG tap is in one of 3 states:
2000 @item @b{Enabled - Not In ByPass} and has a variable bit length
2001 @item @b{Enabled - In ByPass} and has a length of exactly 1 bit.
2002 @item @b{Disabled} and has a length of ZERO and is removed from the circuit.
2005 The IEEE JTAG definition has no concept of a ``disabled'' tap.
2006 @b{Historical note:} this feature was added 28/nov/2008
2008 @b{jtag tapisenabled DOTTED.NAME}
2010 This command returns 1 if the named tap is currently enabled, 0 if not.
2011 This command exists so that scripts that manipulate a JRC (like the
2012 OMAP3530 has) can determine if OpenOCD thinks a tap is presently
2013 enabled or disabled.
2016 @node Target Configuration
2017 @chapter Target Configuration
2020 This chapter discusses how to create a GDB debug target. Before
2021 creating a ``target'' a JTAG tap DOTTED.NAME must exist first.
2023 @section targets [NAME]
2024 @b{Note:} This command name is PLURAL - not singular.
2026 With NO parameter, this plural @b{targets} command lists all known
2027 targets in a human friendly form.
2029 With a parameter, this plural @b{targets} command sets the current
2030 target to the given name. (i.e.: If there are multiple debug targets)
2035 CmdName Type Endian ChainPos State
2036 -- ---------- ---------- ---------- -------- ----------
2037 0: target0 arm7tdmi little 0 halted
2040 @section target COMMANDS
2041 @b{Note:} This command name is SINGULAR - not plural. It is used to
2042 manipulate specific targets, to create targets and other things.
2044 Once a target is created, a TARGETNAME (object) command is created;
2045 see below for details.
2047 The TARGET command accepts these sub-commands:
2049 @item @b{create} .. parameters ..
2050 @* creates a new target, see below for details.
2052 @* Lists all supported target types (perhaps some are not yet in this document).
2054 @* Lists all current debug target names, for example: 'str912.cpu' or 'pxa27.cpu' example usage:
2056 foreach t [target names] {
2057 puts [format "Target: %s\n" $t]
2061 @* Returns the current target. OpenOCD always has, or refers to the ``current target'' in some way.
2062 By default, commands like: ``mww'' (used to write memory) operate on the current target.
2063 @item @b{number} @b{NUMBER}
2064 @* Internally OpenOCD maintains a list of targets - in numerical index
2065 (0..N-1) this command returns the name of the target at index N.
2068 set thename [target number $x]
2069 puts [format "Target %d is: %s\n" $x $thename]
2072 @* Returns the number of targets known to OpenOCD (see number above)
2075 set c [target count]
2076 for { set x 0 } { $x < $c } { incr x } {
2077 # Assuming you have created this function
2078 print_target_details $x
2084 @section TARGETNAME (object) commands
2085 @b{Use:} Once a target is created, an ``object name'' that represents the
2086 target is created. By convention, the target name is identical to the
2087 tap name. In a multiple target system, one can preceed many common
2088 commands with a specific target name and effect only that target.
2090 str912.cpu mww 0x1234 0x42
2091 omap3530.cpu mww 0x5555 123
2094 @b{Model:} The Tcl/Tk language has the concept of object commands. A
2095 good example is a on screen button, once a button is created a button
2096 has a name (a path in Tk terms) and that name is useable as a 1st
2097 class command. For example in Tk, one can create a button and later
2098 configure it like this:
2102 button .foobar -background red -command @{ foo @}
2104 .foobar configure -foreground blue
2106 set x [.foobar cget -background]
2108 puts [format "The button is %s" $x]
2111 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2112 button. Commands available as a ``target object'' are:
2114 @comment START targetobj commands.
2116 @item @b{configure} - configure the target; see Target Config/Cget Options below
2117 @item @b{cget} - query the target configuration; see Target Config/Cget Options below
2118 @item @b{curstate} - current target state (running, halt, etc.
2120 @* Intended for a human to see/read the currently configure target events.
2121 @item @b{Various Memory Commands} See the ``mww'' command elsewhere.
2122 @comment start memory
2132 @item @b{Memory To Array, Array To Memory}
2133 @* These are aimed at a machine interface to memory
2135 @item @b{mem2array ARRAYNAME WIDTH ADDRESS COUNT}
2136 @item @b{array2mem ARRAYNAME WIDTH ADDRESS COUNT}
2138 @* @b{ARRAYNAME} is the name of an array variable
2139 @* @b{WIDTH} is 8/16/32 - indicating the memory access size
2140 @* @b{ADDRESS} is the target memory address
2141 @* @b{COUNT} is the number of elements to process
2143 @item @b{Used during ``reset''}
2144 @* These commands are used internally by the OpenOCD scripts to deal
2145 with odd reset situations and are not documented here.
2147 @item @b{arp_examine}
2151 @item @b{arp_waitstate}
2153 @item @b{invoke-event} @b{EVENT-NAME}
2154 @* Invokes the specific event manually for the target
2157 @anchor{Target Events}
2158 @section Target Events
2160 At various times, certain things can happen, or you want them to happen.
2164 @item What should happen when GDB connects? Should your target reset?
2165 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2166 @item During reset, do you need to write to certain memory location to reconfigure the SDRAM?
2169 All of the above items are handled by target events.
2171 To specify an event action, either during target creation, or later
2172 via ``$_TARGETNAME configure'' see this example.
2174 Syntactially, the option is: ``-event NAME BODY'' where NAME is a
2175 target event name, and BODY is a Tcl procedure or string of commands
2178 The programmers model is the ``-command'' option used in Tcl/Tk
2179 buttons and events. Below are two identical examples, the first
2180 creates and invokes small procedure. The second inlines the procedure.
2183 proc my_attach_proc @{ @} @{
2187 mychip.cpu configure -event gdb-attach my_attach_proc
2188 mychip.cpu configure -event gdb-attach @{
2194 @section Current Events
2195 The following events are available:
2197 @item @b{debug-halted}
2198 @* The target has halted for debug reasons (i.e.: breakpoint)
2199 @item @b{debug-resumed}
2200 @* The target has resumed (i.e.: gdb said run)
2201 @item @b{early-halted}
2202 @* Occurs early in the halt process
2203 @item @b{examine-end}
2204 @* Currently not used (goal: when JTAG examine completes)
2205 @item @b{examine-start}
2206 @* Currently not used (goal: when JTAG examine starts)
2207 @item @b{gdb-attach}
2208 @* When GDB connects
2209 @item @b{gdb-detach}
2210 @* When GDB disconnects
2212 @* When the taret has halted and GDB is not doing anything (see early halt)
2213 @item @b{gdb-flash-erase-start}
2214 @* Before the GDB flash process tries to erase the flash
2215 @item @b{gdb-flash-erase-end}
2216 @* After the GDB flash process has finished erasing the flash
2217 @item @b{gdb-flash-write-start}
2218 @* Before GDB writes to the flash
2219 @item @b{gdb-flash-write-end}
2220 @* After GDB writes to the flash
2222 @* Before the taret steps, gdb is trying to start/resume the target
2224 @* The target has halted
2225 @item @b{old-gdb_program_config}
2226 @* DO NOT USE THIS: Used internally
2227 @item @b{old-pre_resume}
2228 @* DO NOT USE THIS: Used internally
2229 @item @b{reset-assert-pre}
2230 @* Before reset is asserted on the tap.
2231 @item @b{reset-assert-post}
2232 @* Reset is now asserted on the tap.
2233 @item @b{reset-deassert-pre}
2234 @* Reset is about to be released on the tap
2235 @item @b{reset-deassert-post}
2236 @* Reset has been released on the tap
2238 @* Currently not used.
2239 @item @b{reset-halt-post}
2240 @* Currently not usd
2241 @item @b{reset-halt-pre}
2242 @* Currently not used
2243 @item @b{reset-init}
2244 @* Used by @b{reset init} command for board-specific initialization.
2245 This is where you would configure PLLs and clocking, set up DRAM so
2246 you can download programs that don't fit in on-chip SRAM, set up pin
2247 multiplexing, and so on.
2248 @item @b{reset-start}
2249 @* Currently not used
2250 @item @b{reset-wait-pos}
2251 @* Currently not used
2252 @item @b{reset-wait-pre}
2253 @* Currently not used
2254 @item @b{resume-start}
2255 @* Before any target is resumed
2256 @item @b{resume-end}
2257 @* After all targets have resumed
2261 @* Target has resumed
2262 @item @b{tap-enable}
2263 @* Executed by @b{jtag tapenable DOTTED.NAME} command. Example:
2265 jtag configure DOTTED.NAME -event tap-enable @{
2270 @item @b{tap-disable}
2271 @*Executed by @b{jtag tapdisable DOTTED.NAME} command. Example:
2273 jtag configure DOTTED.NAME -event tap-disable @{
2274 puts "Disabling CPU"
2280 @anchor{Target Create}
2281 @section Target Create
2283 @cindex target creation
2286 @b{target} @b{create} <@var{NAME}> <@var{TYPE}> <@var{PARAMS ...}>
2288 @*This command creates a GDB debug target that refers to a specific JTAG tap.
2289 @comment START params
2292 @* Is the name of the debug target. By convention it should be the tap
2293 DOTTED.NAME. This name is also used to create the target object
2294 command, and in other places the target needs to be identified.
2296 @* Specifies the target type, i.e.: ARM7TDMI, or Cortex-M3. Currently supported targets are:
2297 @comment START types
2314 @*PARAMs are various target configuration parameters. The following ones are mandatory:
2315 @comment START mandatory
2317 @item @b{-endian big|little}
2318 @item @b{-chain-position DOTTED.NAME}
2319 @comment end MANDATORY
2324 @section Target Config/Cget Options
2325 These options can be specified when the target is created, or later
2326 via the configure option or to query the target via cget.
2328 You should specify a working area if you can; typically it uses some
2329 on-chip SRAM. Such a working area can speed up many things, including bulk
2330 writes to target memory; flash operations like checking to see if memory needs
2331 to be erased; GDB memory checksumming; and may help perform otherwise
2332 unavailable operations (like some coprocessor operations on ARM7/9 systems).
2334 @item @b{-type} - returns the target type
2335 @item @b{-event NAME BODY} see Target events
2336 @item @b{-work-area-virt [ADDRESS]} specify/set the work area base address
2337 which will be used when an MMU is active.
2338 @item @b{-work-area-phys [ADDRESS]} specify/set the work area base address
2339 which will be used when an MMU is inactive.
2340 @item @b{-work-area-size [ADDRESS]} specify/set the work area
2341 @item @b{-work-area-backup [0|1]} does the work area get backed up;
2342 by default, it doesn't. When possible, use a working_area that doesn't
2343 need to be backed up, since performing a backup slows down operations.
2344 @item @b{-endian [big|little]}
2345 @item @b{-variant [NAME]} some chips have variants OpenOCD needs to know about
2346 @item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
2350 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
2351 set name [target number $x]
2352 set y [$name cget -endian]
2353 set z [$name cget -type]
2354 puts [format "Chip %d is %s, Endian: %s, type: %s" $x $y $z]
2358 @section Target Variants
2361 @* Use variant @option{lm3s} when debugging older Stellaris LM3S targets.
2362 This will cause OpenOCD to use a software reset rather than asserting
2363 SRST, to avoid a issue with clearing the debug registers.
2364 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2365 be detected and the normal reset behaviour used.
2367 @*Supported variants are
2368 @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
2369 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
2371 @* Use variant @option{ejtag_srst} when debugging targets that do not
2372 provide a functional SRST line on the EJTAG connector. This causes
2373 OpenOCD to instead use an EJTAG software reset command to reset the
2374 processor. You still need to enable @option{srst} on the reset
2375 configuration command to enable OpenOCD hardware reset functionality.
2376 @comment END variants
2378 @section working_area - Command Removed
2379 @cindex working_area
2380 @*@b{Please use the ``$_TARGETNAME configure -work-area-... parameters instead}
2381 @* This documentation remains because there are existing scripts that
2382 still use this that need to be converted.
2384 working_area target# address size backup| [virtualaddress]
2386 @* The target# is a the 0 based target numerical index.
2388 @node Flash Commands
2389 @chapter Flash Commands
2391 OpenOCD has different commands for NOR and NAND flash;
2392 the ``flash'' command works with NOR flash, while
2393 the ``nand'' command works with NAND flash.
2394 This partially reflects different hardware technologies:
2395 NOR flash usually supports direct CPU instruction and data bus access,
2396 while data from a NAND flash must be copied to memory before it can be
2397 used. (SPI flash must also be copied to memory before use.)
2398 However, the documentation also uses ``flash'' as a generic term;
2399 for example, ``Put flash configuration in board-specific files''.
2402 As of 28-nov-2008 OpenOCD does not know how to program a SPI
2403 flash that a micro may boot from. Perhaps you, the reader, would like to
2404 contribute support for this.
2409 @item Configure via the command @command{flash bank}
2410 @* Do this in a board-specific configuration file,
2411 passing parameters as needed by the driver.
2412 @item Operate on the flash via @command{flash subcommand}
2413 @* Often commands to manipulate the flash are typed by a human, or run
2414 via a script in some automated way. Common tasks include writing a
2415 boot loader, operating system, or other data.
2417 @* Flashing via GDB requires the flash be configured via ``flash
2418 bank'', and the GDB flash features be enabled.
2419 @xref{GDB Configuration}.
2422 Many CPUs have the ablity to ``boot'' from the first flash bank.
2423 This means that misprograming that bank can ``brick'' a system,
2424 so that it can't boot.
2425 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
2426 board by (re)installing working boot firmware.
2428 @section Flash Configuration Commands
2429 @cindex flash configuration
2431 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
2432 Configures a flash bank which provides persistent storage
2433 for addresses from @math{base} to @math{base + size - 1}.
2434 These banks will often be visible to GDB through the target's memory map.
2435 In some cases, configuring a flash bank will activate extra commands;
2436 see the driver-specific documentation.
2439 @item @var{driver} ... identifies the controller driver
2440 associated with the flash bank being declared.
2441 This is usually @code{cfi} for external flash, or else
2442 the name of a microcontroller with embedded flash memory.
2443 @xref{Flash Driver List}.
2444 @item @var{base} ... Base address of the flash chip.
2445 @item @var{size} ... Size of the chip, in bytes.
2446 For some drivers, this value is detected from the hardware.
2447 @item @var{chip_width} ... Width of the flash chip, in bytes;
2448 ignored for most microcontroller drivers.
2449 @item @var{bus_width} ... Width of the data bus used to access the
2450 chip, in bytes; ignored for most microcontroller drivers.
2451 @item @var{target} ... Names the target used to issue
2452 commands to the flash controller.
2453 @comment Actually, it's currently a controller-specific parameter...
2454 @item @var{driver_options} ... drivers may support, or require,
2455 additional parameters. See the driver-specific documentation
2456 for more information.
2459 This command is not available after OpenOCD initialization has completed.
2460 Use it in board specific configuration files, not interactively.
2464 @comment the REAL name for this command is "ocd_flash_banks"
2465 @comment less confusing would be: "flash list" (like "nand list")
2466 @deffn Command {flash banks}
2467 Prints a one-line summary of each device declared
2468 using @command{flash bank}, numbered from zero.
2469 Note that this is the @emph{plural} form;
2470 the @emph{singular} form is a very different command.
2473 @deffn Command {flash probe} num
2474 Identify the flash, or validate the parameters of the configured flash. Operation
2475 depends on the flash type.
2476 The @var{num} parameter is a value shown by @command{flash banks}.
2477 Most flash commands will implicitly @emph{autoprobe} the bank;
2478 flash drivers can distinguish between probing and autoprobing,
2479 but most don't bother.
2482 @section Erasing, Reading, Writing to Flash
2483 @cindex flash erasing
2484 @cindex flash reading
2485 @cindex flash writing
2486 @cindex flash programming
2488 One feature distinguishing NOR flash from NAND or serial flash technologies
2489 is that for read access, it acts exactly like any other addressible memory.
2490 This means you can use normal memory read commands like @command{mdw} or
2491 @command{dump_image} with it, with no special @command{flash} subcommands.
2492 @xref{Memory access}, and @ref{Image access}.
2494 Write access works differently. Flash memory normally needs to be erased
2495 before it's written. Erasing a sector turns all of its bits to ones, and
2496 writing can turn ones into zeroes. This is why there are special commands
2497 for interactive erasing and writing, and why GDB needs to know which parts
2498 of the address space hold NOR flash memory.
2501 Most of these erase and write commands leverage the fact that NOR flash
2502 chips consume target address space. They implicitly refer to the current
2503 JTAG target, and map from an address in that target's address space
2504 back to a flash bank.
2505 @comment In May 2009, those mappings may fail if any bank associated
2506 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
2507 A few commands use abstract addressing based on bank and sector numbers,
2508 and don't depend on searching the current target and its address space.
2509 Avoid confusing the two command models.
2512 Some flash chips implement software protection against accidental writes,
2513 since such buggy writes could in some cases ``brick'' a system.
2514 For such systems, erasing and writing may require sector protection to be
2516 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
2517 and AT91SAM7 on-chip flash.
2518 @xref{flash protect}.
2520 @anchor{flash erase_sector}
2521 @deffn Command {flash erase_sector} num first last
2522 Erase sectors in bank @var{num}, starting at sector @var{first} up to and including
2523 @var{last}. Sector numbering starts at 0.
2524 The @var{num} parameter is a value shown by @command{flash banks}.
2527 @deffn Command {flash erase_address} address length
2528 Erase sectors starting at @var{address} for @var{length} bytes.
2529 The flash bank to use is inferred from the @var{address}, and
2530 the specified length must stay within that bank.
2531 As a special case, when @var{length} is zero and @var{address} is
2532 the start of the bank, the whole flash is erased.
2535 @deffn Command {flash fillw} address word length
2536 @deffnx Command {flash fillh} address halfword length
2537 @deffnx Command {flash fillb} address byte length
2538 Fills flash memory with the specified @var{word} (32 bits),
2539 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
2540 starting at @var{address} and continuing
2541 for @var{length} units (word/halfword/byte).
2542 No erasure is done before writing; when needed, that must be done
2543 before issuing this command.
2544 Writes are done in blocks of up to 1024 bytes, and each write is
2545 verified by reading back the data and comparing it to what was written.
2546 The flash bank to use is inferred from the @var{address} of
2547 each block, and the specified length must stay within that bank.
2549 @comment no current checks for errors if fill blocks touch multiple banks!
2551 @anchor{flash write_bank}
2552 @deffn Command {flash write_bank} num filename offset
2553 Write the binary @file{filename} to flash bank @var{num},
2554 starting at @var{offset} bytes from the beginning of the bank.
2555 The @var{num} parameter is a value shown by @command{flash banks}.
2558 @anchor{flash write_image}
2559 @deffn Command {flash write_image} [erase] filename [offset] [type]
2560 Write the image @file{filename} to the current target's flash bank(s).
2561 A relocation @var{offset} may be specified, in which case it is added
2562 to the base address for each section in the image.
2563 The file [@var{type}] can be specified
2564 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
2565 @option{elf} (ELF file), @option{s19} (Motorola s19).
2566 @option{mem}, or @option{builder}.
2567 The relevant flash sectors will be erased prior to programming
2568 if the @option{erase} parameter is given.
2569 The flash bank to use is inferred from the @var{address} of
2573 @section Other Flash commands
2574 @cindex flash protection
2576 @deffn Command {flash erase_check} num
2577 Check erase state of sectors in flash bank @var{num},
2578 and display that status.
2579 The @var{num} parameter is a value shown by @command{flash banks}.
2580 This is the only operation that
2581 updates the erase state information displayed by @option{flash info}. That means you have
2582 to issue an @command{flash erase_check} command after erasing or programming the device
2583 to get updated information.
2584 (Code execution may have invalidated any state records kept by OpenOCD.)
2587 @deffn Command {flash info} num
2588 Print info about flash bank @var{num}
2589 The @var{num} parameter is a value shown by @command{flash banks}.
2590 The information includes per-sector protect status.
2593 @anchor{flash protect}
2594 @deffn Command {flash protect} num first last (on|off)
2595 Enable (@var{on}) or disable (@var{off}) protection of flash sectors
2596 @var{first} to @var{last} of flash bank @var{num}.
2597 The @var{num} parameter is a value shown by @command{flash banks}.
2600 @deffn Command {flash protect_check} num
2601 Check protection state of sectors in flash bank @var{num}.
2602 The @var{num} parameter is a value shown by @command{flash banks}.
2603 @comment @option{flash erase_sector} using the same syntax.
2606 @anchor{Flash Driver List}
2607 @section Flash Drivers, Options, and Commands
2608 As noted above, the @command{flash bank} command requires a driver name,
2609 and allows driver-specific options and behaviors.
2610 Some drivers also activate driver-specific commands.
2612 @subsection External Flash
2614 @deffn {Flash Driver} cfi
2615 @cindex Common Flash Interface
2617 The ``Common Flash Interface'' (CFI) is the main standard for
2618 external NOR flash chips, each of which connects to a
2619 specific external chip select on the CPU.
2620 Frequently the first such chip is used to boot the system.
2621 Your board's @code{reset-init} handler might need to
2622 configure additional chip selects using other commands (like: @command{mww} to
2623 configure a bus and its timings) , or
2624 perhaps configure a GPIO pin that controls the ``write protect'' pin
2626 The CFI driver can use a target-specific working area to significantly
2629 The CFI driver can accept the following optional parameters, in any order:
2632 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
2633 like AM29LV010 and similar types.
2634 @item @var{x16_as_x8} ...
2637 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
2638 wide on a sixteen bit bus:
2641 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
2642 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
2646 @subsection Internal Flash (Microcontrollers)
2648 @deffn {Flash Driver} aduc702x
2649 The ADUC702x analog microcontrollers from ST Micro
2650 include internal flash and use ARM7TDMI cores.
2651 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
2652 The setup command only requires the @var{target} argument
2653 since all devices in this family have the same memory layout.
2656 flash bank aduc702x 0 0 0 0 $_TARGETNAME
2660 @deffn {Flash Driver} at91sam7
2661 All members of the AT91SAM7 microcontroller family from Atmel
2662 include internal flash and use ARM7TDMI cores.
2663 The driver automatically recognizes a number of these chips using
2664 the chip identification register, and autoconfigures itself.
2667 flash bank at91sam7 0 0 0 0 $_TARGETNAME
2670 For chips which are not recognized by the controller driver, you must
2671 provide additional parameters in the following order:
2674 @item @var{chip_model} ... label used with @command{flash info}
2676 @item @var{sectors_per_bank}
2677 @item @var{pages_per_sector}
2678 @item @var{pages_size}
2679 @item @var{num_nvm_bits}
2680 @item @var{freq_khz} ... required if an external clock is provided,
2681 optional (but recommended) when the oscillator frequency is known
2684 It is recommended that you provide zeroes for all of those values
2685 except the clock frequency, so that everything except that frequency
2686 will be autoconfigured.
2687 Knowing the frequency helps ensure correct timings for flash access.
2689 The flash controller handles erases automatically on a page (128/256 byte)
2690 basis, so explicit erase commands are not necessary for flash programming.
2691 However, there is an ``EraseAll`` command that can erase an entire flash
2692 plane (of up to 256KB), and it will be used automatically when you issue
2693 @command{flash erase_sector} or @command{flash erase_address} commands.
2695 @deffn Command {at91sam7 gpnvm} bitnum (set|clear)
2696 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
2697 bit for the processor. Each processor has a number of such bits,
2698 used for controlling features such as brownout detection (so they
2699 are not truly general purpose).
2701 This assumes that the first flash bank (number 0) is associated with
2702 the appropriate at91sam7 target.
2707 @deffn {Flash Driver} avr
2708 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
2709 @emph{The current implementation is incomplete.}
2710 @comment - defines mass_erase ... pointless given flash_erase_address
2713 @deffn {Flash Driver} ecosflash
2714 @emph{No idea what this is...}
2715 The @var{ecosflash} driver defines one mandatory parameter,
2716 the name of a modules of target code which is downloaded
2720 @deffn {Flash Driver} lpc2000
2721 Most members of the LPC2000 microcontroller family from NXP
2722 include internal flash and use ARM7TDMI cores.
2723 The @var{lpc2000} driver defines two mandatory and one optional parameters,
2724 which must appear in the following order:
2727 @item @var{variant} ... required, may be
2728 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
2729 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
2730 @item @var{clock_kHz} ... the frequency, in kiloHertz,
2731 at which the core is running
2732 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
2733 telling the driver to calculate a valid checksum for the exception vector table.
2736 LPC flashes don't require the chip and bus width to be specified.
2739 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
2740 lpc2000_v2 14765 calc_checksum
2744 @deffn {Flash Driver} lpc288x
2745 The LPC2888 microcontroller from NXP needs slightly different flash
2746 support from its lpc2000 siblings.
2747 The @var{lpc288x} driver defines one mandatory parameter,
2748 the programming clock rate in Hz.
2749 LPC flashes don't require the chip and bus width to be specified.
2752 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
2756 @deffn {Flash Driver} ocl
2757 @emph{No idea what this is, other than using some arm7/arm9 core.}
2760 flash bank ocl 0 0 0 0 $_TARGETNAME
2764 @deffn {Flash Driver} pic32mx
2765 The PIC32MX microcontrollers are based on the MIPS 4K cores,
2766 and integrate flash memory.
2767 @emph{The current implementation is incomplete.}
2770 flash bank pix32mx 0 0 0 0 $_TARGETNAME
2773 @comment numerous *disabled* commands are defined:
2774 @comment - chip_erase ... pointless given flash_erase_address
2775 @comment - lock, unlock ... pointless given protect on/off (yes?)
2776 @comment - pgm_word ... shouldn't bank be deduced from address??
2777 Some pic32mx-specific commands are defined:
2778 @deffn Command {pic32mx pgm_word} address value bank
2779 Programs the specified 32-bit @var{value} at the given @var{address}
2780 in the specified chip @var{bank}.
2784 @deffn {Flash Driver} stellaris
2785 All members of the Stellaris LM3Sxxx microcontroller family from
2787 include internal flash and use ARM Cortex M3 cores.
2788 The driver automatically recognizes a number of these chips using
2789 the chip identification register, and autoconfigures itself.
2790 @footnote{Currently there is a @command{stellaris mass_erase} command.
2791 That seems pointless since the same effect can be had using the
2792 standard @command{flash erase_address} command.}
2795 flash bank stellaris 0 0 0 0 $_TARGETNAME
2799 @deffn {Flash Driver} stm32x
2800 All members of the STM32 microcontroller family from ST Microelectronics
2801 include internal flash and use ARM Cortex M3 cores.
2802 The driver automatically recognizes a number of these chips using
2803 the chip identification register, and autoconfigures itself.
2806 flash bank stm32x 0 0 0 0 $_TARGETNAME
2809 Some stm32x-specific commands
2810 @footnote{Currently there is a @command{stm32x mass_erase} command.
2811 That seems pointless since the same effect can be had using the
2812 standard @command{flash erase_address} command.}
2815 @deffn Command {stm32x lock} num
2816 Locks the entire stm32 device.
2817 The @var{num} parameter is a value shown by @command{flash banks}.
2820 @deffn Command {stm32x unlock} num
2821 Unlocks the entire stm32 device.
2822 The @var{num} parameter is a value shown by @command{flash banks}.
2825 @deffn Command {stm32x options_read} num
2826 Read and display the stm32 option bytes written by
2827 the @command{stm32x options_write} command.
2828 The @var{num} parameter is a value shown by @command{flash banks}.
2831 @deffn Command {stm32x options_write} num (SWWDG|HWWDG) (RSTSTNDBY|NORSTSTNDBY) (RSTSTOP|NORSTSTOP)
2832 Writes the stm32 option byte with the specified values.
2833 The @var{num} parameter is a value shown by @command{flash banks}.
2837 @deffn {Flash Driver} str7x
2838 All members of the STR7 microcontroller family from ST Microelectronics
2839 include internal flash and use ARM7TDMI cores.
2840 The @var{str7x} driver defines one mandatory parameter, @var{variant},
2841 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
2844 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
2848 @deffn {Flash Driver} str9x
2849 Most members of the STR9 microcontroller family from ST Microelectronics
2850 include internal flash and use ARM966E cores.
2851 The str9 needs the flash controller to be configured using
2852 the @command{str9x flash_config} command prior to Flash programming.
2855 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
2856 str9x flash_config 0 4 2 0 0x80000
2859 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
2860 Configures the str9 flash controller.
2861 The @var{num} parameter is a value shown by @command{flash banks}.
2864 @item @var{bbsr} - Boot Bank Size register
2865 @item @var{nbbsr} - Non Boot Bank Size register
2866 @item @var{bbadr} - Boot Bank Start Address register
2867 @item @var{nbbadr} - Boot Bank Start Address register
2873 @deffn {Flash Driver} tms470
2874 Most members of the TMS470 microcontroller family from Texas Instruments
2875 include internal flash and use ARM7TDMI cores.
2876 This driver doesn't require the chip and bus width to be specified.
2878 Some tms470-specific commands are defined:
2880 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
2881 Saves programming keys in a register, to enable flash erase and write commands.
2884 @deffn Command {tms470 osc_mhz} clock_mhz
2885 Reports the clock speed, which is used to calculate timings.
2888 @deffn Command {tms470 plldis} (0|1)
2889 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
2894 @subsection str9xpec driver
2897 Here is some background info to help
2898 you better understand how this driver works. OpenOCD has two flash drivers for
2902 Standard driver @option{str9x} programmed via the str9 core. Normally used for
2903 flash programming as it is faster than the @option{str9xpec} driver.
2905 Direct programming @option{str9xpec} using the flash controller. This is an
2906 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
2907 core does not need to be running to program using this flash driver. Typical use
2908 for this driver is locking/unlocking the target and programming the option bytes.
2911 Before we run any commands using the @option{str9xpec} driver we must first disable
2912 the str9 core. This example assumes the @option{str9xpec} driver has been
2913 configured for flash bank 0.
2915 # assert srst, we do not want core running
2916 # while accessing str9xpec flash driver
2918 # turn off target polling
2921 str9xpec enable_turbo 0
2923 str9xpec options_read 0
2924 # re-enable str9 core
2925 str9xpec disable_turbo 0
2929 The above example will read the str9 option bytes.
2930 When performing a unlock remember that you will not be able to halt the str9 - it
2931 has been locked. Halting the core is not required for the @option{str9xpec} driver
2932 as mentioned above, just issue the commands above manually or from a telnet prompt.
2934 @subsubsection str9xpec driver options
2936 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target}>
2937 @*Before using the flash commands the turbo mode must be enabled using str9xpec
2938 @option{enable_turbo} <@var{num>.}
2940 Only use this driver for locking/unlocking the device or configuring the option bytes.
2941 Use the standard str9 driver for programming.
2943 @subsubsection str9xpec specific commands
2944 @cindex str9xpec specific commands
2945 These are flash specific commands when using the str9xpec driver.
2948 @item @b{str9xpec enable_turbo} <@var{num}>
2949 @cindex str9xpec enable_turbo
2950 @*enable turbo mode, will simply remove the str9 from the chain and talk
2951 directly to the embedded flash controller.
2952 @item @b{str9xpec disable_turbo} <@var{num}>
2953 @cindex str9xpec disable_turbo
2954 @*restore the str9 into JTAG chain.
2955 @item @b{str9xpec lock} <@var{num}>
2956 @cindex str9xpec lock
2957 @*lock str9 device. The str9 will only respond to an unlock command that will
2959 @item @b{str9xpec unlock} <@var{num}>
2960 @cindex str9xpec unlock
2961 @*unlock str9 device.
2962 @item @b{str9xpec options_read} <@var{num}>
2963 @cindex str9xpec options_read
2964 @*read str9 option bytes.
2965 @item @b{str9xpec options_write} <@var{num}>
2966 @cindex str9xpec options_write
2967 @*write str9 option bytes.
2970 @subsubsection STR9 option byte configuration
2971 @cindex STR9 option byte configuration
2974 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
2975 @cindex str9xpec options_cmap
2976 @*configure str9 boot bank.
2977 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
2978 @cindex str9xpec options_lvdthd
2979 @*configure str9 lvd threshold.
2980 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
2981 @cindex str9xpec options_lvdsel
2982 @*configure str9 lvd source.
2983 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
2984 @cindex str9xpec options_lvdwarn
2985 @*configure str9 lvd reset warning source.
2990 @subsection mFlash Configuration
2991 @cindex mFlash Configuration
2992 @b{mflash bank} <@var{soc}> <@var{base}> <@var{RST pin}> <@var{target}>
2994 @*Configures a mflash for <@var{soc}> host bank at
2995 <@var{base}>. Pin number format is dependent on host GPIO calling convention.
2996 Currently, mflash bank support s3c2440 and pxa270.
2998 (ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1.
3001 mflash bank s3c2440 0x10000000 1b 0
3004 (ex. of pxa270) mflash <@var{RST pin}> is GPIO 43.
3007 mflash bank pxa270 0x08000000 43 0
3010 @subsection mFlash commands
3011 @cindex mFlash commands
3014 @item @b{mflash probe}
3015 @cindex mflash probe
3017 @item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
3018 @cindex mflash write
3019 @*Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
3020 <@var{offset}> bytes from the beginning of the bank.
3021 @item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
3023 @*Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
3025 @item @b{mflash config pll} <@var{frequency}>
3026 @cindex mflash config pll
3027 @*Configure mflash pll. <@var{frequency}> is input frequency of mflash. The order is Hz.
3028 Issuing this command will erase mflash's whole internal nand and write new pll.
3029 After this command, mflash needs power-on-reset for normal operation.
3030 If pll was newly configured, storage and boot(optional) info also need to be update.
3031 @item @b{mflash config boot}
3032 @cindex mflash config boot
3033 @*Configure bootable option. If bootable option is set, mflash offer the first 8 sectors
3035 @item @b{mflash config storage}
3036 @cindex mflash config storage
3037 @*Configure storage information. For the normal storage operation, this information must be
3041 @node NAND Flash Commands
3042 @chapter NAND Flash Commands
3045 Compared to NOR or SPI flash, NAND devices are inexpensive
3046 and high density. Today's NAND chips, and multi-chip modules,
3047 commonly hold multiple GigaBytes of data.
3049 NAND chips consist of a number of ``erase blocks'' of a given
3050 size (such as 128 KBytes), each of which is divided into a
3051 number of pages (of perhaps 512 or 2048 bytes each). Each
3052 page of a NAND flash has an ``out of band'' (OOB) area to hold
3053 Error Correcting Code (ECC) and other metadata, usually 16 bytes
3054 of OOB for every 512 bytes of page data.
3056 One key characteristic of NAND flash is that its error rate
3057 is higher than that of NOR flash. In normal operation, that
3058 ECC is used to correct and detect errors. However, NAND
3059 blocks can also wear out and become unusable; those blocks
3060 are then marked "bad". NAND chips are even shipped from the
3061 manufacturer with a few bad blocks. The highest density chips
3062 use a technology (MLC) that wears out more quickly, so ECC
3063 support is increasingly important as a way to detect blocks
3064 that have begun to fail, and help to preserve data integrity
3065 with techniques such as wear leveling.
3067 Software is used to manage the ECC. Some controllers don't
3068 support ECC directly; in those cases, software ECC is used.
3069 Other controllers speed up the ECC calculations with hardware.
3070 Single-bit error correction hardware is routine. Controllers
3071 geared for newer MLC chips may correct 4 or more errors for
3072 every 512 bytes of data.
3074 You will need to make sure that any data you write using
3075 OpenOCD includes the apppropriate kind of ECC. For example,
3076 that may mean passing the @code{oob_softecc} flag when
3077 writing NAND data, or ensuring that the correct hardware
3080 The basic steps for using NAND devices include:
3082 @item Declare via the command @command{nand device}
3083 @* Do this in a board-specific configuration file,
3084 passing parameters as needed by the controller.
3085 @item Configure each device using @command{nand probe}.
3086 @* Do this only after the associated target is set up,
3087 such as in its reset-init script or in procures defined
3088 to access that device.
3089 @item Operate on the flash via @command{nand subcommand}
3090 @* Often commands to manipulate the flash are typed by a human, or run
3091 via a script in some automated way. Common task include writing a
3092 boot loader, operating system, or other data needed to initialize or
3096 @b{NOTE:} At the time this text was written, the largest NAND
3097 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
3098 This is because the variables used to hold offsets and lengths
3099 are only 32 bits wide.
3100 (Larger chips may work in some cases, unless an offset or length
3101 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
3102 Some larger devices will work, since they are actually multi-chip
3103 modules with two smaller chips and individual chipselect lines.
3105 @section NAND Configuration Commands
3106 @cindex NAND configuration
3108 NAND chips must be declared in configuration scripts,
3109 plus some additional configuration that's done after
3110 OpenOCD has initialized.
3112 @deffn {Config Command} {nand device} controller target [configparams...]
3113 Declares a NAND device, which can be read and written to
3114 after it has been configured through @command{nand probe}.
3115 In OpenOCD, devices are single chips; this is unlike some
3116 operating systems, which may manage multiple chips as if
3117 they were a single (larger) device.
3118 In some cases, configuring a device will activate extra
3119 commands; see the controller-specific documentation.
3121 @b{NOTE:} This command is not available after OpenOCD
3122 initialization has completed. Use it in board specific
3123 configuration files, not interactively.
3126 @item @var{controller} ... identifies the controller driver
3127 associated with the NAND device being declared.
3128 @xref{NAND Driver List}.
3129 @item @var{target} ... names the target used when issuing
3130 commands to the NAND controller.
3131 @comment Actually, it's currently a controller-specific parameter...
3132 @item @var{configparams} ... controllers may support, or require,
3133 additional parameters. See the controller-specific documentation
3134 for more information.
3138 @deffn Command {nand list}
3139 Prints a one-line summary of each device declared
3140 using @command{nand device}, numbered from zero.
3141 Note that un-probed devices show no details.
3144 @deffn Command {nand probe} num
3145 Probes the specified device to determine key characteristics
3146 like its page and block sizes, and how many blocks it has.
3147 The @var{num} parameter is the value shown by @command{nand list}.
3148 You must (successfully) probe a device before you can use
3149 it with most other NAND commands.
3152 @section Erasing, Reading, Writing to NAND Flash
3154 @deffn Command {nand dump} num filename offset length [oob_option]
3155 @cindex NAND reading
3156 Reads binary data from the NAND device and writes it to the file,
3157 starting at the specified offset.
3158 The @var{num} parameter is the value shown by @command{nand list}.
3160 Use a complete path name for @var{filename}, so you don't depend
3161 on the directory used to start the OpenOCD server.
3163 The @var{offset} and @var{length} must be exact multiples of the
3164 device's page size. They describe a data region; the OOB data
3165 associated with each such page may also be accessed.
3167 @b{NOTE:} At the time this text was written, no error correction
3168 was done on the data that's read, unless raw access was disabled
3169 and the underlying NAND controller driver had a @code{read_page}
3170 method which handled that error correction.
3172 By default, only page data is saved to the specified file.
3173 Use an @var{oob_option} parameter to save OOB data:
3175 @item no oob_* parameter
3176 @*Output file holds only page data; OOB is discarded.
3177 @item @code{oob_raw}
3178 @*Output file interleaves page data and OOB data;
3179 the file will be longer than "length" by the size of the
3180 spare areas associated with each data page.
3181 Note that this kind of "raw" access is different from
3182 what's implied by @command{nand raw_access}, which just
3183 controls whether a hardware-aware access method is used.
3184 @item @code{oob_only}
3185 @*Output file has only raw OOB data, and will
3186 be smaller than "length" since it will contain only the
3187 spare areas associated with each data page.
3191 @deffn Command {nand erase} num offset length
3192 @cindex NAND erasing
3193 @cindex NAND programming
3194 Erases blocks on the specified NAND device, starting at the
3195 specified @var{offset} and continuing for @var{length} bytes.
3196 Both of those values must be exact multiples of the device's
3197 block size, and the region they specify must fit entirely in the chip.
3198 The @var{num} parameter is the value shown by @command{nand list}.
3200 @b{NOTE:} This command will try to erase bad blocks, when told
3201 to do so, which will probably invalidate the manufacturer's bad
3203 For the remainder of the current server session, @command{nand info}
3204 will still report that the block ``is'' bad.
3207 @deffn Command {nand write} num filename offset [option...]
3208 @cindex NAND writing
3209 @cindex NAND programming
3210 Writes binary data from the file into the specified NAND device,
3211 starting at the specified offset. Those pages should already
3212 have been erased; you can't change zero bits to one bits.
3213 The @var{num} parameter is the value shown by @command{nand list}.
3215 Use a complete path name for @var{filename}, so you don't depend
3216 on the directory used to start the OpenOCD server.
3218 The @var{offset} must be an exact multiple of the device's page size.
3219 All data in the file will be written, assuming it doesn't run
3220 past the end of the device.
3221 Only full pages are written, and any extra space in the last
3222 page will be filled with 0xff bytes. (That includes OOB data,
3223 if that's being written.)
3225 @b{NOTE:} At the time this text was written, bad blocks are
3226 ignored. That is, this routine will not skip bad blocks,
3227 but will instead try to write them. This can cause problems.
3229 Provide at most one @var{option} parameter. With some
3230 NAND drivers, the meanings of these parameters may change
3231 if @command{nand raw_access} was used to disable hardware ECC.
3233 @item no oob_* parameter
3234 @*File has only page data, which is written.
3235 If raw acccess is in use, the OOB area will not be written.
3236 Otherwise, if the underlying NAND controller driver has
3237 a @code{write_page} routine, that routine may write the OOB
3238 with hardware-computed ECC data.
3239 @item @code{oob_only}
3240 @*File has only raw OOB data, which is written to the OOB area.
3241 Each page's data area stays untouched. @i{This can be a dangerous
3242 option}, since it can invalidate the ECC data.
3243 You may need to force raw access to use this mode.
3244 @item @code{oob_raw}
3245 @*File interleaves data and OOB data, both of which are written
3246 If raw access is enabled, the data is written first, then the
3248 Otherwise, if the underlying NAND controller driver has
3249 a @code{write_page} routine, that routine may modify the OOB
3250 before it's written, to include hardware-computed ECC data.
3251 @item @code{oob_softecc}
3252 @*File has only page data, which is written.
3253 The OOB area is filled with 0xff, except for a standard 1-bit
3254 software ECC code stored in conventional locations.
3255 You might need to force raw access to use this mode, to prevent
3256 the underlying driver from applying hardware ECC.
3257 @item @code{oob_softecc_kw}
3258 @*File has only page data, which is written.
3259 The OOB area is filled with 0xff, except for a 4-bit software ECC
3260 specific to the boot ROM in Marvell Kirkwood SoCs.
3261 You might need to force raw access to use this mode, to prevent
3262 the underlying driver from applying hardware ECC.
3266 @section Other NAND commands
3267 @cindex NAND other commands
3269 @deffn Command {nand check_bad_blocks} [offset length]
3270 Checks for manufacturer bad block markers on the specified NAND
3271 device. If no parameters are provided, checks the whole
3272 device; otherwise, starts at the specified @var{offset} and
3273 continues for @var{length} bytes.
3274 Both of those values must be exact multiples of the device's
3275 block size, and the region they specify must fit entirely in the chip.
3276 The @var{num} parameter is the value shown by @command{nand list}.
3278 @b{NOTE:} Before using this command you should force raw access
3279 with @command{nand raw_access enable} to ensure that the underlying
3280 driver will not try to apply hardware ECC.
3283 @deffn Command {nand info} num
3284 The @var{num} parameter is the value shown by @command{nand list}.
3285 This prints the one-line summary from "nand list", plus for
3286 devices which have been probed this also prints any known
3287 status for each block.
3290 @deffn Command {nand raw_access} num <enable|disable>
3291 Sets or clears an flag affecting how page I/O is done.
3292 The @var{num} parameter is the value shown by @command{nand list}.
3294 This flag is cleared (disabled) by default, but changing that
3295 value won't affect all NAND devices. The key factor is whether
3296 the underlying driver provides @code{read_page} or @code{write_page}
3297 methods. If it doesn't provide those methods, the setting of
3298 this flag is irrelevant; all access is effectively ``raw''.
3300 When those methods exist, they are normally used when reading
3301 data (@command{nand dump} or reading bad block markers) or
3302 writing it (@command{nand write}). However, enabling
3303 raw access (setting the flag) prevents use of those methods,
3304 bypassing hardware ECC logic.
3305 @i{This can be a dangerous option}, since writing blocks
3306 with the wrong ECC data can cause them to be marked as bad.
3309 @anchor{NAND Driver List}
3310 @section NAND Drivers, Options, and Commands
3311 As noted above, the @command{nand device} command allows
3312 driver-specific options and behaviors.
3313 Some controllers also activate controller-specific commands.
3315 @deffn {NAND Driver} davinci
3316 This driver handles the NAND controllers found on DaVinci family
3317 chips from Texas Instruments.
3318 It takes three extra parameters:
3319 address of the NAND chip;
3320 hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
3321 address of the AEMIF controller on this processor.
3323 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
3325 All DaVinci processors support the single-bit ECC hardware,
3326 and newer ones also support the four-bit ECC hardware.
3327 The @code{write_page} and @code{read_page} methods are used
3328 to implement those ECC modes, unless they are disabled using
3329 the @command{nand raw_access} command.
3332 @deffn {NAND Driver} lpc3180
3333 These controllers require an extra @command{nand device}
3334 parameter: the clock rate used by the controller.
3335 @deffn Command {lpc3180 select} num [mlc|slc]
3336 Configures use of the MLC or SLC controller mode.
3337 MLC implies use of hardware ECC.
3338 The @var{num} parameter is the value shown by @command{nand list}.
3341 At this writing, this driver includes @code{write_page}
3342 and @code{read_page} methods. Using @command{nand raw_access}
3343 to disable those methods will prevent use of hardware ECC
3344 in the MLC controller mode, but won't change SLC behavior.
3346 @comment current lpc3180 code won't issue 5-byte address cycles
3348 @deffn {NAND Driver} orion
3349 These controllers require an extra @command{nand device}
3350 parameter: the address of the controller.
3352 nand device orion 0xd8000000
3354 These controllers don't define any specialized commands.
3355 At this writing, their drivers don't include @code{write_page}
3356 or @code{read_page} methods, so @command{nand raw_access} won't
3357 change any behavior.
3360 @deffn {NAND Driver} s3c2410
3361 @deffnx {NAND Driver} s3c2412
3362 @deffnx {NAND Driver} s3c2440
3363 @deffnx {NAND Driver} s3c2443
3364 These S3C24xx family controllers don't have any special
3365 @command{nand device} options, and don't define any
3366 specialized commands.
3367 At this writing, their drivers don't include @code{write_page}
3368 or @code{read_page} methods, so @command{nand raw_access} won't
3369 change any behavior.
3372 @node General Commands
3373 @chapter General Commands
3376 The commands documented in this chapter here are common commands that
3377 you, as a human, may want to type and see the output of. Configuration type
3378 commands are documented elsewhere.
3382 @item @b{Source Of Commands}
3383 @* OpenOCD commands can occur in a configuration script (discussed
3384 elsewhere) or typed manually by a human or supplied programatically,
3385 or via one of several TCP/IP Ports.
3387 @item @b{From the human}
3388 @* A human should interact with the telnet interface (default port: 4444)
3389 or via GDB (default port 3333).
3391 To issue commands from within a GDB session, use the @option{monitor}
3392 command, e.g. use @option{monitor poll} to issue the @option{poll}
3393 command. All output is relayed through the GDB session.
3395 @item @b{Machine Interface}
3396 The Tcl interface's intent is to be a machine interface. The default Tcl
3401 @section Daemon Commands
3403 @subsection sleep [@var{msec}]
3405 @*Wait for n milliseconds before resuming. Useful in connection with script files
3406 (@var{script} command and @var{target_script} configuration).
3408 @subsection shutdown
3410 @*Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
3412 @anchor{debug_level}
3413 @subsection debug_level [@var{n}]
3415 @*Display or adjust debug level to n<0-3>
3417 @subsection fast [@var{enable|disable}]
3419 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
3420 downloads and fast memory access will work if the JTAG interface isn't too fast and
3421 the core doesn't run at a too low frequency. Note that this option only changes the default
3422 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
3425 The target specific "dangerous" optimisation tweaking options may come and go
3426 as more robust and user friendly ways are found to ensure maximum throughput
3427 and robustness with a minimum of configuration.
3429 Typically the "fast enable" is specified first on the command line:
3432 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
3435 @subsection echo <@var{message}>
3437 @*Output message to stdio. e.g. echo "Programming - please wait"
3439 @subsection log_output <@var{file}>
3441 @*Redirect logging to <file> (default: stderr)
3443 @subsection script <@var{file}>
3445 @*Execute commands from <file>
3446 See also: ``source [find FILENAME]''
3448 @section Target state handling
3449 @subsection power <@var{on}|@var{off}>
3451 @*Turn power switch to target on/off.
3452 No arguments: print status.
3453 Not all interfaces support this.
3455 @subsection reg [@option{#}|@option{name}] [value]
3457 @*Access a single register by its number[@option{#}] or by its [@option{name}].
3458 No arguments: list all available registers for the current target.
3459 Number or name argument: display a register.
3460 Number or name and value arguments: set register value.
3462 @subsection poll [@option{on}|@option{off}]
3464 @*Poll the target for its current state. If the target is in debug mode, architecture
3465 specific information about the current state is printed. An optional parameter
3466 allows continuous polling to be enabled and disabled.
3468 @subsection halt [@option{ms}]
3470 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
3471 Default [@option{ms}] is 5 seconds if no arg given.
3472 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
3473 will stop OpenOCD from waiting.
3475 @subsection wait_halt [@option{ms}]
3477 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
3478 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
3481 @subsection resume [@var{address}]
3483 @*Resume the target at its current code position, or at an optional address.
3484 OpenOCD will wait 5 seconds for the target to resume.
3486 @subsection step [@var{address}]
3488 @*Single-step the target at its current code position, or at an optional address.
3490 @anchor{Reset Command}
3491 @subsection reset [@option{run}|@option{halt}|@option{init}]
3493 @*Perform a hard-reset. The optional parameter specifies what should
3494 happen after the reset.
3495 If there is no parameter, a @command{reset run} is executed.
3496 The other options will not work on all systems.
3497 @xref{Reset Configuration}.
3501 @*Let the target run.
3504 @*Immediately halt the target (works only with certain configurations).
3507 @*Immediately halt the target, and execute the reset script (works only with certain
3511 @subsection soft_reset_halt
3513 @*Requesting target halt and executing a soft reset. This is often used
3514 when a target cannot be reset and halted. The target, after reset is
3515 released begins to execute code. OpenOCD attempts to stop the CPU and
3516 then sets the program counter back to the reset vector. Unfortunately
3517 the code that was executed may have left the hardware in an unknown
3521 @anchor{Memory access}
3522 @section Memory access commands
3524 display available RAM memory on OpenOCD host. Used in OpenOCD regression testing scripts. Mainly
3525 useful on embedded targets, PC type hosts have complimentary tools like Valgrind to address
3526 resource tracking problems.
3527 @subsection Memory peek/poke type commands
3528 These commands allow accesses of a specific size to the memory
3529 system. Often these are used to configure the current target in some
3530 special way. For example - one may need to write certian values to the
3531 SDRAM controller to enable SDRAM.
3534 @item To change the current target see the ``targets'' (plural) command
3535 @item In system level scripts these commands are deprecated, please use the TARGET object versions.
3539 @item @b{mdw} <@var{addr}> [@var{count}]
3541 @*display memory words (32bit)
3542 @item @b{mdh} <@var{addr}> [@var{count}]
3544 @*display memory half-words (16bit)
3545 @item @b{mdb} <@var{addr}> [@var{count}]
3547 @*display memory bytes (8bit)
3548 @item @b{mww} <@var{addr}> <@var{value}>
3550 @*write memory word (32bit)
3551 @item @b{mwh} <@var{addr}> <@var{value}>
3553 @*write memory half-word (16bit)
3554 @item @b{mwb} <@var{addr}> <@var{value}>
3556 @*write memory byte (8bit)
3559 @anchor{Image access}
3560 @section Image loading commands
3562 @subsection load_image
3563 @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3565 @*Load image <@var{file}> to target memory at <@var{address}>
3566 @subsection fast_load_image
3567 @b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3568 @cindex fast_load_image
3569 @*Normally you should be using @b{load_image} or GDB load. However, for
3570 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
3571 host), storing the image in memory and uploading the image to the target
3572 can be a way to upload e.g. multiple debug sessions when the binary does not change.
3573 Arguments are the same as @b{load_image}, but the image is stored in OpenOCD host
3574 memory, i.e. does not affect target. This approach is also useful when profiling
3575 target programming performance as I/O and target programming can easily be profiled
3577 @subsection fast_load
3580 @*Loads an image stored in memory by @b{fast_load_image} to the current target. Must be preceeded by fast_load_image.
3582 @subsection dump_image
3583 @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
3585 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
3586 (binary) <@var{file}>.
3587 @subsection verify_image
3588 @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3589 @cindex verify_image
3590 @*Verify <@var{file}> against target memory starting at <@var{address}>.
3591 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
3594 @section Breakpoint commands
3595 @cindex Breakpoint commands
3597 @item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
3599 @*set breakpoint <address> <length> [hw]
3600 @item @b{rbp} <@var{addr}>
3602 @*remove breakpoint <adress>
3603 @item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
3605 @*set watchpoint <address> <length> <r/w/a> [value] [mask]
3606 @item @b{rwp} <@var{addr}>
3608 @*remove watchpoint <adress>
3611 @section Misc Commands
3612 @cindex Other Target Commands
3614 @item @b{profile} <@var{seconds}> <@var{gmon.out}>
3616 Profiling samples the CPU's program counter as quickly as possible, which is useful for non-intrusive stochastic profiling.
3620 @section Architecture and Core Specific Commands
3621 @cindex Architecture Specific Commands
3622 @cindex Core Specific Commands
3624 Most CPUs have specialized JTAG operations to support debugging.
3625 OpenOCD packages most such operations in its standard command framework.
3626 Some of those operations don't fit well in that framework, so they are
3627 exposed here using architecture or implementation specific commands.
3629 @anchor{ARM Tracing}
3630 @subsection ARM Tracing
3634 CPUs based on ARM cores may include standard tracing interfaces,
3635 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
3636 address and data bus trace records to a ``Trace Port''.
3640 Development-oriented boards will sometimes provide a high speed
3641 trace connector for collecting that data, when the particular CPU
3642 supports such an interface.
3643 (The standard connector is a 38-pin Mictor, with both JTAG
3644 and trace port support.)
3645 Those trace connectors are supported by higher end JTAG adapters
3646 and some logic analyzer modules; frequently those modules can
3647 buffer several megabytes of trace data.
3648 Configuring an ETM coupled to such an external trace port belongs
3649 in the board-specific configuration file.
3651 If the CPU doesn't provide an external interface, it probably
3652 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
3653 dedicated SRAM. 4KBytes is one common ETB size.
3654 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
3655 (target) configuration file, since it works the same on all boards.
3658 ETM support in OpenOCD doesn't seem to be widely used yet.
3661 ETM support may be buggy, and at least some @command{etm config}
3662 parameters should be detected by asking the ETM for them.
3663 It seems like a GDB hookup should be possible,
3664 as well as triggering trace on specific events
3665 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
3666 There should be GUI tools to manipulate saved trace data and help
3667 analyse it in conjunction with the source code.
3668 It's unclear how much of a common interface is shared
3669 with the current XScale trace support, or should be
3670 shared with eventual Nexus-style trace module support.
3673 @subsubsection ETM Configuration
3674 ETM setup is coupled with the trace port driver configuration.
3676 @deffn {Config Command} {etm config} target width mode clocking driver
3677 Declares the ETM associated with @var{target}, and associates it
3678 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
3680 Several of the parameters must reflect the trace port configuration.
3681 The @var{width} must be either 4, 8, or 16.
3682 The @var{mode} must be @option{normal}, @option{multiplexted},
3683 or @option{demultiplexted}.
3684 The @var{clocking} must be @option{half} or @option{full}.
3687 You can see the ETM registers using the @command{reg} command, although
3688 not all of those possible registers are present in every ETM.
3692 @deffn Command {etm info}
3693 Displays information about the current target's ETM.
3696 @deffn Command {etm status}
3697 Displays status of the current target's ETM:
3698 is the ETM idle, or is it collecting data?
3699 Did trace data overflow?
3703 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
3704 Displays what data that ETM will collect.
3705 If arguments are provided, first configures that data.
3706 When the configuration changes, tracing is stopped
3707 and any buffered trace data is invalidated.
3710 @item @var{type} ... one of
3711 @option{none} (save nothing),
3712 @option{data} (save data),
3713 @option{address} (save addresses),
3714 @option{all} (save data and addresses)
3715 @item @var{context_id_bits} ... 0, 8, 16, or 32
3716 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
3717 @item @var{branch_output} ... @option{enable} or @option{disable}
3721 @deffn Command {etm trigger_percent} percent
3722 @emph{Buggy and effectively a NOP ... @var{percent} from 2..100}
3725 @subsubsection ETM Trace Operation
3727 After setting up the ETM, you can use it to collect data.
3728 That data can be exported to files for later analysis.
3729 It can also be parsed with OpenOCD, for basic sanity checking.
3731 @deffn Command {etm analyze}
3732 Reads trace data into memory, if it wasn't already present.
3733 Decodes and prints the data that was collected.
3736 @deffn Command {etm dump} filename
3737 Stores the captured trace data in @file{filename}.
3740 @deffn Command {etm image} filename [base_address] [type]
3741 Opens an image file.
3744 @deffn Command {etm load} filename
3745 Loads captured trace data from @file{filename}.
3748 @deffn Command {etm start}
3749 Starts trace data collection.
3752 @deffn Command {etm stop}
3753 Stops trace data collection.
3756 @anchor{Trace Port Drivers}
3757 @subsubsection Trace Port Drivers
3759 To use an ETM trace port it must be associated with a driver.
3761 @deffn {Trace Port Driver} dummy
3762 Use the @option{dummy} driver if you are configuring an ETM that's
3763 not connected to anything (on-chip ETB or off-chip trace connector).
3764 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
3765 any trace data collection.}
3766 @deffn {Config Command} {etm_dummy config} target
3767 Associates the ETM for @var{target} with a dummy driver.
3771 @deffn {Trace Port Driver} etb
3772 Use the @option{etb} driver if you are configuring an ETM
3773 to use on-chip ETB memory.
3774 @deffn {Config Command} {etb config} target etb_tap
3775 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
3776 You can see the ETB registers using the @command{reg} command.
3780 @deffn {Trace Port Driver} oocd_trace
3781 This driver isn't available unless OpenOCD was explicitly configured
3782 with the @option{--enable-oocd_trace} option. You probably don't want
3783 to configure it unless you've built the appropriate prototype hardware;
3784 it's @emph{proof-of-concept} software.
3786 Use the @option{oocd_trace} driver if you are configuring an ETM that's
3787 connected to an off-chip trace connector.
3789 @deffn {Config Command} {oocd_trace config} target tty
3790 Associates the ETM for @var{target} with a trace driver which
3791 collects data through the serial port @var{tty}.
3794 @deffn Command {oocd_trace resync}
3795 Re-synchronizes with the capture clock.
3798 @deffn Command {oocd_trace status}
3799 Reports whether the capture clock is locked or not.
3804 @subsection ARMv4 and ARMv5 Architecture
3805 @cindex ARMv4 specific commands
3806 @cindex ARMv5 specific commands
3808 These commands are specific to ARM architecture v4 and v5,
3809 including all ARM7 or ARM9 systems and Intel XScale.
3810 They are available in addition to other core-specific
3811 commands that may be available.
3813 @deffn Command {armv4_5 core_state} [arm|thumb]
3814 Displays the core_state, optionally changing it to process
3815 either @option{arm} or @option{thumb} instructions.
3816 The target may later be resumed in the currently set core_state.
3817 (Processors may also support the Jazelle state, but
3818 that is not currently supported in OpenOCD.)
3821 @deffn Command {armv4_5 disassemble} address count [thumb]
3823 Disassembles @var{count} instructions starting at @var{address}.
3824 If @option{thumb} is specified, Thumb (16-bit) instructions are used;
3825 else ARM (32-bit) instructions are used.
3826 (Processors may also support the Jazelle state, but
3827 those instructions are not currently understood by OpenOCD.)
3830 @deffn Command {armv4_5 reg}
3831 Display a list of all banked core registers, fetching the current value from every
3832 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
3836 @subsubsection ARM7 and ARM9 specific commands
3837 @cindex ARM7 specific commands
3838 @cindex ARM9 specific commands
3840 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
3841 ARM9TDMI, ARM920T or ARM926EJ-S.
3842 They are available in addition to the ARMv4/5 commands,
3843 and any other core-specific commands that may be available.
3845 @deffn Command {arm7_9 dbgrq} (enable|disable)
3846 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
3847 instead of breakpoints. This should be
3848 safe for all but ARM7TDMI--S cores (like Philips LPC).
3851 @deffn Command {arm7_9 dcc_downloads} (enable|disable)
3853 Control the use of the debug communications channel (DCC) to write larger (>128 byte)
3854 amounts of memory. DCC downloads offer a huge speed increase, but might be
3855 unsafe, especially with targets running at very low speeds. This command was introduced
3856 with OpenOCD rev. 60, and requires a few bytes of working area.
3859 @anchor{arm7_9 fast_memory_access}
3860 @deffn Command {arm7_9 fast_memory_access} (enable|disable)
3861 Enable or disable memory writes and reads that don't check completion of
3862 the operation. This provides a huge speed increase, especially with USB JTAG
3863 cables (FT2232), but might be unsafe if used with targets running at very low
3864 speeds, like the 32kHz startup clock of an AT91RM9200.
3867 @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
3868 @emph{This is intended for use while debugging OpenOCD; you probably
3871 Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
3872 as used in the specified @var{mode}
3873 (where e.g. mode 16 is "user" and mode 19 is "supervisor";
3874 the M4..M0 bits of the PSR).
3875 Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
3876 Register 16 is the mode-specific SPSR,
3877 unless the specified mode is 0xffffffff (32-bit all-ones)
3878 in which case register 16 is the CPSR.
3879 The write goes directly to the CPU, bypassing the register cache.
3882 @deffn {Debug Command} {arm7_9 write_xpsr} word (0|1)
3883 @emph{This is intended for use while debugging OpenOCD; you probably
3886 If the second parameter is zero, writes @var{word} to the
3887 Current Program Status register (CPSR).
3888 Else writes @var{word} to the current mode's Saved PSR (SPSR).
3889 In both cases, this bypasses the register cache.
3892 @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (0|1)
3893 @emph{This is intended for use while debugging OpenOCD; you probably
3896 Writes eight bits to the CPSR or SPSR,
3897 first rotating them by @math{2*rotate} bits,
3898 and bypassing the register cache.
3899 This has lower JTAG overhead than writing the entire CPSR or SPSR
3900 with @command{arm7_9 write_xpsr}.
3903 @subsubsection ARM720T specific commands
3904 @cindex ARM720T specific commands
3906 These commands are available to ARM720T based CPUs,
3907 which are implementations of the ARMv4T architecture
3908 based on the ARM7TDMI-S integer core.
3909 They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
3911 @deffn Command {arm720t cp15} regnum [value]
3912 Display cp15 register @var{regnum};
3913 else if a @var{value} is provided, that value is written to that register.
3916 @deffn Command {arm720t mdw_phys} addr [count]
3917 @deffnx Command {arm720t mdh_phys} addr [count]
3918 @deffnx Command {arm720t mdb_phys} addr [count]
3919 Display contents of physical address @var{addr}, as
3920 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
3921 or 8-bit bytes (@command{mdb_phys}).
3922 If @var{count} is specified, displays that many units.
3925 @deffn Command {arm720t mww_phys} addr word
3926 @deffnx Command {arm720t mwh_phys} addr halfword
3927 @deffnx Command {arm720t mwb_phys} addr byte
3928 Writes the specified @var{word} (32 bits),
3929 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3930 at the specified physical address @var{addr}.
3933 @deffn Command {arm720t virt2phys} va
3934 Translate a virtual address @var{va} to a physical address
3935 and display the result.
3938 @subsubsection ARM9TDMI specific commands
3939 @cindex ARM9TDMI specific commands
3941 Many ARM9-family CPUs are built around ARM9TDMI integer cores,
3942 or processors resembling ARM9TDMI, and can use these commands.
3943 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
3945 @deffn Command {arm9tdmi vector_catch} (all|none|list)
3946 Catch arm9 interrupt vectors, can be @option{all}, @option{none},
3947 or a list with one or more of the following:
3948 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
3949 @option{irq} @option{fiq}.
3952 @subsubsection ARM920T specific commands
3953 @cindex ARM920T specific commands
3955 These commands are available to ARM920T based CPUs,
3956 which are implementations of the ARMv4T architecture
3957 built using the ARM9TDMI integer core.
3958 They are available in addition to the ARMv4/5, ARM7/ARM9,
3959 and ARM9TDMI commands.
3961 @deffn Command {arm920t cache_info}
3962 Print information about the caches found. This allows to see whether your target
3963 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
3966 @deffn Command {arm920t cp15} regnum [value]
3967 Display cp15 register @var{regnum};
3968 else if a @var{value} is provided, that value is written to that register.
3971 @deffn Command {arm920t cp15i} opcode [value [address]]
3972 Interpreted access using cp15 @var{opcode}.
3973 If no @var{value} is provided, the result is displayed.
3974 Else if that value is written using the specified @var{address},
3975 or using zero if no other address is not provided.
3978 @deffn Command {arm920t mdw_phys} addr [count]
3979 @deffnx Command {arm920t mdh_phys} addr [count]
3980 @deffnx Command {arm920t mdb_phys} addr [count]
3981 Display contents of physical address @var{addr}, as
3982 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
3983 or 8-bit bytes (@command{mdb_phys}).
3984 If @var{count} is specified, displays that many units.
3987 @deffn Command {arm920t mww_phys} addr word
3988 @deffnx Command {arm920t mwh_phys} addr halfword
3989 @deffnx Command {arm920t mwb_phys} addr byte
3990 Writes the specified @var{word} (32 bits),
3991 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3992 at the specified physical address @var{addr}.
3995 @deffn Command {arm920t read_cache} filename
3996 Dump the content of ICache and DCache to a file named @file{filename}.
3999 @deffn Command {arm920t read_mmu} filename
4000 Dump the content of the ITLB and DTLB to a file named @file{filename}.
4003 @deffn Command {arm920t virt2phys} @var{va}
4004 Translate a virtual address @var{va} to a physical address
4005 and display the result.
4008 @subsubsection ARM926EJ-S specific commands
4009 @cindex ARM926EJ-S specific commands
4011 These commands are available to ARM926EJ-S based CPUs,
4012 which are implementations of the ARMv5TEJ architecture
4013 based on the ARM9EJ-S integer core.
4014 They are available in addition to the ARMv4/5, ARM7/ARM9,
4015 and ARM9TDMI commands.
4017 @deffn Command {arm926ejs cache_info}
4018 Print information about the caches found.
4021 @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
4022 Accesses cp15 register @var{regnum} using
4023 @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
4024 If a @var{value} is provided, that value is written to that register.
4025 Else that register is read and displayed.
4028 @deffn Command {arm926ejs mdw_phys} addr [count]
4029 @deffnx Command {arm926ejs mdh_phys} addr [count]
4030 @deffnx Command {arm926ejs mdb_phys} addr [count]
4031 Display contents of physical address @var{addr}, as
4032 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4033 or 8-bit bytes (@command{mdb_phys}).
4034 If @var{count} is specified, displays that many units.
4037 @deffn Command {arm926ejs mww_phys} addr word
4038 @deffnx Command {arm926ejs mwh_phys} addr halfword
4039 @deffnx Command {arm926ejs mwb_phys} addr byte
4040 Writes the specified @var{word} (32 bits),
4041 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4042 at the specified physical address @var{addr}.
4045 @deffn Command {arm926ejs virt2phys} @var{va}
4046 Translate a virtual address @var{va} to a physical address
4047 and display the result.
4050 @subsubsection ARM966E specific commands
4051 @cindex ARM966E specific commands
4053 These commands are available to ARM966 based CPUs,
4054 which are implementations of the ARMv5TE architecture.
4055 They are available in addition to the ARMv4/5, ARM7/ARM9,
4056 and ARM9TDMI commands.
4058 @deffn Command {arm966e cp15} regnum [value]
4059 Display cp15 register @var{regnum};
4060 else if a @var{value} is provided, that value is written to that register.
4063 @subsubsection XScale specific commands
4064 @cindex XScale specific commands
4066 These commands are available to XScale based CPUs,
4067 which are implementations of the ARMv5TE architecture.
4069 @deffn Command {xscale analyze_trace}
4070 Displays the contents of the trace buffer.
4073 @deffn Command {xscale cache_clean_address} address
4074 Changes the address used when cleaning the data cache.
4077 @deffn Command {xscale cache_info}
4078 Displays information about the CPU caches.
4081 @deffn Command {xscale cp15} regnum [value]
4082 Display cp15 register @var{regnum};
4083 else if a @var{value} is provided, that value is written to that register.
4086 @deffn Command {xscale debug_handler} target address
4087 Changes the address used for the specified target's debug handler.
4090 @deffn Command {xscale dcache} (enable|disable)
4091 Enables or disable the CPU's data cache.
4094 @deffn Command {xscale dump_trace} filename
4095 Dumps the raw contents of the trace buffer to @file{filename}.
4098 @deffn Command {xscale icache} (enable|disable)
4099 Enables or disable the CPU's instruction cache.
4102 @deffn Command {xscale mmu} (enable|disable)
4103 Enables or disable the CPU's memory management unit.
4106 @deffn Command {xscale trace_buffer} (enable|disable) [fill [n] | wrap]
4107 Enables or disables the trace buffer,
4108 and controls how it is emptied.
4111 @deffn Command {xscale trace_image} filename [offset [type]]
4112 Opens a trace image from @file{filename}, optionally rebasing
4113 its segment addresses by @var{offset}.
4114 The image @var{type} may be one of
4115 @option{bin} (binary), @option{ihex} (Intel hex),
4116 @option{elf} (ELF file), @option{s19} (Motorola s19),
4117 @option{mem}, or @option{builder}.
4120 @deffn Command {xscale vector_catch} mask
4121 Provide a bitmask showing the vectors to catch.
4124 @subsection ARMv6 Architecture
4126 @subsubsection ARM11 specific commands
4127 @cindex ARM11 specific commands
4129 @deffn Command {arm11 mcr} p1 p2 p3 p4 p5
4130 Read coprocessor register
4133 @deffn Command {arm11 memwrite burst} [value]
4134 Displays the value of the memwrite burst-enable flag,
4135 which is enabled by default.
4136 If @var{value} is defined, first assigns that.
4139 @deffn Command {arm11 memwrite error_fatal} [value]
4140 Displays the value of the memwrite error_fatal flag,
4141 which is enabled by default.
4142 If @var{value} is defined, first assigns that.
4145 @deffn Command {arm11 mrc} p1 p2 p3 p4 p5 value
4146 Write coprocessor register
4149 @deffn Command {arm11 no_increment} [value]
4150 Displays the value of the flag controlling whether
4151 some read or write operations increment the pointer
4152 (the default behavior) or not (acting like a FIFO).
4153 If @var{value} is defined, first assigns that.
4156 @deffn Command {arm11 step_irq_enable} [value]
4157 Displays the value of the flag controlling whether
4158 IRQs are enabled during single stepping;
4159 they is disabled by default.
4160 If @var{value} is defined, first assigns that.
4163 @subsection ARMv7 Architecture
4165 @subsubsection Cortex-M3 specific commands
4166 @cindex Cortex-M3 specific commands
4168 @deffn Command {cortex_m3 maskisr} (on|off)
4169 Control masking (disabling) interrupts during target step/resume.
4172 @section Target DCC Requests
4173 @cindex Linux-ARM DCC support
4176 OpenOCD can handle certain target requests; currently debugmsgs
4177 @command{target_request debugmsgs}
4178 are only supported for arm7_9 and cortex_m3.
4180 See libdcc in the contrib dir for more details.
4181 Linux-ARM kernels have a ``Kernel low-level debugging
4182 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
4183 depends on CONFIG_DEBUG_LL) which uses this mechanism to
4184 deliver messages before a serial console can be activated.
4186 @deffn Command {target_request debugmsgs} [enable|disable|charmsg]
4187 Displays current handling of target DCC message requests.
4188 These messages may be sent to the debugger while the target is running.
4189 The optional @option{enable} and @option{charmsg} parameters
4190 both enable the messages, while @option{disable} disables them.
4191 With @option{charmsg} the DCC words each contain one character,
4192 as used by Linux with CONFIG_DEBUG_ICEDCC;
4193 otherwise the libdcc format is used.
4197 @chapter JTAG Commands
4198 @cindex JTAG Commands
4199 Generally most people will not use the bulk of these commands. They
4200 are mostly used by the OpenOCD developers or those who need to
4201 directly manipulate the JTAG taps.
4203 In general these commands control JTAG taps at a very low level. For
4204 example if you need to control a JTAG Route Controller (i.e.: the
4205 OMAP3530 on the Beagle Board has one) you might use these commands in
4206 a script or an event procedure.
4210 @item @b{scan_chain}
4212 @*Print current scan chain configuration.
4213 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
4215 @*Toggle reset lines.
4216 @item @b{endstate} <@var{tap_state}>
4218 @*Finish JTAG operations in <@var{tap_state}>.
4219 @item @b{runtest} <@var{num_cycles}>
4221 @*Move to Run-Test/Idle, and execute <@var{num_cycles}>
4222 @item @b{statemove} [@var{tap_state}]
4224 @*Move to current endstate or [@var{tap_state}]
4225 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
4227 @*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
4228 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
4230 @*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
4231 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
4232 @cindex verify_ircapture
4233 @*Verify value captured during Capture-IR. Default is enabled.
4234 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
4236 @*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
4237 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
4239 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
4244 Available tap_states are:
4284 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
4285 be used to access files on PCs (either the developer's PC or some other PC).
4287 The way this works on the ZY1000 is to prefix a filename by
4288 "/tftp/ip/" and append the TFTP path on the TFTP
4289 server (tftpd). For example,
4292 load_image /tftp/10.0.0.96/c:\temp\abc.elf
4295 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
4296 if the file was hosted on the embedded host.
4298 In order to achieve decent performance, you must choose a TFTP server
4299 that supports a packet size bigger than the default packet size (512 bytes). There
4300 are numerous TFTP servers out there (free and commercial) and you will have to do
4301 a bit of googling to find something that fits your requirements.
4303 @node Sample Scripts
4304 @chapter Sample Scripts
4307 This page shows how to use the Target Library.
4309 The configuration script can be divided into the following sections:
4311 @item Daemon configuration
4313 @item JTAG scan chain
4314 @item Target configuration
4315 @item Flash configuration
4318 Detailed information about each section can be found at OpenOCD configuration.
4320 @section AT91R40008 example
4321 @cindex AT91R40008 example
4322 To start OpenOCD with a target script for the AT91R40008 CPU and reset
4323 the CPU upon startup of the OpenOCD daemon.
4325 openocd -f interface/parport.cfg -f target/at91r40008.cfg \
4326 -c "init" -c "reset"
4330 @node GDB and OpenOCD
4331 @chapter GDB and OpenOCD
4333 OpenOCD complies with the remote gdbserver protocol, and as such can be used
4334 to debug remote targets.
4336 @anchor{Connecting to GDB}
4337 @section Connecting to GDB
4338 @cindex Connecting to GDB
4339 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
4340 instance GDB 6.3 has a known bug that produces bogus memory access
4341 errors, which has since been fixed: look up 1836 in
4342 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
4344 OpenOCD can communicate with GDB in two ways:
4348 A socket (TCP/IP) connection is typically started as follows:
4350 target remote localhost:3333
4352 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
4354 A pipe connection is typically started as follows:
4356 target remote | openocd --pipe
4358 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
4359 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
4363 To list the available OpenOCD commands type @command{monitor help} on the
4366 OpenOCD supports the gdb @option{qSupported} packet, this enables information
4367 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
4368 packet size and the device's memory map.
4370 Previous versions of OpenOCD required the following GDB options to increase
4371 the packet size and speed up GDB communication:
4373 set remote memory-write-packet-size 1024
4374 set remote memory-write-packet-size fixed
4375 set remote memory-read-packet-size 1024
4376 set remote memory-read-packet-size fixed
4378 This is now handled in the @option{qSupported} PacketSize and should not be required.
4380 @section Programming using GDB
4381 @cindex Programming using GDB
4383 By default the target memory map is sent to GDB. This can be disabled by
4384 the following OpenOCD configuration option:
4386 gdb_memory_map disable
4388 For this to function correctly a valid flash configuration must also be set
4389 in OpenOCD. For faster performance you should also configure a valid
4392 Informing GDB of the memory map of the target will enable GDB to protect any
4393 flash areas of the target and use hardware breakpoints by default. This means
4394 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
4395 using a memory map. @xref{gdb_breakpoint_override}.
4397 To view the configured memory map in GDB, use the GDB command @option{info mem}
4398 All other unassigned addresses within GDB are treated as RAM.
4400 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
4401 This can be changed to the old behaviour by using the following GDB command
4403 set mem inaccessible-by-default off
4406 If @command{gdb_flash_program enable} is also used, GDB will be able to
4407 program any flash memory using the vFlash interface.
4409 GDB will look at the target memory map when a load command is given, if any
4410 areas to be programmed lie within the target flash area the vFlash packets
4413 If the target needs configuring before GDB programming, an event
4414 script can be executed:
4416 $_TARGETNAME configure -event EVENTNAME BODY
4419 To verify any flash programming the GDB command @option{compare-sections}
4422 @node Tcl Scripting API
4423 @chapter Tcl Scripting API
4424 @cindex Tcl Scripting API
4428 The commands are stateless. E.g. the telnet command line has a concept
4429 of currently active target, the Tcl API proc's take this sort of state
4430 information as an argument to each proc.
4432 There are three main types of return values: single value, name value
4433 pair list and lists.
4435 Name value pair. The proc 'foo' below returns a name/value pair
4441 > set foo(you) Oyvind
4442 > set foo(mouse) Micky
4443 > set foo(duck) Donald
4451 me Duane you Oyvind mouse Micky duck Donald
4453 Thus, to get the names of the associative array is easy:
4455 foreach { name value } [set foo] {
4456 puts "Name: $name, Value: $value"
4460 Lists returned must be relatively small. Otherwise a range
4461 should be passed in to the proc in question.
4463 @section Internal low-level Commands
4465 By low-level, the intent is a human would not directly use these commands.
4467 Low-level commands are (should be) prefixed with "ocd_", e.g.
4468 @command{ocd_flash_banks}
4469 is the low level API upon which @command{flash banks} is implemented.
4472 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
4474 Read memory and return as a Tcl array for script processing
4475 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
4477 Convert a Tcl array to memory locations and write the values
4478 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
4480 Return information about the flash banks
4483 OpenOCD commands can consist of two words, e.g. "flash banks". The
4484 startup.tcl "unknown" proc will translate this into a Tcl proc
4485 called "flash_banks".
4487 @section OpenOCD specific Global Variables
4491 Real Tcl has ::tcl_platform(), and platform::identify, and many other
4492 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
4493 holds one of the following values:
4496 @item @b{winxx} Built using Microsoft Visual Studio
4497 @item @b{linux} Linux is the underlying operating sytem
4498 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
4499 @item @b{cygwin} Running under Cygwin
4500 @item @b{mingw32} Running under MingW32
4501 @item @b{other} Unknown, none of the above.
4504 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
4507 We should add support for a variable like Tcl variable
4508 @code{tcl_platform(platform)}, it should be called
4509 @code{jim_platform} (because it
4510 is jim, not real tcl).
4514 @chapter Deprecated/Removed Commands
4515 @cindex Deprecated/Removed Commands
4516 Certain OpenOCD commands have been deprecated/removed during the various revisions.
4519 @item @b{arm7_9 fast_writes}
4520 @cindex arm7_9 fast_writes
4521 @*Use @command{arm7_9 fast_memory_access} instead.
4522 @xref{arm7_9 fast_memory_access}.
4523 @item @b{arm7_9 force_hw_bkpts}
4524 @cindex arm7_9 force_hw_bkpts
4525 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
4526 for flash if the GDB memory map has been set up(default when flash is declared in
4527 target configuration). @xref{gdb_breakpoint_override}.
4528 @item @b{arm7_9 sw_bkpts}
4529 @cindex arm7_9 sw_bkpts
4530 @*On by default. @xref{gdb_breakpoint_override}.
4531 @item @b{daemon_startup}
4532 @cindex daemon_startup
4533 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
4534 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
4535 and @option{target cortex_m3 little reset_halt 0}.
4536 @item @b{dump_binary}
4538 @*use @option{dump_image} command with same args. @xref{dump_image}.
4539 @item @b{flash erase}
4541 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
4542 @item @b{flash write}
4544 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
4545 @item @b{flash write_binary}
4546 @cindex flash write_binary
4547 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
4548 @item @b{flash auto_erase}
4549 @cindex flash auto_erase
4550 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
4552 @item @b{jtag_speed} value
4553 @*@xref{JTAG Speed}.
4554 Usually, a value of zero means maximum
4555 speed. The actual effect of this option depends on the JTAG interface used.
4557 @item wiggler: maximum speed / @var{number}
4558 @item ft2232: 6MHz / (@var{number}+1)
4559 @item amt jtagaccel: 8 / 2**@var{number}
4560 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
4561 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
4562 @comment end speed list.
4565 @item @b{load_binary}
4567 @*use @option{load_image} command with same args. @xref{load_image}.
4568 @item @b{run_and_halt_time}
4569 @cindex run_and_halt_time
4570 @*This command has been removed for simpler reset behaviour, it can be simulated with the
4577 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
4579 @*use the create subcommand of @option{target}.
4580 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
4581 @cindex target_script
4582 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
4583 @item @b{working_area}
4584 @cindex working_area
4585 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
4593 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
4595 @cindex adaptive clocking
4598 In digital circuit design it is often refered to as ``clock
4599 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
4600 operating at some speed, your target is operating at another. The two
4601 clocks are not synchronised, they are ``asynchronous''
4603 In order for the two to work together they must be synchronised. Otherwise
4604 the two systems will get out of sync with each other and nothing will
4605 work. There are 2 basic options:
4608 Use a special circuit.
4610 One clock must be some multiple slower than the other.
4613 @b{Does this really matter?} For some chips and some situations, this
4614 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
4615 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
4616 program/enable the oscillators and eventually the main clock. It is in
4617 those critical times you must slow the JTAG clock to sometimes 1 to
4620 Imagine debugging a 500MHz ARM926 hand held battery powered device
4621 that ``deep sleeps'' at 32kHz between every keystroke. It can be
4624 @b{Solution #1 - A special circuit}
4626 In order to make use of this, your JTAG dongle must support the RTCK
4627 feature. Not all dongles support this - keep reading!
4629 The RTCK signal often found in some ARM chips is used to help with
4630 this problem. ARM has a good description of the problem described at
4631 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
4632 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
4633 work? / how does adaptive clocking work?''.
4635 The nice thing about adaptive clocking is that ``battery powered hand
4636 held device example'' - the adaptiveness works perfectly all the
4637 time. One can set a break point or halt the system in the deep power
4638 down code, slow step out until the system speeds up.
4640 @b{Solution #2 - Always works - but may be slower}
4642 Often this is a perfectly acceptable solution.
4644 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
4645 the target clock speed. But what that ``magic division'' is varies
4646 depending on the chips on your board. @b{ARM rule of thumb} Most ARM
4647 based systems require an 8:1 division. @b{Xilinx rule of thumb} is
4648 1/12 the clock speed.
4650 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
4652 You can still debug the 'low power' situations - you just need to
4653 manually adjust the clock speed at every step. While painful and
4654 tedious, it is not always practical.
4656 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
4657 have a special debug mode in your application that does a ``high power
4658 sleep''. If you are careful - 98% of your problems can be debugged
4661 To set the JTAG frequency use the command:
4669 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
4671 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
4672 around Windows filenames.
4685 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
4687 Make sure you have Cygwin installed, or at least a version of OpenOCD that
4688 claims to come with all the necessary DLLs. When using Cygwin, try launching
4689 OpenOCD from the Cygwin shell.
4691 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
4692 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
4693 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
4695 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
4696 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
4697 software breakpoints consume one of the two available hardware breakpoints.
4699 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
4701 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
4702 clock at the time you're programming the flash. If you've specified the crystal's
4703 frequency, make sure the PLL is disabled. If you've specified the full core speed
4704 (e.g. 60MHz), make sure the PLL is enabled.
4706 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
4707 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
4708 out while waiting for end of scan, rtck was disabled".
4710 Make sure your PC's parallel port operates in EPP mode. You might have to try several
4711 settings in your PC BIOS (ECP, EPP, and different versions of those).
4713 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
4714 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
4715 memory read caused data abort".
4717 The errors are non-fatal, and are the result of GDB trying to trace stack frames
4718 beyond the last valid frame. It might be possible to prevent this by setting up
4719 a proper "initial" stack frame, if you happen to know what exactly has to
4720 be done, feel free to add this here.
4722 @b{Simple:} In your startup code - push 8 registers of zeros onto the
4723 stack before calling main(). What GDB is doing is ``climbing'' the run
4724 time stack by reading various values on the stack using the standard
4725 call frame for the target. GDB keeps going - until one of 2 things
4726 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
4727 stackframes have been processed. By pushing zeros on the stack, GDB
4730 @b{Debugging Interrupt Service Routines} - In your ISR before you call
4731 your C code, do the same - artifically push some zeros onto the stack,
4732 remember to pop them off when the ISR is done.
4734 @b{Also note:} If you have a multi-threaded operating system, they
4735 often do not @b{in the intrest of saving memory} waste these few
4739 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
4740 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
4742 This warning doesn't indicate any serious problem, as long as you don't want to
4743 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
4744 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
4745 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
4746 independently. With this setup, it's not possible to halt the core right out of
4747 reset, everything else should work fine.
4749 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
4750 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
4751 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
4752 quit with an error message. Is there a stability issue with OpenOCD?
4754 No, this is not a stability issue concerning OpenOCD. Most users have solved
4755 this issue by simply using a self-powered USB hub, which they connect their
4756 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
4757 supply stable enough for the Amontec JTAGkey to be operated.
4759 @b{Laptops running on battery have this problem too...}
4761 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
4762 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
4763 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
4764 What does that mean and what might be the reason for this?
4766 First of all, the reason might be the USB power supply. Try using a self-powered
4767 hub instead of a direct connection to your computer. Secondly, the error code 4
4768 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
4769 chip ran into some sort of error - this points us to a USB problem.
4771 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
4772 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
4773 What does that mean and what might be the reason for this?
4775 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
4776 has closed the connection to OpenOCD. This might be a GDB issue.
4778 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
4779 are described, there is a parameter for specifying the clock frequency
4780 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
4781 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
4782 specified in kilohertz. However, I do have a quartz crystal of a
4783 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
4784 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
4787 No. The clock frequency specified here must be given as an integral number.
4788 However, this clock frequency is used by the In-Application-Programming (IAP)
4789 routines of the LPC2000 family only, which seems to be very tolerant concerning
4790 the given clock frequency, so a slight difference between the specified clock
4791 frequency and the actual clock frequency will not cause any trouble.
4793 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
4795 Well, yes and no. Commands can be given in arbitrary order, yet the
4796 devices listed for the JTAG scan chain must be given in the right
4797 order (jtag newdevice), with the device closest to the TDO-Pin being
4798 listed first. In general, whenever objects of the same type exist
4799 which require an index number, then these objects must be given in the
4800 right order (jtag newtap, targets and flash banks - a target
4801 references a jtag newtap and a flash bank references a target).
4803 You can use the ``scan_chain'' command to verify and display the tap order.
4805 Also, some commands can't execute until after @command{init} has been
4806 processed. Such commands include @command{nand probe} and everything
4807 else that needs to write to controller registers, perhaps for setting
4808 up DRAM and loading it with code.
4810 @item @b{JTAG Tap Order} JTAG tap order - command order
4812 Many newer devices have multiple JTAG taps. For example: ST
4813 Microsystems STM32 chips have two taps, a ``boundary scan tap'' and
4814 ``Cortex-M3'' tap. Example: The STM32 reference manual, Document ID:
4815 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
4816 connected to the boundary scan tap, which then connects to the
4817 Cortex-M3 tap, which then connects to the TDO pin.
4819 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
4820 (2) The boundary scan tap. If your board includes an additional JTAG
4821 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
4822 place it before or after the STM32 chip in the chain. For example:
4825 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
4826 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
4827 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
4828 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
4829 @item Xilinx TDO Pin -> OpenOCD TDO (input)
4832 The ``jtag device'' commands would thus be in the order shown below. Note:
4835 @item jtag newtap Xilinx tap -irlen ...
4836 @item jtag newtap stm32 cpu -irlen ...
4837 @item jtag newtap stm32 bs -irlen ...
4838 @item # Create the debug target and say where it is
4839 @item target create stm32.cpu -chain-position stm32.cpu ...
4843 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
4844 log file, I can see these error messages: Error: arm7_9_common.c:561
4845 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
4851 @node Tcl Crash Course
4852 @chapter Tcl Crash Course
4855 Not everyone knows Tcl - this is not intended to be a replacement for
4856 learning Tcl, the intent of this chapter is to give you some idea of
4857 how the Tcl scripts work.
4859 This chapter is written with two audiences in mind. (1) OpenOCD users
4860 who need to understand a bit more of how JIM-Tcl works so they can do
4861 something useful, and (2) those that want to add a new command to
4864 @section Tcl Rule #1
4865 There is a famous joke, it goes like this:
4867 @item Rule #1: The wife is always correct
4868 @item Rule #2: If you think otherwise, See Rule #1
4871 The Tcl equal is this:
4874 @item Rule #1: Everything is a string
4875 @item Rule #2: If you think otherwise, See Rule #1
4878 As in the famous joke, the consequences of Rule #1 are profound. Once
4879 you understand Rule #1, you will understand Tcl.
4881 @section Tcl Rule #1b
4882 There is a second pair of rules.
4884 @item Rule #1: Control flow does not exist. Only commands
4885 @* For example: the classic FOR loop or IF statement is not a control
4886 flow item, they are commands, there is no such thing as control flow
4888 @item Rule #2: If you think otherwise, See Rule #1
4889 @* Actually what happens is this: There are commands that by
4890 convention, act like control flow key words in other languages. One of
4891 those commands is the word ``for'', another command is ``if''.
4894 @section Per Rule #1 - All Results are strings
4895 Every Tcl command results in a string. The word ``result'' is used
4896 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
4897 Everything is a string}
4899 @section Tcl Quoting Operators
4900 In life of a Tcl script, there are two important periods of time, the
4901 difference is subtle.
4904 @item Evaluation Time
4907 The two key items here are how ``quoted things'' work in Tcl. Tcl has
4908 three primary quoting constructs, the [square-brackets] the
4909 @{curly-braces@} and ``double-quotes''
4911 By now you should know $VARIABLES always start with a $DOLLAR
4912 sign. BTW: To set a variable, you actually use the command ``set'', as
4913 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
4914 = 1'' statement, but without the equal sign.
4917 @item @b{[square-brackets]}
4918 @* @b{[square-brackets]} are command substitutions. It operates much
4919 like Unix Shell `back-ticks`. The result of a [square-bracket]
4920 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
4921 string}. These two statements are roughly identical:
4925 echo "The Date is: $X"
4928 puts "The Date is: $X"
4930 @item @b{``double-quoted-things''}
4931 @* @b{``double-quoted-things''} are just simply quoted
4932 text. $VARIABLES and [square-brackets] are expanded in place - the
4933 result however is exactly 1 string. @i{Remember Rule #1 - Everything
4937 puts "It is now \"[date]\", $x is in 1 hour"
4939 @item @b{@{Curly-Braces@}}
4940 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
4941 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
4942 'single-quote' operators in BASH shell scripts, with the added
4943 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
4944 nested 3 times@}@}@} NOTE: [date] is perhaps a bad example, as of
4945 28/nov/2008, Jim/OpenOCD does not have a date command.
4948 @section Consequences of Rule 1/2/3/4
4950 The consequences of Rule 1 are profound.
4952 @subsection Tokenisation & Execution.
4954 Of course, whitespace, blank lines and #comment lines are handled in
4957 As a script is parsed, each (multi) line in the script file is
4958 tokenised and according to the quoting rules. After tokenisation, that
4959 line is immedatly executed.
4961 Multi line statements end with one or more ``still-open''
4962 @{curly-braces@} which - eventually - closes a few lines later.
4964 @subsection Command Execution
4966 Remember earlier: There are no ``control flow''
4967 statements in Tcl. Instead there are COMMANDS that simply act like
4968 control flow operators.
4970 Commands are executed like this:
4973 @item Parse the next line into (argc) and (argv[]).
4974 @item Look up (argv[0]) in a table and call its function.
4975 @item Repeat until End Of File.
4978 It sort of works like this:
4981 ReadAndParse( &argc, &argv );
4983 cmdPtr = LookupCommand( argv[0] );
4985 (*cmdPtr->Execute)( argc, argv );
4989 When the command ``proc'' is parsed (which creates a procedure
4990 function) it gets 3 parameters on the command line. @b{1} the name of
4991 the proc (function), @b{2} the list of parameters, and @b{3} the body
4992 of the function. Not the choice of words: LIST and BODY. The PROC
4993 command stores these items in a table somewhere so it can be found by
4996 @subsection The FOR command
4998 The most interesting command to look at is the FOR command. In Tcl,
4999 the FOR command is normally implemented in C. Remember, FOR is a
5000 command just like any other command.
5002 When the ascii text containing the FOR command is parsed, the parser
5003 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
5007 @item The ascii text 'for'
5008 @item The start text
5009 @item The test expression
5014 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
5015 Remember @i{Rule #1 - Everything is a string.} The key point is this:
5016 Often many of those parameters are in @{curly-braces@} - thus the
5017 variables inside are not expanded or replaced until later.
5019 Remember that every Tcl command looks like the classic ``main( argc,
5020 argv )'' function in C. In JimTCL - they actually look like this:
5024 MyCommand( Jim_Interp *interp,
5026 Jim_Obj * const *argvs );
5029 Real Tcl is nearly identical. Although the newer versions have
5030 introduced a byte-code parser and intepreter, but at the core, it
5031 still operates in the same basic way.
5033 @subsection FOR command implementation
5035 To understand Tcl it is perhaps most helpful to see the FOR
5036 command. Remember, it is a COMMAND not a control flow structure.
5038 In Tcl there are two underlying C helper functions.
5040 Remember Rule #1 - You are a string.
5042 The @b{first} helper parses and executes commands found in an ascii
5043 string. Commands can be seperated by semicolons, or newlines. While
5044 parsing, variables are expanded via the quoting rules.
5046 The @b{second} helper evaluates an ascii string as a numerical
5047 expression and returns a value.
5049 Here is an example of how the @b{FOR} command could be
5050 implemented. The pseudo code below does not show error handling.
5052 void Execute_AsciiString( void *interp, const char *string );
5054 int Evaluate_AsciiExpression( void *interp, const char *string );
5057 MyForCommand( void *interp,
5062 SetResult( interp, "WRONG number of parameters");
5066 // argv[0] = the ascii string just like C
5068 // Execute the start statement.
5069 Execute_AsciiString( interp, argv[1] );
5073 i = Evaluate_AsciiExpression(interp, argv[2]);
5078 Execute_AsciiString( interp, argv[3] );
5080 // Execute the LOOP part
5081 Execute_AsciiString( interp, argv[4] );
5085 SetResult( interp, "" );
5090 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
5091 in the same basic way.
5093 @section OpenOCD Tcl Usage
5095 @subsection source and find commands
5096 @b{Where:} In many configuration files
5097 @* Example: @b{ source [find FILENAME] }
5098 @*Remember the parsing rules
5100 @item The FIND command is in square brackets.
5101 @* The FIND command is executed with the parameter FILENAME. It should
5102 find the full path to the named file. The RESULT is a string, which is
5103 substituted on the orginal command line.
5104 @item The command source is executed with the resulting filename.
5105 @* SOURCE reads a file and executes as a script.
5107 @subsection format command
5108 @b{Where:} Generally occurs in numerous places.
5109 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
5115 puts [format "The answer: %d" [expr $x * $y]]
5118 @item The SET command creates 2 variables, X and Y.
5119 @item The double [nested] EXPR command performs math
5120 @* The EXPR command produces numerical result as a string.
5122 @item The format command is executed, producing a single string
5123 @* Refer to Rule #1.
5124 @item The PUTS command outputs the text.
5126 @subsection Body or Inlined Text
5127 @b{Where:} Various TARGET scripts.
5130 proc someproc @{@} @{
5131 ... multiple lines of stuff ...
5133 $_TARGETNAME configure -event FOO someproc
5134 #2 Good - no variables
5135 $_TARGETNAME confgure -event foo "this ; that;"
5136 #3 Good Curly Braces
5137 $_TARGETNAME configure -event FOO @{
5140 #4 DANGER DANGER DANGER
5141 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
5144 @item The $_TARGETNAME is an OpenOCD variable convention.
5145 @*@b{$_TARGETNAME} represents the last target created, the value changes
5146 each time a new target is created. Remember the parsing rules. When
5147 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
5148 the name of the target which happens to be a TARGET (object)
5150 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
5151 @*There are 4 examples:
5153 @item The TCLBODY is a simple string that happens to be a proc name
5154 @item The TCLBODY is several simple commands seperated by semicolons
5155 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
5156 @item The TCLBODY is a string with variables that get expanded.
5159 In the end, when the target event FOO occurs the TCLBODY is
5160 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
5161 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
5163 Remember the parsing rules. In case #3, @{curly-braces@} mean the
5164 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
5165 and the text is evaluated. In case #4, they are replaced before the
5166 ``Target Object Command'' is executed. This occurs at the same time
5167 $_TARGETNAME is replaced. In case #4 the date will never
5168 change. @{BTW: [date] is perhaps a bad example, as of 28/nov/2008,
5169 Jim/OpenOCD does not have a date command@}
5171 @subsection Global Variables
5172 @b{Where:} You might discover this when writing your own procs @* In
5173 simple terms: Inside a PROC, if you need to access a global variable
5174 you must say so. See also ``upvar''. Example:
5176 proc myproc @{ @} @{
5177 set y 0 #Local variable Y
5178 global x #Global variable X
5179 puts [format "X=%d, Y=%d" $x $y]
5182 @section Other Tcl Hacks
5183 @b{Dynamic variable creation}
5185 # Dynamically create a bunch of variables.
5186 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
5188 set vn [format "BIT%d" $x]
5192 set $vn [expr (1 << $x)]
5195 @b{Dynamic proc/command creation}
5197 # One "X" function - 5 uart functions.
5198 foreach who @{A B C D E@}
5199 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
5203 @node Target Library
5204 @chapter Target Library
5205 @cindex Target Library
5207 OpenOCD comes with a target configuration script library. These scripts can be
5208 used as-is or serve as a starting point.
5210 The target library is published together with the OpenOCD executable and
5211 the path to the target library is in the OpenOCD script search path.
5212 Similarly there are example scripts for configuring the JTAG interface.
5214 The command line below uses the example parport configuration script
5215 that ship with OpenOCD, then configures the str710.cfg target and
5216 finally issues the init and reset commands. The communication speed
5217 is set to 10kHz for reset and 8MHz for post reset.
5220 openocd -f interface/parport.cfg -f target/str710.cfg \
5221 -c "init" -c "reset"
5224 To list the target scripts available:
5227 $ ls /usr/local/lib/openocd/target
5229 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
5230 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
5231 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
5232 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
5237 @node OpenOCD Concept Index
5238 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
5239 @comment case issue with ``Index.html'' and ``index.html''
5240 @comment Occurs when creating ``--html --no-split'' output
5241 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
5242 @unnumbered OpenOCD Concept Index
5246 @node Command and Driver Index
5247 @unnumbered Command and Driver Index