1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * Terry Lv <r65388@freescale.com>
10 #include <dwc_ahsata.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
19 #include <linux/bitops.h>
20 #include <linux/ctype.h>
21 #include <linux/errno.h>
22 #include "dwc_ahsata_priv.h"
24 struct sata_port_regs {
48 struct sata_host_regs {
77 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
78 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
80 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
82 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
84 return base + 0x100 + (port * 0x80);
87 static int waiting_for_cmd_completed(u8 *offset,
95 ((status = readl(offset)) & sign) && i < timeout_msec;
99 return (i < timeout_msec) ? 0 : -1;
102 static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
104 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
106 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
107 writel(0x02060b14, &host_mmio->oobr);
112 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
114 u32 tmp, cap_save, num_ports;
115 int i, j, timeout = 1000;
116 struct sata_port_regs *port_mmio = NULL;
117 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
118 int clk = mxc_get_clock(MXC_SATA_CLK);
120 cap_save = readl(&host_mmio->cap);
121 cap_save |= SATA_HOST_CAP_SSS;
123 /* global controller reset */
124 tmp = readl(&host_mmio->ghc);
125 if ((tmp & SATA_HOST_GHC_HR) == 0)
126 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
128 while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
132 debug("controller reset failed (0x%x)\n", tmp);
137 writel(clk / 1000, &host_mmio->timer1ms);
139 ahci_setup_oobr(uc_priv, 0);
141 writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
142 writel(cap_save, &host_mmio->cap);
143 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
144 writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
147 * Determine which Ports are implemented by the DWC_ahsata,
148 * by reading the PI register. This bit map value aids the
149 * software to determine how many Ports are available and
150 * which Port registers need to be initialized.
152 uc_priv->cap = readl(&host_mmio->cap);
153 uc_priv->port_map = readl(&host_mmio->pi);
155 /* Determine how many command slots the HBA supports */
156 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
158 debug("cap 0x%x port_map 0x%x n_ports %d\n",
159 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
161 for (i = 0; i < uc_priv->n_ports; i++) {
162 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
163 port_mmio = uc_priv->port[i].port_mmio;
165 /* Ensure that the DWC_ahsata is in idle state */
166 tmp = readl(&port_mmio->cmd);
169 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
170 * are all cleared, the Port is in an idle state.
172 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
173 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
176 * System software places a Port into the idle state by
177 * clearing P#CMD.ST and waiting for P#CMD.CR to return
180 tmp &= ~SATA_PORT_CMD_ST;
181 writel_with_flush(tmp, &port_mmio->cmd);
184 * spec says 500 msecs for each bit, so
185 * this is slightly incorrect.
190 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR)
195 debug("port reset failed (0x%x)\n", tmp);
201 tmp = readl(&port_mmio->cmd);
202 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
204 /* Wait for spin-up to finish */
206 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD)
210 debug("Spin-Up can't finish!\n");
214 for (j = 0; j < 100; ++j) {
216 tmp = readl(&port_mmio->ssts);
217 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
218 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
222 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
224 while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X)
228 debug("Can't find DIAG_X set!\n");
233 * For each implemented Port, clear the P#SERR
234 * register, by writing ones to each implemented\
237 tmp = readl(&port_mmio->serr);
238 debug("P#SERR 0x%x\n",
240 writel(tmp, &port_mmio->serr);
242 /* Ack any pending irq events for this port */
243 tmp = readl(&host_mmio->is);
244 debug("IS 0x%x\n", tmp);
246 writel(tmp, &host_mmio->is);
248 writel(1 << i, &host_mmio->is);
250 /* set irq mask (enables interrupts) */
251 writel(DEF_PORT_IRQ, &port_mmio->ie);
253 /* register linkup ports */
254 tmp = readl(&port_mmio->ssts);
255 debug("Port %d status: 0x%x\n", i, tmp);
256 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
257 uc_priv->link_port_map |= (0x01 << i);
260 tmp = readl(&host_mmio->ghc);
261 debug("GHC 0x%x\n", tmp);
262 writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
263 tmp = readl(&host_mmio->ghc);
264 debug("GHC 0x%x\n", tmp);
269 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
271 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
272 u32 vers, cap, impl, speed;
276 vers = readl(&host_mmio->vs);
278 impl = uc_priv->port_map;
280 speed = (cap & SATA_HOST_CAP_ISS_MASK)
281 >> SATA_HOST_CAP_ISS_OFFSET;
291 printf("AHCI %02x%02x.%02x%02x "
292 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
297 ((cap >> 8) & 0x1f) + 1,
306 cap & (1 << 31) ? "64bit " : "",
307 cap & (1 << 30) ? "ncq " : "",
308 cap & (1 << 28) ? "ilck " : "",
309 cap & (1 << 27) ? "stag " : "",
310 cap & (1 << 26) ? "pm " : "",
311 cap & (1 << 25) ? "led " : "",
312 cap & (1 << 24) ? "clo " : "",
313 cap & (1 << 19) ? "nz " : "",
314 cap & (1 << 18) ? "only " : "",
315 cap & (1 << 17) ? "pmp " : "",
316 cap & (1 << 15) ? "pio " : "",
317 cap & (1 << 14) ? "slum " : "",
318 cap & (1 << 13) ? "part " : "");
321 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
322 unsigned char *buf, int buf_len)
324 struct ahci_ioports *pp = &uc_priv->port[port];
325 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
326 u32 sg_count, max_bytes;
329 max_bytes = MAX_DATA_BYTES_PER_SG;
330 sg_count = ((buf_len - 1) / max_bytes) + 1;
331 if (sg_count > AHCI_MAX_SG) {
332 printf("Error:Too much sg!\n");
336 for (i = 0; i < sg_count; i++) {
338 cpu_to_le32((u32)buf + i * max_bytes);
339 ahci_sg->addr_hi = 0;
340 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
345 buf_len -= max_bytes;
351 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
353 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
354 AHCI_CMD_SLOT_SZ * cmd_slot);
356 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
357 cmd_hdr->opts = cpu_to_le32(opts);
359 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
360 #ifdef CONFIG_PHYS_64BIT
361 pp->cmd_slot->tbl_addr_hi =
362 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
366 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
368 static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
369 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
372 struct ahci_ioports *pp = &uc_priv->port[port];
373 struct sata_port_regs *port_mmio = pp->port_mmio;
375 int sg_count = 0, cmd_slot = 0;
377 cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
378 if (32 == cmd_slot) {
379 printf("Can't find empty command slot!\n");
383 /* Check xfer length */
384 if (buf_len > MAX_BYTES_PER_TRANS) {
385 printf("Max transfer length is %dB\n\r",
386 MAX_BYTES_PER_TRANS);
390 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
392 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
393 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
396 flush_cache((ulong)buf, buf_len);
398 ahci_fill_cmd_slot(pp, cmd_slot, opts);
400 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
401 writel_with_flush(1 << cmd_slot, &port_mmio->ci);
403 if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
405 printf("timeout exit!\n");
408 invalidate_dcache_range((int)(pp->cmd_slot),
409 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
410 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
411 pp->cmd_slot->status);
413 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
418 static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
420 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
421 struct sata_fis_h2d *cfis = &h2d;
423 memset(cfis, 0, sizeof(struct sata_fis_h2d));
424 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
425 cfis->pm_port_c = 1 << 7;
426 cfis->command = ATA_CMD_SET_FEATURES;
427 cfis->features = SETFEATURES_XFER;
428 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
430 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
433 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
435 struct ahci_ioports *pp = &uc_priv->port[port];
436 struct sata_port_regs *port_mmio = pp->port_mmio;
439 int timeout = 10000000;
441 debug("Enter start port: %d\n", port);
442 port_status = readl(&port_mmio->ssts);
443 debug("Port %d status: %x\n", port, port_status);
444 if ((port_status & 0xf) != 0x03) {
445 printf("No Link on this port!\n");
449 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
452 printf("No mem for table!\n");
456 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
457 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
460 * First item in chunk of DMA memory: 32-slot command table,
461 * 32 bytes each in size
463 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
464 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
465 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
468 * Second item: Received-FIS area, 256-Byte aligned
471 mem += AHCI_RX_FIS_SZ;
474 * Third item: data area for storing a single command
475 * and its scatter-gather table
478 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
480 mem += AHCI_CMD_TBL_HDR;
482 writel_with_flush(0x00004444, &port_mmio->dmacr);
483 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
484 writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
485 writel_with_flush(pp->rx_fis, &port_mmio->fb);
488 writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
491 /* Wait device ready */
492 while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
493 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
497 debug("Device not ready for BSY, DRQ and"
502 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
503 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
504 PORT_CMD_START, &port_mmio->cmd);
506 debug("Exit start port %d\n", port);
511 static void dwc_ahsata_print_info(struct blk_desc *pdev)
513 printf("SATA Device Info:\n\r");
514 #ifdef CONFIG_SYS_64BIT_LBA
515 printf("S/N: %s\n\rProduct model number: %s\n\r"
516 "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
517 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
519 printf("S/N: %s\n\rProduct model number: %s\n\r"
520 "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
521 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
525 static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
527 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
528 struct sata_fis_h2d *cfis = &h2d;
529 u8 port = uc_priv->hard_port_no;
531 memset(cfis, 0, sizeof(struct sata_fis_h2d));
533 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
534 cfis->pm_port_c = 0x80; /* is command */
535 cfis->command = ATA_CMD_ID_ATA;
537 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
539 ata_swap_buf_le16(id, ATA_ID_WORDS);
542 static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
544 uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
545 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
546 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
549 static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
550 u32 blkcnt, u8 *buffer, int is_write)
552 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
553 struct sata_fis_h2d *cfis = &h2d;
554 u8 port = uc_priv->hard_port_no;
559 memset(cfis, 0, sizeof(struct sata_fis_h2d));
561 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
562 cfis->pm_port_c = 0x80; /* is command */
563 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
564 cfis->device = ATA_LBA;
566 cfis->device |= (block >> 24) & 0xf;
567 cfis->lba_high = (block >> 16) & 0xff;
568 cfis->lba_mid = (block >> 8) & 0xff;
569 cfis->lba_low = block & 0xff;
570 cfis->sector_count = (u8)(blkcnt & 0xff);
572 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
573 ATA_SECT_SIZE * blkcnt, is_write) > 0)
579 static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
581 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
582 struct sata_fis_h2d *cfis = &h2d;
583 u8 port = uc_priv->hard_port_no;
585 memset(cfis, 0, sizeof(struct sata_fis_h2d));
587 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
588 cfis->pm_port_c = 0x80; /* is command */
589 cfis->command = ATA_CMD_FLUSH;
591 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
594 static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
595 lbaint_t blkcnt, u8 *buffer, int is_write)
597 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
598 struct sata_fis_h2d *cfis = &h2d;
599 u8 port = uc_priv->hard_port_no;
604 memset(cfis, 0, sizeof(struct sata_fis_h2d));
606 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
607 cfis->pm_port_c = 0x80; /* is command */
609 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
612 cfis->lba_high_exp = (block >> 40) & 0xff;
613 cfis->lba_mid_exp = (block >> 32) & 0xff;
614 cfis->lba_low_exp = (block >> 24) & 0xff;
615 cfis->lba_high = (block >> 16) & 0xff;
616 cfis->lba_mid = (block >> 8) & 0xff;
617 cfis->lba_low = block & 0xff;
618 cfis->device = ATA_LBA;
619 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
620 cfis->sector_count = blkcnt & 0xff;
622 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
623 ATA_SECT_SIZE * blkcnt, is_write) > 0)
629 static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
631 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
632 struct sata_fis_h2d *cfis = &h2d;
633 u8 port = uc_priv->hard_port_no;
635 memset(cfis, 0, sizeof(struct sata_fis_h2d));
637 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
638 cfis->pm_port_c = 0x80; /* is command */
639 cfis->command = ATA_CMD_FLUSH_EXT;
641 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
644 static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
646 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
647 uc_priv->flags |= SATA_FLAG_WCACHE;
648 if (ata_id_has_flush(id))
649 uc_priv->flags |= SATA_FLAG_FLUSH;
650 if (ata_id_has_flush_ext(id))
651 uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
654 static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
655 lbaint_t blkcnt, const void *buffer,
666 max_blks = ATA_MAX_SECTORS_LBA48;
669 if (blks > max_blks) {
670 if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
676 addr += ATA_SECT_SIZE * max_blks;
678 if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
683 addr += ATA_SECT_SIZE * blks;
690 static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
691 lbaint_t blkcnt, const void *buffer,
702 max_blks = ATA_MAX_SECTORS;
704 if (blks > max_blks) {
705 if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
711 addr += ATA_SECT_SIZE * max_blks;
713 if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
718 addr += ATA_SECT_SIZE * blks;
725 static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv)
730 linkmap = uc_priv->link_port_map;
733 printf("No port device detected!\n");
737 for (i = 0; i < uc_priv->n_ports; i++) {
738 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
739 if (ahci_port_start(uc_priv, (u8)i)) {
740 printf("Can not start port %d\n", i);
743 uc_priv->hard_port_no = i;
751 static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
752 struct blk_desc *pdev)
754 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
755 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
756 u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
758 u8 port = uc_priv->hard_port_no;
759 ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
761 /* Identify device to get information */
762 dwc_ahsata_identify(uc_priv, id);
765 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
766 memcpy(pdev->product, serial, sizeof(serial));
768 /* Firmware version */
769 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
770 memcpy(pdev->revision, firmware, sizeof(firmware));
773 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
774 memcpy(pdev->vendor, product, sizeof(product));
777 n_sectors = ata_id_n_sectors(id);
778 pdev->lba = (u32)n_sectors;
780 pdev->type = DEV_TYPE_HARDDISK;
781 pdev->blksz = ATA_SECT_SIZE;
784 /* Check if support LBA48 */
785 if (ata_id_has_lba48(id)) {
787 debug("Device support LBA48\n\r");
790 /* Get the NCQ queue depth from device */
791 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
792 uc_priv->flags |= ata_id_queue_depth(id);
794 /* Get the xfer mode from device */
795 dwc_ahsata_xfer_mode(uc_priv, id);
797 /* Get the write cache status from device */
798 dwc_ahsata_init_wcache(uc_priv, id);
800 /* Set the xfer mode to highest speed */
801 ahci_set_feature(uc_priv, port);
803 dwc_ahsata_print_info(pdev);
809 * SATA interface between low level driver and command layer
811 static ulong sata_read_common(struct ahci_uc_priv *uc_priv,
812 struct blk_desc *desc, ulong blknr,
813 lbaint_t blkcnt, void *buffer)
818 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
821 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
827 static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
828 struct blk_desc *desc, ulong blknr,
829 lbaint_t blkcnt, const void *buffer)
832 u32 flags = uc_priv->flags;
835 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
837 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT))
838 dwc_ahsata_flush_cache_ext(uc_priv);
840 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
842 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH))
843 dwc_ahsata_flush_cache(uc_priv);
849 #if !CONFIG_IS_ENABLED(AHCI)
850 static int ahci_init_one(int pdev)
853 struct ahci_uc_priv *uc_priv = NULL;
855 uc_priv = malloc(sizeof(struct ahci_uc_priv));
856 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
859 uc_priv->host_flags = ATA_FLAG_SATA
865 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
867 /* initialize adapter */
868 rc = ahci_host_init(uc_priv);
872 ahci_print_info(uc_priv);
874 /* Save the uc_private struct to block device struct */
875 sata_dev_desc[pdev].priv = uc_priv;
883 int init_sata(int dev)
885 struct ahci_uc_priv *uc_priv = NULL;
887 #if defined(CONFIG_MX6)
888 if (!is_mx6dq() && !is_mx6dqp())
891 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
892 printf("The sata index %d is out of ranges\n\r", dev);
898 uc_priv = sata_dev_desc[dev].priv;
900 return dwc_ahci_start_ports(uc_priv) ? 1 : 0;
903 int reset_sata(int dev)
905 struct ahci_uc_priv *uc_priv;
906 struct sata_host_regs *host_mmio;
908 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
909 printf("The sata index %d is out of ranges\n\r", dev);
913 uc_priv = sata_dev_desc[dev].priv;
915 /* not initialized, so nothing to reset */
918 host_mmio = uc_priv->mmio_base;
919 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
920 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
926 int sata_port_status(int dev, int port)
928 struct sata_port_regs *port_mmio;
929 struct ahci_uc_priv *uc_priv = NULL;
931 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
934 if (sata_dev_desc[dev].priv == NULL)
937 uc_priv = sata_dev_desc[dev].priv;
938 port_mmio = uc_priv->port[port].port_mmio;
940 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK;
944 * SATA interface between low level driver and command layer
946 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
948 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
950 return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
954 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
956 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
958 return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
962 int scan_sata(int dev)
964 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
965 struct blk_desc *pdev = &sata_dev_desc[dev];
967 return dwc_ahsata_scan_common(uc_priv, pdev);
969 #endif /* CONFIG_IS_ENABLED(AHCI) */
971 #if CONFIG_IS_ENABLED(AHCI)
973 int dwc_ahsata_port_status(struct udevice *dev, int port)
975 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
976 struct sata_port_regs *port_mmio;
978 port_mmio = uc_priv->port[port].port_mmio;
979 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO;
982 int dwc_ahsata_bus_reset(struct udevice *dev)
984 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
985 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
987 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
988 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
994 int dwc_ahsata_scan(struct udevice *dev)
996 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
997 struct blk_desc *desc;
1002 * Create only one block device and do detection
1003 * to make sure that there won't be a lot of
1004 * block devices created
1006 device_find_first_child(dev, &blk);
1008 ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk",
1009 IF_TYPE_SATA, -1, 512, 0, &blk);
1011 debug("Can't create device\n");
1016 desc = dev_get_uclass_platdata(blk);
1017 ret = dwc_ahsata_scan_common(uc_priv, desc);
1019 debug("%s: Failed to scan bus\n", __func__);
1026 int dwc_ahsata_probe(struct udevice *dev)
1028 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1031 uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
1032 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
1033 uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
1035 /* initialize adapter */
1036 ret = ahci_host_init(uc_priv);
1040 ahci_print_info(uc_priv);
1042 return dwc_ahci_start_ports(uc_priv);
1045 static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr,
1046 lbaint_t blkcnt, void *buffer)
1048 struct blk_desc *desc = dev_get_uclass_platdata(blk);
1049 struct udevice *dev = dev_get_parent(blk);
1050 struct ahci_uc_priv *uc_priv;
1052 uc_priv = dev_get_uclass_priv(dev);
1053 return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer);
1056 static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr,
1057 lbaint_t blkcnt, const void *buffer)
1059 struct blk_desc *desc = dev_get_uclass_platdata(blk);
1060 struct udevice *dev = dev_get_parent(blk);
1061 struct ahci_uc_priv *uc_priv;
1063 uc_priv = dev_get_uclass_priv(dev);
1064 return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer);
1067 static const struct blk_ops dwc_ahsata_blk_ops = {
1068 .read = dwc_ahsata_read,
1069 .write = dwc_ahsata_write,
1072 U_BOOT_DRIVER(dwc_ahsata_blk) = {
1073 .name = "dwc_ahsata_blk",
1075 .ops = &dwc_ahsata_blk_ops,