2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 * Terry Lv <r65388@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <linux/bitops.h>
18 #include <linux/ctype.h>
19 #include <linux/errno.h>
20 #include "dwc_ahsata_priv.h"
22 struct sata_port_regs {
46 struct sata_host_regs {
75 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
76 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
78 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
80 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
82 return base + 0x100 + (port * 0x80);
85 static int waiting_for_cmd_completed(u8 *offset,
93 ((status = readl(offset)) & sign) && i < timeout_msec;
97 return (i < timeout_msec) ? 0 : -1;
100 static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
102 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
104 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
105 writel(0x02060b14, &host_mmio->oobr);
110 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
112 u32 tmp, cap_save, num_ports;
113 int i, j, timeout = 1000;
114 struct sata_port_regs *port_mmio = NULL;
115 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
116 int clk = mxc_get_clock(MXC_SATA_CLK);
118 cap_save = readl(&host_mmio->cap);
119 cap_save |= SATA_HOST_CAP_SSS;
121 /* global controller reset */
122 tmp = readl(&host_mmio->ghc);
123 if ((tmp & SATA_HOST_GHC_HR) == 0)
124 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
126 while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
130 debug("controller reset failed (0x%x)\n", tmp);
135 writel(clk / 1000, &host_mmio->timer1ms);
137 ahci_setup_oobr(uc_priv, 0);
139 writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
140 writel(cap_save, &host_mmio->cap);
141 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
142 writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
145 * Determine which Ports are implemented by the DWC_ahsata,
146 * by reading the PI register. This bit map value aids the
147 * software to determine how many Ports are available and
148 * which Port registers need to be initialized.
150 uc_priv->cap = readl(&host_mmio->cap);
151 uc_priv->port_map = readl(&host_mmio->pi);
153 /* Determine how many command slots the HBA supports */
154 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
156 debug("cap 0x%x port_map 0x%x n_ports %d\n",
157 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
159 for (i = 0; i < uc_priv->n_ports; i++) {
160 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
161 port_mmio = uc_priv->port[i].port_mmio;
163 /* Ensure that the DWC_ahsata is in idle state */
164 tmp = readl(&port_mmio->cmd);
167 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
168 * are all cleared, the Port is in an idle state.
170 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
171 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
174 * System software places a Port into the idle state by
175 * clearing P#CMD.ST and waiting for P#CMD.CR to return
178 tmp &= ~SATA_PORT_CMD_ST;
179 writel_with_flush(tmp, &port_mmio->cmd);
182 * spec says 500 msecs for each bit, so
183 * this is slightly incorrect.
188 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR)
193 debug("port reset failed (0x%x)\n", tmp);
199 tmp = readl(&port_mmio->cmd);
200 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
202 /* Wait for spin-up to finish */
204 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD)
208 debug("Spin-Up can't finish!\n");
212 for (j = 0; j < 100; ++j) {
214 tmp = readl(&port_mmio->ssts);
215 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
216 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
220 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
222 while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X)
226 debug("Can't find DIAG_X set!\n");
231 * For each implemented Port, clear the P#SERR
232 * register, by writing ones to each implemented\
235 tmp = readl(&port_mmio->serr);
236 debug("P#SERR 0x%x\n",
238 writel(tmp, &port_mmio->serr);
240 /* Ack any pending irq events for this port */
241 tmp = readl(&host_mmio->is);
242 debug("IS 0x%x\n", tmp);
244 writel(tmp, &host_mmio->is);
246 writel(1 << i, &host_mmio->is);
248 /* set irq mask (enables interrupts) */
249 writel(DEF_PORT_IRQ, &port_mmio->ie);
251 /* register linkup ports */
252 tmp = readl(&port_mmio->ssts);
253 debug("Port %d status: 0x%x\n", i, tmp);
254 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
255 uc_priv->link_port_map |= (0x01 << i);
258 tmp = readl(&host_mmio->ghc);
259 debug("GHC 0x%x\n", tmp);
260 writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
261 tmp = readl(&host_mmio->ghc);
262 debug("GHC 0x%x\n", tmp);
267 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
269 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
270 u32 vers, cap, impl, speed;
274 vers = readl(&host_mmio->vs);
276 impl = uc_priv->port_map;
278 speed = (cap & SATA_HOST_CAP_ISS_MASK)
279 >> SATA_HOST_CAP_ISS_OFFSET;
289 printf("AHCI %02x%02x.%02x%02x "
290 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
295 ((cap >> 8) & 0x1f) + 1,
304 cap & (1 << 31) ? "64bit " : "",
305 cap & (1 << 30) ? "ncq " : "",
306 cap & (1 << 28) ? "ilck " : "",
307 cap & (1 << 27) ? "stag " : "",
308 cap & (1 << 26) ? "pm " : "",
309 cap & (1 << 25) ? "led " : "",
310 cap & (1 << 24) ? "clo " : "",
311 cap & (1 << 19) ? "nz " : "",
312 cap & (1 << 18) ? "only " : "",
313 cap & (1 << 17) ? "pmp " : "",
314 cap & (1 << 15) ? "pio " : "",
315 cap & (1 << 14) ? "slum " : "",
316 cap & (1 << 13) ? "part " : "");
319 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
320 unsigned char *buf, int buf_len)
322 struct ahci_ioports *pp = &uc_priv->port[port];
323 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
324 u32 sg_count, max_bytes;
327 max_bytes = MAX_DATA_BYTES_PER_SG;
328 sg_count = ((buf_len - 1) / max_bytes) + 1;
329 if (sg_count > AHCI_MAX_SG) {
330 printf("Error:Too much sg!\n");
334 for (i = 0; i < sg_count; i++) {
336 cpu_to_le32((u32)buf + i * max_bytes);
337 ahci_sg->addr_hi = 0;
338 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
343 buf_len -= max_bytes;
349 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
351 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
352 AHCI_CMD_SLOT_SZ * cmd_slot);
354 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
355 cmd_hdr->opts = cpu_to_le32(opts);
357 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
358 #ifdef CONFIG_PHYS_64BIT
359 pp->cmd_slot->tbl_addr_hi =
360 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
364 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
366 static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
367 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
370 struct ahci_ioports *pp = &uc_priv->port[port];
371 struct sata_port_regs *port_mmio = pp->port_mmio;
373 int sg_count = 0, cmd_slot = 0;
375 cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
376 if (32 == cmd_slot) {
377 printf("Can't find empty command slot!\n");
381 /* Check xfer length */
382 if (buf_len > MAX_BYTES_PER_TRANS) {
383 printf("Max transfer length is %dB\n\r",
384 MAX_BYTES_PER_TRANS);
388 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
390 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
391 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
394 flush_cache((ulong)buf, buf_len);
396 ahci_fill_cmd_slot(pp, cmd_slot, opts);
398 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
399 writel_with_flush(1 << cmd_slot, &port_mmio->ci);
401 if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
403 printf("timeout exit!\n");
406 invalidate_dcache_range((int)(pp->cmd_slot),
407 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
408 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
409 pp->cmd_slot->status);
411 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
416 static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
418 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
419 struct sata_fis_h2d *cfis = &h2d;
421 memset(cfis, 0, sizeof(struct sata_fis_h2d));
422 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
423 cfis->pm_port_c = 1 << 7;
424 cfis->command = ATA_CMD_SET_FEATURES;
425 cfis->features = SETFEATURES_XFER;
426 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
428 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
431 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
433 struct ahci_ioports *pp = &uc_priv->port[port];
434 struct sata_port_regs *port_mmio = pp->port_mmio;
437 int timeout = 10000000;
439 debug("Enter start port: %d\n", port);
440 port_status = readl(&port_mmio->ssts);
441 debug("Port %d status: %x\n", port, port_status);
442 if ((port_status & 0xf) != 0x03) {
443 printf("No Link on this port!\n");
447 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
450 printf("No mem for table!\n");
454 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
455 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
458 * First item in chunk of DMA memory: 32-slot command table,
459 * 32 bytes each in size
461 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
462 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
463 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
466 * Second item: Received-FIS area, 256-Byte aligned
469 mem += AHCI_RX_FIS_SZ;
472 * Third item: data area for storing a single command
473 * and its scatter-gather table
476 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
478 mem += AHCI_CMD_TBL_HDR;
480 writel_with_flush(0x00004444, &port_mmio->dmacr);
481 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
482 writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
483 writel_with_flush(pp->rx_fis, &port_mmio->fb);
486 writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
489 /* Wait device ready */
490 while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
491 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
495 debug("Device not ready for BSY, DRQ and"
500 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
501 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
502 PORT_CMD_START, &port_mmio->cmd);
504 debug("Exit start port %d\n", port);
509 static void dwc_ahsata_print_info(struct blk_desc *pdev)
511 printf("SATA Device Info:\n\r");
512 #ifdef CONFIG_SYS_64BIT_LBA
513 printf("S/N: %s\n\rProduct model number: %s\n\r"
514 "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
515 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
517 printf("S/N: %s\n\rProduct model number: %s\n\r"
518 "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
519 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
523 static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
525 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
526 struct sata_fis_h2d *cfis = &h2d;
527 u8 port = uc_priv->hard_port_no;
529 memset(cfis, 0, sizeof(struct sata_fis_h2d));
531 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
532 cfis->pm_port_c = 0x80; /* is command */
533 cfis->command = ATA_CMD_ID_ATA;
535 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
537 ata_swap_buf_le16(id, ATA_ID_WORDS);
540 static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
542 uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
543 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
544 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
547 static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
548 u32 blkcnt, u8 *buffer, int is_write)
550 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
551 struct sata_fis_h2d *cfis = &h2d;
552 u8 port = uc_priv->hard_port_no;
557 memset(cfis, 0, sizeof(struct sata_fis_h2d));
559 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
560 cfis->pm_port_c = 0x80; /* is command */
561 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
562 cfis->device = ATA_LBA;
564 cfis->device |= (block >> 24) & 0xf;
565 cfis->lba_high = (block >> 16) & 0xff;
566 cfis->lba_mid = (block >> 8) & 0xff;
567 cfis->lba_low = block & 0xff;
568 cfis->sector_count = (u8)(blkcnt & 0xff);
570 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
571 ATA_SECT_SIZE * blkcnt, is_write) > 0)
577 static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
579 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
580 struct sata_fis_h2d *cfis = &h2d;
581 u8 port = uc_priv->hard_port_no;
583 memset(cfis, 0, sizeof(struct sata_fis_h2d));
585 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
586 cfis->pm_port_c = 0x80; /* is command */
587 cfis->command = ATA_CMD_FLUSH;
589 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
592 static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
593 lbaint_t blkcnt, u8 *buffer, int is_write)
595 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
596 struct sata_fis_h2d *cfis = &h2d;
597 u8 port = uc_priv->hard_port_no;
602 memset(cfis, 0, sizeof(struct sata_fis_h2d));
604 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
605 cfis->pm_port_c = 0x80; /* is command */
607 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
610 cfis->lba_high_exp = (block >> 40) & 0xff;
611 cfis->lba_mid_exp = (block >> 32) & 0xff;
612 cfis->lba_low_exp = (block >> 24) & 0xff;
613 cfis->lba_high = (block >> 16) & 0xff;
614 cfis->lba_mid = (block >> 8) & 0xff;
615 cfis->lba_low = block & 0xff;
616 cfis->device = ATA_LBA;
617 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
618 cfis->sector_count = blkcnt & 0xff;
620 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
621 ATA_SECT_SIZE * blkcnt, is_write) > 0)
627 static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
629 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
630 struct sata_fis_h2d *cfis = &h2d;
631 u8 port = uc_priv->hard_port_no;
633 memset(cfis, 0, sizeof(struct sata_fis_h2d));
635 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
636 cfis->pm_port_c = 0x80; /* is command */
637 cfis->command = ATA_CMD_FLUSH_EXT;
639 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
642 static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
644 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
645 uc_priv->flags |= SATA_FLAG_WCACHE;
646 if (ata_id_has_flush(id))
647 uc_priv->flags |= SATA_FLAG_FLUSH;
648 if (ata_id_has_flush_ext(id))
649 uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
652 static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
653 lbaint_t blkcnt, const void *buffer,
664 max_blks = ATA_MAX_SECTORS_LBA48;
667 if (blks > max_blks) {
668 if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
674 addr += ATA_SECT_SIZE * max_blks;
676 if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
681 addr += ATA_SECT_SIZE * blks;
688 static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
689 lbaint_t blkcnt, const void *buffer,
700 max_blks = ATA_MAX_SECTORS;
702 if (blks > max_blks) {
703 if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
709 addr += ATA_SECT_SIZE * max_blks;
711 if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
716 addr += ATA_SECT_SIZE * blks;
723 static int ahci_init_one(int pdev)
726 struct ahci_uc_priv *uc_priv = NULL;
728 uc_priv = malloc(sizeof(struct ahci_uc_priv));
729 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
732 uc_priv->host_flags = ATA_FLAG_SATA
738 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
740 /* initialize adapter */
741 rc = ahci_host_init(uc_priv);
745 ahci_print_info(uc_priv);
747 /* Save the uc_private struct to block device struct */
748 sata_dev_desc[pdev].priv = uc_priv;
756 int init_sata(int dev)
760 struct ahci_uc_priv *uc_priv = NULL;
762 #if defined(CONFIG_MX6)
763 if (!is_mx6dq() && !is_mx6dqp())
766 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
767 printf("The sata index %d is out of ranges\n\r", dev);
773 uc_priv = sata_dev_desc[dev].priv;
774 linkmap = uc_priv->link_port_map;
777 printf("No port device detected!\n");
781 for (i = 0; i < uc_priv->n_ports; i++) {
782 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
783 if (ahci_port_start(uc_priv, (u8)i)) {
784 printf("Can not start port %d\n", i);
787 uc_priv->hard_port_no = i;
795 int reset_sata(int dev)
797 struct ahci_uc_priv *uc_priv;
798 struct sata_host_regs *host_mmio;
800 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
801 printf("The sata index %d is out of ranges\n\r", dev);
805 uc_priv = sata_dev_desc[dev].priv;
807 /* not initialized, so nothing to reset */
810 host_mmio = uc_priv->mmio_base;
811 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
812 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
818 int sata_port_status(int dev, int port)
820 struct sata_port_regs *port_mmio;
821 struct ahci_uc_priv *uc_priv = NULL;
823 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
826 if (sata_dev_desc[dev].priv == NULL)
829 uc_priv = sata_dev_desc[dev].priv;
830 port_mmio = uc_priv->port[port].port_mmio;
832 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK;
836 * SATA interface between low level driver and command layer
838 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
840 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
843 if (sata_dev_desc[dev].lba48)
844 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt,
847 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt,
852 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
855 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
856 u32 flags = uc_priv->flags;
858 if (sata_dev_desc[dev].lba48) {
859 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
861 if ((flags & SATA_FLAG_WCACHE) &&
862 (flags & SATA_FLAG_FLUSH_EXT))
863 dwc_ahsata_flush_cache_ext(uc_priv);
865 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
867 if ((flags & SATA_FLAG_WCACHE) &&
868 (flags & SATA_FLAG_FLUSH))
869 dwc_ahsata_flush_cache(uc_priv);
874 int scan_sata(int dev)
876 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
877 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
878 u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
881 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
882 u8 port = uc_priv->hard_port_no;
883 struct blk_desc *pdev = &sata_dev_desc[dev];
885 id = (u16 *)memalign(ARCH_DMA_MINALIGN,
886 roundup(ARCH_DMA_MINALIGN,
887 (ATA_ID_WORDS * 2)));
889 printf("id malloc failed\n\r");
893 /* Identify device to get information */
894 dwc_ahsata_identify(uc_priv, id);
897 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
898 memcpy(pdev->product, serial, sizeof(serial));
900 /* Firmware version */
901 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
902 memcpy(pdev->revision, firmware, sizeof(firmware));
905 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
906 memcpy(pdev->vendor, product, sizeof(product));
909 n_sectors = ata_id_n_sectors(id);
910 pdev->lba = (u32)n_sectors;
912 pdev->type = DEV_TYPE_HARDDISK;
913 pdev->blksz = ATA_SECT_SIZE;
916 /* Check if support LBA48 */
917 if (ata_id_has_lba48(id)) {
919 debug("Device support LBA48\n\r");
922 /* Get the NCQ queue depth from device */
923 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
924 uc_priv->flags |= ata_id_queue_depth(id);
926 /* Get the xfer mode from device */
927 dwc_ahsata_xfer_mode(uc_priv, id);
929 /* Get the write cache status from device */
930 dwc_ahsata_init_wcache(uc_priv, id);
932 /* Set the xfer mode to highest speed */
933 ahci_set_feature(uc_priv, port);
937 dwc_ahsata_print_info(&sata_dev_desc[dev]);