2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 * with the reference on libata and ahci drvier in kernel
14 #include <asm/processor.h>
15 #include <asm/errno.h>
20 #include <linux/ctype.h>
23 static int ata_io_flush(u8 port);
25 struct ahci_probe_ent *probe_ent = NULL;
26 u16 *ataid[AHCI_MAX_PORTS];
28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
31 * Some controllers limit number of blocks they can read/write at once.
32 * Contemporary SSD devices work much faster if the read/write size is aligned
33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
36 #ifndef MAX_SATA_BLOCKS_READ_WRITE
37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
40 /* Maximum timeouts for each event */
41 #define WAIT_MS_SPINUP 20000
42 #define WAIT_MS_DATAIO 10000
43 #define WAIT_MS_FLUSH 5000
44 #define WAIT_MS_LINKUP 200
46 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
48 return base + 0x100 + (port * 0x80);
52 static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base,
53 unsigned int port_idx)
55 base = ahci_port_base(base, port_idx);
57 port->cmd_addr = base;
58 port->scr_addr = base + PORT_SCR;
62 #define msleep(a) udelay(a * 1000)
64 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
66 const unsigned long start = begin;
67 const unsigned long end = start + len;
69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
70 flush_dcache_range(start, end);
74 * SATA controller DMAs to physical RAM. Ensure data from the
75 * controller is invalidated from dcache; next access comes from
78 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
80 const unsigned long start = begin;
81 const unsigned long end = start + len;
83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
84 invalidate_dcache_range(start, end);
88 * Ensure data for SATA controller is flushed out of dcache and
89 * written to physical memory.
91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
93 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
94 AHCI_PORT_PRIV_DMA_SZ);
97 static int waiting_for_cmd_completed(void __iomem *offset,
104 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
107 return (i < timeout_msec) ? 0 : -1;
110 int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
114 void __iomem *port_mmio = probe_ent->port[port].port_mmio;
117 * Bring up SATA link.
118 * SATA link bringup time is usually less than 1 ms; only very
119 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
121 while (j < WAIT_MS_LINKUP) {
122 tmp = readl(port_mmio + PORT_SCR_STAT);
123 tmp &= PORT_SCR_STAT_DET_MASK;
124 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
132 #ifdef CONFIG_SUNXI_AHCI
133 /* The sunxi AHCI controller requires this undocumented setup */
134 static void sunxi_dma_init(void __iomem *port_mmio)
136 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
140 int ahci_reset(void __iomem *base)
143 u32 __iomem *host_ctl_reg = base + HOST_CTL;
144 u32 tmp = readl(host_ctl_reg); /* global controller reset */
146 if ((tmp & HOST_RESET) == 0)
147 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
150 * reset must complete within 1 second, or
151 * the hardware should be considered fried.
155 tmp = readl(host_ctl_reg);
157 } while ((i > 0) && (tmp & HOST_RESET));
160 printf("controller reset failed (0x%x)\n", tmp);
167 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
169 #ifndef CONFIG_SCSI_AHCI_PLAT
170 pci_dev_t pdev = probe_ent->dev;
172 unsigned short vendor;
174 void __iomem *mmio = probe_ent->mmio_base;
175 u32 tmp, cap_save, cmd;
177 void __iomem *port_mmio;
180 debug("ahci_host_init: start\n");
182 cap_save = readl(mmio + HOST_CAP);
183 cap_save &= ((1 << 28) | (1 << 17));
184 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
186 ret = ahci_reset(probe_ent->mmio_base);
190 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
191 writel(cap_save, mmio + HOST_CAP);
192 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
194 #ifndef CONFIG_SCSI_AHCI_PLAT
195 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
197 if (vendor == PCI_VENDOR_ID_INTEL) {
199 pci_read_config_word(pdev, 0x92, &tmp16);
201 pci_write_config_word(pdev, 0x92, tmp16);
204 probe_ent->cap = readl(mmio + HOST_CAP);
205 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
206 port_map = probe_ent->port_map;
207 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
209 debug("cap 0x%x port_map 0x%x n_ports %d\n",
210 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
212 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
213 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
215 for (i = 0; i < probe_ent->n_ports; i++) {
216 if (!(port_map & (1 << i)))
218 probe_ent->port[i].port_mmio = ahci_port_base(mmio, i);
219 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
220 ahci_setup_port(&probe_ent->port[i], mmio, i);
222 /* make sure port is not active */
223 tmp = readl(port_mmio + PORT_CMD);
224 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
225 PORT_CMD_FIS_RX | PORT_CMD_START)) {
226 debug("Port %d is active. Deactivating.\n", i);
227 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
228 PORT_CMD_FIS_RX | PORT_CMD_START);
229 writel_with_flush(tmp, port_mmio + PORT_CMD);
231 /* spec says 500 msecs for each bit, so
232 * this is slightly incorrect.
237 #ifdef CONFIG_SUNXI_AHCI
238 sunxi_dma_init(port_mmio);
241 /* Add the spinup command to whatever mode bits may
242 * already be on in the command register.
244 cmd = readl(port_mmio + PORT_CMD);
245 cmd |= PORT_CMD_SPIN_UP;
246 writel_with_flush(cmd, port_mmio + PORT_CMD);
248 /* Bring up SATA link. */
249 ret = ahci_link_up(probe_ent, i);
251 printf("SATA link %d timeout.\n", i);
254 debug("SATA link ok.\n");
257 /* Clear error status */
258 tmp = readl(port_mmio + PORT_SCR_ERR);
260 writel(tmp, port_mmio + PORT_SCR_ERR);
262 debug("Spinning up device on SATA port %d... ", i);
265 while (j < WAIT_MS_SPINUP) {
266 tmp = readl(port_mmio + PORT_TFDATA);
267 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
270 tmp = readl(port_mmio + PORT_SCR_STAT);
271 tmp &= PORT_SCR_STAT_DET_MASK;
272 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
277 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
278 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
279 debug("SATA link %d down (COMINIT received), retrying...\n", i);
284 printf("Target spinup took %d ms.\n", j);
285 if (j == WAIT_MS_SPINUP)
290 tmp = readl(port_mmio + PORT_SCR_ERR);
291 debug("PORT_SCR_ERR 0x%x\n", tmp);
292 writel(tmp, port_mmio + PORT_SCR_ERR);
294 /* ack any pending irq events for this port */
295 tmp = readl(port_mmio + PORT_IRQ_STAT);
296 debug("PORT_IRQ_STAT 0x%x\n", tmp);
298 writel(tmp, port_mmio + PORT_IRQ_STAT);
300 writel(1 << i, mmio + HOST_IRQ_STAT);
302 /* register linkup ports */
303 tmp = readl(port_mmio + PORT_SCR_STAT);
304 debug("SATA port %d status: 0x%x\n", i, tmp);
305 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
306 probe_ent->link_port_map |= (0x01 << i);
309 tmp = readl(mmio + HOST_CTL);
310 debug("HOST_CTL 0x%x\n", tmp);
311 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
312 tmp = readl(mmio + HOST_CTL);
313 debug("HOST_CTL 0x%x\n", tmp);
314 #ifndef CONFIG_SCSI_AHCI_PLAT
315 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
316 tmp |= PCI_COMMAND_MASTER;
317 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
323 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
325 #ifndef CONFIG_SCSI_AHCI_PLAT
326 pci_dev_t pdev = probe_ent->dev;
329 void __iomem *mmio = probe_ent->mmio_base;
330 u32 vers, cap, cap2, impl, speed;
334 vers = readl(mmio + HOST_VERSION);
335 cap = probe_ent->cap;
336 cap2 = readl(mmio + HOST_CAP2);
337 impl = probe_ent->port_map;
339 speed = (cap >> 20) & 0xf;
349 #ifdef CONFIG_SCSI_AHCI_PLAT
352 pci_read_config_word(pdev, 0x0a, &cc);
355 else if (cc == 0x0106)
357 else if (cc == 0x0104)
362 printf("AHCI %02x%02x.%02x%02x "
363 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
368 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
374 cap & (1 << 31) ? "64bit " : "",
375 cap & (1 << 30) ? "ncq " : "",
376 cap & (1 << 28) ? "ilck " : "",
377 cap & (1 << 27) ? "stag " : "",
378 cap & (1 << 26) ? "pm " : "",
379 cap & (1 << 25) ? "led " : "",
380 cap & (1 << 24) ? "clo " : "",
381 cap & (1 << 19) ? "nz " : "",
382 cap & (1 << 18) ? "only " : "",
383 cap & (1 << 17) ? "pmp " : "",
384 cap & (1 << 16) ? "fbss " : "",
385 cap & (1 << 15) ? "pio " : "",
386 cap & (1 << 14) ? "slum " : "",
387 cap & (1 << 13) ? "part " : "",
388 cap & (1 << 7) ? "ccc " : "",
389 cap & (1 << 6) ? "ems " : "",
390 cap & (1 << 5) ? "sxs " : "",
391 cap2 & (1 << 2) ? "apst " : "",
392 cap2 & (1 << 1) ? "nvmp " : "",
393 cap2 & (1 << 0) ? "boh " : "");
396 #ifndef CONFIG_SCSI_AHCI_PLAT
397 static int ahci_init_one(pci_dev_t pdev)
402 probe_ent = malloc(sizeof(struct ahci_probe_ent));
404 printf("%s: No memory for probe_ent\n", __func__);
408 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
409 probe_ent->dev = pdev;
411 probe_ent->host_flags = ATA_FLAG_SATA
416 probe_ent->pio_mask = 0x1f;
417 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
419 probe_ent->mmio_base = pci_map_bar(pdev, PCI_BASE_ADDRESS_5,
421 debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
424 * JMicron-specific fixup:
425 * make sure we're in AHCI mode
427 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
428 if (vendor == 0x197b)
429 pci_write_config_byte(pdev, 0x41, 0xa1);
431 /* initialize adapter */
432 rc = ahci_host_init(probe_ent);
436 ahci_print_info(probe_ent);
445 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
447 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
449 struct ahci_ioports *pp = &(probe_ent->port[port]);
450 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
454 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
455 if (sg_count > AHCI_MAX_SG) {
456 printf("Error:Too much sg!\n");
460 for (i = 0; i < sg_count; i++) {
462 cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT);
463 ahci_sg->addr_hi = 0;
464 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
465 (buf_len < MAX_DATA_BYTE_COUNT
467 : (MAX_DATA_BYTE_COUNT - 1)));
469 buf_len -= MAX_DATA_BYTE_COUNT;
476 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
478 pp->cmd_slot->opts = cpu_to_le32(opts);
479 pp->cmd_slot->status = 0;
480 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
481 #ifdef CONFIG_PHYS_64BIT
482 pp->cmd_slot->tbl_addr_hi =
483 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
488 #ifdef CONFIG_AHCI_SETFEATURES_XFER
489 static void ahci_set_feature(u8 port)
491 struct ahci_ioports *pp = &(probe_ent->port[port]);
492 void __iomem *port_mmio = pp->port_mmio;
493 u32 cmd_fis_len = 5; /* five dwords */
497 memset(fis, 0, sizeof(fis));
500 fis[2] = ATA_CMD_SET_FEATURES;
501 fis[3] = SETFEATURES_XFER;
502 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
504 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
505 ahci_fill_cmd_slot(pp, cmd_fis_len);
506 ahci_dcache_flush_sata_cmd(pp);
507 writel(1, port_mmio + PORT_CMD_ISSUE);
508 readl(port_mmio + PORT_CMD_ISSUE);
510 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
511 WAIT_MS_DATAIO, 0x1)) {
512 printf("set feature error on port %d!\n", port);
517 static int wait_spinup(void __iomem *port_mmio)
522 start = get_timer(0);
524 tf_data = readl(port_mmio + PORT_TFDATA);
525 if (!(tf_data & ATA_BUSY))
527 } while (get_timer(start) < WAIT_MS_SPINUP);
532 static int ahci_port_start(u8 port)
534 struct ahci_ioports *pp = &(probe_ent->port[port]);
535 void __iomem *port_mmio = pp->port_mmio;
539 debug("Enter start port: %d\n", port);
540 port_status = readl(port_mmio + PORT_SCR_STAT);
541 debug("Port %d status: %x\n", port, port_status);
542 if ((port_status & 0xf) != 0x03) {
543 printf("No Link on this port!\n");
547 mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
550 printf("%s: No mem for table!\n", __func__);
554 /* Aligned to 2048-bytes */
555 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
556 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
559 * First item in chunk of DMA memory: 32-slot command table,
560 * 32 bytes each in size
563 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
564 debug("cmd_slot = %p\n", pp->cmd_slot);
565 mem += (AHCI_CMD_SLOT_SZ + 224);
568 * Second item: Received-FIS area
570 pp->rx_fis = virt_to_phys((void *)mem);
571 mem += AHCI_RX_FIS_SZ;
574 * Third item: data area for storing a single command
575 * and its scatter-gather table
577 pp->cmd_tbl = virt_to_phys((void *)mem);
578 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
580 mem += AHCI_CMD_TBL_HDR;
582 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
584 writel_with_flush((unsigned long)pp->cmd_slot,
585 port_mmio + PORT_LST_ADDR);
587 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
589 #ifdef CONFIG_SUNXI_AHCI
590 sunxi_dma_init(port_mmio);
593 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
594 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
595 PORT_CMD_START, port_mmio + PORT_CMD);
597 debug("Exit start port %d\n", port);
600 * Make sure interface is not busy based on error and status
601 * information from task file data register before proceeding
603 return wait_spinup(port_mmio);
607 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
608 int buf_len, u8 is_write)
611 struct ahci_ioports *pp = &(probe_ent->port[port]);
612 void __iomem *port_mmio = pp->port_mmio;
617 debug("Enter %s: for port %d\n", __func__, port);
619 if (port > probe_ent->n_ports) {
620 printf("Invalid port number %d\n", port);
624 port_status = readl(port_mmio + PORT_SCR_STAT);
625 if ((port_status & 0xf) != 0x03) {
626 debug("No Link on port %d!\n", port);
630 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
632 sg_count = ahci_fill_sg(port, buf, buf_len);
633 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
634 ahci_fill_cmd_slot(pp, opts);
636 ahci_dcache_flush_sata_cmd(pp);
637 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
639 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
641 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
642 WAIT_MS_DATAIO, 0x1)) {
643 printf("timeout exit!\n");
647 ahci_dcache_invalidate_range((unsigned long)buf,
648 (unsigned long)buf_len);
649 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
655 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
658 for (i = 0; i < len / 2; i++)
659 target[i] = swab16(src[i]);
660 return (char *)target;
664 * SCSI INQUIRY command operation.
666 static int ata_scsiop_inquiry(ccb *pccb)
668 static const u8 hdr[] = {
671 0x5, /* claim SPC-3 version compatibility */
677 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
680 /* Clean ccb data buffer */
681 memset(pccb->pdata, 0, pccb->datalen);
683 memcpy(pccb->pdata, hdr, sizeof(hdr));
685 if (pccb->datalen <= 35)
688 memset(fis, 0, sizeof(fis));
689 /* Construct the FIS */
690 fis[0] = 0x27; /* Host to device FIS. */
691 fis[1] = 1 << 7; /* Command FIS. */
692 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
694 /* Read id from sata */
697 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
698 ATA_ID_WORDS * 2, 0)) {
699 debug("scsi_ahci: SCSI inquiry command failure.\n");
704 ataid[port] = malloc(ATA_ID_WORDS * 2);
706 printf("%s: No memory for ataid[port]\n", __func__);
713 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
714 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
716 memcpy(&pccb->pdata[8], "ATA ", 8);
717 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
718 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
728 * SCSI READ10/WRITE10 command operation.
730 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
735 u8 *user_buffer = pccb->pdata;
736 u32 user_buffer_size = pccb->datalen;
738 /* Retrieve the base LBA number from the ccb structure. */
739 if (pccb->cmd[0] == SCSI_READ16) {
740 memcpy(&lba, pccb->cmd + 2, 8);
741 lba = be64_to_cpu(lba);
744 memcpy(&temp, pccb->cmd + 2, 4);
745 lba = be32_to_cpu(temp);
749 * Retrieve the base LBA number and the block count from
752 * For 10-byte and 16-byte SCSI R/W commands, transfer
753 * length 0 means transfer 0 block of data.
754 * However, for ATA R/W commands, sector count 0 means
755 * 256 or 65536 sectors, not 0 sectors as in SCSI.
757 * WARNING: one or two older ATA drives treat 0 as 0...
759 if (pccb->cmd[0] == SCSI_READ16)
760 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
762 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
764 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
765 is_write ? "write" : "read", blocks, lba);
768 memset(fis, 0, sizeof(fis));
769 fis[0] = 0x27; /* Host to device FIS. */
770 fis[1] = 1 << 7; /* Command FIS. */
771 /* Command byte (read/write). */
772 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
775 u16 now_blocks; /* number of blocks per iteration */
776 u32 transfer_size; /* number of bytes per iteration */
778 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
780 transfer_size = ATA_SECT_SIZE * now_blocks;
781 if (transfer_size > user_buffer_size) {
782 printf("scsi_ahci: Error: buffer too small.\n");
787 * LBA48 SATA command but only use 32bit address range within
788 * that (unless we've enabled 64bit LBA support). The next
789 * smaller command range (28bit) is too small.
791 fis[4] = (lba >> 0) & 0xff;
792 fis[5] = (lba >> 8) & 0xff;
793 fis[6] = (lba >> 16) & 0xff;
794 fis[7] = 1 << 6; /* device reg: set LBA mode */
795 fis[8] = ((lba >> 24) & 0xff);
796 #ifdef CONFIG_SYS_64BIT_LBA
797 if (pccb->cmd[0] == SCSI_READ16) {
798 fis[9] = ((lba >> 32) & 0xff);
799 fis[10] = ((lba >> 40) & 0xff);
803 fis[3] = 0xe0; /* features */
805 /* Block (sector) count */
806 fis[12] = (now_blocks >> 0) & 0xff;
807 fis[13] = (now_blocks >> 8) & 0xff;
809 /* Read/Write from ahci */
810 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
811 user_buffer, transfer_size,
813 debug("scsi_ahci: SCSI %s10 command failure.\n",
814 is_write ? "WRITE" : "READ");
818 /* If this transaction is a write, do a following flush.
819 * Writes in u-boot are so rare, and the logic to know when is
820 * the last write and do a flush only there is sufficiently
821 * difficult. Just do a flush after every write. This incurs,
822 * usually, one extra flush when the rare writes do happen.
825 if (-EIO == ata_io_flush(pccb->target))
828 user_buffer += transfer_size;
829 user_buffer_size -= transfer_size;
830 blocks -= now_blocks;
839 * SCSI READ CAPACITY10 command operation.
841 static int ata_scsiop_read_capacity10(ccb *pccb)
847 if (!ataid[pccb->target]) {
848 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
850 "\tPlease run SCSI commmand INQUIRY firstly!\n");
854 cap64 = ata_id_n_sectors(ataid[pccb->target]);
855 if (cap64 > 0x100000000ULL)
858 cap = cpu_to_be32(cap64);
859 memcpy(pccb->pdata, &cap, sizeof(cap));
861 block_size = cpu_to_be32((u32)512);
862 memcpy(&pccb->pdata[4], &block_size, 4);
869 * SCSI READ CAPACITY16 command operation.
871 static int ata_scsiop_read_capacity16(ccb *pccb)
876 if (!ataid[pccb->target]) {
877 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
879 "\tPlease run SCSI commmand INQUIRY firstly!\n");
883 cap = ata_id_n_sectors(ataid[pccb->target]);
884 cap = cpu_to_be64(cap);
885 memcpy(pccb->pdata, &cap, sizeof(cap));
887 block_size = cpu_to_be64((u64)512);
888 memcpy(&pccb->pdata[8], &block_size, 8);
895 * SCSI TEST UNIT READY command operation.
897 static int ata_scsiop_test_unit_ready(ccb *pccb)
899 return (ataid[pccb->target]) ? 0 : -EPERM;
903 int scsi_exec(ccb *pccb)
907 switch (pccb->cmd[0]) {
910 ret = ata_scsiop_read_write(pccb, 0);
913 ret = ata_scsiop_read_write(pccb, 1);
915 case SCSI_RD_CAPAC10:
916 ret = ata_scsiop_read_capacity10(pccb);
918 case SCSI_RD_CAPAC16:
919 ret = ata_scsiop_read_capacity16(pccb);
922 ret = ata_scsiop_test_unit_ready(pccb);
925 ret = ata_scsiop_inquiry(pccb);
928 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
933 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
941 void scsi_low_level_init(int busdevfunc)
946 #ifndef CONFIG_SCSI_AHCI_PLAT
947 ahci_init_one(busdevfunc);
950 linkmap = probe_ent->link_port_map;
952 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
953 if (((linkmap >> i) & 0x01)) {
954 if (ahci_port_start((u8) i)) {
955 printf("Can not start port %d\n", i);
958 #ifdef CONFIG_AHCI_SETFEATURES_XFER
959 ahci_set_feature((u8) i);
965 #ifdef CONFIG_SCSI_AHCI_PLAT
966 int ahci_init(void __iomem *base)
971 probe_ent = malloc(sizeof(struct ahci_probe_ent));
973 printf("%s: No memory for probe_ent\n", __func__);
977 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
979 probe_ent->host_flags = ATA_FLAG_SATA
984 probe_ent->pio_mask = 0x1f;
985 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
987 probe_ent->mmio_base = base;
989 /* initialize adapter */
990 rc = ahci_host_init(probe_ent);
994 ahci_print_info(probe_ent);
996 linkmap = probe_ent->link_port_map;
998 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
999 if (((linkmap >> i) & 0x01)) {
1000 if (ahci_port_start((u8) i)) {
1001 printf("Can not start port %d\n", i);
1004 #ifdef CONFIG_AHCI_SETFEATURES_XFER
1005 ahci_set_feature((u8) i);
1013 void __weak scsi_init(void)
1020 * In the general case of generic rotating media it makes sense to have a
1021 * flush capability. It probably even makes sense in the case of SSDs because
1022 * one cannot always know for sure what kind of internal cache/flush mechanism
1023 * is embodied therein. At first it was planned to invoke this after the last
1024 * write to disk and before rebooting. In practice, knowing, a priori, which
1025 * is the last write is difficult. Because writing to the disk in u-boot is
1026 * very rare, this flush command will be invoked after every block write.
1028 static int ata_io_flush(u8 port)
1031 struct ahci_ioports *pp = &(probe_ent->port[port]);
1032 void __iomem *port_mmio = pp->port_mmio;
1033 u32 cmd_fis_len = 5; /* five dwords */
1035 /* Preset the FIS */
1037 fis[0] = 0x27; /* Host to device FIS. */
1038 fis[1] = 1 << 7; /* Command FIS. */
1039 fis[2] = ATA_CMD_FLUSH_EXT;
1041 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1042 ahci_fill_cmd_slot(pp, cmd_fis_len);
1043 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1045 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1046 WAIT_MS_FLUSH, 0x1)) {
1047 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1055 __weak void scsi_bus_reset(void)
1060 void scsi_print_error(ccb * pccb)
1062 /*The ahci error info can be read in the ahci driver*/