2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 * with the reference on libata and ahci drvier in kernel
14 #include <asm/processor.h>
15 #include <asm/errno.h>
20 #include <linux/ctype.h>
23 static int ata_io_flush(u8 port);
25 struct ahci_probe_ent *probe_ent = NULL;
26 u16 *ataid[AHCI_MAX_PORTS];
28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
31 * Some controllers limit number of blocks they can read/write at once.
32 * Contemporary SSD devices work much faster if the read/write size is aligned
33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
36 #ifndef MAX_SATA_BLOCKS_READ_WRITE
37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
40 /* Maximum timeouts for each event */
41 #define WAIT_MS_SPINUP 20000
42 #define WAIT_MS_DATAIO 5000
43 #define WAIT_MS_FLUSH 5000
44 #define WAIT_MS_LINKUP 200
46 static inline u32 ahci_port_base(u32 base, u32 port)
48 return base + 0x100 + (port * 0x80);
52 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
53 unsigned int port_idx)
55 base = ahci_port_base(base, port_idx);
57 port->cmd_addr = base;
58 port->scr_addr = base + PORT_SCR;
62 #define msleep(a) udelay(a * 1000)
64 static void ahci_dcache_flush_range(unsigned begin, unsigned len)
66 const unsigned long start = begin;
67 const unsigned long end = start + len;
69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
70 flush_dcache_range(start, end);
74 * SATA controller DMAs to physical RAM. Ensure data from the
75 * controller is invalidated from dcache; next access comes from
78 static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
80 const unsigned long start = begin;
81 const unsigned long end = start + len;
83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
84 invalidate_dcache_range(start, end);
88 * Ensure data for SATA controller is flushed out of dcache and
89 * written to physical memory.
91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
93 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
94 AHCI_PORT_PRIV_DMA_SZ);
97 static int waiting_for_cmd_completed(volatile u8 *offset,
104 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
107 return (i < timeout_msec) ? 0 : -1;
110 int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
114 u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
117 * Bring up SATA link.
118 * SATA link bringup time is usually less than 1 ms; only very
119 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
121 while (j < WAIT_MS_LINKUP) {
122 tmp = readl(port_mmio + PORT_SCR_STAT);
123 tmp &= PORT_SCR_STAT_DET_MASK;
124 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
132 #ifdef CONFIG_SUNXI_AHCI
133 /* The sunxi AHCI controller requires this undocumented setup */
134 static void sunxi_dma_init(volatile u8 *port_mmio)
136 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
140 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
142 #ifndef CONFIG_SCSI_AHCI_PLAT
143 pci_dev_t pdev = probe_ent->dev;
145 unsigned short vendor;
147 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
148 u32 tmp, cap_save, cmd;
150 volatile u8 *port_mmio;
153 debug("ahci_host_init: start\n");
155 cap_save = readl(mmio + HOST_CAP);
156 cap_save &= ((1 << 28) | (1 << 17));
157 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
159 /* global controller reset */
160 tmp = readl(mmio + HOST_CTL);
161 if ((tmp & HOST_RESET) == 0)
162 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
164 /* reset must complete within 1 second, or
165 * the hardware should be considered fried.
170 tmp = readl(mmio + HOST_CTL);
172 debug("controller reset failed (0x%x)\n", tmp);
175 } while (tmp & HOST_RESET);
177 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
178 writel(cap_save, mmio + HOST_CAP);
179 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
181 #ifndef CONFIG_SCSI_AHCI_PLAT
182 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
184 if (vendor == PCI_VENDOR_ID_INTEL) {
186 pci_read_config_word(pdev, 0x92, &tmp16);
188 pci_write_config_word(pdev, 0x92, tmp16);
191 probe_ent->cap = readl(mmio + HOST_CAP);
192 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
193 port_map = probe_ent->port_map;
194 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
196 debug("cap 0x%x port_map 0x%x n_ports %d\n",
197 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
199 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
200 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
202 for (i = 0; i < probe_ent->n_ports; i++) {
203 if (!(port_map & (1 << i)))
205 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
206 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
207 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
209 /* make sure port is not active */
210 tmp = readl(port_mmio + PORT_CMD);
211 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
212 PORT_CMD_FIS_RX | PORT_CMD_START)) {
213 debug("Port %d is active. Deactivating.\n", i);
214 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
215 PORT_CMD_FIS_RX | PORT_CMD_START);
216 writel_with_flush(tmp, port_mmio + PORT_CMD);
218 /* spec says 500 msecs for each bit, so
219 * this is slightly incorrect.
224 #ifdef CONFIG_SUNXI_AHCI
225 sunxi_dma_init(port_mmio);
228 /* Add the spinup command to whatever mode bits may
229 * already be on in the command register.
231 cmd = readl(port_mmio + PORT_CMD);
232 cmd |= PORT_CMD_SPIN_UP;
233 writel_with_flush(cmd, port_mmio + PORT_CMD);
235 /* Bring up SATA link. */
236 ret = ahci_link_up(probe_ent, i);
238 printf("SATA link %d timeout.\n", i);
241 debug("SATA link ok.\n");
244 /* Clear error status */
245 tmp = readl(port_mmio + PORT_SCR_ERR);
247 writel(tmp, port_mmio + PORT_SCR_ERR);
249 debug("Spinning up device on SATA port %d... ", i);
252 while (j < WAIT_MS_SPINUP) {
253 tmp = readl(port_mmio + PORT_TFDATA);
254 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
257 tmp = readl(port_mmio + PORT_SCR_STAT);
258 tmp &= PORT_SCR_STAT_DET_MASK;
259 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
264 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
265 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
266 debug("SATA link %d down (COMINIT received), retrying...\n", i);
271 printf("Target spinup took %d ms.\n", j);
272 if (j == WAIT_MS_SPINUP)
277 tmp = readl(port_mmio + PORT_SCR_ERR);
278 debug("PORT_SCR_ERR 0x%x\n", tmp);
279 writel(tmp, port_mmio + PORT_SCR_ERR);
281 /* ack any pending irq events for this port */
282 tmp = readl(port_mmio + PORT_IRQ_STAT);
283 debug("PORT_IRQ_STAT 0x%x\n", tmp);
285 writel(tmp, port_mmio + PORT_IRQ_STAT);
287 writel(1 << i, mmio + HOST_IRQ_STAT);
289 /* set irq mask (enables interrupts) */
290 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
292 /* register linkup ports */
293 tmp = readl(port_mmio + PORT_SCR_STAT);
294 debug("SATA port %d status: 0x%x\n", i, tmp);
295 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
296 probe_ent->link_port_map |= (0x01 << i);
299 tmp = readl(mmio + HOST_CTL);
300 debug("HOST_CTL 0x%x\n", tmp);
301 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
302 tmp = readl(mmio + HOST_CTL);
303 debug("HOST_CTL 0x%x\n", tmp);
304 #ifndef CONFIG_SCSI_AHCI_PLAT
305 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
306 tmp |= PCI_COMMAND_MASTER;
307 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
313 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
315 #ifndef CONFIG_SCSI_AHCI_PLAT
316 pci_dev_t pdev = probe_ent->dev;
319 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
320 u32 vers, cap, cap2, impl, speed;
324 vers = readl(mmio + HOST_VERSION);
325 cap = probe_ent->cap;
326 cap2 = readl(mmio + HOST_CAP2);
327 impl = probe_ent->port_map;
329 speed = (cap >> 20) & 0xf;
339 #ifdef CONFIG_SCSI_AHCI_PLAT
342 pci_read_config_word(pdev, 0x0a, &cc);
345 else if (cc == 0x0106)
347 else if (cc == 0x0104)
352 printf("AHCI %02x%02x.%02x%02x "
353 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
358 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
364 cap & (1 << 31) ? "64bit " : "",
365 cap & (1 << 30) ? "ncq " : "",
366 cap & (1 << 28) ? "ilck " : "",
367 cap & (1 << 27) ? "stag " : "",
368 cap & (1 << 26) ? "pm " : "",
369 cap & (1 << 25) ? "led " : "",
370 cap & (1 << 24) ? "clo " : "",
371 cap & (1 << 19) ? "nz " : "",
372 cap & (1 << 18) ? "only " : "",
373 cap & (1 << 17) ? "pmp " : "",
374 cap & (1 << 16) ? "fbss " : "",
375 cap & (1 << 15) ? "pio " : "",
376 cap & (1 << 14) ? "slum " : "",
377 cap & (1 << 13) ? "part " : "",
378 cap & (1 << 7) ? "ccc " : "",
379 cap & (1 << 6) ? "ems " : "",
380 cap & (1 << 5) ? "sxs " : "",
381 cap2 & (1 << 2) ? "apst " : "",
382 cap2 & (1 << 1) ? "nvmp " : "",
383 cap2 & (1 << 0) ? "boh " : "");
386 #ifndef CONFIG_SCSI_AHCI_PLAT
387 static int ahci_init_one(pci_dev_t pdev)
392 probe_ent = malloc(sizeof(struct ahci_probe_ent));
394 printf("%s: No memory for probe_ent\n", __func__);
398 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
399 probe_ent->dev = pdev;
401 probe_ent->host_flags = ATA_FLAG_SATA
406 probe_ent->pio_mask = 0x1f;
407 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
409 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
410 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
413 * JMicron-specific fixup:
414 * make sure we're in AHCI mode
416 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
417 if (vendor == 0x197b)
418 pci_write_config_byte(pdev, 0x41, 0xa1);
420 /* initialize adapter */
421 rc = ahci_host_init(probe_ent);
425 ahci_print_info(probe_ent);
434 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
436 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
438 struct ahci_ioports *pp = &(probe_ent->port[port]);
439 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
443 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
444 if (sg_count > AHCI_MAX_SG) {
445 printf("Error:Too much sg!\n");
449 for (i = 0; i < sg_count; i++) {
451 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
452 ahci_sg->addr_hi = 0;
453 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
454 (buf_len < MAX_DATA_BYTE_COUNT
456 : (MAX_DATA_BYTE_COUNT - 1)));
458 buf_len -= MAX_DATA_BYTE_COUNT;
465 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
467 pp->cmd_slot->opts = cpu_to_le32(opts);
468 pp->cmd_slot->status = 0;
469 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
470 pp->cmd_slot->tbl_addr_hi = 0;
474 #ifdef CONFIG_AHCI_SETFEATURES_XFER
475 static void ahci_set_feature(u8 port)
477 struct ahci_ioports *pp = &(probe_ent->port[port]);
478 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
479 u32 cmd_fis_len = 5; /* five dwords */
483 memset(fis, 0, sizeof(fis));
486 fis[2] = ATA_CMD_SET_FEATURES;
487 fis[3] = SETFEATURES_XFER;
488 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
490 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
491 ahci_fill_cmd_slot(pp, cmd_fis_len);
492 ahci_dcache_flush_sata_cmd(pp);
493 writel(1, port_mmio + PORT_CMD_ISSUE);
494 readl(port_mmio + PORT_CMD_ISSUE);
496 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
497 WAIT_MS_DATAIO, 0x1)) {
498 printf("set feature error on port %d!\n", port);
504 static int ahci_port_start(u8 port)
506 struct ahci_ioports *pp = &(probe_ent->port[port]);
507 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
511 debug("Enter start port: %d\n", port);
512 port_status = readl(port_mmio + PORT_SCR_STAT);
513 debug("Port %d status: %x\n", port, port_status);
514 if ((port_status & 0xf) != 0x03) {
515 printf("No Link on this port!\n");
519 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
522 printf("%s: No mem for table!\n", __func__);
526 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
527 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
530 * First item in chunk of DMA memory: 32-slot command table,
531 * 32 bytes each in size
534 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
535 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
536 mem += (AHCI_CMD_SLOT_SZ + 224);
539 * Second item: Received-FIS area
541 pp->rx_fis = virt_to_phys((void *)mem);
542 mem += AHCI_RX_FIS_SZ;
545 * Third item: data area for storing a single command
546 * and its scatter-gather table
548 pp->cmd_tbl = virt_to_phys((void *)mem);
549 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
551 mem += AHCI_CMD_TBL_HDR;
553 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
555 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
557 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
559 #ifdef CONFIG_SUNXI_AHCI
560 sunxi_dma_init(port_mmio);
563 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
564 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
565 PORT_CMD_START, port_mmio + PORT_CMD);
567 debug("Exit start port %d\n", port);
573 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
574 int buf_len, u8 is_write)
577 struct ahci_ioports *pp = &(probe_ent->port[port]);
578 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
583 debug("Enter %s: for port %d\n", __func__, port);
585 if (port > probe_ent->n_ports) {
586 printf("Invalid port number %d\n", port);
590 port_status = readl(port_mmio + PORT_SCR_STAT);
591 if ((port_status & 0xf) != 0x03) {
592 debug("No Link on port %d!\n", port);
596 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
598 sg_count = ahci_fill_sg(port, buf, buf_len);
599 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
600 ahci_fill_cmd_slot(pp, opts);
602 ahci_dcache_flush_sata_cmd(pp);
603 ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
605 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
607 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
608 WAIT_MS_DATAIO, 0x1)) {
609 printf("timeout exit!\n");
613 ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
614 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
620 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
623 for (i = 0; i < len / 2; i++)
624 target[i] = swab16(src[i]);
625 return (char *)target;
629 * SCSI INQUIRY command operation.
631 static int ata_scsiop_inquiry(ccb *pccb)
633 static const u8 hdr[] = {
636 0x5, /* claim SPC-3 version compatibility */
642 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
645 /* Clean ccb data buffer */
646 memset(pccb->pdata, 0, pccb->datalen);
648 memcpy(pccb->pdata, hdr, sizeof(hdr));
650 if (pccb->datalen <= 35)
653 memset(fis, 0, sizeof(fis));
654 /* Construct the FIS */
655 fis[0] = 0x27; /* Host to device FIS. */
656 fis[1] = 1 << 7; /* Command FIS. */
657 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
659 /* Read id from sata */
662 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
663 ATA_ID_WORDS * 2, 0)) {
664 debug("scsi_ahci: SCSI inquiry command failure.\n");
669 ataid[port] = malloc(ATA_ID_WORDS * 2);
671 printf("%s: No memory for ataid[port]\n", __func__);
678 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
679 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
681 memcpy(&pccb->pdata[8], "ATA ", 8);
682 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
683 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
693 * SCSI READ10/WRITE10 command operation.
695 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
700 u8 *user_buffer = pccb->pdata;
701 u32 user_buffer_size = pccb->datalen;
703 /* Retrieve the base LBA number from the ccb structure. */
704 memcpy(&lba, pccb->cmd + 2, sizeof(lba));
705 lba = be32_to_cpu(lba);
708 * And the number of blocks.
710 * For 10-byte and 16-byte SCSI R/W commands, transfer
711 * length 0 means transfer 0 block of data.
712 * However, for ATA R/W commands, sector count 0 means
713 * 256 or 65536 sectors, not 0 sectors as in SCSI.
715 * WARNING: one or two older ATA drives treat 0 as 0...
717 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
719 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
720 is_write ? "write" : "read", (unsigned)lba, blocks);
723 memset(fis, 0, sizeof(fis));
724 fis[0] = 0x27; /* Host to device FIS. */
725 fis[1] = 1 << 7; /* Command FIS. */
726 /* Command byte (read/write). */
727 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
730 u16 now_blocks; /* number of blocks per iteration */
731 u32 transfer_size; /* number of bytes per iteration */
733 now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
735 transfer_size = ATA_SECT_SIZE * now_blocks;
736 if (transfer_size > user_buffer_size) {
737 printf("scsi_ahci: Error: buffer too small.\n");
741 /* LBA48 SATA command but only use 32bit address range within
742 * that. The next smaller command range (28bit) is too small.
744 fis[4] = (lba >> 0) & 0xff;
745 fis[5] = (lba >> 8) & 0xff;
746 fis[6] = (lba >> 16) & 0xff;
747 fis[7] = 1 << 6; /* device reg: set LBA mode */
748 fis[8] = ((lba >> 24) & 0xff);
749 fis[3] = 0xe0; /* features */
751 /* Block (sector) count */
752 fis[12] = (now_blocks >> 0) & 0xff;
753 fis[13] = (now_blocks >> 8) & 0xff;
755 /* Read/Write from ahci */
756 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
757 user_buffer, user_buffer_size,
759 debug("scsi_ahci: SCSI %s10 command failure.\n",
760 is_write ? "WRITE" : "READ");
764 /* If this transaction is a write, do a following flush.
765 * Writes in u-boot are so rare, and the logic to know when is
766 * the last write and do a flush only there is sufficiently
767 * difficult. Just do a flush after every write. This incurs,
768 * usually, one extra flush when the rare writes do happen.
771 if (-EIO == ata_io_flush(pccb->target))
774 user_buffer += transfer_size;
775 user_buffer_size -= transfer_size;
776 blocks -= now_blocks;
785 * SCSI READ CAPACITY10 command operation.
787 static int ata_scsiop_read_capacity10(ccb *pccb)
793 if (!ataid[pccb->target]) {
794 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
796 "\tPlease run SCSI commmand INQUIRY firstly!\n");
800 cap64 = ata_id_n_sectors(ataid[pccb->target]);
801 if (cap64 > 0x100000000ULL)
804 cap = cpu_to_be32(cap64);
805 memcpy(pccb->pdata, &cap, sizeof(cap));
807 block_size = cpu_to_be32((u32)512);
808 memcpy(&pccb->pdata[4], &block_size, 4);
815 * SCSI READ CAPACITY16 command operation.
817 static int ata_scsiop_read_capacity16(ccb *pccb)
822 if (!ataid[pccb->target]) {
823 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
825 "\tPlease run SCSI commmand INQUIRY firstly!\n");
829 cap = ata_id_n_sectors(ataid[pccb->target]);
830 cap = cpu_to_be64(cap);
831 memcpy(pccb->pdata, &cap, sizeof(cap));
833 block_size = cpu_to_be64((u64)512);
834 memcpy(&pccb->pdata[8], &block_size, 8);
841 * SCSI TEST UNIT READY command operation.
843 static int ata_scsiop_test_unit_ready(ccb *pccb)
845 return (ataid[pccb->target]) ? 0 : -EPERM;
849 int scsi_exec(ccb *pccb)
853 switch (pccb->cmd[0]) {
855 ret = ata_scsiop_read_write(pccb, 0);
858 ret = ata_scsiop_read_write(pccb, 1);
860 case SCSI_RD_CAPAC10:
861 ret = ata_scsiop_read_capacity10(pccb);
863 case SCSI_RD_CAPAC16:
864 ret = ata_scsiop_read_capacity16(pccb);
867 ret = ata_scsiop_test_unit_ready(pccb);
870 ret = ata_scsiop_inquiry(pccb);
873 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
878 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
886 void scsi_low_level_init(int busdevfunc)
891 #ifndef CONFIG_SCSI_AHCI_PLAT
892 ahci_init_one(busdevfunc);
895 linkmap = probe_ent->link_port_map;
897 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
898 if (((linkmap >> i) & 0x01)) {
899 if (ahci_port_start((u8) i)) {
900 printf("Can not start port %d\n", i);
903 #ifdef CONFIG_AHCI_SETFEATURES_XFER
904 ahci_set_feature((u8) i);
910 #ifdef CONFIG_SCSI_AHCI_PLAT
911 int ahci_init(u32 base)
916 probe_ent = malloc(sizeof(struct ahci_probe_ent));
918 printf("%s: No memory for probe_ent\n", __func__);
922 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
924 probe_ent->host_flags = ATA_FLAG_SATA
929 probe_ent->pio_mask = 0x1f;
930 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
932 probe_ent->mmio_base = base;
934 /* initialize adapter */
935 rc = ahci_host_init(probe_ent);
939 ahci_print_info(probe_ent);
941 linkmap = probe_ent->link_port_map;
943 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
944 if (((linkmap >> i) & 0x01)) {
945 if (ahci_port_start((u8) i)) {
946 printf("Can not start port %d\n", i);
949 #ifdef CONFIG_AHCI_SETFEATURES_XFER
950 ahci_set_feature((u8) i);
958 void __weak scsi_init(void)
965 * In the general case of generic rotating media it makes sense to have a
966 * flush capability. It probably even makes sense in the case of SSDs because
967 * one cannot always know for sure what kind of internal cache/flush mechanism
968 * is embodied therein. At first it was planned to invoke this after the last
969 * write to disk and before rebooting. In practice, knowing, a priori, which
970 * is the last write is difficult. Because writing to the disk in u-boot is
971 * very rare, this flush command will be invoked after every block write.
973 static int ata_io_flush(u8 port)
976 struct ahci_ioports *pp = &(probe_ent->port[port]);
977 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
978 u32 cmd_fis_len = 5; /* five dwords */
982 fis[0] = 0x27; /* Host to device FIS. */
983 fis[1] = 1 << 7; /* Command FIS. */
984 fis[2] = ATA_CMD_FLUSH_EXT;
986 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
987 ahci_fill_cmd_slot(pp, cmd_fis_len);
988 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
990 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
991 WAIT_MS_FLUSH, 0x1)) {
992 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1000 void scsi_bus_reset(void)
1006 void scsi_print_error(ccb * pccb)
1008 /*The ahci error info can be read in the ahci driver*/