2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * with the reference on libata and ahci drvier in kernel
31 #include <asm/processor.h>
32 #include <asm/errno.h>
37 #include <linux/ctype.h>
40 struct ahci_probe_ent *probe_ent = NULL;
41 hd_driveid_t *ataid[AHCI_MAX_PORTS];
43 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
46 static inline u32 ahci_port_base(u32 base, u32 port)
48 return base + 0x100 + (port * 0x80);
52 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
53 unsigned int port_idx)
55 base = ahci_port_base(base, port_idx);
57 port->cmd_addr = base;
58 port->scr_addr = base + PORT_SCR;
62 #define msleep(a) udelay(a * 1000)
63 #define ssleep(a) msleep(a * 1000)
65 static int waiting_for_cmd_completed(volatile u8 *offset,
72 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
75 return (i < timeout_msec) ? 0 : -1;
79 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
81 pci_dev_t pdev = probe_ent->dev;
82 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
86 volatile u8 *port_mmio;
87 unsigned short vendor;
89 cap_save = readl(mmio + HOST_CAP);
90 cap_save &= ((1 << 28) | (1 << 17));
91 cap_save |= (1 << 27);
93 /* global controller reset */
94 tmp = readl(mmio + HOST_CTL);
95 if ((tmp & HOST_RESET) == 0)
96 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
98 /* reset must complete within 1 second, or
99 * the hardware should be considered fried.
103 tmp = readl(mmio + HOST_CTL);
104 if (tmp & HOST_RESET) {
105 debug("controller reset failed (0x%x)\n", tmp);
109 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
110 writel(cap_save, mmio + HOST_CAP);
111 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
113 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
115 if (vendor == PCI_VENDOR_ID_INTEL) {
117 pci_read_config_word(pdev, 0x92, &tmp16);
119 pci_write_config_word(pdev, 0x92, tmp16);
122 probe_ent->cap = readl(mmio + HOST_CAP);
123 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
124 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
126 debug("cap 0x%x port_map 0x%x n_ports %d\n",
127 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
129 for (i = 0; i < probe_ent->n_ports; i++) {
130 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
131 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
132 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
134 /* make sure port is not active */
135 tmp = readl(port_mmio + PORT_CMD);
136 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
137 PORT_CMD_FIS_RX | PORT_CMD_START)) {
138 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
139 PORT_CMD_FIS_RX | PORT_CMD_START);
140 writel_with_flush(tmp, port_mmio + PORT_CMD);
142 /* spec says 500 msecs for each bit, so
143 * this is slightly incorrect.
148 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
153 tmp = readl(port_mmio + PORT_SCR_STAT);
154 if ((tmp & 0xf) == 0x3)
159 tmp = readl(port_mmio + PORT_SCR_ERR);
160 debug("PORT_SCR_ERR 0x%x\n", tmp);
161 writel(tmp, port_mmio + PORT_SCR_ERR);
163 /* ack any pending irq events for this port */
164 tmp = readl(port_mmio + PORT_IRQ_STAT);
165 debug("PORT_IRQ_STAT 0x%x\n", tmp);
167 writel(tmp, port_mmio + PORT_IRQ_STAT);
169 writel(1 << i, mmio + HOST_IRQ_STAT);
171 /* set irq mask (enables interrupts) */
172 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
174 /*register linkup ports */
175 tmp = readl(port_mmio + PORT_SCR_STAT);
176 debug("Port %d status: 0x%x\n", i, tmp);
177 if ((tmp & 0xf) == 0x03)
178 probe_ent->link_port_map |= (0x01 << i);
181 tmp = readl(mmio + HOST_CTL);
182 debug("HOST_CTL 0x%x\n", tmp);
183 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
184 tmp = readl(mmio + HOST_CTL);
185 debug("HOST_CTL 0x%x\n", tmp);
187 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
188 tmp |= PCI_COMMAND_MASTER;
189 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
195 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
197 pci_dev_t pdev = probe_ent->dev;
198 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
199 u32 vers, cap, impl, speed;
204 vers = readl(mmio + HOST_VERSION);
205 cap = probe_ent->cap;
206 impl = probe_ent->port_map;
208 speed = (cap >> 20) & 0xf;
216 pci_read_config_word(pdev, 0x0a, &cc);
219 else if (cc == 0x0106)
221 else if (cc == 0x0104)
226 printf("AHCI %02x%02x.%02x%02x "
227 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
232 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
237 cap & (1 << 31) ? "64bit " : "",
238 cap & (1 << 30) ? "ncq " : "",
239 cap & (1 << 28) ? "ilck " : "",
240 cap & (1 << 27) ? "stag " : "",
241 cap & (1 << 26) ? "pm " : "",
242 cap & (1 << 25) ? "led " : "",
243 cap & (1 << 24) ? "clo " : "",
244 cap & (1 << 19) ? "nz " : "",
245 cap & (1 << 18) ? "only " : "",
246 cap & (1 << 17) ? "pmp " : "",
247 cap & (1 << 15) ? "pio " : "",
248 cap & (1 << 14) ? "slum " : "",
249 cap & (1 << 13) ? "part " : "");
252 static int ahci_init_one(pci_dev_t pdev)
258 memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
260 probe_ent = malloc(sizeof(struct ahci_probe_ent));
261 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
262 probe_ent->dev = pdev;
264 pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase);
267 probe_ent->host_flags = ATA_FLAG_SATA
272 probe_ent->pio_mask = 0x1f;
273 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
275 probe_ent->mmio_base = iobase;
278 * JMicron-specific fixup:
279 * make sure we're in AHCI mode
281 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
282 if (vendor == 0x197b)
283 pci_write_config_byte(pdev, 0x41, 0xa1);
285 /* initialize adapter */
286 rc = ahci_host_init(probe_ent);
290 ahci_print_info(probe_ent);
299 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
301 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
303 struct ahci_ioports *pp = &(probe_ent->port[port]);
304 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
308 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
309 if (sg_count > AHCI_MAX_SG) {
310 printf("Error:Too much sg!\n");
314 for (i = 0; i < sg_count; i++) {
316 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
317 ahci_sg->addr_hi = 0;
318 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
319 (buf_len < MAX_DATA_BYTE_COUNT
321 : (MAX_DATA_BYTE_COUNT - 1)));
323 buf_len -= MAX_DATA_BYTE_COUNT;
330 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
332 pp->cmd_slot->opts = cpu_to_le32(opts);
333 pp->cmd_slot->status = 0;
334 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
335 pp->cmd_slot->tbl_addr_hi = 0;
339 static void ahci_set_feature(u8 port)
341 struct ahci_ioports *pp = &(probe_ent->port[port]);
342 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
343 u32 cmd_fis_len = 5; /* five dwords */
350 fis[2] = ATA_CMD_SETF;
351 fis[3] = SETFEATURES_XFER;
352 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
354 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
355 ahci_fill_cmd_slot(pp, cmd_fis_len);
356 writel(1, port_mmio + PORT_CMD_ISSUE);
357 readl(port_mmio + PORT_CMD_ISSUE);
359 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
360 printf("set feature error!\n");
365 static int ahci_port_start(u8 port)
367 struct ahci_ioports *pp = &(probe_ent->port[port]);
368 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
372 debug("Enter start port: %d\n", port);
373 port_status = readl(port_mmio + PORT_SCR_STAT);
374 debug("Port %d status: %x\n", port, port_status);
375 if ((port_status & 0xf) != 0x03) {
376 printf("No Link on this port!\n");
380 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
383 printf("No mem for table!\n");
387 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
388 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
391 * First item in chunk of DMA memory: 32-slot command table,
392 * 32 bytes each in size
394 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
395 debug("cmd_slot = 0x%x\n", pp->cmd_slot);
396 mem += (AHCI_CMD_SLOT_SZ + 224);
399 * Second item: Received-FIS area
402 mem += AHCI_RX_FIS_SZ;
405 * Third item: data area for storing a single command
406 * and its scatter-gather table
409 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
411 mem += AHCI_CMD_TBL_HDR;
412 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
414 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
416 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
418 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
419 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
420 PORT_CMD_START, port_mmio + PORT_CMD);
422 debug("Exit start port %d\n", port);
428 static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
432 struct ahci_ioports *pp = &(probe_ent->port[port]);
433 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
438 debug("Enter get_ahci_device_data: for port %d\n", port);
440 if (port > probe_ent->n_ports) {
441 printf("Invaild port number %d\n", port);
445 port_status = readl(port_mmio + PORT_SCR_STAT);
446 if ((port_status & 0xf) != 0x03) {
447 debug("No Link on port %d!\n", port);
451 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
453 sg_count = ahci_fill_sg(port, buf, buf_len);
454 opts = (fis_len >> 2) | (sg_count << 16);
455 ahci_fill_cmd_slot(pp, opts);
457 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
459 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
460 printf("timeout exit!\n");
463 debug("get_ahci_device_data: %d byte transferred.\n",
464 pp->cmd_slot->status);
470 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
473 for (i = 0; i < len / 2; i++)
474 target[i] = le16_to_cpu(src[i]);
475 return (char *)target;
479 static void dump_ataid(hd_driveid_t *ataid)
481 debug("(49)ataid->capability = 0x%x\n", ataid->capability);
482 debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
483 debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
484 debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
485 debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
486 debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
487 debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
488 debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
489 debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
490 debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
491 debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
492 debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
493 debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
494 debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
495 debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
500 * SCSI INQUIRY command operation.
502 static int ata_scsiop_inquiry(ccb *pccb)
507 0x5, /* claim SPC-3 version compatibility */
515 /* Clean ccb data buffer */
516 memset(pccb->pdata, 0, pccb->datalen);
518 memcpy(pccb->pdata, hdr, sizeof(hdr));
520 if (pccb->datalen <= 35)
524 /* Construct the FIS */
525 fis[0] = 0x27; /* Host to device FIS. */
526 fis[1] = 1 << 7; /* Command FIS. */
527 fis[2] = ATA_CMD_IDENT; /* Command byte. */
529 /* Read id from sata */
531 if (!(tmpid = malloc(sizeof(hd_driveid_t))))
534 if (get_ahci_device_data(port, (u8 *) & fis, 20,
535 tmpid, sizeof(hd_driveid_t))) {
536 debug("scsi_ahci: SCSI inquiry command failure.\n");
542 ataid[port] = (hd_driveid_t *) tmpid;
544 memcpy(&pccb->pdata[8], "ATA ", 8);
545 ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
546 ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
548 dump_ataid(ataid[port]);
554 * SCSI READ10 command operation.
556 static int ata_scsiop_read10(ccb * pccb)
562 lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16)
563 | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]);
564 len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]);
566 /* For 10-byte and 16-byte SCSI R/W commands, transfer
567 * length 0 means transfer 0 block of data.
568 * However, for ATA R/W commands, sector count 0 means
569 * 256 or 65536 sectors, not 0 sectors as in SCSI.
571 * WARNING: one or two older ATA drives treat 0 as 0...
577 /* Construct the FIS */
578 fis[0] = 0x27; /* Host to device FIS. */
579 fis[1] = 1 << 7; /* Command FIS. */
580 fis[2] = ATA_CMD_RD_DMA; /* Command byte. */
582 /* LBA address, only support LBA28 in this driver */
583 fis[4] = pccb->cmd[5];
584 fis[5] = pccb->cmd[4];
585 fis[6] = pccb->cmd[3];
586 fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0;
589 fis[12] = pccb->cmd[8];
590 fis[13] = pccb->cmd[7];
593 if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20,
594 pccb->pdata, pccb->datalen)) {
595 debug("scsi_ahci: SCSI READ10 command failure.\n");
604 * SCSI READ CAPACITY10 command operation.
606 static int ata_scsiop_read_capacity10(ccb *pccb)
610 if (!ataid[pccb->target]) {
611 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
613 "\tPlease run SCSI commmand INQUIRY firstly!\n");
619 *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity);
624 memcpy(pccb->pdata, buf, 8);
631 * SCSI TEST UNIT READY command operation.
633 static int ata_scsiop_test_unit_ready(ccb *pccb)
635 return (ataid[pccb->target]) ? 0 : -EPERM;
639 int scsi_exec(ccb *pccb)
643 switch (pccb->cmd[0]) {
645 ret = ata_scsiop_read10(pccb);
648 ret = ata_scsiop_read_capacity10(pccb);
651 ret = ata_scsiop_test_unit_ready(pccb);
654 ret = ata_scsiop_inquiry(pccb);
657 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
662 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
670 void scsi_low_level_init(int busdevfunc)
675 ahci_init_one(busdevfunc);
677 linkmap = probe_ent->link_port_map;
679 for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) {
680 if (((linkmap >> i) & 0x01)) {
681 if (ahci_port_start((u8) i)) {
682 printf("Can not start port %d\n", i);
685 ahci_set_feature((u8) i);
691 void scsi_bus_reset(void)
697 void scsi_print_error(ccb * pccb)
699 /*The ahci error info can be read in the ahci driver*/