2 * Copyright (C) 2008,2010 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
25 #include <asm/fsl_serdes.h>
31 extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
33 #ifndef CONFIG_SYS_SATA1_FLAGS
34 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
36 #ifndef CONFIG_SYS_SATA2_FLAGS
37 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
40 static struct fsl_sata_info fsl_sata_info[] = {
42 {CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS},
47 {CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS},
53 static inline void sdelay(unsigned long sec)
56 for (i = 0; i < sec; i++)
60 void dprint_buffer(unsigned char *buf, int len)
68 for (i = 0; i < len; i++) {
69 printf("%02x ", *buf++);
79 static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
81 printf("Status FIS dump:\n\r");
82 printf("fis_type: %02x\n\r", s->fis_type);
83 printf("pm_port_i: %02x\n\r", s->pm_port_i);
84 printf("status: %02x\n\r", s->status);
85 printf("error: %02x\n\r", s->error);
86 printf("lba_low: %02x\n\r", s->lba_low);
87 printf("lba_mid: %02x\n\r", s->lba_mid);
88 printf("lba_high: %02x\n\r", s->lba_high);
89 printf("device: %02x\n\r", s->device);
90 printf("lba_low_exp: %02x\n\r", s->lba_low_exp);
91 printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp);
92 printf("lba_high_exp: %02x\n\r", s->lba_high_exp);
93 printf("res1: %02x\n\r", s->res1);
94 printf("sector_count: %02x\n\r", s->sector_count);
95 printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
98 static int ata_wait_register(volatile unsigned *addr, u32 mask,
99 u32 val, u32 timeout_msec)
104 for (i = 0; (((temp = in_le32(addr)) & mask) != val)
105 && i < timeout_msec; i++)
107 return (i < timeout_msec) ? 0 : -1;
110 int init_sata(int dev)
113 cmd_hdr_tbl_t *cmd_hdr;
121 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
122 printf("the sata index %d is out of ranges\n\r", dev);
126 #ifdef CONFIG_MPC85xx
127 if ((dev == 0) && (!is_serdes_configured(SATA1))) {
128 printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
131 if ((dev == 1) && (!is_serdes_configured(SATA2))) {
132 printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
137 /* Allocate SATA device driver struct */
138 sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
140 printf("alloc the sata device struct failed\n\r");
143 /* Zero all of the device driver struct */
144 memset((void *)sata, 0, sizeof(fsl_sata_t));
146 /* Save the private struct to block device struct */
147 sata_dev_desc[dev].priv = (void *)sata;
149 sprintf(sata->name, "SATA%d", dev);
151 /* Set the controller register base address to device struct */
152 reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
153 sata->reg_base = reg;
155 /* Allocate the command header table, 4 bytes aligned */
156 length = sizeof(struct cmd_hdr_tbl);
157 align = SATA_HC_CMD_HDR_TBL_ALIGN;
158 sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
160 printf("alloc the command header failed\n\r");
164 cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
166 sata->cmd_hdr = cmd_hdr;
168 /* Zero all of the command header table */
169 memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
171 /* Allocate command descriptor for all command */
172 length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
173 align = SATA_HC_CMD_DESC_ALIGN;
174 sata->cmd_desc_offset = (void *)malloc(length + align);
175 if (!sata->cmd_desc_offset) {
176 printf("alloc the command descriptor failed\n\r");
179 sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
181 /* Zero all of command descriptor */
182 memset((void *)sata->cmd_desc_offset, 0, length + align);
184 /* Link the command descriptor to command header */
185 for (i = 0; i < SATA_HC_MAX_CMD; i++) {
186 cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
187 & ~(CMD_HDR_CDA_ALIGN - 1);
188 cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
191 /* To have safe state, force the controller offline */
192 val32 = in_le32(®->hcontrol);
193 val32 &= ~HCONTROL_ONOFF;
194 val32 |= HCONTROL_FORCE_OFFLINE;
195 out_le32(®->hcontrol, val32);
197 /* Wait the controller offline */
198 ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000);
200 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
202 * For P1022/1013 Rev1.0 silicon, after power on SATA host
203 * controller is configured in legacy mode instead of the
204 * expected enterprise mode. software needs to clear bit[28]
205 * of HControl register to change to enterprise mode from
210 if (IS_SVR_REV(svr, 1, 0) &&
211 ((SVR_SOC_VER(svr) == SVR_P1022) ||
212 (SVR_SOC_VER(svr) == SVR_P1022_E) ||
213 (SVR_SOC_VER(svr) == SVR_P1013) ||
214 (SVR_SOC_VER(svr) == SVR_P1013_E))) {
215 out_le32(®->hstatus, 0x20000000);
216 out_le32(®->hcontrol, 0x00000100);
221 /* Set the command header base address to CHBA register to tell DMA */
222 out_le32(®->chba, (u32)cmd_hdr & ~0x3);
224 /* Snoop for the command header */
225 val32 = in_le32(®->hcontrol);
226 val32 |= HCONTROL_HDR_SNOOP;
227 out_le32(®->hcontrol, val32);
229 /* Disable all of interrupts */
230 val32 = in_le32(®->hcontrol);
231 val32 &= ~HCONTROL_INT_EN_ALL;
232 out_le32(®->hcontrol, val32);
234 /* Clear all of interrupts */
235 val32 = in_le32(®->hstatus);
236 out_le32(®->hstatus, val32);
238 /* Set the ICC, no interrupt coalescing */
239 out_le32(®->icc, 0x01000000);
241 /* No PM attatched, the SATA device direct connect */
242 out_le32(®->cqpmp, 0);
244 /* Clear SError register */
245 val32 = in_le32(®->serror);
246 out_le32(®->serror, val32);
248 /* Clear CER register */
249 val32 = in_le32(®->cer);
250 out_le32(®->cer, val32);
252 /* Clear DER register */
253 val32 = in_le32(®->der);
254 out_le32(®->der, val32);
256 /* No device detection or initialization action requested */
257 out_le32(®->scontrol, 0x00000300);
259 /* Configure the transport layer, default value */
260 out_le32(®->transcfg, 0x08000016);
262 /* Configure the link layer, default value */
263 out_le32(®->linkcfg, 0x0000ff34);
265 /* Bring the controller online */
266 val32 = in_le32(®->hcontrol);
267 val32 |= HCONTROL_ONOFF;
268 out_le32(®->hcontrol, val32);
272 /* print sata device name */
274 printf("%s ", sata->name);
276 printf(" %s ", sata->name);
278 /* Wait PHY RDY signal changed for 500ms */
279 ata_wait_register(®->hstatus, HSTATUS_PHY_RDY,
280 HSTATUS_PHY_RDY, 500);
283 val32 = in_le32(®->hstatus);
284 if (val32 & HSTATUS_PHY_RDY) {
288 printf("(No RDY)\n\r");
292 /* Wait for signature updated, which is 1st D2H */
293 ata_wait_register(®->hstatus, HSTATUS_SIGNATURE,
294 HSTATUS_SIGNATURE, 10000);
296 if (val32 & HSTATUS_SIGNATURE) {
297 sig = in_le32(®->sig);
298 debug("Signature updated, the sig =%08x\n\r", sig);
299 sata->ata_device_type = ata_dev_classify(sig);
302 /* Check the speed */
303 val32 = in_le32(®->sstatus);
304 if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
305 printf("(1.5 Gbps)\n\r");
306 else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
307 printf("(3 Gbps)\n\r");
312 /* Hardware reset, like Power-on and COMRESET */
313 void fsl_sata_hardware_reset(u32 reg_base)
315 fsl_sata_reg_t *reg = (fsl_sata_reg_t *)reg_base;
318 /* Disable the SATA interface and put PHY offline */
319 scontrol = in_le32(®->scontrol);
320 scontrol = (scontrol & 0x0f0) | 0x304;
321 out_le32(®->scontrol, scontrol);
323 /* No speed strict */
324 scontrol = in_le32(®->scontrol);
325 scontrol = scontrol & ~0x0f0;
326 out_le32(®->scontrol, scontrol);
328 /* Issue PHY wake/reset, Hardware_reset_asserted */
329 scontrol = in_le32(®->scontrol);
330 scontrol = (scontrol & 0x0f0) | 0x301;
331 out_le32(®->scontrol, scontrol);
335 /* Resume PHY, COMRESET negated, the device initialize hardware
336 * and execute diagnostics, send good status-signature to host,
337 * which is D2H register FIS, and then the device enter idle state.
339 scontrol = in_le32(®->scontrol);
340 scontrol = (scontrol & 0x0f0) | 0x300;
341 out_le32(®->scontrol, scontrol);
347 static void fsl_sata_dump_regs(fsl_sata_reg_t *reg)
349 printf("\n\rSATA: %08x\n\r", (u32)reg);
350 printf("CQR: %08x\n\r", in_le32(®->cqr));
351 printf("CAR: %08x\n\r", in_le32(®->car));
352 printf("CCR: %08x\n\r", in_le32(®->ccr));
353 printf("CER: %08x\n\r", in_le32(®->cer));
354 printf("CQR: %08x\n\r", in_le32(®->cqr));
355 printf("DER: %08x\n\r", in_le32(®->der));
356 printf("CHBA: %08x\n\r", in_le32(®->chba));
357 printf("HStatus: %08x\n\r", in_le32(®->hstatus));
358 printf("HControl: %08x\n\r", in_le32(®->hcontrol));
359 printf("CQPMP: %08x\n\r", in_le32(®->cqpmp));
360 printf("SIG: %08x\n\r", in_le32(®->sig));
361 printf("ICC: %08x\n\r", in_le32(®->icc));
362 printf("SStatus: %08x\n\r", in_le32(®->sstatus));
363 printf("SError: %08x\n\r", in_le32(®->serror));
364 printf("SControl: %08x\n\r", in_le32(®->scontrol));
365 printf("SNotification: %08x\n\r", in_le32(®->snotification));
366 printf("TransCfg: %08x\n\r", in_le32(®->transcfg));
367 printf("TransStatus: %08x\n\r", in_le32(®->transstatus));
368 printf("LinkCfg: %08x\n\r", in_le32(®->linkcfg));
369 printf("LinkCfg1: %08x\n\r", in_le32(®->linkcfg1));
370 printf("LinkCfg2: %08x\n\r", in_le32(®->linkcfg2));
371 printf("LinkStatus: %08x\n\r", in_le32(®->linkstatus));
372 printf("LinkStatus1: %08x\n\r", in_le32(®->linkstatus1));
373 printf("PhyCtrlCfg: %08x\n\r", in_le32(®->phyctrlcfg));
374 printf("SYSPR: %08x\n\r", in_be32(®->syspr));
377 static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
378 int is_ncq, int tag, u8 *buffer, u32 len)
380 cmd_hdr_entry_t *cmd_hdr;
381 cmd_desc_t *cmd_desc;
388 fsl_sata_reg_t *reg = sata->reg_base;
391 /* Check xfer length */
392 if (len > SATA_HC_MAX_XFER_LEN) {
393 printf("max transfer length is 64MB\n\r");
397 /* Setup the command descriptor */
398 cmd_desc = sata->cmd_desc + tag;
400 /* Get the pointer cfis of command descriptor */
401 h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
403 /* Zero the cfis of command descriptor */
404 memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
406 /* Copy the cfis from user to command descriptor */
407 h2d->fis_type = cfis->fis_type;
408 h2d->pm_port_c = cfis->pm_port_c;
409 h2d->command = cfis->command;
411 h2d->features = cfis->features;
412 h2d->features_exp = cfis->features_exp;
414 h2d->lba_low = cfis->lba_low;
415 h2d->lba_mid = cfis->lba_mid;
416 h2d->lba_high = cfis->lba_high;
417 h2d->lba_low_exp = cfis->lba_low_exp;
418 h2d->lba_mid_exp = cfis->lba_mid_exp;
419 h2d->lba_high_exp = cfis->lba_high_exp;
422 h2d->sector_count = cfis->sector_count;
423 h2d->sector_count_exp = cfis->sector_count_exp;
425 h2d->sector_count = (u8)(tag << 3);
428 h2d->device = cfis->device;
429 h2d->control = cfis->control;
431 /* Setup the PRD table */
432 prde = (prd_entry_t *)cmd_desc->prdt;
433 memset((void *)prde, 0, sizeof(struct prdt));
437 for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
440 prde->dba = cpu_to_le32((u32)buffer & ~0x3);
441 debug("dba = %08x\n\r", (u32)buffer);
443 if (len < PRD_ENTRY_MAX_XFER_SZ) {
444 ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
445 debug("ext_c_ddc1 = %08x, len = %08x\n\r", ext_c_ddc, len);
446 prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
451 ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
452 debug("ext_c_ddc2 = %08x, len = %08x\n\r", ext_c_ddc, len);
453 prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
454 buffer += PRD_ENTRY_MAX_XFER_SZ;
455 len -= PRD_ENTRY_MAX_XFER_SZ;
461 /* Setup the command slot of cmd hdr */
462 cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
464 cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
466 val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
467 val32 |= sizeof(sata_fis_h2d_t);
468 cmd_hdr->prde_fis_len = cpu_to_le32(val32);
470 cmd_hdr->ttl = cpu_to_le32(ttl);
473 val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
475 val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP | CMD_HDR_ATTR_FPDMA;
478 tag &= CMD_HDR_ATTR_TAG;
481 debug("attribute = %08x\n\r", val32);
482 cmd_hdr->attribute = cpu_to_le32(val32);
484 /* Make sure cmd desc and cmd slot valid before commmand issue */
488 val32 = (u32)(h2d->pm_port_c & 0x0f);
489 out_le32(®->cqpmp, val32);
492 if (ata_wait_register(®->car, (1 << tag), 0, 10000))
493 printf("Wait no active time out\n\r");
496 if (!(in_le32(®->cqr) & (1 << tag))) {
498 out_le32(®->cqr, val32);
501 /* Wait command completed for 10s */
502 if (ata_wait_register(®->ccr, (1 << tag), (1 << tag), 10000)) {
504 printf("Non-NCQ command time out\n\r");
506 printf("NCQ command time out\n\r");
509 val32 = in_le32(®->cer);
513 fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
514 printf("CE at device\n\r");
515 fsl_sata_dump_regs(reg);
516 der = in_le32(®->der);
517 out_le32(®->cer, val32);
518 out_le32(®->der, der);
521 /* Clear complete flags */
522 val32 = in_le32(®->ccr);
523 out_le32(®->ccr, val32);
528 static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
529 int tag, u8 *buffer, u32 len)
534 static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
535 enum cmd_type command_type, int tag, u8 *buffer, u32 len)
539 if (tag > SATA_HC_MAX_CMD || tag < 0) {
540 printf("tag is out of range, tag=%d\n\r", tag);
544 switch (command_type) {
546 rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
549 rc = fsl_ata_exec_reset_cmd(sata, cfis, tag, buffer, len);
552 rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
555 case CMD_VENDOR_BIST:
557 printf("not support now\n\r");
566 static void fsl_sata_identify(int dev, u16 *id)
568 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
569 struct sata_fis_h2d h2d, *cfis = &h2d;
571 memset(cfis, 0, sizeof(struct sata_fis_h2d));
573 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
574 cfis->pm_port_c = 0x80; /* is command */
575 cfis->command = ATA_CMD_ID_ATA;
577 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
578 ata_swap_buf_le16(id, ATA_ID_WORDS);
581 static void fsl_sata_xfer_mode(int dev, u16 *id)
583 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
585 sata->pio = id[ATA_ID_PIO_MODES];
586 sata->mwdma = id[ATA_ID_MWDMA_MODES];
587 sata->udma = id[ATA_ID_UDMA_MODES];
588 debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio, sata->mwdma, sata->udma);
591 static void fsl_sata_set_features(int dev)
593 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
594 struct sata_fis_h2d h2d, *cfis = &h2d;
597 memset(cfis, 0, sizeof(struct sata_fis_h2d));
599 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
600 cfis->pm_port_c = 0x80; /* is command */
601 cfis->command = ATA_CMD_SET_FEATURES;
602 cfis->features = SETFEATURES_XFER;
604 /* First check the device capablity */
605 udma_cap = (u8)(sata->udma & 0xff);
606 debug("udma_cap %02x\n\r", udma_cap);
608 if (udma_cap == ATA_UDMA6)
609 cfis->sector_count = XFER_UDMA_6;
610 if (udma_cap == ATA_UDMA5)
611 cfis->sector_count = XFER_UDMA_5;
612 if (udma_cap == ATA_UDMA4)
613 cfis->sector_count = XFER_UDMA_4;
614 if (udma_cap == ATA_UDMA3)
615 cfis->sector_count = XFER_UDMA_3;
617 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
620 static u32 fsl_sata_rw_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
622 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
623 struct sata_fis_h2d h2d, *cfis = &h2d;
628 memset(cfis, 0, sizeof(struct sata_fis_h2d));
630 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
631 cfis->pm_port_c = 0x80; /* is command */
632 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
633 cfis->device = ATA_LBA;
635 cfis->device |= (block >> 24) & 0xf;
636 cfis->lba_high = (block >> 16) & 0xff;
637 cfis->lba_mid = (block >> 8) & 0xff;
638 cfis->lba_low = block & 0xff;
639 cfis->sector_count = (u8)(blkcnt & 0xff);
641 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
645 void fsl_sata_flush_cache(int dev)
647 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
648 struct sata_fis_h2d h2d, *cfis = &h2d;
650 memset(cfis, 0, sizeof(struct sata_fis_h2d));
652 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
653 cfis->pm_port_c = 0x80; /* is command */
654 cfis->command = ATA_CMD_FLUSH;
656 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
659 static u32 fsl_sata_rw_cmd_ext(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
661 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
662 struct sata_fis_h2d h2d, *cfis = &h2d;
667 memset(cfis, 0, sizeof(struct sata_fis_h2d));
669 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
670 cfis->pm_port_c = 0x80; /* is command */
672 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
675 cfis->lba_high_exp = (block >> 40) & 0xff;
676 cfis->lba_mid_exp = (block >> 32) & 0xff;
677 cfis->lba_low_exp = (block >> 24) & 0xff;
678 cfis->lba_high = (block >> 16) & 0xff;
679 cfis->lba_mid = (block >> 8) & 0xff;
680 cfis->lba_low = block & 0xff;
681 cfis->device = ATA_LBA;
682 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
683 cfis->sector_count = blkcnt & 0xff;
685 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
689 u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
691 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
692 struct sata_fis_h2d h2d, *cfis = &h2d;
696 if (sata->lba48 != 1) {
697 printf("execute FPDMA command on non-LBA48 hard disk\n\r");
703 memset(cfis, 0, sizeof(struct sata_fis_h2d));
705 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
706 cfis->pm_port_c = 0x80; /* is command */
708 cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
709 : ATA_CMD_FPDMA_READ;
711 cfis->lba_high_exp = (block >> 40) & 0xff;
712 cfis->lba_mid_exp = (block >> 32) & 0xff;
713 cfis->lba_low_exp = (block >> 24) & 0xff;
714 cfis->lba_high = (block >> 16) & 0xff;
715 cfis->lba_mid = (block >> 8) & 0xff;
716 cfis->lba_low = block & 0xff;
718 cfis->device = ATA_LBA;
719 cfis->features_exp = (blkcnt >> 8) & 0xff;
720 cfis->features = blkcnt & 0xff;
722 if (sata->queue_depth >= SATA_HC_MAX_CMD)
723 ncq_channel = SATA_HC_MAX_CMD - 1;
725 ncq_channel = sata->queue_depth - 1;
727 /* Use the latest queue */
728 fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer, ATA_SECT_SIZE * blkcnt);
732 void fsl_sata_flush_cache_ext(int dev)
734 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
735 struct sata_fis_h2d h2d, *cfis = &h2d;
737 memset(cfis, 0, sizeof(struct sata_fis_h2d));
739 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
740 cfis->pm_port_c = 0x80; /* is command */
741 cfis->command = ATA_CMD_FLUSH_EXT;
743 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
746 /* Software reset, set SRST of the Device Control register */
747 void fsl_sata_software_reset(int dev)
752 static void fsl_sata_init_wcache(int dev, u16 *id)
754 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
756 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
758 if (ata_id_has_flush(id))
760 if (ata_id_has_flush_ext(id))
764 static int fsl_sata_get_wcache(int dev)
766 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
770 static int fsl_sata_get_flush(int dev)
772 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
776 static int fsl_sata_get_flush_ext(int dev)
778 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
779 return sata->flush_ext;
782 u32 ata_low_level_rw_lba48(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write)
792 max_blks = ATA_MAX_SECTORS_LBA48;
794 if (blks > max_blks) {
795 if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
796 fsl_sata_rw_cmd_ext(dev, start, max_blks, addr, is_write);
798 fsl_sata_rw_ncq_cmd(dev, start, max_blks, addr, is_write);
801 addr += ATA_SECT_SIZE * max_blks;
803 if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
804 fsl_sata_rw_cmd_ext(dev, start, blks, addr, is_write);
806 fsl_sata_rw_ncq_cmd(dev, start, blks, addr, is_write);
809 addr += ATA_SECT_SIZE * blks;
816 u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write)
826 max_blks = ATA_MAX_SECTORS;
828 if (blks > max_blks) {
829 fsl_sata_rw_cmd(dev, start, max_blks, addr, is_write);
832 addr += ATA_SECT_SIZE * max_blks;
834 fsl_sata_rw_cmd(dev, start, blks, addr, is_write);
837 addr += ATA_SECT_SIZE * blks;
845 * SATA interface between low level driver and command layer
847 ulong sata_read(int dev, u32 blknr, u32 blkcnt, void *buffer)
850 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
853 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
855 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
859 ulong sata_write(int dev, u32 blknr, u32 blkcnt, void *buffer)
862 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
865 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
866 if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush_ext(dev))
867 fsl_sata_flush_cache_ext(dev);
869 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
870 if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush(dev))
871 fsl_sata_flush_cache(dev);
876 int scan_sata(int dev)
878 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
879 unsigned char serial[ATA_ID_SERNO_LEN + 1];
880 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
881 unsigned char product[ATA_ID_PROD_LEN + 1];
885 /* if no detected link */
889 id = (u16 *)malloc(ATA_ID_WORDS * 2);
891 printf("id malloc failed\n\r");
895 /* Identify device to get information */
896 fsl_sata_identify(dev, id);
899 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
900 memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
902 /* Firmware version */
903 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
904 memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
907 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
908 memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
911 n_sectors = ata_id_n_sectors(id);
912 sata_dev_desc[dev].lba = (u32)n_sectors;
915 /* Check if support LBA48 */
916 if (ata_id_has_lba48(id)) {
918 debug("Device support LBA48\n\r");
920 debug("Device supports LBA28\n\r");
923 /* Get the NCQ queue depth from device */
924 sata->queue_depth = ata_id_queue_depth(id);
926 /* Get the xfer mode from device */
927 fsl_sata_xfer_mode(dev, id);
929 /* Get the write cache status from device */
930 fsl_sata_init_wcache(dev, id);
932 /* Set the xfer mode to highest speed */
933 fsl_sata_set_features(dev);
935 fsl_sata_identify(dev, id);