2 * Copyright (C) 2008 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
30 extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
32 #ifndef CONFIG_SYS_SATA1_FLAGS
33 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
35 #ifndef CONFIG_SYS_SATA2_FLAGS
36 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
39 static struct fsl_sata_info fsl_sata_info[] = {
41 {CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS},
46 {CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS},
52 static inline void mdelay(unsigned long msec)
55 for (i = 0; i < msec; i++)
59 static inline void sdelay(unsigned long sec)
62 for (i = 0; i < sec; i++)
66 void dprint_buffer(unsigned char *buf, int len)
74 for (i = 0; i < len; i++) {
75 printf("%02x ", *buf++);
85 static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
87 printf("Status FIS dump:\n\r");
88 printf("fis_type: %02x\n\r", s->fis_type);
89 printf("pm_port_i: %02x\n\r", s->pm_port_i);
90 printf("status: %02x\n\r", s->status);
91 printf("error: %02x\n\r", s->error);
92 printf("lba_low: %02x\n\r", s->lba_low);
93 printf("lba_mid: %02x\n\r", s->lba_mid);
94 printf("lba_high: %02x\n\r", s->lba_high);
95 printf("device: %02x\n\r", s->device);
96 printf("lba_low_exp: %02x\n\r", s->lba_low_exp);
97 printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp);
98 printf("lba_high_exp: %02x\n\r", s->lba_high_exp);
99 printf("res1: %02x\n\r", s->res1);
100 printf("sector_count: %02x\n\r", s->sector_count);
101 printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
104 static int ata_wait_register(volatile unsigned *addr, u32 mask,
105 u32 val, u32 timeout_msec)
110 for (i = 0; (((temp = in_le32(addr)) & mask) != val)
111 && i < timeout_msec; i++)
113 return (i < timeout_msec) ? 0 : -1;
116 int init_sata(int dev)
119 cmd_hdr_tbl_t *cmd_hdr;
127 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
128 printf("the sata index %d is out of ranges\n\r", dev);
132 /* Allocate SATA device driver struct */
133 sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
135 printf("alloc the sata device struct failed\n\r");
138 /* Zero all of the device driver struct */
139 memset((void *)sata, 0, sizeof(fsl_sata_t));
141 /* Save the private struct to block device struct */
142 sata_dev_desc[dev].priv = (void *)sata;
144 sprintf(sata->name, "SATA%d", dev);
146 /* Set the controller register base address to device struct */
147 reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
148 sata->reg_base = reg;
150 /* Allocate the command header table, 4 bytes aligned */
151 length = sizeof(struct cmd_hdr_tbl);
152 align = SATA_HC_CMD_HDR_TBL_ALIGN;
153 sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
155 printf("alloc the command header failed\n\r");
159 cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
161 sata->cmd_hdr = cmd_hdr;
163 /* Zero all of the command header table */
164 memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
166 /* Allocate command descriptor for all command */
167 length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
168 align = SATA_HC_CMD_DESC_ALIGN;
169 sata->cmd_desc_offset = (void *)malloc(length + align);
170 if (!sata->cmd_desc_offset) {
171 printf("alloc the command descriptor failed\n\r");
174 sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
176 /* Zero all of command descriptor */
177 memset((void *)sata->cmd_desc_offset, 0, length + align);
179 /* Link the command descriptor to command header */
180 for (i = 0; i < SATA_HC_MAX_CMD; i++) {
181 cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
182 & ~(CMD_HDR_CDA_ALIGN - 1);
183 cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
186 /* To have safe state, force the controller offline */
187 val32 = in_le32(®->hcontrol);
188 val32 &= ~HCONTROL_ONOFF;
189 val32 |= HCONTROL_FORCE_OFFLINE;
190 out_le32(®->hcontrol, val32);
192 /* Wait the controller offline */
193 ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000);
195 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
197 * For P1022/1013 Rev1.0 silicon, after power on SATA host
198 * controller is configured in legacy mode instead of the
199 * expected enterprise mode. software needs to clear bit[28]
200 * of HControl register to change to enterprise mode from
205 if (IS_SVR_REV(svr, 1, 0) &&
206 ((SVR_SOC_VER(svr) == SVR_P1022) ||
207 (SVR_SOC_VER(svr) == SVR_P1022_E) ||
208 (SVR_SOC_VER(svr) == SVR_P1013) ||
209 (SVR_SOC_VER(svr) == SVR_P1013_E))) {
210 out_le32(®->hstatus, 0x20000000);
211 out_le32(®->hcontrol, 0x00000100);
216 /* Set the command header base address to CHBA register to tell DMA */
217 out_le32(®->chba, (u32)cmd_hdr & ~0x3);
219 /* Snoop for the command header */
220 val32 = in_le32(®->hcontrol);
221 val32 |= HCONTROL_HDR_SNOOP;
222 out_le32(®->hcontrol, val32);
224 /* Disable all of interrupts */
225 val32 = in_le32(®->hcontrol);
226 val32 &= ~HCONTROL_INT_EN_ALL;
227 out_le32(®->hcontrol, val32);
229 /* Clear all of interrupts */
230 val32 = in_le32(®->hstatus);
231 out_le32(®->hstatus, val32);
233 /* Set the ICC, no interrupt coalescing */
234 out_le32(®->icc, 0x01000000);
236 /* No PM attatched, the SATA device direct connect */
237 out_le32(®->cqpmp, 0);
239 /* Clear SError register */
240 val32 = in_le32(®->serror);
241 out_le32(®->serror, val32);
243 /* Clear CER register */
244 val32 = in_le32(®->cer);
245 out_le32(®->cer, val32);
247 /* Clear DER register */
248 val32 = in_le32(®->der);
249 out_le32(®->der, val32);
251 /* No device detection or initialization action requested */
252 out_le32(®->scontrol, 0x00000300);
254 /* Configure the transport layer, default value */
255 out_le32(®->transcfg, 0x08000016);
257 /* Configure the link layer, default value */
258 out_le32(®->linkcfg, 0x0000ff34);
260 /* Bring the controller online */
261 val32 = in_le32(®->hcontrol);
262 val32 |= HCONTROL_ONOFF;
263 out_le32(®->hcontrol, val32);
267 /* print sata device name */
269 printf("%s ", sata->name);
271 printf(" %s ", sata->name);
273 /* Wait PHY RDY signal changed for 500ms */
274 ata_wait_register(®->hstatus, HSTATUS_PHY_RDY,
275 HSTATUS_PHY_RDY, 500);
278 val32 = in_le32(®->hstatus);
279 if (val32 & HSTATUS_PHY_RDY) {
283 printf("(No RDY)\n\r");
287 /* Wait for signature updated, which is 1st D2H */
288 ata_wait_register(®->hstatus, HSTATUS_SIGNATURE,
289 HSTATUS_SIGNATURE, 10000);
291 if (val32 & HSTATUS_SIGNATURE) {
292 sig = in_le32(®->sig);
293 debug("Signature updated, the sig =%08x\n\r", sig);
294 sata->ata_device_type = ata_dev_classify(sig);
297 /* Check the speed */
298 val32 = in_le32(®->sstatus);
299 if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
300 printf("(1.5 Gbps)\n\r");
301 else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
302 printf("(3 Gbps)\n\r");
307 /* Hardware reset, like Power-on and COMRESET */
308 void fsl_sata_hardware_reset(u32 reg_base)
310 fsl_sata_reg_t *reg = (fsl_sata_reg_t *)reg_base;
313 /* Disable the SATA interface and put PHY offline */
314 scontrol = in_le32(®->scontrol);
315 scontrol = (scontrol & 0x0f0) | 0x304;
316 out_le32(®->scontrol, scontrol);
318 /* No speed strict */
319 scontrol = in_le32(®->scontrol);
320 scontrol = scontrol & ~0x0f0;
321 out_le32(®->scontrol, scontrol);
323 /* Issue PHY wake/reset, Hardware_reset_asserted */
324 scontrol = in_le32(®->scontrol);
325 scontrol = (scontrol & 0x0f0) | 0x301;
326 out_le32(®->scontrol, scontrol);
330 /* Resume PHY, COMRESET negated, the device initialize hardware
331 * and execute diagnostics, send good status-signature to host,
332 * which is D2H register FIS, and then the device enter idle state.
334 scontrol = in_le32(®->scontrol);
335 scontrol = (scontrol & 0x0f0) | 0x300;
336 out_le32(®->scontrol, scontrol);
342 static void fsl_sata_dump_regs(fsl_sata_reg_t *reg)
344 printf("\n\rSATA: %08x\n\r", (u32)reg);
345 printf("CQR: %08x\n\r", in_le32(®->cqr));
346 printf("CAR: %08x\n\r", in_le32(®->car));
347 printf("CCR: %08x\n\r", in_le32(®->ccr));
348 printf("CER: %08x\n\r", in_le32(®->cer));
349 printf("CQR: %08x\n\r", in_le32(®->cqr));
350 printf("DER: %08x\n\r", in_le32(®->der));
351 printf("CHBA: %08x\n\r", in_le32(®->chba));
352 printf("HStatus: %08x\n\r", in_le32(®->hstatus));
353 printf("HControl: %08x\n\r", in_le32(®->hcontrol));
354 printf("CQPMP: %08x\n\r", in_le32(®->cqpmp));
355 printf("SIG: %08x\n\r", in_le32(®->sig));
356 printf("ICC: %08x\n\r", in_le32(®->icc));
357 printf("SStatus: %08x\n\r", in_le32(®->sstatus));
358 printf("SError: %08x\n\r", in_le32(®->serror));
359 printf("SControl: %08x\n\r", in_le32(®->scontrol));
360 printf("SNotification: %08x\n\r", in_le32(®->snotification));
361 printf("TransCfg: %08x\n\r", in_le32(®->transcfg));
362 printf("TransStatus: %08x\n\r", in_le32(®->transstatus));
363 printf("LinkCfg: %08x\n\r", in_le32(®->linkcfg));
364 printf("LinkCfg1: %08x\n\r", in_le32(®->linkcfg1));
365 printf("LinkCfg2: %08x\n\r", in_le32(®->linkcfg2));
366 printf("LinkStatus: %08x\n\r", in_le32(®->linkstatus));
367 printf("LinkStatus1: %08x\n\r", in_le32(®->linkstatus1));
368 printf("PhyCtrlCfg: %08x\n\r", in_le32(®->phyctrlcfg));
369 printf("SYSPR: %08x\n\r", in_be32(®->syspr));
372 static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
373 int is_ncq, int tag, u8 *buffer, u32 len)
375 cmd_hdr_entry_t *cmd_hdr;
376 cmd_desc_t *cmd_desc;
383 fsl_sata_reg_t *reg = sata->reg_base;
386 /* Check xfer length */
387 if (len > SATA_HC_MAX_XFER_LEN) {
388 printf("max transfer length is 64MB\n\r");
392 /* Setup the command descriptor */
393 cmd_desc = sata->cmd_desc + tag;
395 /* Get the pointer cfis of command descriptor */
396 h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
398 /* Zero the cfis of command descriptor */
399 memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
401 /* Copy the cfis from user to command descriptor */
402 h2d->fis_type = cfis->fis_type;
403 h2d->pm_port_c = cfis->pm_port_c;
404 h2d->command = cfis->command;
406 h2d->features = cfis->features;
407 h2d->features_exp = cfis->features_exp;
409 h2d->lba_low = cfis->lba_low;
410 h2d->lba_mid = cfis->lba_mid;
411 h2d->lba_high = cfis->lba_high;
412 h2d->lba_low_exp = cfis->lba_low_exp;
413 h2d->lba_mid_exp = cfis->lba_mid_exp;
414 h2d->lba_high_exp = cfis->lba_high_exp;
417 h2d->sector_count = cfis->sector_count;
418 h2d->sector_count_exp = cfis->sector_count_exp;
420 h2d->sector_count = (u8)(tag << 3);
423 h2d->device = cfis->device;
424 h2d->control = cfis->control;
426 /* Setup the PRD table */
427 prde = (prd_entry_t *)cmd_desc->prdt;
428 memset((void *)prde, 0, sizeof(struct prdt));
432 for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
435 prde->dba = cpu_to_le32((u32)buffer & ~0x3);
436 debug("dba = %08x\n\r", (u32)buffer);
438 if (len < PRD_ENTRY_MAX_XFER_SZ) {
439 ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
440 debug("ext_c_ddc1 = %08x, len = %08x\n\r", ext_c_ddc, len);
441 prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
446 ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
447 debug("ext_c_ddc2 = %08x, len = %08x\n\r", ext_c_ddc, len);
448 prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
449 buffer += PRD_ENTRY_MAX_XFER_SZ;
450 len -= PRD_ENTRY_MAX_XFER_SZ;
456 /* Setup the command slot of cmd hdr */
457 cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
459 cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
461 val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
462 val32 |= sizeof(sata_fis_h2d_t);
463 cmd_hdr->prde_fis_len = cpu_to_le32(val32);
465 cmd_hdr->ttl = cpu_to_le32(ttl);
468 val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
470 val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP | CMD_HDR_ATTR_FPDMA;
473 tag &= CMD_HDR_ATTR_TAG;
476 debug("attribute = %08x\n\r", val32);
477 cmd_hdr->attribute = cpu_to_le32(val32);
479 /* Make sure cmd desc and cmd slot valid before commmand issue */
483 val32 = (u32)(h2d->pm_port_c & 0x0f);
484 out_le32(®->cqpmp, val32);
487 if (ata_wait_register(®->car, (1 << tag), 0, 10000))
488 printf("Wait no active time out\n\r");
491 if (!(in_le32(®->cqr) & (1 << tag))) {
493 out_le32(®->cqr, val32);
496 /* Wait command completed for 10s */
497 if (ata_wait_register(®->ccr, (1 << tag), (1 << tag), 10000)) {
499 printf("Non-NCQ command time out\n\r");
501 printf("NCQ command time out\n\r");
504 val32 = in_le32(®->cer);
508 fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
509 printf("CE at device\n\r");
510 fsl_sata_dump_regs(reg);
511 der = in_le32(®->der);
512 out_le32(®->cer, val32);
513 out_le32(®->der, der);
516 /* Clear complete flags */
517 val32 = in_le32(®->ccr);
518 out_le32(®->ccr, val32);
523 static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
524 int tag, u8 *buffer, u32 len)
529 static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
530 enum cmd_type command_type, int tag, u8 *buffer, u32 len)
534 if (tag > SATA_HC_MAX_CMD || tag < 0) {
535 printf("tag is out of range, tag=%d\n\r", tag);
539 switch (command_type) {
541 rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
544 rc = fsl_ata_exec_reset_cmd(sata, cfis, tag, buffer, len);
547 rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
550 case CMD_VENDOR_BIST:
552 printf("not support now\n\r");
561 static void fsl_sata_identify(int dev, u16 *id)
563 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
564 struct sata_fis_h2d h2d, *cfis = &h2d;
566 memset(cfis, 0, sizeof(struct sata_fis_h2d));
568 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
569 cfis->pm_port_c = 0x80; /* is command */
570 cfis->command = ATA_CMD_ID_ATA;
572 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
573 ata_swap_buf_le16(id, ATA_ID_WORDS);
576 static void fsl_sata_xfer_mode(int dev, u16 *id)
578 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
580 sata->pio = id[ATA_ID_PIO_MODES];
581 sata->mwdma = id[ATA_ID_MWDMA_MODES];
582 sata->udma = id[ATA_ID_UDMA_MODES];
583 debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio, sata->mwdma, sata->udma);
586 static void fsl_sata_set_features(int dev)
588 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
589 struct sata_fis_h2d h2d, *cfis = &h2d;
592 memset(cfis, 0, sizeof(struct sata_fis_h2d));
594 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
595 cfis->pm_port_c = 0x80; /* is command */
596 cfis->command = ATA_CMD_SET_FEATURES;
597 cfis->features = SETFEATURES_XFER;
599 /* First check the device capablity */
600 udma_cap = (u8)(sata->udma & 0xff);
601 debug("udma_cap %02x\n\r", udma_cap);
603 if (udma_cap == ATA_UDMA6)
604 cfis->sector_count = XFER_UDMA_6;
605 if (udma_cap == ATA_UDMA5)
606 cfis->sector_count = XFER_UDMA_5;
607 if (udma_cap == ATA_UDMA4)
608 cfis->sector_count = XFER_UDMA_4;
609 if (udma_cap == ATA_UDMA3)
610 cfis->sector_count = XFER_UDMA_3;
612 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
615 static u32 fsl_sata_rw_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
617 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
618 struct sata_fis_h2d h2d, *cfis = &h2d;
623 memset(cfis, 0, sizeof(struct sata_fis_h2d));
625 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
626 cfis->pm_port_c = 0x80; /* is command */
627 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
628 cfis->device = ATA_LBA;
630 cfis->device |= (block >> 24) & 0xf;
631 cfis->lba_high = (block >> 16) & 0xff;
632 cfis->lba_mid = (block >> 8) & 0xff;
633 cfis->lba_low = block & 0xff;
634 cfis->sector_count = (u8)(blkcnt & 0xff);
636 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
640 void fsl_sata_flush_cache(int dev)
642 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
643 struct sata_fis_h2d h2d, *cfis = &h2d;
645 memset(cfis, 0, sizeof(struct sata_fis_h2d));
647 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
648 cfis->pm_port_c = 0x80; /* is command */
649 cfis->command = ATA_CMD_FLUSH;
651 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
654 static u32 fsl_sata_rw_cmd_ext(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
656 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
657 struct sata_fis_h2d h2d, *cfis = &h2d;
662 memset(cfis, 0, sizeof(struct sata_fis_h2d));
664 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
665 cfis->pm_port_c = 0x80; /* is command */
667 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
670 cfis->lba_high_exp = (block >> 40) & 0xff;
671 cfis->lba_mid_exp = (block >> 32) & 0xff;
672 cfis->lba_low_exp = (block >> 24) & 0xff;
673 cfis->lba_high = (block >> 16) & 0xff;
674 cfis->lba_mid = (block >> 8) & 0xff;
675 cfis->lba_low = block & 0xff;
676 cfis->device = ATA_LBA;
677 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
678 cfis->sector_count = blkcnt & 0xff;
680 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
684 u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
686 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
687 struct sata_fis_h2d h2d, *cfis = &h2d;
691 if (sata_dev_desc[dev].lba48 != 1) {
692 printf("execute FPDMA command on non-LBA48 hard disk\n\r");
698 memset(cfis, 0, sizeof(struct sata_fis_h2d));
700 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
701 cfis->pm_port_c = 0x80; /* is command */
703 cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
704 : ATA_CMD_FPDMA_READ;
706 cfis->lba_high_exp = (block >> 40) & 0xff;
707 cfis->lba_mid_exp = (block >> 32) & 0xff;
708 cfis->lba_low_exp = (block >> 24) & 0xff;
709 cfis->lba_high = (block >> 16) & 0xff;
710 cfis->lba_mid = (block >> 8) & 0xff;
711 cfis->lba_low = block & 0xff;
713 cfis->device = ATA_LBA;
714 cfis->features_exp = (blkcnt >> 8) & 0xff;
715 cfis->features = blkcnt & 0xff;
717 if (sata->queue_depth >= SATA_HC_MAX_CMD)
718 ncq_channel = SATA_HC_MAX_CMD - 1;
720 ncq_channel = sata->queue_depth - 1;
722 /* Use the latest queue */
723 fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer, ATA_SECT_SIZE * blkcnt);
727 void fsl_sata_flush_cache_ext(int dev)
729 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
730 struct sata_fis_h2d h2d, *cfis = &h2d;
732 memset(cfis, 0, sizeof(struct sata_fis_h2d));
734 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
735 cfis->pm_port_c = 0x80; /* is command */
736 cfis->command = ATA_CMD_FLUSH_EXT;
738 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
741 /* Software reset, set SRST of the Device Control register */
742 void fsl_sata_software_reset(int dev)
747 static void fsl_sata_init_wcache(int dev, u16 *id)
749 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
751 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
753 if (ata_id_has_flush(id))
755 if (ata_id_has_flush_ext(id))
759 static int fsl_sata_get_wcache(int dev)
761 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
765 static int fsl_sata_get_flush(int dev)
767 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
771 static int fsl_sata_get_flush_ext(int dev)
773 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
774 return sata->flush_ext;
777 u32 ata_low_level_rw_lba48(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write)
787 max_blks = ATA_MAX_SECTORS_LBA48;
789 if (blks > max_blks) {
790 if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
791 fsl_sata_rw_cmd_ext(dev, start, max_blks, addr, is_write);
793 fsl_sata_rw_ncq_cmd(dev, start, max_blks, addr, is_write);
796 addr += ATA_SECT_SIZE * max_blks;
798 if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
799 fsl_sata_rw_cmd_ext(dev, start, blks, addr, is_write);
801 fsl_sata_rw_ncq_cmd(dev, start, blks, addr, is_write);
804 addr += ATA_SECT_SIZE * blks;
811 u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write)
821 max_blks = ATA_MAX_SECTORS;
823 if (blks > max_blks) {
824 fsl_sata_rw_cmd(dev, start, max_blks, addr, is_write);
827 addr += ATA_SECT_SIZE * max_blks;
829 fsl_sata_rw_cmd(dev, start, blks, addr, is_write);
832 addr += ATA_SECT_SIZE * blks;
840 * SATA interface between low level driver and command layer
842 ulong sata_read(int dev, u32 blknr, u32 blkcnt, void *buffer)
846 if (sata_dev_desc[dev].lba48)
847 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
849 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
853 ulong sata_write(int dev, u32 blknr, u32 blkcnt, void *buffer)
857 if (sata_dev_desc[dev].lba48) {
858 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
859 if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush_ext(dev))
860 fsl_sata_flush_cache_ext(dev);
862 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
863 if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush(dev))
864 fsl_sata_flush_cache(dev);
869 int scan_sata(int dev)
871 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
872 unsigned char serial[ATA_ID_SERNO_LEN + 1];
873 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
874 unsigned char product[ATA_ID_PROD_LEN + 1];
878 /* if no detected link */
882 id = (u16 *)malloc(ATA_ID_WORDS * 2);
884 printf("id malloc failed\n\r");
888 /* Identify device to get information */
889 fsl_sata_identify(dev, id);
892 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
893 memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
895 /* Firmware version */
896 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
897 memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
900 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
901 memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
904 n_sectors = ata_id_n_sectors(id);
905 sata_dev_desc[dev].lba = (u32)n_sectors;
907 /* Check if support LBA48 */
908 if (ata_id_has_lba48(id)) {
909 sata_dev_desc[dev].lba48 = 1;
910 debug("Device support LBA48\n\r");
913 /* Get the NCQ queue depth from device */
914 sata->queue_depth = ata_id_queue_depth(id);
916 /* Get the xfer mode from device */
917 fsl_sata_xfer_mode(dev, id);
919 /* Get the write cache status from device */
920 fsl_sata_init_wcache(dev, id);
922 /* Set the xfer mode to highest speed */
923 fsl_sata_set_features(dev);
925 fsl_sata_identify(dev, id);