2 * Faraday FTIDE020 ATA Controller (AHB)
4 * (C) Copyright 2011 Andes Technology
5 * Greentime Hu <greentime@andestech.com>
6 * Macpaul Lin <macpaul@andestech.com>
7 * Kuo-Wei Chou <kwchou@andestech.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /* ftide020.c - ide support functions for the FTIDE020_S controller */
35 #include <api_public.h>
40 #define FTIDE_BASE CONFIG_SYS_ATA_BASE_ADDR
43 * data address - The CMD and DATA use the same FIFO in FTIDE020_S
44 * FTIDE_DATA = CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_DATA_OFFSET
45 * = &ftide020->rw_fifo
47 #define FTIDE_DATA (&ftide020->rw_fifo)
49 /* command and data I/O macros */
51 #define WRITE_DATA(x) outl((x), &ftide020->rw_fifo) /* 0x00 */
52 #define READ_DATA() inl(&ftide020->rw_fifo) /* 0x00 */
53 /* 0x04 - R: Status Reg, W: CMD_FIFO */
54 #define WRITE_CMD(x) outl((x), &ftide020->cmd_fifo) /* 0x04 */
55 #define READ_STATUS() inl(&ftide020->cmd_fifo) /* 0x04 */
57 #define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
59 void ftide_set_device(int cx8, int dev)
61 static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
63 WRITE_CMD(SET_DEV_CMD | IDE_SET_CX8(cx8) | dev);
66 unsigned char ide_read_register(int dev, unsigned int port)
68 static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
70 ftide_set_device(0, dev);
71 WRITE_CMD(READ_REG_CMD | IDE_REG_CS_READ(CONFIG_IDE_REG_CS) |
72 IDE_REG_DA_WRITE(port));
74 return READ_DATA() & 0xff;
77 void ide_write_register(int dev, unsigned int port, unsigned char val)
79 static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
81 ftide_set_device(0, dev);
82 WRITE_CMD(WRITE_REG_CMD | IDE_REG_CS_WRITE(CONFIG_IDE_REG_CS) |
83 IDE_REG_DA_WRITE(port) | val);
86 void ide_write_data(int dev, ulong *sect_buf, int words)
88 static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
90 ftide_set_device(0, dev);
91 WRITE_CMD(WRITE_DATA_CMD | ((words << 2) - 1));
94 outsl(FTIDE_DATA, sect_buf, words);
97 void ide_read_data(int dev, ulong *sect_buf, int words)
99 static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
101 ftide_set_device(0, dev);
102 WRITE_CMD(READ_DATA_CMD | ((words << 2) - 1));
105 insl(FTIDE_DATA, sect_buf, words);
108 void ftide_dfifo_ready(ulong *time)
110 static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
112 while (!(READ_STATUS() & STATUS_RFE)) {
120 extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
122 /* Reset_IDE_controller */
123 static void reset_ide_controller(void)
125 static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
128 val = inl(&ftide020->cr);
131 outl(val, &ftide020->cr);
133 /* wait until reset OK, this is poor HW design */
135 val &= ~(CONTROL_RST);
136 outl(val, &ftide020->cr);
140 outl(val, &ftide020->cr);
142 /* wait until reset OK, this is poor HW design */
144 val &= ~(CONTROL_SRST);
145 outl(val, &ftide020->cr);
147 /* IORDY enable for PIO, for 2 device */
148 val |= (CONTROL_IRE0 | CONTROL_IRE1);
149 outl(val, &ftide020->cr);
152 /* IDE clock frequence */
153 uint ftide_clock_freq(void)
156 * todo: To aquire dynamic system frequency is dependend on the power
157 * management unit which the ftide020 is connected to. In current,
158 * there are only few PMU supports in u-boot.
159 * So this function is wait for future enhancement.
164 /* Calculate Timing Registers */
165 static unsigned int timing_cal(u16 t0, u16 t1, u16 t2, u16 t4)
167 unsigned int val, ahb_ns = 8;
170 T1 = (u8) (t1 / ahb_ns);
171 if ((T1 * ahb_ns) == t1)
174 T2 = (u8) (t2 / ahb_ns);
175 if ((T2 * ahb_ns) == t2)
178 T4 = (u8) (t4 / ahb_ns);
179 if ((T4 * ahb_ns) == t4)
182 TEOC = (u8) (t0 / ahb_ns);
183 if ((TEOC * ahb_ns) == t0)
186 TEOC = ((TEOC > (T1 + T2 + T4)) ? (TEOC - (T1 + T2 + T4)) : 0);
189 * Here the fields in data timing registers in PIO mode
190 * is accessed the same way as command timing registers.
192 val = DT_REG_PIO_T1(T1) |
195 DT_REG_PIO_TEOC(TEOC);
200 /* Set Timing Register */
201 static unsigned int set_mode_timing(u8 dev, u8 id, u8 mode)
203 static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
205 u8 tcyc, tcvs, tmli, tenv, tack, trp;
206 unsigned int val, sysclk = 8;
208 if (id >= TATOL_TIMING)
211 sysclk = ftide_clock_freq();
214 if (mode < REG_MODE) {
215 t0 = REG_ACCESS_TIMING[REG_T0][mode];
216 t1 = REG_ACCESS_TIMING[REG_T1][mode];
217 t2 = REG_ACCESS_TIMING[REG_T2][mode];
218 t4 = REG_ACCESS_TIMING[REG_T4][mode];
220 val = timing_cal(t0, t1, t2, t4);
221 outl(val, (dev ? &ftide020->ctrd1 : &ftide020->ctrd0));
226 if (mode < PIO_MODE) {
227 t0 = PIO_ACCESS_TIMING[PIO_T0][mode];
228 t1 = PIO_ACCESS_TIMING[PIO_T1][mode];
229 t2 = PIO_ACCESS_TIMING[PIO_T2][mode];
230 t4 = PIO_ACCESS_TIMING[PIO_T4][mode];
232 val = timing_cal(t0, t1, t2, t4);
234 outl(val, (dev ? &ftide020->dtrd1 : &ftide020->dtrd0));
239 if (mode < UDMA_MODE) {
242 * for tcyc, tcvs, tmli, tenv, trp, tack
244 tcyc = (u8) (((UDMA_ACCESS_TIMING[UDMA_TCYC][mode] \
245 * sysclk) + 9990) / 10000);
246 tcvs = (u8) (((UDMA_ACCESS_TIMING[UDMA_TCVS][mode] \
247 * sysclk) + 9990) / 10000);
248 tmli = (u8) (((UDMA_ACCESS_TIMING[UDMA_TMLI][mode] \
249 * sysclk) + 9990) / 10000);
250 tenv = (u8) (((UDMA_ACCESS_TIMING[UDMA_TENV][mode] \
251 * sysclk) + 9990) / 10000);
252 trp = (u8) (((UDMA_ACCESS_TIMING[UDMA_TRP][mode] \
253 * sysclk) + 9990) / 10000);
254 tack = (u8) (((UDMA_ACCESS_TIMING[UDMA_TACK][mode] \
255 * sysclk) + 9990) / 10000);
257 val = DT_REG_UDMA_TENV((tenv > 0) ? (tenv - 1) : 0) |
258 DT_REG_UDMA_TMLI((tmli > 0) ? (tmli - 1) : 0) |
259 DT_REG_UDMA_TCYC((tcyc > 0) ? (tcyc - 1) : 0) |
260 DT_REG_UDMA_TACK((tack > 0) ? (tack - 1) : 0) |
261 DT_REG_UDMA_TCVS((tcvs > 0) ? (tcvs - 1) : 0) |
262 DT_REG_UDMA_TRP((trp > 0) ? (trp - 1) : 0);
264 outl(val, (dev ? &ftide020->dtrd1 : &ftide020->dtrd0));
273 static void ftide_read_hwrev(void)
275 static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
278 rev = inl(&ftide020->revision);
281 static int ftide_controller_probe(void)
283 static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
286 bak = inl(&ftide020->ctrd1);
288 /* probing by using shorter setup time */
289 outl(CONFIG_CTRD1_PROBE_T1, &ftide020->ctrd1);
290 if ((inl(&ftide020->ctrd1) & 0xff) != CONFIG_CTRD1_PROBE_T1) {
291 outl(bak, &ftide020->ctrd1);
295 /* probing by using longer setup time */
296 outl(CONFIG_CTRD1_PROBE_T2, &ftide020->ctrd1);
297 if ((inl(&ftide020->ctrd1) & 0xff) != CONFIG_CTRD1_PROBE_T2) {
298 outl(bak, &ftide020->ctrd1);
302 outl(bak, &ftide020->ctrd1);
307 /* ide_preinit() was migrated from linux driver ide_probe_for_ftide() */
308 int ide_preinit(void)
310 static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
316 for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; i++)
317 ide_bus_offset[i] = -ATA_STATUS;
319 /* auto-detect IDE controller */
320 if (ftide_controller_probe()) {
321 printf("Faraday %s driver version %s\n", FTIDE_IP_NAME,
322 FTIDE_DRIVER_VERSION);
324 printf("Faraday ATA controller not found.\n");
328 /* check HW IP revision */
331 /* set FIFO threshold */
332 outl(((WRITE_FIFO - RX_THRESH) << 16) | RX_THRESH, &ftide020->dmatirr);
334 /* set Device_0 PIO_4 timing */
335 set_mode_timing(0, CMD_TIMING, REG_MODE4);
336 set_mode_timing(0, PIO_TIMING, PIO_MODE4);
338 /* set Device_1 PIO_4 timing */
339 set_mode_timing(1, CMD_TIMING, REG_MODE4);
340 set_mode_timing(1, PIO_TIMING, PIO_MODE4);
344 outl(0x0, &ftide020->cr);
347 outl(0x0fff0fff, &ftide020->ahbtr);
350 /* Enable controller Interrupt */
351 val = inl(&ftide020->cr);
353 /* Enable: IDE IRQ, IDE Terminate ERROR IRQ, AHB Timeout error IRQ */
354 val |= (CONTROL_IIE | CONTROL_TERIE | CONTROL_AERIE);
355 outl(val, &ftide020->cr);
362 void ide_set_reset(int flag)
364 debug("ide_set_reset()\n");
365 reset_ide_controller();