2 bool "AT91 clock drivers"
6 This option is used to enable the AT91 clock driver.
7 The driver supports the AT91 clock generator, including
8 the oscillators and PLLs, such as main clock, slow clock,
9 PLLA, UTMI PLL. Clocks can also be a source clock of other
10 clocks a tree structure, such as master clock, usb device
11 clock, matrix clock and generic clock.
12 Devices can use a common clock API to request a particular
13 clock, enable it and get its rate.
16 bool "Support UTMI PLL Clock"
19 select SPL_REGMAP if SPL_DM
21 select SPL_SYSCON if SPL_DM
23 This option is used to enable the AT91 UTMI PLL clock
24 driver. It is the clock provider of USB, and UPLLCK is the
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
27 fast crystal oscillator to meet the frequency accuracy
31 bool "Support USB OHCI Input Clock"
34 This option is used to enable the USB Input Clock, from
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
36 and USBDIV field of the PMC_USB register.
39 bool "Support H32MX 32-bit Matrix Clock"
42 This option is used to enable the AT91 H32MX matrixes
43 clock driver. There are H64MX and H32MX matrixes clocks,
44 H64MX 64-bit matrix clocks are MCK. The H32MX 32-bit
45 matrix clock is to be configured as MCK if MCK does not
46 exceed 83 MHz, else it is to be configured as MCK/2.
48 config AT91_GENERIC_CLK
49 bool "Support Generic Clock"
52 This option is used to enable the AT91 generic clock
53 driver. Some peripherals may need a second clock source
54 that may be different from the system clock. This second
55 clock is the generic clock (GCLK) and is managed by
56 the PMC via PMC_PCR register.