git.sur5r.net Git - u-boot/blob - drivers/clk/at91/clk-plladiv.c

   1 /*
   2  * Copyright (C) 2018 Microhip / Atmel Corporation
   3  *               Wenyou.Yang <wenyou.yang@microchip.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk-uclass.h>
  10 #include <dm/device.h>
  11 #include <linux/io.h>
  12 #include <mach/at91_pmc.h>
  13 #include "pmc.h"
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 static int at91_plladiv_clk_enable(struct clk *clk)
  18 {
  19         return 0;
  20 }
  21
  22 static ulong at91_plladiv_clk_get_rate(struct clk *clk)
  23 {
  24         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  25         struct at91_pmc *pmc = plat->reg_base;
  26         struct clk source;
  27         ulong clk_rate;
  28         int ret;
  29
  30         ret = clk_get_by_index(clk->dev, 0, &source);
  31         if (ret)
  32                 return -EINVAL;
  33
  34         clk_rate = clk_get_rate(&source);
  35         if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2)
  36                 clk_rate /= 2;
  37
  38         return clk_rate;
  39 }
  40
  41 static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)
  42 {
  43         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  44         struct at91_pmc *pmc = plat->reg_base;
  45         struct clk source;
  46         ulong parent_rate;
  47         int ret;
  48
  49         ret = clk_get_by_index(clk->dev, 0, &source);
  50         if (ret)
  51                 return -EINVAL;
  52
  53         parent_rate = clk_get_rate(&source);
  54         if ((parent_rate != rate) && ((parent_rate) / 2 != rate))
  55                 return -EINVAL;
  56
  57         if (parent_rate != rate) {
  58                 writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2),
  59                        &pmc->mckr);
  60         }
  61
  62         return 0;
  63 }
  64
  65 static struct clk_ops at91_plladiv_clk_ops = {
  66         .enable = at91_plladiv_clk_enable,
  67         .get_rate = at91_plladiv_clk_get_rate,
  68         .set_rate = at91_plladiv_clk_set_rate,
  69 };
  70
  71 static int at91_plladiv_clk_probe(struct udevice *dev)
  72 {
  73         return at91_pmc_core_probe(dev);
  74 }
  75
  76 static const struct udevice_id at91_plladiv_clk_match[] = {
  77         { .compatible = "atmel,at91sam9x5-clk-plldiv" },
  78         {}
  79 };
  80
  81 U_BOOT_DRIVER(at91_plladiv_clk) = {
  82         .name = "at91-plladiv-clk",
  83         .id = UCLASS_CLK,
  84         .of_match = at91_plladiv_clk_match,
  85         .probe = at91_plladiv_clk_probe,
  86         .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  87         .ops = &at91_plladiv_clk_ops,
  88 };