]> git.sur5r.net Git - u-boot/blob - drivers/clk/clk-uclass.c
spi: mxc: Fix compilation problem of DM_SPI class driver
[u-boot] / drivers / clk / clk-uclass.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2015 Google, Inc
4  * Written by Simon Glass <sjg@chromium.org>
5  * Copyright (c) 2016, NVIDIA CORPORATION.
6  * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
7  */
8
9 #include <common.h>
10 #include <clk.h>
11 #include <clk-uclass.h>
12 #include <dm.h>
13 #include <dm/read.h>
14 #include <dt-structs.h>
15 #include <errno.h>
16
17 static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
18 {
19         return (const struct clk_ops *)dev->driver->ops;
20 }
21
22 #if CONFIG_IS_ENABLED(OF_CONTROL)
23 # if CONFIG_IS_ENABLED(OF_PLATDATA)
24 int clk_get_by_index_platdata(struct udevice *dev, int index,
25                               struct phandle_1_arg *cells, struct clk *clk)
26 {
27         int ret;
28
29         if (index != 0)
30                 return -ENOSYS;
31         ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
32         if (ret)
33                 return ret;
34         clk->id = cells[0].arg[0];
35
36         return 0;
37 }
38 # else
39 static int clk_of_xlate_default(struct clk *clk,
40                                 struct ofnode_phandle_args *args)
41 {
42         debug("%s(clk=%p)\n", __func__, clk);
43
44         if (args->args_count > 1) {
45                 debug("Invaild args_count: %d\n", args->args_count);
46                 return -EINVAL;
47         }
48
49         if (args->args_count)
50                 clk->id = args->args[0];
51         else
52                 clk->id = 0;
53
54         return 0;
55 }
56
57 static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
58                                    int index, struct clk *clk)
59 {
60         int ret;
61         struct ofnode_phandle_args args;
62         struct udevice *dev_clk;
63         const struct clk_ops *ops;
64
65         debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
66
67         assert(clk);
68         clk->dev = NULL;
69
70         ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
71                                          index, &args);
72         if (ret) {
73                 debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
74                       __func__, ret);
75                 return ret;
76         }
77
78         ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
79         if (ret) {
80                 debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
81                       __func__, ret);
82                 return ret;
83         }
84
85         clk->dev = dev_clk;
86
87         ops = clk_dev_ops(dev_clk);
88
89         if (ops->of_xlate)
90                 ret = ops->of_xlate(clk, &args);
91         else
92                 ret = clk_of_xlate_default(clk, &args);
93         if (ret) {
94                 debug("of_xlate() failed: %d\n", ret);
95                 return ret;
96         }
97
98         return clk_request(dev_clk, clk);
99 }
100
101 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
102 {
103         return clk_get_by_indexed_prop(dev, "clocks", index, clk);
104 }
105
106 int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
107 {
108         int i, ret, err, count;
109         
110         bulk->count = 0;
111
112         count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
113         if (count < 1)
114                 return count;
115
116         bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
117         if (!bulk->clks)
118                 return -ENOMEM;
119
120         for (i = 0; i < count; i++) {
121                 ret = clk_get_by_index(dev, i, &bulk->clks[i]);
122                 if (ret < 0)
123                         goto bulk_get_err;
124
125                 ++bulk->count;
126         }
127
128         return 0;
129
130 bulk_get_err:
131         err = clk_release_all(bulk->clks, bulk->count);
132         if (err)
133                 debug("%s: could release all clocks for %p\n",
134                       __func__, dev);
135
136         return ret;
137 }
138
139 static int clk_set_default_parents(struct udevice *dev)
140 {
141         struct clk clk, parent_clk;
142         int index;
143         int num_parents;
144         int ret;
145
146         num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
147                                                   "#clock-cells");
148         if (num_parents < 0) {
149                 debug("%s: could not read assigned-clock-parents for %p\n",
150                       __func__, dev);
151                 return 0;
152         }
153
154         for (index = 0; index < num_parents; index++) {
155                 ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
156                                               index, &parent_clk);
157                 if (ret) {
158                         debug("%s: could not get parent clock %d for %s\n",
159                               __func__, index, dev_read_name(dev));
160                         return ret;
161                 }
162
163                 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
164                                               index, &clk);
165                 if (ret) {
166                         debug("%s: could not get assigned clock %d for %s\n",
167                               __func__, index, dev_read_name(dev));
168                         return ret;
169                 }
170
171                 ret = clk_set_parent(&clk, &parent_clk);
172
173                 /*
174                  * Not all drivers may support clock-reparenting (as of now).
175                  * Ignore errors due to this.
176                  */
177                 if (ret == -ENOSYS)
178                         continue;
179
180                 if (ret) {
181                         debug("%s: failed to reparent clock %d for %s\n",
182                               __func__, index, dev_read_name(dev));
183                         return ret;
184                 }
185         }
186
187         return 0;
188 }
189
190 static int clk_set_default_rates(struct udevice *dev)
191 {
192         struct clk clk;
193         int index;
194         int num_rates;
195         int size;
196         int ret = 0;
197         u32 *rates = NULL;
198
199         size = dev_read_size(dev, "assigned-clock-rates");
200         if (size < 0)
201                 return 0;
202
203         num_rates = size / sizeof(u32);
204         rates = calloc(num_rates, sizeof(u32));
205         if (!rates)
206                 return -ENOMEM;
207
208         ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
209         if (ret)
210                 goto fail;
211
212         for (index = 0; index < num_rates; index++) {
213                 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
214                                               index, &clk);
215                 if (ret) {
216                         debug("%s: could not get assigned clock %d for %s\n",
217                               __func__, index, dev_read_name(dev));
218                         continue;
219                 }
220
221                 ret = clk_set_rate(&clk, rates[index]);
222                 if (ret < 0) {
223                         debug("%s: failed to set rate on clock %d for %s\n",
224                               __func__, index, dev_read_name(dev));
225                         break;
226                 }
227         }
228
229 fail:
230         free(rates);
231         return ret;
232 }
233
234 int clk_set_defaults(struct udevice *dev)
235 {
236         int ret;
237
238         /* If this is running pre-reloc state, don't take any action. */
239         if (!(gd->flags & GD_FLG_RELOC))
240                 return 0;
241
242         debug("%s(%s)\n", __func__, dev_read_name(dev));
243
244         ret = clk_set_default_parents(dev);
245         if (ret)
246                 return ret;
247
248         ret = clk_set_default_rates(dev);
249         if (ret < 0)
250                 return ret;
251
252         return 0;
253 }
254 # endif /* OF_PLATDATA */
255
256 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
257 {
258         int index;
259
260         debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
261         clk->dev = NULL;
262
263         index = dev_read_stringlist_search(dev, "clock-names", name);
264         if (index < 0) {
265                 debug("fdt_stringlist_search() failed: %d\n", index);
266                 return index;
267         }
268
269         return clk_get_by_index(dev, index, clk);
270 }
271
272 int clk_release_all(struct clk *clk, int count)
273 {
274         int i, ret;
275
276         for (i = 0; i < count; i++) {
277                 debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
278
279                 /* check if clock has been previously requested */
280                 if (!clk[i].dev)
281                         continue;
282
283                 ret = clk_disable(&clk[i]);
284                 if (ret && ret != -ENOSYS)
285                         return ret;
286
287                 ret = clk_free(&clk[i]);
288                 if (ret && ret != -ENOSYS)
289                         return ret;
290         }
291
292         return 0;
293 }
294
295 #endif /* OF_CONTROL */
296
297 int clk_request(struct udevice *dev, struct clk *clk)
298 {
299         const struct clk_ops *ops = clk_dev_ops(dev);
300
301         debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
302
303         clk->dev = dev;
304
305         if (!ops->request)
306                 return 0;
307
308         return ops->request(clk);
309 }
310
311 int clk_free(struct clk *clk)
312 {
313         const struct clk_ops *ops = clk_dev_ops(clk->dev);
314
315         debug("%s(clk=%p)\n", __func__, clk);
316
317         if (!ops->free)
318                 return 0;
319
320         return ops->free(clk);
321 }
322
323 ulong clk_get_rate(struct clk *clk)
324 {
325         const struct clk_ops *ops = clk_dev_ops(clk->dev);
326
327         debug("%s(clk=%p)\n", __func__, clk);
328
329         if (!ops->get_rate)
330                 return -ENOSYS;
331
332         return ops->get_rate(clk);
333 }
334
335 ulong clk_set_rate(struct clk *clk, ulong rate)
336 {
337         const struct clk_ops *ops = clk_dev_ops(clk->dev);
338
339         debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
340
341         if (!ops->set_rate)
342                 return -ENOSYS;
343
344         return ops->set_rate(clk, rate);
345 }
346
347 int clk_set_parent(struct clk *clk, struct clk *parent)
348 {
349         const struct clk_ops *ops = clk_dev_ops(clk->dev);
350
351         debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
352
353         if (!ops->set_parent)
354                 return -ENOSYS;
355
356         return ops->set_parent(clk, parent);
357 }
358
359 int clk_enable(struct clk *clk)
360 {
361         const struct clk_ops *ops = clk_dev_ops(clk->dev);
362
363         debug("%s(clk=%p)\n", __func__, clk);
364
365         if (!ops->enable)
366                 return -ENOSYS;
367
368         return ops->enable(clk);
369 }
370
371 int clk_enable_bulk(struct clk_bulk *bulk)
372 {
373         int i, ret;
374
375         for (i = 0; i < bulk->count; i++) {
376                 ret = clk_enable(&bulk->clks[i]);
377                 if (ret < 0 && ret != -ENOSYS)
378                         return ret;
379         }
380
381         return 0;
382 }
383
384 int clk_disable(struct clk *clk)
385 {
386         const struct clk_ops *ops = clk_dev_ops(clk->dev);
387
388         debug("%s(clk=%p)\n", __func__, clk);
389
390         if (!ops->disable)
391                 return -ENOSYS;
392
393         return ops->disable(clk);
394 }
395
396 int clk_disable_bulk(struct clk_bulk *bulk)
397 {
398         int i, ret;
399
400         for (i = 0; i < bulk->count; i++) {
401                 ret = clk_disable(&bulk->clks[i]);
402                 if (ret < 0 && ret != -ENOSYS)
403                         return ret;
404         }
405
406         return 0;
407 }
408
409 UCLASS_DRIVER(clk) = {
410         .id             = UCLASS_CLK,
411         .name           = "clk",
412 };