1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
8 #include <clk-uclass.h>
14 #include <mach/pic32.h>
15 #include <dt-bindings/clock/microchip,clock.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 /* Primary oscillator */
20 #define SYS_POSC_CLK_HZ 24000000
23 #define SYS_FRC_CLK_HZ 8000000
27 #define OSCTUNE 0x0010
28 #define SPLLCON 0x0020
29 #define REFO1CON 0x0080
30 #define REFO1TRIM 0x0090
34 #define ICLK_MASK 0x00000080
35 #define PLLIDIV_MASK 0x00000007
36 #define PLLODIV_MASK 0x00000007
37 #define CUROSC_MASK 0x00000007
38 #define PLLMUL_MASK 0x0000007F
39 #define FRCDIV_MASK 0x00000007
42 #define PBDIV_MASK 0x00000007
45 #define SCLK_SRC_FRC1 0
46 #define SCLK_SRC_SPLL 1
47 #define SCLK_SRC_POSC 2
48 #define SCLK_SRC_FRC2 7
50 /* Reference Oscillator Control Reg fields */
51 #define REFO_SEL_MASK 0x0f
52 #define REFO_SEL_SHIFT 0
53 #define REFO_ACTIVE BIT(8)
54 #define REFO_DIVSW_EN BIT(9)
55 #define REFO_OE BIT(12)
56 #define REFO_ON BIT(15)
57 #define REFO_DIV_SHIFT 16
58 #define REFO_DIV_MASK 0x7fff
60 /* Reference Oscillator Trim Register Fields */
61 #define REFO_TRIM_REG 0x10
62 #define REFO_TRIM_MASK 0x1ff
63 #define REFO_TRIM_SHIFT 23
64 #define REFO_TRIM_MAX 511
66 #define ROCLK_SRC_SCLK 0x0
67 #define ROCLK_SRC_SPLL 0x7
68 #define ROCLK_SRC_ROCLKI 0x8
71 #define MPLL_IDIV 0x3f
72 #define MPLL_MULT 0xff
73 #define MPLL_ODIV1 0x7
74 #define MPLL_ODIV2 0x7
75 #define MPLL_VREG_RDY BIT(23)
76 #define MPLL_RDY BIT(31)
77 #define MPLL_IDIV_SHIFT 0
78 #define MPLL_MULT_SHIFT 8
79 #define MPLL_ODIV1_SHIFT 24
80 #define MPLL_ODIV2_SHIFT 27
81 #define MPLL_IDIV_INIT 0x03
82 #define MPLL_MULT_INIT 0x32
83 #define MPLL_ODIV1_INIT 0x02
84 #define MPLL_ODIV2_INIT 0x01
86 struct pic32_clk_priv {
88 void __iomem *syscfg_base;
91 static ulong pic32_get_pll_rate(struct pic32_clk_priv *priv)
93 u32 iclk, idiv, odiv, mult;
96 v = readl(priv->iobase + SPLLCON);
97 iclk = (v & ICLK_MASK);
98 idiv = ((v >> 8) & PLLIDIV_MASK) + 1;
99 odiv = ((v >> 24) & PLLODIV_MASK);
100 mult = ((v >> 16) & PLLMUL_MASK) + 1;
102 plliclk = iclk ? SYS_FRC_CLK_HZ : SYS_POSC_CLK_HZ;
111 return ((plliclk / idiv) * mult) / odiv;
114 static ulong pic32_get_sysclk(struct pic32_clk_priv *priv)
122 v = readl(priv->iobase + OSCCON);
123 curr_osc = (v >> 12) & CUROSC_MASK;
127 frcdiv = ((v >> 24) & FRCDIV_MASK);
128 div = ((1 << frcdiv) + 1) + (128 * (frcdiv == 7));
129 hz = SYS_FRC_CLK_HZ / div;
133 hz = pic32_get_pll_rate(priv);
137 hz = SYS_POSC_CLK_HZ;
142 printf("clk: unknown sclk_src.\n");
149 static ulong pic32_get_pbclk(struct pic32_clk_priv *priv, int periph)
154 WARN_ON((periph < PB1CLK) || (periph > PB7CLK));
156 clk_freq = pic32_get_sysclk(priv);
158 reg = priv->iobase + PB1DIV + (periph - PB1CLK) * 0x10;
159 div = (readl(reg) & PBDIV_MASK) + 1;
161 return clk_freq / div;
164 static ulong pic32_get_cpuclk(struct pic32_clk_priv *priv)
166 return pic32_get_pbclk(priv, PB7CLK);
169 static ulong pic32_set_refclk(struct pic32_clk_priv *priv, int periph,
170 int parent_rate, int rate, int parent_id)
176 WARN_ON((periph < REF1CLK) || (periph > REF5CLK));
178 /* calculate dividers,
179 * rate = parent_rate / [2 * (div + (trim / 512))]
181 if (parent_rate <= rate) {
185 div = parent_rate / (rate << 1);
189 frac -= (u64)(div << 9);
190 trim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX : (u32)frac;
193 reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20;
196 writel(REFO_ON | REFO_OE, reg + _CLR_OFFSET);
198 /* wait till previous src change is active */
199 wait_for_bit_le32(reg, REFO_DIVSW_EN | REFO_ACTIVE,
200 false, CONFIG_SYS_HZ, false);
204 v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT);
205 v |= (parent_id << REFO_SEL_SHIFT);
208 v &= ~(REFO_DIV_MASK << REFO_DIV_SHIFT);
209 v |= (div << REFO_DIV_SHIFT);
213 v = readl(reg + REFO_TRIM_REG);
214 v &= ~(REFO_TRIM_MASK << REFO_TRIM_SHIFT);
215 v |= (trim << REFO_TRIM_SHIFT);
216 writel(v, reg + REFO_TRIM_REG);
219 writel(REFO_ON | REFO_OE, reg + _SET_OFFSET);
222 writel(REFO_DIVSW_EN, reg + _SET_OFFSET);
224 /* wait for divider switching to complete */
225 return wait_for_bit_le32(reg, REFO_DIVSW_EN, false,
226 CONFIG_SYS_HZ, false);
229 static ulong pic32_get_refclk(struct pic32_clk_priv *priv, int periph)
231 u32 rodiv, rotrim, rosel, v, parent_rate;
235 WARN_ON((periph < REF1CLK) || (periph > REF5CLK));
237 reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20;
240 rosel = (v >> REFO_SEL_SHIFT) & REFO_SEL_MASK;
242 rodiv = (v >> REFO_DIV_SHIFT) & REFO_DIV_MASK;
245 v = readl(reg + REFO_TRIM_REG);
246 rotrim = (v >> REFO_TRIM_SHIFT) & REFO_TRIM_MASK;
251 /* get parent rate */
254 parent_rate = pic32_get_cpuclk(priv);
257 parent_rate = pic32_get_pll_rate(priv);
265 * rate = parent_rate / [2 * (div + (trim / 512))]
270 rate64 = parent_rate;
272 do_div(rate64, rodiv);
275 v = parent_rate / (rodiv << 1);
280 static ulong pic32_get_mpll_rate(struct pic32_clk_priv *priv)
286 v = readl(priv->syscfg_base + CFGMPLL);
287 idiv = v & MPLL_IDIV;
288 mul = (v >> MPLL_MULT_SHIFT) & MPLL_MULT;
289 odiv1 = (v >> MPLL_ODIV1_SHIFT) & MPLL_ODIV1;
290 odiv2 = (v >> MPLL_ODIV2_SHIFT) & MPLL_ODIV2;
292 rate = (SYS_POSC_CLK_HZ / idiv) * mul;
299 static int pic32_mpll_init(struct pic32_clk_priv *priv)
304 v = (MPLL_IDIV_INIT << MPLL_IDIV_SHIFT) |
305 (MPLL_MULT_INIT << MPLL_MULT_SHIFT) |
306 (MPLL_ODIV1_INIT << MPLL_ODIV1_SHIFT) |
307 (MPLL_ODIV2_INIT << MPLL_ODIV2_SHIFT);
309 writel(v, priv->syscfg_base + CFGMPLL);
312 mask = MPLL_RDY | MPLL_VREG_RDY;
313 return wait_for_bit_le32(priv->syscfg_base + CFGMPLL, mask,
314 true, get_tbclk(), false);
317 static void pic32_clk_init(struct udevice *dev)
319 const void *blob = gd->fdt_blob;
320 struct pic32_clk_priv *priv;
325 priv = dev_get_priv(dev);
326 pll_hz = pic32_get_pll_rate(priv);
328 /* Initialize REFOs as not initialized and enabled on reset. */
329 for (i = REF1CLK; i <= REF5CLK; i++) {
330 snprintf(propname, sizeof(propname),
331 "microchip,refo%d-frequency", i - REF1CLK + 1);
332 rate = fdtdec_get_int(blob, dev_of_offset(dev), propname, 0);
334 pic32_set_refclk(priv, i, pll_hz, rate, ROCLK_SRC_SPLL);
338 pic32_mpll_init(priv);
341 static ulong pic32_get_rate(struct clk *clk)
343 struct pic32_clk_priv *priv = dev_get_priv(clk->dev);
347 case PB1CLK ... PB7CLK:
348 rate = pic32_get_pbclk(priv, clk->id);
350 case REF1CLK ... REF5CLK:
351 rate = pic32_get_refclk(priv, clk->id);
354 rate = pic32_get_pll_rate(priv);
357 rate = pic32_get_mpll_rate(priv);
367 static ulong pic32_set_rate(struct clk *clk, ulong rate)
369 struct pic32_clk_priv *priv = dev_get_priv(clk->dev);
373 case REF1CLK ... REF5CLK:
374 pll_hz = pic32_get_pll_rate(priv);
375 pic32_set_refclk(priv, clk->id, pll_hz, rate, ROCLK_SRC_SPLL);
384 static struct clk_ops pic32_pic32_clk_ops = {
385 .set_rate = pic32_set_rate,
386 .get_rate = pic32_get_rate,
389 static int pic32_clk_probe(struct udevice *dev)
391 struct pic32_clk_priv *priv = dev_get_priv(dev);
395 addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
397 if (addr == FDT_ADDR_T_NONE)
400 priv->iobase = ioremap(addr, size);
404 priv->syscfg_base = pic32_get_syscfg_base();
406 /* initialize clocks */
412 static const struct udevice_id pic32_clk_ids[] = {
413 { .compatible = "microchip,pic32mzda-clk"},
417 U_BOOT_DRIVER(pic32_clk) = {
420 .of_match = pic32_clk_ids,
421 .flags = DM_FLAG_PRE_RELOC,
422 .ops = &pic32_pic32_clk_ops,
423 .probe = pic32_clk_probe,
424 .priv_auto_alloc_size = sizeof(struct pic32_clk_priv),