2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0
13 #include <asm/arch/clock.h>
14 #include <asm/arch/cru_rk3288.h>
15 #include <asm/arch/grf_rk3288.h>
16 #include <asm/arch/hardware.h>
17 #include <dt-bindings/clock/rk3288-cru.h>
18 #include <dm/device-internal.h>
20 #include <dm/uclass-internal.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 struct rk3288_clk_plat {
25 enum rk_clk_id clk_id;
28 struct rk3288_clk_priv {
29 struct rk3288_grf *grf;
30 struct rk3288_cru *cru;
41 VCO_MAX_HZ = 2200U * 1000000,
42 VCO_MIN_HZ = 440 * 1000000,
43 OUTPUT_MAX_HZ = 2200U * 1000000,
44 OUTPUT_MIN_HZ = 27500000,
45 FREF_MAX_HZ = 2200U * 1000000,
46 FREF_MIN_HZ = 269 * 1000000,
57 PLL_BWADJ_MASK = 0x0fff,
62 /* CLKSEL1: pd bus clk pll sel: codec or general */
63 PD_BUS_SEL_PLL_MASK = 15,
67 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
68 PD_BUS_PCLK_DIV_SHIFT = 12,
69 PD_BUS_PCLK_DIV_MASK = 7,
71 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
72 PD_BUS_HCLK_DIV_SHIFT = 8,
73 PD_BUS_HCLK_DIV_MASK = 3,
75 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
76 PD_BUS_ACLK_DIV0_SHIFT = 3,
77 PD_BUS_ACLK_DIV0_MASK = 0x1f,
78 PD_BUS_ACLK_DIV1_SHIFT = 0,
79 PD_BUS_ACLK_DIV1_MASK = 0x7,
83 * peripheral bus pclk div:
84 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
86 PERI_PCLK_DIV_SHIFT = 12,
87 PERI_PCLK_DIV_MASK = 7,
89 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
90 PERI_HCLK_DIV_SHIFT = 8,
91 PERI_HCLK_DIV_MASK = 3,
94 * peripheral bus aclk div:
95 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
97 PERI_ACLK_DIV_SHIFT = 0,
98 PERI_ACLK_DIV_MASK = 0x1f,
100 SOCSTS_DPLL_LOCK = 1 << 5,
101 SOCSTS_APLL_LOCK = 1 << 6,
102 SOCSTS_CPLL_LOCK = 1 << 7,
103 SOCSTS_GPLL_LOCK = 1 << 8,
104 SOCSTS_NPLL_LOCK = 1 << 9,
107 #define RATE_TO_DIV(input_rate, output_rate) \
108 ((input_rate) / (output_rate) - 1);
110 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
112 #define PLL_DIVISORS(hz, _nr, _no) {\
113 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
114 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
115 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
116 "divisors on line " __stringify(__LINE__));
118 /* Keep divisors as low as possible to reduce jitter and power usage */
119 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
120 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
121 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
123 int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp)
127 for (uclass_find_first_device(UCLASS_CLK, &dev);
129 uclass_find_next_device(&dev)) {
130 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
132 if (plat->clk_id == clk_id) {
134 return device_probe(dev);
141 void *rockchip_get_cru(void)
143 struct rk3288_clk_priv *priv;
147 ret = rkclk_get_clk(CLK_GENERAL, &dev);
150 priv = dev_get_priv(dev);
154 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
155 const struct pll_div *div)
157 int pll_id = rk_pll_id(clk_id);
158 struct rk3288_pll *pll = &cru->pll[pll_id];
159 /* All PLLs have same VCO and output frequency range restrictions. */
160 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
161 uint output_hz = vco_hz / div->no;
163 debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
164 pll, div->nf, div->nr, div->no, vco_hz, output_hz);
165 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
166 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
167 (div->no == 1 || !(div->no % 2)));
170 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
172 rk_clrsetreg(&pll->con0,
173 CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
174 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
175 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
176 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
180 /* return form rest */
181 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
186 static inline unsigned int log2(unsigned int value)
188 return fls(value) - 1;
191 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
194 static const struct pll_div dpll_cfg[] = {
195 {.nf = 25, .nr = 2, .no = 1},
196 {.nf = 400, .nr = 9, .no = 2},
197 {.nf = 500, .nr = 9, .no = 2},
198 {.nf = 100, .nr = 3, .no = 1},
202 debug("%s: cru=%p, grf=%p, hz=%u\n", __func__, cru, grf, hz);
207 case 533000000: /* actually 533.3P MHz */
210 case 666000000: /* actually 666.6P MHz */
217 debug("Unsupported SDRAM frequency, add to clock.c!");
221 /* pll enter slow-mode */
222 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
223 DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
225 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
227 /* wait for pll lock */
228 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
231 /* PLL enter normal-mode */
232 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
233 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
238 #ifndef CONFIG_SPL_BUILD
239 #define VCO_MAX_KHZ 2200000
240 #define VCO_MIN_KHZ 440000
241 #define FREF_MAX_KHZ 2200000
242 #define FREF_MIN_KHZ 269
244 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
246 uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
248 uint diff_khz, best_diff_khz;
249 const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
252 uint freq_khz = freq_hz / 1000;
255 printf("%s: the frequency can not be 0 Hz\n", __func__);
259 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
261 *ext_div = DIV_ROUND_UP(no, max_no);
262 no = DIV_ROUND_UP(no, *ext_div);
265 /* only even divisors (and 1) are supported */
267 no = DIV_ROUND_UP(no, 2) * 2;
269 vco_khz = freq_khz * no;
273 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
274 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
281 best_diff_khz = vco_khz;
282 for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
283 fref_khz = ref_khz / nr;
284 if (fref_khz < FREF_MIN_KHZ)
286 if (fref_khz > FREF_MAX_KHZ)
289 nf = vco_khz / fref_khz;
292 diff_khz = vco_khz - nf * fref_khz;
293 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
295 diff_khz = fref_khz - diff_khz;
298 if (diff_khz >= best_diff_khz)
301 best_diff_khz = diff_khz;
306 if (best_diff_khz > 4 * 1000) {
307 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
308 __func__, freq_hz, best_diff_khz * 1000);
315 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
316 int periph, unsigned int rate_hz)
318 struct pll_div npll_config = {0};
322 ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
326 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
327 NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
328 rkclk_set_pll(cru, CLK_NEW, &npll_config);
330 /* waiting for pll lock */
332 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
337 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
338 NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
340 /* vop dclk source clk: npll,dclk_div: 1 */
343 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
344 (lcdc_div - 1) << 8 | 2 << 0);
347 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
348 (lcdc_div - 1) << 8 | 2 << 6);
356 #ifdef CONFIG_SPL_BUILD
357 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
363 /* pll enter slow-mode */
364 rk_clrsetreg(&cru->cru_mode_con,
365 GPLL_MODE_MASK << GPLL_MODE_SHIFT |
366 CPLL_MODE_MASK << CPLL_MODE_SHIFT,
367 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
368 CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
371 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
372 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
374 /* waiting for pll lock */
375 while ((readl(&grf->soc_status[1]) &
376 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
377 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
381 * pd_bus clock pll source selection and
382 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
384 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
385 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
386 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
387 assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
388 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
390 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
391 assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
392 PD_BUS_ACLK_HZ && pclk_div < 0x7);
394 rk_clrsetreg(&cru->cru_clksel_con[1],
395 PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
396 PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
397 PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
398 PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
399 pclk_div << PD_BUS_PCLK_DIV_SHIFT |
400 hclk_div << PD_BUS_HCLK_DIV_SHIFT |
401 aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
405 * peri clock pll source selection and
406 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
408 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
409 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
411 hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
412 assert((1 << hclk_div) * PERI_HCLK_HZ ==
413 PERI_ACLK_HZ && (hclk_div < 0x4));
415 pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
416 assert((1 << pclk_div) * PERI_PCLK_HZ ==
417 PERI_ACLK_HZ && (pclk_div < 0x4));
419 rk_clrsetreg(&cru->cru_clksel_con[10],
420 PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
421 PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
422 PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
423 pclk_div << PERI_PCLK_DIV_SHIFT |
424 hclk_div << PERI_HCLK_DIV_SHIFT |
425 aclk_div << PERI_ACLK_DIV_SHIFT);
427 /* PLL enter normal-mode */
428 rk_clrsetreg(&cru->cru_mode_con,
429 GPLL_MODE_MASK << GPLL_MODE_SHIFT |
430 CPLL_MODE_MASK << CPLL_MODE_SHIFT,
431 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
432 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
436 /* Get pll rate by id */
437 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
438 enum rk_clk_id clk_id)
442 int pll_id = rk_pll_id(clk_id);
443 struct rk3288_pll *pll = &cru->pll[pll_id];
444 static u8 clk_shift[CLK_COUNT] = {
445 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
446 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
450 con = readl(&cru->cru_mode_con);
451 shift = clk_shift[clk_id];
452 switch ((con >> shift) & APLL_MODE_MASK) {
455 case APLL_MODE_NORMAL:
457 con = readl(&pll->con0);
458 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
459 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
460 con = readl(&pll->con1);
461 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
463 return (24 * nf / (nr * no)) * 1000000;
470 static ulong rk3288_clk_get_rate(struct udevice *dev)
472 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
473 struct rk3288_clk_priv *priv = dev_get_priv(dev);
475 debug("%s\n", dev->name);
476 return rkclk_pll_get_rate(priv->cru, plat->clk_id);
479 static ulong rk3288_clk_set_rate(struct udevice *dev, ulong rate)
481 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
482 struct rk3288_clk_priv *priv = dev_get_priv(dev);
484 debug("%s\n", dev->name);
485 switch (plat->clk_id) {
487 rkclk_configure_ddr(priv->cru, priv->grf, rate);
496 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
505 con = readl(&cru->cru_clksel_con[12]);
506 mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
507 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
510 con = readl(&cru->cru_clksel_con[11]);
511 mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
512 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
515 con = readl(&cru->cru_clksel_con[12]);
516 mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
517 div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
523 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
524 return DIV_TO_RATE(src_rate, div);
527 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
528 int periph, uint freq)
533 debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
534 src_clk_div = RATE_TO_DIV(gclk_rate, freq);
536 if (src_clk_div > 0x3f) {
537 src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
538 mux = EMMC_PLL_SELECT_24MHZ;
539 assert((int)EMMC_PLL_SELECT_24MHZ ==
540 (int)MMC0_PLL_SELECT_24MHZ);
542 mux = EMMC_PLL_SELECT_GENERAL;
543 assert((int)EMMC_PLL_SELECT_GENERAL ==
544 (int)MMC0_PLL_SELECT_GENERAL);
548 rk_clrsetreg(&cru->cru_clksel_con[12],
549 EMMC_PLL_MASK << EMMC_PLL_SHIFT |
550 EMMC_DIV_MASK << EMMC_DIV_SHIFT,
551 mux << EMMC_PLL_SHIFT |
552 (src_clk_div - 1) << EMMC_DIV_SHIFT);
555 rk_clrsetreg(&cru->cru_clksel_con[11],
556 MMC0_PLL_MASK << MMC0_PLL_SHIFT |
557 MMC0_DIV_MASK << MMC0_DIV_SHIFT,
558 mux << MMC0_PLL_SHIFT |
559 (src_clk_div - 1) << MMC0_DIV_SHIFT);
562 rk_clrsetreg(&cru->cru_clksel_con[12],
563 SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
564 SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
565 mux << SDIO0_PLL_SHIFT |
566 (src_clk_div - 1) << SDIO0_DIV_SHIFT);
572 return rockchip_mmc_get_clk(cru, gclk_rate, periph);
575 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
583 con = readl(&cru->cru_clksel_con[25]);
584 mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
585 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
588 con = readl(&cru->cru_clksel_con[25]);
589 mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
590 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
593 con = readl(&cru->cru_clksel_con[39]);
594 mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
595 div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
600 assert(mux == SPI0_PLL_SELECT_GENERAL);
602 return DIV_TO_RATE(gclk_rate, div);
605 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
606 int periph, uint freq)
610 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
611 src_clk_div = RATE_TO_DIV(gclk_rate, freq);
614 rk_clrsetreg(&cru->cru_clksel_con[25],
615 SPI0_PLL_MASK << SPI0_PLL_SHIFT |
616 SPI0_DIV_MASK << SPI0_DIV_SHIFT,
617 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
618 src_clk_div << SPI0_DIV_SHIFT);
621 rk_clrsetreg(&cru->cru_clksel_con[25],
622 SPI1_PLL_MASK << SPI1_PLL_SHIFT |
623 SPI1_DIV_MASK << SPI1_DIV_SHIFT,
624 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
625 src_clk_div << SPI1_DIV_SHIFT);
628 rk_clrsetreg(&cru->cru_clksel_con[39],
629 SPI2_PLL_MASK << SPI2_PLL_SHIFT |
630 SPI2_DIV_MASK << SPI2_DIV_SHIFT,
631 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
632 src_clk_div << SPI2_DIV_SHIFT);
638 return rockchip_spi_get_clk(cru, gclk_rate, periph);
641 static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
643 struct rk3288_clk_priv *priv = dev_get_priv(dev);
644 struct udevice *gclk;
645 ulong new_rate, gclk_rate;
648 ret = rkclk_get_clk(CLK_GENERAL, &gclk);
651 gclk_rate = clk_get_rate(gclk);
656 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph);
661 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, periph);
677 static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
679 struct rk3288_clk_priv *priv = dev_get_priv(dev);
680 struct rk3288_cru *cru = priv->cru;
681 struct udevice *gclk;
682 ulong new_rate, gclk_rate;
685 ret = rkclk_get_clk(CLK_GENERAL, &gclk);
688 gclk_rate = clk_get_rate(gclk);
693 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, periph, rate);
698 new_rate = rockchip_spi_set_clk(cru, gclk_rate, periph, rate);
700 #ifndef CONFIG_SPL_BUILD
703 new_rate = rockchip_vop_set_clk(cru, priv->grf, periph, rate);
706 /* clk_edp_24M source: 24M */
707 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
710 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
712 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
719 /* vop aclk source clk: cpll */
720 div = CPLL_HZ / rate;
721 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
725 rk_clrsetreg(&cru->cru_clksel_con[31],
727 0 << 6 | (div - 1) << 0);
730 rk_clrsetreg(&cru->cru_clksel_con[31],
732 0 << 14 | (div - 1) << 8);
739 /* enable pclk hdmi ctrl */
740 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
742 /* software reset hdmi */
743 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
745 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
756 static struct clk_ops rk3288_clk_ops = {
757 .get_rate = rk3288_clk_get_rate,
758 .set_rate = rk3288_clk_set_rate,
759 .set_periph_rate = rk3288_set_periph_rate,
760 .get_periph_rate = rk3288_get_periph_rate,
763 static int rk3288_clk_probe(struct udevice *dev)
765 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
766 struct rk3288_clk_priv *priv = dev_get_priv(dev);
768 if (plat->clk_id != CLK_OSC) {
769 struct rk3288_clk_priv *parent_priv = dev_get_priv(dev->parent);
771 priv->cru = parent_priv->cru;
772 priv->grf = parent_priv->grf;
775 priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
776 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
777 #ifdef CONFIG_SPL_BUILD
778 rkclk_init(priv->cru, priv->grf);
784 static const char *const clk_name[CLK_COUNT] = {
793 static int rk3288_clk_bind(struct udevice *dev)
795 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
798 /* We only need to set up the root clock */
799 if (dev->of_offset == -1) {
800 plat->clk_id = CLK_OSC;
804 /* Create devices for P main clocks */
805 for (pll = 1; pll < CLK_COUNT; pll++) {
806 struct udevice *child;
807 struct rk3288_clk_plat *cplat;
809 debug("%s %s\n", __func__, clk_name[pll]);
810 ret = device_bind_driver(dev, "clk_rk3288", clk_name[pll],
814 cplat = dev_get_platdata(child);
818 /* The reset driver does not have a device node, so bind it here */
819 ret = device_bind_driver(gd->dm_root, "rk3288_reset", "reset", &dev);
821 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
826 static const struct udevice_id rk3288_clk_ids[] = {
827 { .compatible = "rockchip,rk3288-cru" },
831 U_BOOT_DRIVER(clk_rk3288) = {
832 .name = "clk_rk3288",
834 .of_match = rk3288_clk_ids,
835 .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
836 .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
837 .ops = &rk3288_clk_ops,
838 .bind = rk3288_clk_bind,
839 .probe = rk3288_clk_probe,