2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <clk-uclass.h>
11 #include <stm32_rcc.h>
14 #include <asm/arch/stm32.h>
15 #include <asm/arch/stm32_pwr.h>
17 #include <dt-bindings/mfd/stm32f7-rcc.h>
19 #define RCC_CR_HSION BIT(0)
20 #define RCC_CR_HSEON BIT(16)
21 #define RCC_CR_HSERDY BIT(17)
22 #define RCC_CR_HSEBYP BIT(18)
23 #define RCC_CR_CSSON BIT(19)
24 #define RCC_CR_PLLON BIT(24)
25 #define RCC_CR_PLLRDY BIT(25)
26 #define RCC_CR_PLLSAION BIT(28)
27 #define RCC_CR_PLLSAIRDY BIT(29)
29 #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
30 #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
31 #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
32 #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
33 #define RCC_PLLCFGR_PLLSRC BIT(22)
34 #define RCC_PLLCFGR_PLLM_SHIFT 0
35 #define RCC_PLLCFGR_PLLN_SHIFT 6
36 #define RCC_PLLCFGR_PLLP_SHIFT 16
37 #define RCC_PLLCFGR_PLLQ_SHIFT 24
39 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
40 #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
41 #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
42 #define RCC_CFGR_SW0 BIT(0)
43 #define RCC_CFGR_SW1 BIT(1)
44 #define RCC_CFGR_SW_MASK GENMASK(1, 0)
45 #define RCC_CFGR_SW_HSI 0
46 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
47 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
48 #define RCC_CFGR_SWS0 BIT(2)
49 #define RCC_CFGR_SWS1 BIT(3)
50 #define RCC_CFGR_SWS_MASK GENMASK(3, 2)
51 #define RCC_CFGR_SWS_HSI 0
52 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
53 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
54 #define RCC_CFGR_HPRE_SHIFT 4
55 #define RCC_CFGR_PPRE1_SHIFT 10
56 #define RCC_CFGR_PPRE2_SHIFT 13
58 #define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6)
59 #define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16)
60 #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
61 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
62 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
63 #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
64 #define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29)
66 #define RCC_DCKCFGRX_TIMPRE BIT(24)
67 #define RCC_DCKCFGRX_CK48MSEL BIT(27)
68 #define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
69 #define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
72 * RCC AHB1ENR specific definitions
74 #define RCC_AHB1ENR_ETHMAC_EN BIT(25)
75 #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
76 #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
79 * RCC APB1ENR specific definitions
81 #define RCC_APB1ENR_TIM2EN BIT(0)
82 #define RCC_APB1ENR_PWREN BIT(28)
85 * RCC APB2ENR specific definitions
87 #define RCC_APB2ENR_SYSCFGEN BIT(14)
88 #define RCC_APB2ENR_SAI1EN BIT(22)
90 static const struct stm32_clk_info stm32f4_clk_info = {
97 .apb1_psc = APB_PSC_4,
98 .apb2_psc = APB_PSC_2,
100 .has_overdrive = false,
104 static const struct stm32_clk_info stm32f7_clk_info = {
110 .ahb_psc = AHB_PSC_1,
111 .apb1_psc = APB_PSC_4,
112 .apb2_psc = APB_PSC_2,
114 .has_overdrive = true,
119 struct stm32_rcc_regs *base;
120 struct stm32_pwr_regs *pwr_regs;
121 struct stm32_clk_info info;
122 unsigned long hse_rate;
125 static int configure_clocks(struct udevice *dev)
127 struct stm32_clk *priv = dev_get_priv(dev);
128 struct stm32_rcc_regs *regs = priv->base;
129 struct stm32_pwr_regs *pwr = priv->pwr_regs;
130 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
133 /* Reset RCC configuration */
134 setbits_le32(®s->cr, RCC_CR_HSION);
135 writel(0, ®s->cfgr); /* Reset CFGR */
136 clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON
137 | RCC_CR_PLLON | RCC_CR_PLLSAION));
138 writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */
139 clrbits_le32(®s->cr, RCC_CR_HSEBYP);
140 writel(0, ®s->cir); /* Disable all interrupts */
142 /* Configure for HSE+PLL operation */
143 setbits_le32(®s->cr, RCC_CR_HSEON);
144 while (!(readl(®s->cr) & RCC_CR_HSERDY))
147 setbits_le32(®s->cfgr, ((
148 sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
149 | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
150 | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
152 /* Configure the main PLL */
153 setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
154 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
155 sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
156 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
157 sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
158 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
159 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
160 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
161 sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
163 /* Configure the SAI PLL to get a 48 MHz source */
164 pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 |
165 RCC_PLLSAICFGR_PLLSAIP_4;
166 pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT;
167 writel(pllsaicfgr, ®s->pllsaicfgr);
169 /* Enable the main PLL */
170 setbits_le32(®s->cr, RCC_CR_PLLON);
171 while (!(readl(®s->cr) & RCC_CR_PLLRDY))
174 if (priv->info.v2) { /*stm32f7 case */
175 /* select PLLSAI as 48MHz clock source */
176 setbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
178 /* select 48MHz as SDMMC1 clock source */
179 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
181 /* select 48MHz as SDMMC2 clock source */
182 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
183 } else { /* stm32f4 case */
184 /* select PLLSAI as 48MHz clock source */
185 setbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
187 /* select 48MHz as SDMMC1 clock source */
188 clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
191 /* Enable the SAI PLL */
192 setbits_le32(®s->cr, RCC_CR_PLLSAION);
193 while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY))
196 setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
198 if (priv->info.has_overdrive) {
200 * Enable high performance mode
201 * System frequency up to 200 MHz
203 setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
205 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
207 /* Enable the Over-drive switch */
208 setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
210 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
214 stm32_flash_latency_cfg(5);
215 clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
216 setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL);
218 while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
221 /* gate the SAI clock, needed for MMC 1&2 clocks */
222 setbits_le32(®s->apb2enr, RCC_APB2ENR_SAI1EN);
224 #ifdef CONFIG_ETH_DESIGNWARE
225 /* gate the SYSCFG clock, needed to set RMII ethernet interface */
226 setbits_le32(®s->apb2enr, RCC_APB2ENR_SYSCFGEN);
232 static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
235 struct stm32_rcc_regs *regs = priv->base;
236 u16 pllq, pllm, pllsain, pllsaip;
239 pllq = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
240 >> RCC_PLLCFGR_PLLQ_SHIFT;
242 if (priv->info.v2) /*stm32f7 case */
243 pllsai = readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
245 pllsai = readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
248 /* PLL48CLK is selected from PLLSAI, get PLLSAI value */
249 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
250 pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK)
251 >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
252 pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK)
253 >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
254 return ((priv->hse_rate / pllm) * pllsain) / pllsaip;
256 /* PLL48CLK is selected from PLLQ */
260 static bool stm32_get_timpre(struct stm32_clk *priv)
262 struct stm32_rcc_regs *regs = priv->base;
265 if (priv->info.v2) /*stm32f7 case */
266 val = readl(®s->dckcfgr2);
268 val = readl(®s->dckcfgr);
269 /* get timer prescaler */
270 return !!(val & RCC_DCKCFGRX_TIMPRE);
273 static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk)
276 /* Prescaler table lookups for clock computation */
277 u8 ahb_psc_table[16] = {
278 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
281 shift = ahb_psc_table[(
282 (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
283 >> RCC_CFGR_HPRE_SHIFT)];
285 return sysclk >> shift;
288 static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb)
290 /* Prescaler table lookups for clock computation */
291 u8 apb_psc_table[8] = {
292 0, 0, 0, 0, 1, 2, 3, 4
296 return apb_psc_table[(
297 (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
298 >> RCC_CFGR_PPRE1_SHIFT)];
300 return apb_psc_table[(
301 (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
302 >> RCC_CFGR_PPRE2_SHIFT)];
305 static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
308 struct stm32_rcc_regs *regs = priv->base;
309 u8 shift = stm32_get_apb_shift(regs, apb);
311 if (stm32_get_timpre(priv))
313 * if APB prescaler is configured to a
314 * division factor of 1, 2 or 4
320 return stm32_get_hclk_rate(regs, sysclk);
322 return (sysclk >> shift) * 4;
326 * if APB prescaler is configured to a
327 * division factor of 1
332 return (sysclk >> shift) * 2;
335 static ulong stm32_clk_get_rate(struct clk *clk)
337 struct stm32_clk *priv = dev_get_priv(clk->dev);
338 struct stm32_rcc_regs *regs = priv->base;
341 u16 pllm, plln, pllp;
343 if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
345 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
346 plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
347 >> RCC_PLLCFGR_PLLN_SHIFT);
348 pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
349 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
350 vco = (priv->hse_rate / pllm) * plln;
358 * AHB CLOCK: 3 x 32 bits consecutive registers are used :
359 * AHB1, AHB2 and AHB3
361 case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
362 return stm32_get_hclk_rate(regs, sysclk);
364 case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
365 /* For timer clock, an additionnal prescaler is used*/
367 case STM32F7_APB1_CLOCK(TIM2):
368 case STM32F7_APB1_CLOCK(TIM3):
369 case STM32F7_APB1_CLOCK(TIM4):
370 case STM32F7_APB1_CLOCK(TIM5):
371 case STM32F7_APB1_CLOCK(TIM6):
372 case STM32F7_APB1_CLOCK(TIM7):
373 case STM32F7_APB1_CLOCK(TIM12):
374 case STM32F7_APB1_CLOCK(TIM13):
375 case STM32F7_APB1_CLOCK(TIM14):
376 return stm32_get_timer_rate(priv, sysclk, APB1);
378 return (sysclk >> stm32_get_apb_shift(regs, APB1));
381 case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
383 * particular case for SDMMC1 and SDMMC2 :
384 * 48Mhz source clock can be from main PLL or from
388 case STM32F7_APB2_CLOCK(SDMMC1):
389 if (readl(®s->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL)
390 /* System clock is selected as SDMMC1 clock */
393 return stm32_clk_pll48clk_rate(priv, vco);
395 case STM32F7_APB2_CLOCK(SDMMC2):
396 if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL)
397 /* System clock is selected as SDMMC2 clock */
400 return stm32_clk_pll48clk_rate(priv, vco);
403 /* For timer clock, an additionnal prescaler is used*/
404 case STM32F7_APB2_CLOCK(TIM1):
405 case STM32F7_APB2_CLOCK(TIM8):
406 case STM32F7_APB2_CLOCK(TIM9):
407 case STM32F7_APB2_CLOCK(TIM10):
408 case STM32F7_APB2_CLOCK(TIM11):
409 return stm32_get_timer_rate(priv, sysclk, APB2);
412 return (sysclk >> stm32_get_apb_shift(regs, APB2));
415 pr_err("clock index %ld out of range\n", clk->id);
420 static ulong stm32_set_rate(struct clk *clk, ulong rate)
425 static int stm32_clk_enable(struct clk *clk)
427 struct stm32_clk *priv = dev_get_priv(clk->dev);
428 struct stm32_rcc_regs *regs = priv->base;
429 u32 offset = clk->id / 32;
430 u32 bit_index = clk->id % 32;
432 debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
433 __func__, clk->id, offset, bit_index);
434 setbits_le32(®s->ahb1enr + offset, BIT(bit_index));
439 static int stm32_clk_probe(struct udevice *dev)
441 struct ofnode_phandle_args args;
442 struct udevice *fixed_clock_dev = NULL;
446 debug("%s\n", __func__);
448 struct stm32_clk *priv = dev_get_priv(dev);
451 addr = dev_read_addr(dev);
452 if (addr == FDT_ADDR_T_NONE)
455 priv->base = (struct stm32_rcc_regs *)addr;
457 switch (dev_get_driver_data(dev)) {
459 memcpy(&priv->info, &stm32f4_clk_info,
460 sizeof(struct stm32_clk_info));
463 memcpy(&priv->info, &stm32f7_clk_info,
464 sizeof(struct stm32_clk_info));
470 /* retrieve HSE frequency (external oscillator) */
471 err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
475 pr_err("Can't find fixed clock (%d)", err);
479 err = clk_request(fixed_clock_dev, &clk);
481 pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
487 * set pllm factor accordingly to the external oscillator
488 * frequency (HSE). For STM32F4 and STM32F7, we want VCO
490 * if input PLL frequency is 25Mhz, divide it by 25
493 priv->hse_rate = clk_get_rate(&clk);
495 if (priv->hse_rate < 1000000) {
496 pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
501 priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
503 if (priv->info.has_overdrive) {
504 err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
507 debug("%s: can't find syscon device (%d)\n", __func__,
512 priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
515 configure_clocks(dev);
520 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
522 debug("%s(clk=%p)\n", __func__, clk);
524 if (args->args_count != 2) {
525 debug("Invaild args_count: %d\n", args->args_count);
529 if (args->args_count)
530 clk->id = args->args[1];
537 static struct clk_ops stm32_clk_ops = {
538 .of_xlate = stm32_clk_of_xlate,
539 .enable = stm32_clk_enable,
540 .get_rate = stm32_clk_get_rate,
541 .set_rate = stm32_set_rate,
544 U_BOOT_DRIVER(stm32fx_clk) = {
545 .name = "stm32fx_rcc_clock",
547 .ops = &stm32_clk_ops,
548 .probe = stm32_clk_probe,
549 .priv_auto_alloc_size = sizeof(struct stm32_clk),
550 .flags = DM_FLAG_PRE_RELOC,