2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <clk-uclass.h>
11 #include <stm32_rcc.h>
14 #include <asm/arch/stm32.h>
15 #include <asm/arch/stm32_pwr.h>
17 #include <dt-bindings/mfd/stm32f7-rcc.h>
19 #define RCC_CR_HSION BIT(0)
20 #define RCC_CR_HSEON BIT(16)
21 #define RCC_CR_HSERDY BIT(17)
22 #define RCC_CR_HSEBYP BIT(18)
23 #define RCC_CR_CSSON BIT(19)
24 #define RCC_CR_PLLON BIT(24)
25 #define RCC_CR_PLLRDY BIT(25)
26 #define RCC_CR_PLLSAION BIT(28)
27 #define RCC_CR_PLLSAIRDY BIT(29)
29 #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
30 #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
31 #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
32 #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
33 #define RCC_PLLCFGR_PLLSRC BIT(22)
34 #define RCC_PLLCFGR_PLLM_SHIFT 0
35 #define RCC_PLLCFGR_PLLN_SHIFT 6
36 #define RCC_PLLCFGR_PLLP_SHIFT 16
37 #define RCC_PLLCFGR_PLLQ_SHIFT 24
39 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
40 #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
41 #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
42 #define RCC_CFGR_SW0 BIT(0)
43 #define RCC_CFGR_SW1 BIT(1)
44 #define RCC_CFGR_SW_MASK GENMASK(1, 0)
45 #define RCC_CFGR_SW_HSI 0
46 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
47 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
48 #define RCC_CFGR_SWS0 BIT(2)
49 #define RCC_CFGR_SWS1 BIT(3)
50 #define RCC_CFGR_SWS_MASK GENMASK(3, 2)
51 #define RCC_CFGR_SWS_HSI 0
52 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
53 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
54 #define RCC_CFGR_HPRE_SHIFT 4
55 #define RCC_CFGR_PPRE1_SHIFT 10
56 #define RCC_CFGR_PPRE2_SHIFT 13
58 #define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6)
59 #define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16)
60 #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
61 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
62 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
63 #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
64 #define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29)
66 #define RCC_DCKCFGRX_TIMPRE BIT(24)
67 #define RCC_DCKCFGRX_CK48MSEL BIT(27)
68 #define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
69 #define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
72 * RCC AHB1ENR specific definitions
74 #define RCC_AHB1ENR_ETHMAC_EN BIT(25)
75 #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
76 #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
79 * RCC APB1ENR specific definitions
81 #define RCC_APB1ENR_TIM2EN BIT(0)
82 #define RCC_APB1ENR_PWREN BIT(28)
85 * RCC APB2ENR specific definitions
87 #define RCC_APB2ENR_SYSCFGEN BIT(14)
88 #define RCC_APB2ENR_SAI1EN BIT(22)
90 static const struct stm32_clk_info stm32f4_clk_info = {
97 .apb1_psc = APB_PSC_4,
98 .apb2_psc = APB_PSC_2,
100 .has_overdrive = false,
104 static const struct stm32_clk_info stm32f7_clk_info = {
110 .ahb_psc = AHB_PSC_1,
111 .apb1_psc = APB_PSC_4,
112 .apb2_psc = APB_PSC_2,
114 .has_overdrive = true,
119 struct stm32_rcc_regs *base;
120 struct stm32_pwr_regs *pwr_regs;
121 struct stm32_clk_info info;
122 unsigned long hse_rate;
125 static int configure_clocks(struct udevice *dev)
127 struct stm32_clk *priv = dev_get_priv(dev);
128 struct stm32_rcc_regs *regs = priv->base;
129 struct stm32_pwr_regs *pwr = priv->pwr_regs;
130 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
132 /* Reset RCC configuration */
133 setbits_le32(®s->cr, RCC_CR_HSION);
134 writel(0, ®s->cfgr); /* Reset CFGR */
135 clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON
136 | RCC_CR_PLLON | RCC_CR_PLLSAION));
137 writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */
138 clrbits_le32(®s->cr, RCC_CR_HSEBYP);
139 writel(0, ®s->cir); /* Disable all interrupts */
141 /* Configure for HSE+PLL operation */
142 setbits_le32(®s->cr, RCC_CR_HSEON);
143 while (!(readl(®s->cr) & RCC_CR_HSERDY))
146 setbits_le32(®s->cfgr, ((
147 sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
148 | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
149 | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
151 /* Configure the main PLL */
152 setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
153 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
154 sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
155 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
156 sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
157 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
158 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
159 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
160 sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
162 /* configure SDMMC clock */
163 if (priv->info.v2) { /*stm32f7 case */
164 /* select PLLQ as 48MHz clock source */
165 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
167 /* select 48MHz as SDMMC1 clock source */
168 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
170 /* select 48MHz as SDMMC2 clock source */
171 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
172 } else { /* stm32f4 case */
173 /* select PLLQ as 48MHz clock source */
174 clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
176 /* select 48MHz as SDMMC1 clock source */
177 clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
180 /* Enable the main PLL */
181 setbits_le32(®s->cr, RCC_CR_PLLON);
182 while (!(readl(®s->cr) & RCC_CR_PLLRDY))
185 setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
187 if (priv->info.has_overdrive) {
189 * Enable high performance mode
190 * System frequency up to 200 MHz
192 setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
194 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
196 /* Enable the Over-drive switch */
197 setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
199 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
203 stm32_flash_latency_cfg(5);
204 clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
205 setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL);
207 while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
211 #ifdef CONFIG_ETH_DESIGNWARE
212 /* gate the SYSCFG clock, needed to set RMII ethernet interface */
213 setbits_le32(®s->apb2enr, RCC_APB2ENR_SYSCFGEN);
219 static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
222 struct stm32_rcc_regs *regs = priv->base;
223 u16 pllq, pllm, pllsain, pllsaip;
226 pllq = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
227 >> RCC_PLLCFGR_PLLQ_SHIFT;
229 if (priv->info.v2) /*stm32f7 case */
230 pllsai = readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
232 pllsai = readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
235 /* PLL48CLK is selected from PLLSAI, get PLLSAI value */
236 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
237 pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK)
238 >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
239 pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIP_MASK)
240 >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
241 return ((priv->hse_rate / pllm) * pllsain) / pllsaip;
243 /* PLL48CLK is selected from PLLQ */
247 static bool stm32_get_timpre(struct stm32_clk *priv)
249 struct stm32_rcc_regs *regs = priv->base;
252 if (priv->info.v2) /*stm32f7 case */
253 val = readl(®s->dckcfgr2);
255 val = readl(®s->dckcfgr);
256 /* get timer prescaler */
257 return !!(val & RCC_DCKCFGRX_TIMPRE);
260 static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk)
263 /* Prescaler table lookups for clock computation */
264 u8 ahb_psc_table[16] = {
265 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
268 shift = ahb_psc_table[(
269 (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
270 >> RCC_CFGR_HPRE_SHIFT)];
272 return sysclk >> shift;
275 static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb)
277 /* Prescaler table lookups for clock computation */
278 u8 apb_psc_table[8] = {
279 0, 0, 0, 0, 1, 2, 3, 4
283 return apb_psc_table[(
284 (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
285 >> RCC_CFGR_PPRE1_SHIFT)];
287 return apb_psc_table[(
288 (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
289 >> RCC_CFGR_PPRE2_SHIFT)];
292 static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
295 struct stm32_rcc_regs *regs = priv->base;
296 u8 shift = stm32_get_apb_shift(regs, apb);
298 if (stm32_get_timpre(priv))
300 * if APB prescaler is configured to a
301 * division factor of 1, 2 or 4
307 return stm32_get_hclk_rate(regs, sysclk);
309 return (sysclk >> shift) * 4;
313 * if APB prescaler is configured to a
314 * division factor of 1
319 return (sysclk >> shift) * 2;
322 static ulong stm32_clk_get_rate(struct clk *clk)
324 struct stm32_clk *priv = dev_get_priv(clk->dev);
325 struct stm32_rcc_regs *regs = priv->base;
328 u16 pllm, plln, pllp;
330 if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
332 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
333 plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
334 >> RCC_PLLCFGR_PLLN_SHIFT);
335 pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
336 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
337 vco = (priv->hse_rate / pllm) * plln;
345 * AHB CLOCK: 3 x 32 bits consecutive registers are used :
346 * AHB1, AHB2 and AHB3
348 case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
349 return stm32_get_hclk_rate(regs, sysclk);
351 case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
352 /* For timer clock, an additionnal prescaler is used*/
354 case STM32F7_APB1_CLOCK(TIM2):
355 case STM32F7_APB1_CLOCK(TIM3):
356 case STM32F7_APB1_CLOCK(TIM4):
357 case STM32F7_APB1_CLOCK(TIM5):
358 case STM32F7_APB1_CLOCK(TIM6):
359 case STM32F7_APB1_CLOCK(TIM7):
360 case STM32F7_APB1_CLOCK(TIM12):
361 case STM32F7_APB1_CLOCK(TIM13):
362 case STM32F7_APB1_CLOCK(TIM14):
363 return stm32_get_timer_rate(priv, sysclk, APB1);
365 return (sysclk >> stm32_get_apb_shift(regs, APB1));
368 case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
370 * particular case for SDMMC1 and SDMMC2 :
371 * 48Mhz source clock can be from main PLL or from
375 case STM32F7_APB2_CLOCK(SDMMC1):
376 if (readl(®s->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL)
377 /* System clock is selected as SDMMC1 clock */
380 return stm32_clk_pll48clk_rate(priv, vco);
382 case STM32F7_APB2_CLOCK(SDMMC2):
383 if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL)
384 /* System clock is selected as SDMMC2 clock */
387 return stm32_clk_pll48clk_rate(priv, vco);
390 /* For timer clock, an additionnal prescaler is used*/
391 case STM32F7_APB2_CLOCK(TIM1):
392 case STM32F7_APB2_CLOCK(TIM8):
393 case STM32F7_APB2_CLOCK(TIM9):
394 case STM32F7_APB2_CLOCK(TIM10):
395 case STM32F7_APB2_CLOCK(TIM11):
396 return stm32_get_timer_rate(priv, sysclk, APB2);
399 return (sysclk >> stm32_get_apb_shift(regs, APB2));
402 pr_err("clock index %ld out of range\n", clk->id);
407 static ulong stm32_set_rate(struct clk *clk, ulong rate)
412 static int stm32_clk_enable(struct clk *clk)
414 struct stm32_clk *priv = dev_get_priv(clk->dev);
415 struct stm32_rcc_regs *regs = priv->base;
416 u32 offset = clk->id / 32;
417 u32 bit_index = clk->id % 32;
419 debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
420 __func__, clk->id, offset, bit_index);
421 setbits_le32(®s->ahb1enr + offset, BIT(bit_index));
426 static int stm32_clk_probe(struct udevice *dev)
428 struct ofnode_phandle_args args;
429 struct udevice *fixed_clock_dev = NULL;
433 debug("%s\n", __func__);
435 struct stm32_clk *priv = dev_get_priv(dev);
438 addr = dev_read_addr(dev);
439 if (addr == FDT_ADDR_T_NONE)
442 priv->base = (struct stm32_rcc_regs *)addr;
444 switch (dev_get_driver_data(dev)) {
446 memcpy(&priv->info, &stm32f4_clk_info,
447 sizeof(struct stm32_clk_info));
450 memcpy(&priv->info, &stm32f7_clk_info,
451 sizeof(struct stm32_clk_info));
457 /* retrieve HSE frequency (external oscillator) */
458 err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
462 pr_err("Can't find fixed clock (%d)", err);
466 err = clk_request(fixed_clock_dev, &clk);
468 pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
474 * set pllm factor accordingly to the external oscillator
475 * frequency (HSE). For STM32F4 and STM32F7, we want VCO
477 * if input PLL frequency is 25Mhz, divide it by 25
480 priv->hse_rate = clk_get_rate(&clk);
482 if (priv->hse_rate < 1000000) {
483 pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
488 priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
490 if (priv->info.has_overdrive) {
491 err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
494 debug("%s: can't find syscon device (%d)\n", __func__,
499 priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
502 configure_clocks(dev);
507 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
509 debug("%s(clk=%p)\n", __func__, clk);
511 if (args->args_count != 2) {
512 debug("Invaild args_count: %d\n", args->args_count);
516 if (args->args_count)
517 clk->id = args->args[1];
524 static struct clk_ops stm32_clk_ops = {
525 .of_xlate = stm32_clk_of_xlate,
526 .enable = stm32_clk_enable,
527 .get_rate = stm32_clk_get_rate,
528 .set_rate = stm32_set_rate,
531 U_BOOT_DRIVER(stm32fx_clk) = {
532 .name = "stm32fx_rcc_clock",
534 .ops = &stm32_clk_ops,
535 .probe = stm32_clk_probe,
536 .priv_auto_alloc_size = sizeof(struct stm32_clk),
537 .flags = DM_FLAG_PRE_RELOC,