git.sur5r.net Git - u-boot/blob - drivers/clk/clk_stm32f7.c

   1 /*
   2  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   3  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11
  12 #include <asm/io.h>
  13 #include <asm/arch/rcc.h>
  14 #include <asm/arch/stm32.h>
  15 #include <asm/arch/stm32_periph.h>
  16 #include <asm/arch/stm32_pwr.h>
  17
  18 #include <dt-bindings/mfd/stm32f7-rcc.h>
  19
  20 #define RCC_CR_HSION                    BIT(0)
  21 #define RCC_CR_HSEON                    BIT(16)
  22 #define RCC_CR_HSERDY                   BIT(17)
  23 #define RCC_CR_HSEBYP                   BIT(18)
  24 #define RCC_CR_CSSON                    BIT(19)
  25 #define RCC_CR_PLLON                    BIT(24)
  26 #define RCC_CR_PLLRDY                   BIT(25)
  27
  28 #define RCC_PLLCFGR_PLLM_MASK           GENMASK(5, 0)
  29 #define RCC_PLLCFGR_PLLN_MASK           GENMASK(14, 6)
  30 #define RCC_PLLCFGR_PLLP_MASK           GENMASK(17, 16)
  31 #define RCC_PLLCFGR_PLLQ_MASK           GENMASK(27, 24)
  32 #define RCC_PLLCFGR_PLLSRC              BIT(22)
  33 #define RCC_PLLCFGR_PLLM_SHIFT          0
  34 #define RCC_PLLCFGR_PLLN_SHIFT          6
  35 #define RCC_PLLCFGR_PLLP_SHIFT          16
  36 #define RCC_PLLCFGR_PLLQ_SHIFT          24
  37
  38 #define RCC_CFGR_AHB_PSC_MASK           GENMASK(7, 4)
  39 #define RCC_CFGR_APB1_PSC_MASK          GENMASK(12, 10)
  40 #define RCC_CFGR_APB2_PSC_MASK          GENMASK(15, 13)
  41 #define RCC_CFGR_SW0                    BIT(0)
  42 #define RCC_CFGR_SW1                    BIT(1)
  43 #define RCC_CFGR_SW_MASK                GENMASK(1, 0)
  44 #define RCC_CFGR_SW_HSI                 0
  45 #define RCC_CFGR_SW_HSE                 RCC_CFGR_SW0
  46 #define RCC_CFGR_SW_PLL                 RCC_CFGR_SW1
  47 #define RCC_CFGR_SWS0                   BIT(2)
  48 #define RCC_CFGR_SWS1                   BIT(3)
  49 #define RCC_CFGR_SWS_MASK               GENMASK(3, 2)
  50 #define RCC_CFGR_SWS_HSI                0
  51 #define RCC_CFGR_SWS_HSE                RCC_CFGR_SWS0
  52 #define RCC_CFGR_SWS_PLL                RCC_CFGR_SWS1
  53 #define RCC_CFGR_HPRE_SHIFT             4
  54 #define RCC_CFGR_PPRE1_SHIFT            10
  55 #define RCC_CFGR_PPRE2_SHIFT            13
  56
  57
  58 struct pll_psc {
  59         u8      pll_m;
  60         u16     pll_n;
  61         u8      pll_p;
  62         u8      pll_q;
  63         u8      ahb_psc;
  64         u8      apb1_psc;
  65         u8      apb2_psc;
  66 };
  67
  68 #define AHB_PSC_1                       0
  69 #define AHB_PSC_2                       0x8
  70 #define AHB_PSC_4                       0x9
  71 #define AHB_PSC_8                       0xA
  72 #define AHB_PSC_16                      0xB
  73 #define AHB_PSC_64                      0xC
  74 #define AHB_PSC_128                     0xD
  75 #define AHB_PSC_256                     0xE
  76 #define AHB_PSC_512                     0xF
  77
  78 #define APB_PSC_1                       0
  79 #define APB_PSC_2                       0x4
  80 #define APB_PSC_4                       0x5
  81 #define APB_PSC_8                       0x6
  82 #define APB_PSC_16                      0x7
  83
  84 struct stm32_clk_info {
  85         struct pll_psc sys_pll_psc;
  86         bool has_overdrive;
  87 };
  88
  89 struct stm32_clk_info stm32f4_clk_info = {
  90         /* 180 MHz */
  91         .sys_pll_psc = {
  92                 .pll_m = 8,
  93                 .pll_n = 360,
  94                 .pll_p = 2,
  95                 .pll_q = 8,
  96                 .ahb_psc = AHB_PSC_1,
  97                 .apb1_psc = APB_PSC_4,
  98                 .apb2_psc = APB_PSC_2,
  99         },
 100         .has_overdrive = false,
 101 };
 102
 103 struct stm32_clk_info stm32f7_clk_info = {
 104         /* 200 MHz */
 105         .sys_pll_psc = {
 106                 .pll_m = 25,
 107                 .pll_n = 400,
 108                 .pll_p = 2,
 109                 .pll_q = 8,
 110                 .ahb_psc = AHB_PSC_1,
 111                 .apb1_psc = APB_PSC_4,
 112                 .apb2_psc = APB_PSC_2,
 113         },
 114         .has_overdrive = true,
 115 };
 116
 117 struct stm32_clk {
 118         struct stm32_rcc_regs *base;
 119         struct stm32_pwr_regs *pwr_regs;
 120         struct stm32_clk_info *info;
 121 };
 122
 123 static int configure_clocks(struct udevice *dev)
 124 {
 125         struct stm32_clk *priv = dev_get_priv(dev);
 126         struct stm32_rcc_regs *regs = priv->base;
 127         struct stm32_pwr_regs *pwr = priv->pwr_regs;
 128         struct pll_psc sys_pll_psc = priv->info->sys_pll_psc;
 129
 130         /* Reset RCC configuration */
 131         setbits_le32(&regs->cr, RCC_CR_HSION);
 132         writel(0, &regs->cfgr); /* Reset CFGR */
 133         clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
 134                 | RCC_CR_PLLON));
 135         writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
 136         clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
 137         writel(0, &regs->cir); /* Disable all interrupts */
 138
 139         /* Configure for HSE+PLL operation */
 140         setbits_le32(&regs->cr, RCC_CR_HSEON);
 141         while (!(readl(&regs->cr) & RCC_CR_HSERDY))
 142                 ;
 143
 144         setbits_le32(&regs->cfgr, ((
 145                 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
 146                 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
 147                 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
 148
 149         /* Configure the main PLL */
 150         setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
 151         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
 152                         sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT);
 153         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
 154                         sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT);
 155         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
 156                         ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
 157         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
 158                         sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
 159
 160         /* Enable the main PLL */
 161         setbits_le32(&regs->cr, RCC_CR_PLLON);
 162         while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
 163                 ;
 164
 165         setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
 166
 167         if (priv->info->has_overdrive) {
 168                 /*
 169                  * Enable high performance mode
 170                  * System frequency up to 200 MHz
 171                  */
 172                 setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
 173                 /* Infinite wait! */
 174                 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
 175                         ;
 176                 /* Enable the Over-drive switch */
 177                 setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
 178                 /* Infinite wait! */
 179                 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
 180                         ;
 181         }
 182
 183         stm32_flash_latency_cfg(5);
 184         clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
 185         setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
 186
 187         while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
 188                         RCC_CFGR_SWS_PLL)
 189                 ;
 190
 191         return 0;
 192 }
 193
 194 static unsigned long stm32_clk_get_rate(struct clk *clk)
 195 {
 196         struct stm32_clk *priv = dev_get_priv(clk->dev);
 197         struct stm32_rcc_regs *regs = priv->base;
 198         u32 sysclk = 0;
 199         u32 shift = 0;
 200         /* Prescaler table lookups for clock computation */
 201         u8 ahb_psc_table[16] = {
 202                 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
 203         };
 204         u8 apb_psc_table[8] = {
 205                 0, 0, 0, 0, 1, 2, 3, 4
 206         };
 207
 208         if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
 209                         RCC_CFGR_SWS_PLL) {
 210                 u16 pllm, plln, pllp;
 211                 pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
 212                 plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
 213                         >> RCC_PLLCFGR_PLLN_SHIFT);
 214                 pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
 215                         >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
 216                 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
 217         } else {
 218                 return -EINVAL;
 219         }
 220
 221         switch (clk->id) {
 222         /*
 223          * AHB CLOCK: 3 x 32 bits consecutive registers are used :
 224          * AHB1, AHB2 and AHB3
 225          */
 226         case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
 227                 shift = ahb_psc_table[(
 228                         (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
 229                         >> RCC_CFGR_HPRE_SHIFT)];
 230                 return sysclk >>= shift;
 231                 break;
 232         /* APB1 CLOCK */
 233         case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
 234                 shift = apb_psc_table[(
 235                         (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
 236                         >> RCC_CFGR_PPRE1_SHIFT)];
 237                 return sysclk >>= shift;
 238                 break;
 239         /* APB2 CLOCK */
 240         case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
 241                 shift = apb_psc_table[(
 242                         (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
 243                         >> RCC_CFGR_PPRE2_SHIFT)];
 244                 return sysclk >>= shift;
 245                 break;
 246         default:
 247                 pr_err("clock index %ld out of range\n", clk->id);
 248                 return -EINVAL;
 249                 break;
 250         }
 251 }
 252
 253 static int stm32_clk_enable(struct clk *clk)
 254 {
 255         struct stm32_clk *priv = dev_get_priv(clk->dev);
 256         struct stm32_rcc_regs *regs = priv->base;
 257         u32 offset = clk->id / 32;
 258         u32 bit_index = clk->id % 32;
 259
 260         debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
 261               __func__, clk->id, offset, bit_index);
 262         setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
 263
 264         return 0;
 265 }
 266
 267 void clock_setup(int peripheral)
 268 {
 269         switch (peripheral) {
 270         case SYSCFG_CLOCK_CFG:
 271                 setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
 272                 break;
 273         case TIMER2_CLOCK_CFG:
 274                 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
 275                 break;
 276         case STMMAC_CLOCK_CFG:
 277                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
 278                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
 279                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
 280                 break;
 281         default:
 282                 break;
 283         }
 284 }
 285
 286 static int stm32_clk_probe(struct udevice *dev)
 287 {
 288         struct ofnode_phandle_args args;
 289         int err;
 290
 291         debug("%s: stm32_clk_probe\n", __func__);
 292
 293         struct stm32_clk *priv = dev_get_priv(dev);
 294         fdt_addr_t addr;
 295
 296         addr = dev_read_addr(dev);
 297         if (addr == FDT_ADDR_T_NONE)
 298                 return -EINVAL;
 299
 300         priv->base = (struct stm32_rcc_regs *)addr;
 301         priv->info = (struct stm32_clk_info *)dev_get_driver_data(dev);
 302
 303         if (priv->info->has_overdrive) {
 304                 err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
 305                                                  &args);
 306                 if (err) {
 307                         debug("%s: can't find syscon device (%d)\n", __func__,
 308                               err);
 309                         return err;
 310                 }
 311
 312                 priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
 313         }
 314
 315         configure_clocks(dev);
 316
 317         return 0;
 318 }
 319
 320 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 321 {
 322         debug("%s(clk=%p)\n", __func__, clk);
 323
 324         if (args->args_count != 2) {
 325                 debug("Invaild args_count: %d\n", args->args_count);
 326                 return -EINVAL;
 327         }
 328
 329         if (args->args_count)
 330                 clk->id = args->args[1];
 331         else
 332                 clk->id = 0;
 333
 334         return 0;
 335 }
 336
 337 static struct clk_ops stm32_clk_ops = {
 338         .of_xlate       = stm32_clk_of_xlate,
 339         .enable         = stm32_clk_enable,
 340         .get_rate       = stm32_clk_get_rate,
 341 };
 342
 343 static const struct udevice_id stm32_clk_ids[] = {
 344         { .compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32f4_clk_info},
 345         { .compatible = "st,stm32f746-rcc", .data = (ulong)&stm32f7_clk_info},
 346         {}
 347 };
 348
 349 U_BOOT_DRIVER(stm32f7_clk) = {
 350         .name                   = "stm32f7_clk",
 351         .id                     = UCLASS_CLK,
 352         .of_match               = stm32_clk_ids,
 353         .ops                    = &stm32_clk_ops,
 354         .probe                  = stm32_clk_probe,
 355         .priv_auto_alloc_size   = sizeof(struct stm32_clk),
 356         .flags                  = DM_FLAG_PRE_RELOC,
 357 };