git.sur5r.net Git - u-boot/blob - drivers/clk/clk_stm32f7.c

   1 /*
   2  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   3  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/rcc.h>
  13 #include <asm/arch/stm32.h>
  14 #include <asm/arch/stm32_periph.h>
  15
  16 #include <dt-bindings/mfd/stm32f7-rcc.h>
  17
  18 #define RCC_CR_HSION                    BIT(0)
  19 #define RCC_CR_HSEON                    BIT(16)
  20 #define RCC_CR_HSERDY                   BIT(17)
  21 #define RCC_CR_HSEBYP                   BIT(18)
  22 #define RCC_CR_CSSON                    BIT(19)
  23 #define RCC_CR_PLLON                    BIT(24)
  24 #define RCC_CR_PLLRDY                   BIT(25)
  25
  26 #define RCC_PLLCFGR_PLLM_MASK           GENMASK(5, 0)
  27 #define RCC_PLLCFGR_PLLN_MASK           GENMASK(14, 6)
  28 #define RCC_PLLCFGR_PLLP_MASK           GENMASK(17, 16)
  29 #define RCC_PLLCFGR_PLLQ_MASK           GENMASK(27, 24)
  30 #define RCC_PLLCFGR_PLLSRC              BIT(22)
  31 #define RCC_PLLCFGR_PLLM_SHIFT          0
  32 #define RCC_PLLCFGR_PLLN_SHIFT          6
  33 #define RCC_PLLCFGR_PLLP_SHIFT          16
  34 #define RCC_PLLCFGR_PLLQ_SHIFT          24
  35
  36 #define RCC_CFGR_AHB_PSC_MASK           GENMASK(7, 4)
  37 #define RCC_CFGR_APB1_PSC_MASK          GENMASK(12, 10)
  38 #define RCC_CFGR_APB2_PSC_MASK          GENMASK(15, 13)
  39 #define RCC_CFGR_SW0                    BIT(0)
  40 #define RCC_CFGR_SW1                    BIT(1)
  41 #define RCC_CFGR_SW_MASK                GENMASK(1, 0)
  42 #define RCC_CFGR_SW_HSI                 0
  43 #define RCC_CFGR_SW_HSE                 RCC_CFGR_SW0
  44 #define RCC_CFGR_SW_PLL                 RCC_CFGR_SW1
  45 #define RCC_CFGR_SWS0                   BIT(2)
  46 #define RCC_CFGR_SWS1                   BIT(3)
  47 #define RCC_CFGR_SWS_MASK               GENMASK(3, 2)
  48 #define RCC_CFGR_SWS_HSI                0
  49 #define RCC_CFGR_SWS_HSE                RCC_CFGR_SWS0
  50 #define RCC_CFGR_SWS_PLL                RCC_CFGR_SWS1
  51 #define RCC_CFGR_HPRE_SHIFT             4
  52 #define RCC_CFGR_PPRE1_SHIFT            10
  53 #define RCC_CFGR_PPRE2_SHIFT            13
  54
  55 /*
  56  * Offsets of some PWR registers
  57  */
  58 #define PWR_CR1_ODEN                    BIT(16)
  59 #define PWR_CR1_ODSWEN                  BIT(17)
  60 #define PWR_CSR1_ODRDY                  BIT(16)
  61 #define PWR_CSR1_ODSWRDY                BIT(17)
  62
  63 struct pll_psc {
  64         u8      pll_m;
  65         u16     pll_n;
  66         u8      pll_p;
  67         u8      pll_q;
  68         u8      ahb_psc;
  69         u8      apb1_psc;
  70         u8      apb2_psc;
  71 };
  72
  73 #define AHB_PSC_1                       0
  74 #define AHB_PSC_2                       0x8
  75 #define AHB_PSC_4                       0x9
  76 #define AHB_PSC_8                       0xA
  77 #define AHB_PSC_16                      0xB
  78 #define AHB_PSC_64                      0xC
  79 #define AHB_PSC_128                     0xD
  80 #define AHB_PSC_256                     0xE
  81 #define AHB_PSC_512                     0xF
  82
  83 #define APB_PSC_1                       0
  84 #define APB_PSC_2                       0x4
  85 #define APB_PSC_4                       0x5
  86 #define APB_PSC_8                       0x6
  87 #define APB_PSC_16                      0x7
  88
  89 struct stm32_clk {
  90         struct stm32_rcc_regs *base;
  91 };
  92
  93 #if !defined(CONFIG_STM32_HSE_HZ)
  94 #error "CONFIG_STM32_HSE_HZ not defined!"
  95 #else
  96 #if (CONFIG_STM32_HSE_HZ == 25000000)
  97 #if (CONFIG_SYS_CLK_FREQ == 200000000)
  98 /* 200 MHz */
  99 struct pll_psc sys_pll_psc = {
 100         .pll_m = 25,
 101         .pll_n = 400,
 102         .pll_p = 2,
 103         .pll_q = 8,
 104         .ahb_psc = AHB_PSC_1,
 105         .apb1_psc = APB_PSC_4,
 106         .apb2_psc = APB_PSC_2
 107 };
 108 #endif
 109 #else
 110 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
 111 #endif
 112 #endif
 113
 114 static int configure_clocks(struct udevice *dev)
 115 {
 116         struct stm32_clk *priv = dev_get_priv(dev);
 117         struct stm32_rcc_regs *regs = priv->base;
 118
 119         /* Reset RCC configuration */
 120         setbits_le32(&regs->cr, RCC_CR_HSION);
 121         writel(0, &regs->cfgr); /* Reset CFGR */
 122         clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
 123                 | RCC_CR_PLLON));
 124         writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
 125         clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
 126         writel(0, &regs->cir); /* Disable all interrupts */
 127
 128         /* Configure for HSE+PLL operation */
 129         setbits_le32(&regs->cr, RCC_CR_HSEON);
 130         while (!(readl(&regs->cr) & RCC_CR_HSERDY))
 131                 ;
 132
 133         setbits_le32(&regs->cfgr, ((
 134                 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
 135                 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
 136                 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
 137
 138         /* Configure the main PLL */
 139         setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
 140         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
 141                         sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT);
 142         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
 143                         sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT);
 144         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
 145                         ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
 146         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
 147                         sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
 148
 149         /* Enable the main PLL */
 150         setbits_le32(&regs->cr, RCC_CR_PLLON);
 151         while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
 152                 ;
 153
 154         /* Enable high performance mode, System frequency up to 200 MHz */
 155         setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
 156         setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
 157         /* Infinite wait! */
 158         while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
 159                 ;
 160         /* Enable the Over-drive switch */
 161         setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
 162         /* Infinite wait! */
 163         while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
 164                 ;
 165
 166         stm32_flash_latency_cfg(5);
 167         clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
 168         setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
 169
 170         while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
 171                         RCC_CFGR_SWS_PLL)
 172                 ;
 173
 174         return 0;
 175 }
 176
 177 static unsigned long stm32_clk_get_rate(struct clk *clk)
 178 {
 179         struct stm32_clk *priv = dev_get_priv(clk->dev);
 180         struct stm32_rcc_regs *regs = priv->base;
 181         u32 sysclk = 0;
 182         u32 shift = 0;
 183         /* Prescaler table lookups for clock computation */
 184         u8 ahb_psc_table[16] = {
 185                 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
 186         };
 187         u8 apb_psc_table[8] = {
 188                 0, 0, 0, 0, 1, 2, 3, 4
 189         };
 190
 191         if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
 192                         RCC_CFGR_SWS_PLL) {
 193                 u16 pllm, plln, pllp;
 194                 pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
 195                 plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
 196                         >> RCC_PLLCFGR_PLLN_SHIFT);
 197                 pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
 198                         >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
 199                 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
 200         } else {
 201                 return -EINVAL;
 202         }
 203
 204         switch (clk->id) {
 205         /*
 206          * AHB CLOCK: 3 x 32 bits consecutive registers are used :
 207          * AHB1, AHB2 and AHB3
 208          */
 209         case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
 210                 shift = ahb_psc_table[(
 211                         (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
 212                         >> RCC_CFGR_HPRE_SHIFT)];
 213                 return sysclk >>= shift;
 214                 break;
 215         /* APB1 CLOCK */
 216         case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
 217                 shift = apb_psc_table[(
 218                         (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
 219                         >> RCC_CFGR_PPRE1_SHIFT)];
 220                 return sysclk >>= shift;
 221                 break;
 222         /* APB2 CLOCK */
 223         case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
 224                 shift = apb_psc_table[(
 225                         (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
 226                         >> RCC_CFGR_PPRE2_SHIFT)];
 227                 return sysclk >>= shift;
 228                 break;
 229         default:
 230                 pr_err("clock index %ld out of range\n", clk->id);
 231                 return -EINVAL;
 232                 break;
 233         }
 234 }
 235
 236 static int stm32_clk_enable(struct clk *clk)
 237 {
 238         struct stm32_clk *priv = dev_get_priv(clk->dev);
 239         struct stm32_rcc_regs *regs = priv->base;
 240         u32 offset = clk->id / 32;
 241         u32 bit_index = clk->id % 32;
 242
 243         debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
 244               __func__, clk->id, offset, bit_index);
 245         setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
 246
 247         return 0;
 248 }
 249
 250 void clock_setup(int peripheral)
 251 {
 252         switch (peripheral) {
 253         case SYSCFG_CLOCK_CFG:
 254                 setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
 255                 break;
 256         case TIMER2_CLOCK_CFG:
 257                 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
 258                 break;
 259         case STMMAC_CLOCK_CFG:
 260                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
 261                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
 262                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
 263                 break;
 264         default:
 265                 break;
 266         }
 267 }
 268
 269 static int stm32_clk_probe(struct udevice *dev)
 270 {
 271         debug("%s: stm32_clk_probe\n", __func__);
 272
 273         struct stm32_clk *priv = dev_get_priv(dev);
 274         fdt_addr_t addr;
 275
 276         addr = devfdt_get_addr(dev);
 277         if (addr == FDT_ADDR_T_NONE)
 278                 return -EINVAL;
 279
 280         priv->base = (struct stm32_rcc_regs *)addr;
 281
 282         configure_clocks(dev);
 283
 284         return 0;
 285 }
 286
 287 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 288 {
 289         debug("%s(clk=%p)\n", __func__, clk);
 290
 291         if (args->args_count != 2) {
 292                 debug("Invaild args_count: %d\n", args->args_count);
 293                 return -EINVAL;
 294         }
 295
 296         if (args->args_count)
 297                 clk->id = args->args[1];
 298         else
 299                 clk->id = 0;
 300
 301         return 0;
 302 }
 303
 304 static struct clk_ops stm32_clk_ops = {
 305         .of_xlate       = stm32_clk_of_xlate,
 306         .enable         = stm32_clk_enable,
 307         .get_rate       = stm32_clk_get_rate,
 308 };
 309
 310 static const struct udevice_id stm32_clk_ids[] = {
 311         { .compatible = "st,stm32f42xx-rcc"},
 312         {}
 313 };
 314
 315 U_BOOT_DRIVER(stm32f7_clk) = {
 316         .name                   = "stm32f7_clk",
 317         .id                     = UCLASS_CLK,
 318         .of_match               = stm32_clk_ids,
 319         .ops                    = &stm32_clk_ops,
 320         .probe                  = stm32_clk_probe,
 321         .priv_auto_alloc_size   = sizeof(struct stm32_clk),
 322         .flags                  = DM_FLAG_PRE_RELOC,
 323 };