2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <clk-uclass.h>
16 #include <dt-bindings/clock/stm32h7-clks.h>
18 /* RCC CR specific definitions */
19 #define RCC_CR_HSION BIT(0)
20 #define RCC_CR_HSIRDY BIT(2)
22 #define RCC_CR_HSEON BIT(16)
23 #define RCC_CR_HSERDY BIT(17)
24 #define RCC_CR_HSEBYP BIT(18)
25 #define RCC_CR_PLL1ON BIT(24)
26 #define RCC_CR_PLL1RDY BIT(25)
28 #define RCC_CR_HSIDIV_MASK GENMASK(4, 3)
29 #define RCC_CR_HSIDIV_SHIFT 3
31 #define RCC_CFGR_SW_MASK GENMASK(2, 0)
32 #define RCC_CFGR_SW_HSI 0
33 #define RCC_CFGR_SW_CSI 1
34 #define RCC_CFGR_SW_HSE 2
35 #define RCC_CFGR_SW_PLL1 3
36 #define RCC_CFGR_TIMPRE BIT(15)
38 #define RCC_PLLCKSELR_PLLSRC_HSI 0
39 #define RCC_PLLCKSELR_PLLSRC_CSI 1
40 #define RCC_PLLCKSELR_PLLSRC_HSE 2
41 #define RCC_PLLCKSELR_PLLSRC_NO_CLK 3
43 #define RCC_PLLCKSELR_PLLSRC_MASK GENMASK(1, 0)
45 #define RCC_PLLCKSELR_DIVM1_SHIFT 4
46 #define RCC_PLLCKSELR_DIVM1_MASK GENMASK(9, 4)
48 #define RCC_PLL1DIVR_DIVN1_MASK GENMASK(8, 0)
50 #define RCC_PLL1DIVR_DIVP1_SHIFT 9
51 #define RCC_PLL1DIVR_DIVP1_MASK GENMASK(15, 9)
53 #define RCC_PLL1DIVR_DIVQ1_SHIFT 16
54 #define RCC_PLL1DIVR_DIVQ1_MASK GENMASK(22, 16)
56 #define RCC_PLL1DIVR_DIVR1_SHIFT 24
57 #define RCC_PLL1DIVR_DIVR1_MASK GENMASK(30, 24)
59 #define RCC_PLL1FRACR_FRACN1_SHIFT 3
60 #define RCC_PLL1FRACR_FRACN1_MASK GENMASK(15, 3)
62 #define RCC_PLLCFGR_PLL1RGE_SHIFT 2
63 #define PLL1RGE_1_2_MHZ 0
64 #define PLL1RGE_2_4_MHZ 1
65 #define PLL1RGE_4_8_MHZ 2
66 #define PLL1RGE_8_16_MHZ 3
67 #define RCC_PLLCFGR_DIVP1EN BIT(16)
68 #define RCC_PLLCFGR_DIVQ1EN BIT(17)
69 #define RCC_PLLCFGR_DIVR1EN BIT(18)
71 #define RCC_D1CFGR_HPRE_MASK GENMASK(3, 0)
72 #define RCC_D1CFGR_HPRE_DIVIDED BIT(3)
73 #define RCC_D1CFGR_HPRE_DIVIDER GENMASK(2, 0)
75 #define RCC_D1CFGR_HPRE_DIV2 8
77 #define RCC_D1CFGR_D1PPRE_SHIFT 4
78 #define RCC_D1CFGR_D1PPRE_DIVIDED BIT(6)
79 #define RCC_D1CFGR_D1PPRE_DIVIDER GENMASK(5, 4)
81 #define RCC_D1CFGR_D1CPRE_SHIFT 8
82 #define RCC_D1CFGR_D1CPRE_DIVIDER GENMASK(10, 8)
83 #define RCC_D1CFGR_D1CPRE_DIVIDED BIT(11)
85 #define RCC_D2CFGR_D2PPRE1_SHIFT 4
86 #define RCC_D2CFGR_D2PPRE1_DIVIDED BIT(6)
87 #define RCC_D2CFGR_D2PPRE1_DIVIDER GENMASK(5, 4)
89 #define RCC_D2CFGR_D2PPRE2_SHIFT 8
90 #define RCC_D2CFGR_D2PPRE2_DIVIDED BIT(10)
91 #define RCC_D2CFGR_D2PPRE2_DIVIDER GENMASK(9, 8)
93 #define RCC_D3CFGR_D3PPRE_SHIFT 4
94 #define RCC_D3CFGR_D3PPRE_DIVIDED BIT(6)
95 #define RCC_D3CFGR_D3PPRE_DIVIDER GENMASK(5, 4)
97 #define RCC_D1CCIPR_FMCSRC_MASK GENMASK(1, 0)
98 #define FMCSRC_HCLKD1 0
99 #define FMCSRC_PLL1_Q_CK 1
100 #define FMCSRC_PLL2_R_CK 2
101 #define FMCSRC_PER_CK 3
103 #define RCC_D1CCIPR_QSPISRC_MASK GENMASK(5, 4)
104 #define RCC_D1CCIPR_QSPISRC_SHIFT 4
105 #define QSPISRC_HCLKD1 0
106 #define QSPISRC_PLL1_Q_CK 1
107 #define QSPISRC_PLL2_R_CK 2
108 #define QSPISRC_PER_CK 3
111 #define PWR_CR3_SCUEN BIT(2)
112 #define PWR_D3CR 0x18
113 #define PWR_D3CR_VOS_MASK GENMASK(15, 14)
114 #define PWR_D3CR_VOS_SHIFT 14
115 #define VOS_SCALE_3 1
116 #define VOS_SCALE_2 2
117 #define VOS_SCALE_1 3
118 #define PWR_D3CR_VOSREADY BIT(13)
120 struct stm32_rcc_regs {
121 u32 cr; /* 0x00 Source Control Register */
122 u32 icscr; /* 0x04 Internal Clock Source Calibration Register */
123 u32 crrcr; /* 0x08 Clock Recovery RC Register */
124 u32 reserved1; /* 0x0c reserved */
125 u32 cfgr; /* 0x10 Clock Configuration Register */
126 u32 reserved2; /* 0x14 reserved */
127 u32 d1cfgr; /* 0x18 Domain 1 Clock Configuration Register */
128 u32 d2cfgr; /* 0x1c Domain 2 Clock Configuration Register */
129 u32 d3cfgr; /* 0x20 Domain 3 Clock Configuration Register */
130 u32 reserved3; /* 0x24 reserved */
131 u32 pllckselr; /* 0x28 PLLs Clock Source Selection Register */
132 u32 pllcfgr; /* 0x2c PLLs Configuration Register */
133 u32 pll1divr; /* 0x30 PLL1 Dividers Configuration Register */
134 u32 pll1fracr; /* 0x34 PLL1 Fractional Divider Register */
135 u32 pll2divr; /* 0x38 PLL2 Dividers Configuration Register */
136 u32 pll2fracr; /* 0x3c PLL2 Fractional Divider Register */
137 u32 pll3divr; /* 0x40 PLL3 Dividers Configuration Register */
138 u32 pll3fracr; /* 0x44 PLL3 Fractional Divider Register */
139 u32 reserved4; /* 0x48 reserved */
140 u32 d1ccipr; /* 0x4c Domain 1 Kernel Clock Configuration Register */
141 u32 d2ccip1r; /* 0x50 Domain 2 Kernel Clock Configuration Register */
142 u32 d2ccip2r; /* 0x54 Domain 2 Kernel Clock Configuration Register */
143 u32 d3ccipr; /* 0x58 Domain 3 Kernel Clock Configuration Register */
144 u32 reserved5; /* 0x5c reserved */
145 u32 cier; /* 0x60 Clock Source Interrupt Enable Register */
146 u32 cifr; /* 0x64 Clock Source Interrupt Flag Register */
147 u32 cicr; /* 0x68 Clock Source Interrupt Clear Register */
148 u32 reserved6; /* 0x6c reserved */
149 u32 bdcr; /* 0x70 Backup Domain Control Register */
150 u32 csr; /* 0x74 Clock Control and Status Register */
151 u32 reserved7; /* 0x78 reserved */
153 u32 ahb3rstr; /* 0x7c AHB3 Peripheral Reset Register */
154 u32 ahb1rstr; /* 0x80 AHB1 Peripheral Reset Register */
155 u32 ahb2rstr; /* 0x84 AHB2 Peripheral Reset Register */
156 u32 ahb4rstr; /* 0x88 AHB4 Peripheral Reset Register */
158 u32 apb3rstr; /* 0x8c APB3 Peripheral Reset Register */
159 u32 apb1lrstr; /* 0x90 APB1 low Peripheral Reset Register */
160 u32 apb1hrstr; /* 0x94 APB1 high Peripheral Reset Register */
161 u32 apb2rstr; /* 0x98 APB2 Clock Register */
162 u32 apb4rstr; /* 0x9c APB4 Clock Register */
164 u32 gcr; /* 0xa0 Global Control Register */
165 u32 reserved8; /* 0xa4 reserved */
166 u32 d3amr; /* 0xa8 D3 Autonomous mode Register */
167 u32 reserved9[9];/* 0xac to 0xcc reserved */
168 u32 rsr; /* 0xd0 Reset Status Register */
169 u32 ahb3enr; /* 0xd4 AHB3 Clock Register */
170 u32 ahb1enr; /* 0xd8 AHB1 Clock Register */
171 u32 ahb2enr; /* 0xdc AHB2 Clock Register */
172 u32 ahb4enr; /* 0xe0 AHB4 Clock Register */
174 u32 apb3enr; /* 0xe4 APB3 Clock Register */
175 u32 apb1lenr; /* 0xe8 APB1 low Clock Register */
176 u32 apb1henr; /* 0xec APB1 high Clock Register */
177 u32 apb2enr; /* 0xf0 APB2 Clock Register */
178 u32 apb4enr; /* 0xf4 APB4 Clock Register */
181 #define RCC_AHB3ENR offsetof(struct stm32_rcc_regs, ahb3enr)
182 #define RCC_AHB1ENR offsetof(struct stm32_rcc_regs, ahb1enr)
183 #define RCC_AHB2ENR offsetof(struct stm32_rcc_regs, ahb2enr)
184 #define RCC_AHB4ENR offsetof(struct stm32_rcc_regs, ahb4enr)
185 #define RCC_APB3ENR offsetof(struct stm32_rcc_regs, apb3enr)
186 #define RCC_APB1LENR offsetof(struct stm32_rcc_regs, apb1lenr)
187 #define RCC_APB1HENR offsetof(struct stm32_rcc_regs, apb1henr)
188 #define RCC_APB2ENR offsetof(struct stm32_rcc_regs, apb2enr)
189 #define RCC_APB4ENR offsetof(struct stm32_rcc_regs, apb4enr)
198 * the way all these entries are sorted in this array could seem
199 * unlogical, but we are dependant of kernel DT_bindings,
200 * where clocks are separate in 2 banks, peripheral clocks and
204 static const struct clk_cfg clk_map[] = {
205 {RCC_AHB3ENR, 31, "d1sram1"}, /* peripheral clocks */
206 {RCC_AHB3ENR, 30, "itcm"},
207 {RCC_AHB3ENR, 29, "dtcm2"},
208 {RCC_AHB3ENR, 28, "dtcm1"},
209 {RCC_AHB3ENR, 8, "flitf"},
210 {RCC_AHB3ENR, 5, "jpgdec"},
211 {RCC_AHB3ENR, 4, "dma2d"},
212 {RCC_AHB3ENR, 0, "mdma"},
213 {RCC_AHB1ENR, 28, "usb2ulpi"},
214 {RCC_AHB1ENR, 17, "eth1rx"},
215 {RCC_AHB1ENR, 16, "eth1tx"},
216 {RCC_AHB1ENR, 15, "eth1mac"},
217 {RCC_AHB1ENR, 14, "art"},
218 {RCC_AHB1ENR, 26, "usb1ulpi"},
219 {RCC_AHB1ENR, 1, "dma2"},
220 {RCC_AHB1ENR, 0, "dma1"},
221 {RCC_AHB2ENR, 31, "d2sram3"},
222 {RCC_AHB2ENR, 30, "d2sram2"},
223 {RCC_AHB2ENR, 29, "d2sram1"},
224 {RCC_AHB2ENR, 5, "hash"},
225 {RCC_AHB2ENR, 4, "crypt"},
226 {RCC_AHB2ENR, 0, "camitf"},
227 {RCC_AHB4ENR, 28, "bkpram"},
228 {RCC_AHB4ENR, 25, "hsem"},
229 {RCC_AHB4ENR, 21, "bdma"},
230 {RCC_AHB4ENR, 19, "crc"},
231 {RCC_AHB4ENR, 10, "gpiok"},
232 {RCC_AHB4ENR, 9, "gpioj"},
233 {RCC_AHB4ENR, 8, "gpioi"},
234 {RCC_AHB4ENR, 7, "gpioh"},
235 {RCC_AHB4ENR, 6, "gpiog"},
236 {RCC_AHB4ENR, 5, "gpiof"},
237 {RCC_AHB4ENR, 4, "gpioe"},
238 {RCC_AHB4ENR, 3, "gpiod"},
239 {RCC_AHB4ENR, 2, "gpioc"},
240 {RCC_AHB4ENR, 1, "gpiob"},
241 {RCC_AHB4ENR, 0, "gpioa"},
242 {RCC_APB3ENR, 6, "wwdg1"},
243 {RCC_APB1LENR, 29, "dac12"},
244 {RCC_APB1LENR, 11, "wwdg2"},
245 {RCC_APB1LENR, 8, "tim14"},
246 {RCC_APB1LENR, 7, "tim13"},
247 {RCC_APB1LENR, 6, "tim12"},
248 {RCC_APB1LENR, 5, "tim7"},
249 {RCC_APB1LENR, 4, "tim6"},
250 {RCC_APB1LENR, 3, "tim5"},
251 {RCC_APB1LENR, 2, "tim4"},
252 {RCC_APB1LENR, 1, "tim3"},
253 {RCC_APB1LENR, 0, "tim2"},
254 {RCC_APB1HENR, 5, "mdios"},
255 {RCC_APB1HENR, 4, "opamp"},
256 {RCC_APB1HENR, 1, "crs"},
257 {RCC_APB2ENR, 18, "tim17"},
258 {RCC_APB2ENR, 17, "tim16"},
259 {RCC_APB2ENR, 16, "tim15"},
260 {RCC_APB2ENR, 1, "tim8"},
261 {RCC_APB2ENR, 0, "tim1"},
262 {RCC_APB4ENR, 26, "tmpsens"},
263 {RCC_APB4ENR, 16, "rtcapb"},
264 {RCC_APB4ENR, 15, "vref"},
265 {RCC_APB4ENR, 14, "comp12"},
266 {RCC_APB4ENR, 1, "syscfg"},
267 {RCC_AHB3ENR, 16, "sdmmc1"}, /* kernel clocks */
268 {RCC_AHB3ENR, 14, "quadspi"},
269 {RCC_AHB3ENR, 12, "fmc"},
270 {RCC_AHB1ENR, 27, "usb2otg"},
271 {RCC_AHB1ENR, 25, "usb1otg"},
272 {RCC_AHB1ENR, 5, "adc12"},
273 {RCC_AHB2ENR, 9, "sdmmc2"},
274 {RCC_AHB2ENR, 6, "rng"},
275 {RCC_AHB4ENR, 24, "adc3"},
276 {RCC_APB3ENR, 4, "dsi"},
277 {RCC_APB3ENR, 3, "ltdc"},
278 {RCC_APB1LENR, 31, "usart8"},
279 {RCC_APB1LENR, 30, "usart7"},
280 {RCC_APB1LENR, 27, "hdmicec"},
281 {RCC_APB1LENR, 23, "i2c3"},
282 {RCC_APB1LENR, 22, "i2c2"},
283 {RCC_APB1LENR, 21, "i2c1"},
284 {RCC_APB1LENR, 20, "uart5"},
285 {RCC_APB1LENR, 19, "uart4"},
286 {RCC_APB1LENR, 18, "usart3"},
287 {RCC_APB1LENR, 17, "usart2"},
288 {RCC_APB1LENR, 16, "spdifrx"},
289 {RCC_APB1LENR, 15, "spi3"},
290 {RCC_APB1LENR, 14, "spi2"},
291 {RCC_APB1LENR, 9, "lptim1"},
292 {RCC_APB1HENR, 8, "fdcan"},
293 {RCC_APB1HENR, 2, "swp"},
294 {RCC_APB2ENR, 29, "hrtim"},
295 {RCC_APB2ENR, 28, "dfsdm1"},
296 {RCC_APB2ENR, 24, "sai3"},
297 {RCC_APB2ENR, 23, "sai2"},
298 {RCC_APB2ENR, 22, "sai1"},
299 {RCC_APB2ENR, 20, "spi5"},
300 {RCC_APB2ENR, 13, "spi4"},
301 {RCC_APB2ENR, 12, "spi1"},
302 {RCC_APB2ENR, 5, "usart6"},
303 {RCC_APB2ENR, 4, "usart1"},
304 {RCC_APB4ENR, 21, "sai4a"},
305 {RCC_APB4ENR, 21, "sai4b"},
306 {RCC_APB4ENR, 12, "lptim5"},
307 {RCC_APB4ENR, 11, "lptim4"},
308 {RCC_APB4ENR, 10, "lptim3"},
309 {RCC_APB4ENR, 9, "lptim2"},
310 {RCC_APB4ENR, 7, "i2c4"},
311 {RCC_APB4ENR, 5, "spi6"},
312 {RCC_APB4ENR, 3, "lpuart1"},
316 struct stm32_rcc_regs *rcc_base;
317 struct regmap *pwr_regmap;
331 * pll1_p = 250MHz / pll1_q = 250MHz pll1_r = 250Mhz
333 struct pll_psc sys_pll_psc = {
346 int configure_clocks(struct udevice *dev)
348 struct stm32_clk *priv = dev_get_priv(dev);
349 struct stm32_rcc_regs *regs = priv->rcc_base;
350 uint8_t *pwr_base = (uint8_t *)regmap_get_range(priv->pwr_regmap, 0);
351 uint32_t pllckselr = 0;
352 uint32_t pll1divr = 0;
353 uint32_t pllcfgr = 0;
356 setbits_le32(®s->cr, RCC_CR_HSION);
357 while (!(readl(®s->cr) & RCC_CR_HSIRDY))
360 /* Reset CFGR, now HSI is the default system clock */
361 writel(0, ®s->cfgr);
363 /* Set all kernel domain clock registers to reset value*/
364 writel(0x0, ®s->d1ccipr);
365 writel(0x0, ®s->d2ccip1r);
366 writel(0x0, ®s->d2ccip2r);
368 /* Set voltage scaling at scale 1 (1,15 - 1,26 Volts) */
369 clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK,
370 VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT);
371 /* Lock supply configuration update */
372 clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN);
373 while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY))
376 /* disable HSE to configure it */
377 clrbits_le32(®s->cr, RCC_CR_HSEON);
378 while ((readl(®s->cr) & RCC_CR_HSERDY))
381 /* clear HSE bypass and set it ON */
382 clrbits_le32(®s->cr, RCC_CR_HSEBYP);
384 setbits_le32(®s->cr, RCC_CR_HSEON);
385 while (!(readl(®s->cr) & RCC_CR_HSERDY))
388 /* pll setup, disable it */
389 clrbits_le32(®s->cr, RCC_CR_PLL1ON);
390 while ((readl(®s->cr) & RCC_CR_PLL1RDY))
393 /* Select HSE as PLL clock source */
394 pllckselr |= RCC_PLLCKSELR_PLLSRC_HSE;
395 pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT;
396 writel(pllckselr, ®s->pllckselr);
398 pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT;
399 pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT;
400 pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT;
401 pll1divr |= (sys_pll_psc.divn - 1);
402 writel(pll1divr, ®s->pll1divr);
404 pllcfgr |= PLL1RGE_4_8_MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT;
405 pllcfgr |= RCC_PLLCFGR_DIVP1EN;
406 pllcfgr |= RCC_PLLCFGR_DIVQ1EN;
407 pllcfgr |= RCC_PLLCFGR_DIVR1EN;
408 writel(pllcfgr, ®s->pllcfgr);
410 /* pll setup, enable it */
411 setbits_le32(®s->cr, RCC_CR_PLL1ON);
413 /* set HPRE (/2) DI clk --> 125MHz */
414 clrsetbits_le32(®s->d1cfgr, RCC_D1CFGR_HPRE_MASK,
415 RCC_D1CFGR_HPRE_DIV2);
417 /* select PLL1 as system clock source (sys_ck)*/
418 clrsetbits_le32(®s->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1);
419 while ((readl(®s->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1)
422 /* sdram: use pll1_q as fmc_k clk */
423 clrsetbits_le32(®s->d1ccipr, RCC_D1CCIPR_FMCSRC_MASK,
429 static u32 stm32_get_HSI_divider(struct stm32_rcc_regs *regs)
433 /* get HSI divider value */
434 divider = readl(®s->cr) & RCC_CR_HSIDIV_MASK;
435 divider = divider >> RCC_CR_HSIDIV_SHIFT;
450 static const char * const pllsrc_name[PLLSRC_NB] = {
456 [TIMER] = "timer-clk"
459 static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc)
462 struct udevice *fixed_clock_dev = NULL;
465 const char *name = pllsrc_name[pllsrc];
467 debug("%s name %s\n", __func__, name);
470 ret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev);
472 pr_err("Can't find clk %s (%d)", name, ret);
476 ret = clk_request(fixed_clock_dev, &clk);
478 pr_err("Can't request %s clk (%d)", name, ret);
484 divider = stm32_get_HSI_divider(regs);
486 debug("%s divider %d rate %ld\n", __func__,
487 divider, clk_get_rate(&clk));
489 return clk_get_rate(&clk) >> divider;
498 static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
499 enum pll1_output output)
502 u32 divm1, divn1, divp1, divq1, divr1, fracn1;
506 switch (readl(®s->pllckselr) & RCC_PLLCKSELR_PLLSRC_MASK) {
507 case RCC_PLLCKSELR_PLLSRC_HSI:
508 pllsrc = stm32_get_rate(regs, HSI);
510 case RCC_PLLCKSELR_PLLSRC_CSI:
511 pllsrc = stm32_get_rate(regs, CSI);
513 case RCC_PLLCKSELR_PLLSRC_HSE:
514 pllsrc = stm32_get_rate(regs, HSE);
516 case RCC_PLLCKSELR_PLLSRC_NO_CLK:
517 /* shouldn't happen */
518 pr_err("wrong value for RCC_PLLCKSELR register\n");
523 /* pllsrc = 0 ? no need to go ahead */
527 /* get divm1, divp1, divn1 and divr1 */
528 divm1 = readl(®s->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK;
529 divm1 = divm1 >> RCC_PLLCKSELR_DIVM1_SHIFT;
531 divn1 = (readl(®s->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1;
533 divp1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK;
534 divp1 = (divp1 >> RCC_PLL1DIVR_DIVP1_SHIFT) + 1;
536 divq1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVQ1_MASK;
537 divq1 = (divq1 >> RCC_PLL1DIVR_DIVQ1_SHIFT) + 1;
539 divr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;
540 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1;
542 fracn1 = readl(®s->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK;
543 fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT;
545 vco = (pllsrc / divm1) * divn1;
546 rate = (pllsrc * fracn1) / (divm1 * 8192);
548 debug("%s divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n",
549 __func__, divm1, divn1, divp1, divq1, divr1);
550 debug("%s fracn1 = %d vco = %ld rate = %ld\n",
551 __func__, fracn1, vco, rate);
555 return (vco + rate) / divp1;
558 return (vco + rate) / divq1;
562 return (vco + rate) / divr1;
569 static u32 stm32_get_apb_psc(struct stm32_rcc_regs *regs, enum apb apb)
571 u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
572 u32 d2cfgr = readl(®s->d2cfgr);
575 if (d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED)
576 /* get D2 domain APB1 prescaler */
577 return prescaler_table[
578 ((d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER)
579 >> RCC_D2CFGR_D2PPRE1_SHIFT)];
581 if (d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED)
582 /* get D2 domain APB2 prescaler */
583 return prescaler_table[
584 ((d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER)
585 >> RCC_D2CFGR_D2PPRE2_SHIFT)];
591 static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
594 struct stm32_rcc_regs *regs = priv->rcc_base;
595 u32 psc = stm32_get_apb_psc(regs, apb);
597 if (readl(®s->cfgr) & RCC_CFGR_TIMPRE)
599 * if APB prescaler is configured to a
600 * division factor of 1, 2 or 4
612 pr_err("unexpected prescaler value (%d)\n", psc);
625 pr_err("unexpected prescaler value (%d)\n", psc);
630 static ulong stm32_clk_get_rate(struct clk *clk)
632 struct stm32_clk *priv = dev_get_priv(clk->dev);
633 struct stm32_rcc_regs *regs = priv->rcc_base;
637 /* prescaler table lookups for clock computation */
638 u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
642 * get system clock (sys_ck) source
643 * can be HSI_CK, CSI_CK, HSE_CK or pll1_p_ck
645 source = readl(®s->cfgr) & RCC_CFGR_SW_MASK;
647 case RCC_CFGR_SW_PLL1:
648 sysclk = stm32_get_PLL1_rate(regs, PLL1_P_CK);
650 case RCC_CFGR_SW_HSE:
651 sysclk = stm32_get_rate(regs, HSE);
654 case RCC_CFGR_SW_CSI:
655 sysclk = stm32_get_rate(regs, CSI);
658 case RCC_CFGR_SW_HSI:
659 sysclk = stm32_get_rate(regs, HSI);
663 /* sysclk = 0 ? no need to go ahead */
667 debug("%s system clock: source = %d freq = %ld\n",
668 __func__, source, sysclk);
670 d1cfgr = readl(®s->d1cfgr);
672 if (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDED) {
673 /* get D1 domain Core prescaler */
674 idx = (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDER) >>
675 RCC_D1CFGR_D1CPRE_SHIFT;
676 sysclk = sysclk / prescaler_table[idx];
679 if (d1cfgr & RCC_D1CFGR_HPRE_DIVIDED) {
680 /* get D1 domain AHB prescaler */
681 idx = d1cfgr & RCC_D1CFGR_HPRE_DIVIDER;
682 sysclk = sysclk / prescaler_table[idx];
685 gate_offset = clk_map[clk->id].gate_offset;
687 debug("%s clk->id=%ld gate_offset=0x%x sysclk=%ld\n",
688 __func__, clk->id, gate_offset, sysclk);
690 switch (gate_offset) {
699 if (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDED) {
700 /* get D1 domain APB3 prescaler */
701 idx = (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDER) >>
702 RCC_D1CFGR_D1PPRE_SHIFT;
703 sysclk = sysclk / prescaler_table[idx];
706 debug("%s system clock: freq after APB3 prescaler = %ld\n",
713 d3cfgr = readl(®s->d3cfgr);
714 if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
715 /* get D3 domain APB4 prescaler */
716 idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
717 RCC_D3CFGR_D3PPRE_SHIFT;
718 sysclk = sysclk / prescaler_table[idx];
721 debug("%s system clock: freq after APB4 prescaler = %ld\n",
729 /* special case for GPT timers */
740 return stm32_get_timer_rate(priv, sysclk, APB1);
743 debug("%s system clock: freq after APB1 prescaler = %ld\n",
746 return (sysclk / stm32_get_apb_psc(regs, APB1));
750 /* special case for timers */
757 return stm32_get_timer_rate(priv, sysclk, APB2);
760 debug("%s system clock: freq after APB2 prescaler = %ld\n",
763 return (sysclk / stm32_get_apb_psc(regs, APB2));
768 pr_err("unexpected gate_offset value (0x%x)\n", gate_offset);
774 static int stm32_clk_enable(struct clk *clk)
776 struct stm32_clk *priv = dev_get_priv(clk->dev);
777 struct stm32_rcc_regs *regs = priv->rcc_base;
780 unsigned long clk_id = clk->id;
782 gate_offset = clk_map[clk_id].gate_offset;
783 gate_bit_index = clk_map[clk_id].gate_bit_idx;
785 debug("%s: clkid=%ld gate offset=0x%x bit_index=%d name=%s\n",
786 __func__, clk->id, gate_offset, gate_bit_index,
787 clk_map[clk_id].name);
789 setbits_le32(®s->cr + (gate_offset / 4), BIT(gate_bit_index));
794 static int stm32_clk_probe(struct udevice *dev)
796 struct stm32_clk *priv = dev_get_priv(dev);
797 struct udevice *syscon;
801 addr = dev_read_addr(dev);
802 if (addr == FDT_ADDR_T_NONE)
805 priv->rcc_base = (struct stm32_rcc_regs *)addr;
807 /* get corresponding syscon phandle */
808 err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
809 "st,syscfg", &syscon);
812 pr_err("unable to find syscon device\n");
816 priv->pwr_regmap = syscon_get_regmap(syscon);
817 if (!priv->pwr_regmap) {
818 pr_err("unable to find regmap\n");
822 configure_clocks(dev);
827 static int stm32_clk_of_xlate(struct clk *clk,
828 struct ofnode_phandle_args *args)
830 if (args->args_count != 1) {
831 debug("Invaild args_count: %d\n", args->args_count);
835 if (args->args_count) {
836 clk->id = args->args[0];
838 * this computation convert DT clock index which is used to
839 * point into 2 separate clock arrays (peripheral and kernel
840 * clocks bank) (see include/dt-bindings/clock/stm32h7-clks.h)
841 * into index to point into only one array where peripheral
842 * and kernel clocks are consecutive
844 if (clk->id >= KERN_BANK) {
845 clk->id -= KERN_BANK;
846 clk->id += LAST_PERIF_BANK - PERIF_BANK + 1;
848 clk->id -= PERIF_BANK;
854 debug("%s clk->id %ld\n", __func__, clk->id);
859 static struct clk_ops stm32_clk_ops = {
860 .of_xlate = stm32_clk_of_xlate,
861 .enable = stm32_clk_enable,
862 .get_rate = stm32_clk_get_rate,
865 U_BOOT_DRIVER(stm32h7_clk) = {
866 .name = "stm32h7_rcc_clock",
868 .ops = &stm32_clk_ops,
869 .probe = stm32_clk_probe,
870 .priv_auto_alloc_size = sizeof(struct stm32_clk),
871 .flags = DM_FLAG_PRE_RELOC,