git.sur5r.net Git - u-boot/blob - drivers/clk/clk_stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk-uclass.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <regmap.h>
  11 #include <spl.h>
  12 #include <syscon.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <dt-bindings/clock/stm32mp1-clks.h>
  16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  17
  18 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  19 /* activate clock tree initialization in the driver */
  20 #define STM32MP1_CLOCK_TREE_INIT
  21 #endif
  22
  23 #define MAX_HSI_HZ              64000000
  24
  25 /* TIMEOUT */
  26 #define TIMEOUT_200MS           200000
  27 #define TIMEOUT_1S              1000000
  28
  29 /* STGEN registers */
  30 #define STGENC_CNTCR            0x00
  31 #define STGENC_CNTSR            0x04
  32 #define STGENC_CNTCVL           0x08
  33 #define STGENC_CNTCVU           0x0C
  34 #define STGENC_CNTFID0          0x20
  35
  36 #define STGENC_CNTCR_EN         BIT(0)
  37
  38 /* RCC registers */
  39 #define RCC_OCENSETR            0x0C
  40 #define RCC_OCENCLRR            0x10
  41 #define RCC_HSICFGR             0x18
  42 #define RCC_MPCKSELR            0x20
  43 #define RCC_ASSCKSELR           0x24
  44 #define RCC_RCK12SELR           0x28
  45 #define RCC_MPCKDIVR            0x2C
  46 #define RCC_AXIDIVR             0x30
  47 #define RCC_APB4DIVR            0x3C
  48 #define RCC_APB5DIVR            0x40
  49 #define RCC_RTCDIVR             0x44
  50 #define RCC_MSSCKSELR           0x48
  51 #define RCC_PLL1CR              0x80
  52 #define RCC_PLL1CFGR1           0x84
  53 #define RCC_PLL1CFGR2           0x88
  54 #define RCC_PLL1FRACR           0x8C
  55 #define RCC_PLL1CSGR            0x90
  56 #define RCC_PLL2CR              0x94
  57 #define RCC_PLL2CFGR1           0x98
  58 #define RCC_PLL2CFGR2           0x9C
  59 #define RCC_PLL2FRACR           0xA0
  60 #define RCC_PLL2CSGR            0xA4
  61 #define RCC_I2C46CKSELR         0xC0
  62 #define RCC_CPERCKSELR          0xD0
  63 #define RCC_STGENCKSELR         0xD4
  64 #define RCC_DDRITFCR            0xD8
  65 #define RCC_BDCR                0x140
  66 #define RCC_RDLSICR             0x144
  67 #define RCC_MP_APB4ENSETR       0x200
  68 #define RCC_MP_APB5ENSETR       0x208
  69 #define RCC_MP_AHB5ENSETR       0x210
  70 #define RCC_MP_AHB6ENSETR       0x218
  71 #define RCC_OCRDYR              0x808
  72 #define RCC_DBGCFGR             0x80C
  73 #define RCC_RCK3SELR            0x820
  74 #define RCC_RCK4SELR            0x824
  75 #define RCC_MCUDIVR             0x830
  76 #define RCC_APB1DIVR            0x834
  77 #define RCC_APB2DIVR            0x838
  78 #define RCC_APB3DIVR            0x83C
  79 #define RCC_PLL3CR              0x880
  80 #define RCC_PLL3CFGR1           0x884
  81 #define RCC_PLL3CFGR2           0x888
  82 #define RCC_PLL3FRACR           0x88C
  83 #define RCC_PLL3CSGR            0x890
  84 #define RCC_PLL4CR              0x894
  85 #define RCC_PLL4CFGR1           0x898
  86 #define RCC_PLL4CFGR2           0x89C
  87 #define RCC_PLL4FRACR           0x8A0
  88 #define RCC_PLL4CSGR            0x8A4
  89 #define RCC_I2C12CKSELR         0x8C0
  90 #define RCC_I2C35CKSELR         0x8C4
  91 #define RCC_UART6CKSELR         0x8E4
  92 #define RCC_UART24CKSELR        0x8E8
  93 #define RCC_UART35CKSELR        0x8EC
  94 #define RCC_UART78CKSELR        0x8F0
  95 #define RCC_SDMMC12CKSELR       0x8F4
  96 #define RCC_SDMMC3CKSELR        0x8F8
  97 #define RCC_ETHCKSELR           0x8FC
  98 #define RCC_QSPICKSELR          0x900
  99 #define RCC_FMCCKSELR           0x904
 100 #define RCC_USBCKSELR           0x91C
 101 #define RCC_MP_APB1ENSETR       0xA00
 102 #define RCC_MP_APB2ENSETR       0XA08
 103 #define RCC_MP_APB3ENSETR       0xA10
 104 #define RCC_MP_AHB2ENSETR       0xA18
 105 #define RCC_MP_AHB4ENSETR       0xA28
 106
 107 /* used for most of SELR register */
 108 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 109 #define RCC_SELR_SRCRDY         BIT(31)
 110
 111 /* Values of RCC_MPCKSELR register */
 112 #define RCC_MPCKSELR_HSI        0
 113 #define RCC_MPCKSELR_HSE        1
 114 #define RCC_MPCKSELR_PLL        2
 115 #define RCC_MPCKSELR_PLL_MPUDIV 3
 116
 117 /* Values of RCC_ASSCKSELR register */
 118 #define RCC_ASSCKSELR_HSI       0
 119 #define RCC_ASSCKSELR_HSE       1
 120 #define RCC_ASSCKSELR_PLL       2
 121
 122 /* Values of RCC_MSSCKSELR register */
 123 #define RCC_MSSCKSELR_HSI       0
 124 #define RCC_MSSCKSELR_HSE       1
 125 #define RCC_MSSCKSELR_CSI       2
 126 #define RCC_MSSCKSELR_PLL       3
 127
 128 /* Values of RCC_CPERCKSELR register */
 129 #define RCC_CPERCKSELR_HSI      0
 130 #define RCC_CPERCKSELR_CSI      1
 131 #define RCC_CPERCKSELR_HSE      2
 132
 133 /* used for most of DIVR register : max div for RTC */
 134 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 135 #define RCC_DIVR_DIVRDY         BIT(31)
 136
 137 /* Masks for specific DIVR registers */
 138 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 139 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 140 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 141 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 142
 143 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 144 #define RCC_MP_ENCLRR_OFFSET    4
 145
 146 /* Fields of RCC_BDCR register */
 147 #define RCC_BDCR_LSEON          BIT(0)
 148 #define RCC_BDCR_LSEBYP         BIT(1)
 149 #define RCC_BDCR_LSERDY         BIT(2)
 150 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 151 #define RCC_BDCR_LSEDRV_SHIFT   4
 152 #define RCC_BDCR_LSECSSON       BIT(8)
 153 #define RCC_BDCR_RTCCKEN        BIT(20)
 154 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 155 #define RCC_BDCR_RTCSRC_SHIFT   16
 156
 157 /* Fields of RCC_RDLSICR register */
 158 #define RCC_RDLSICR_LSION       BIT(0)
 159 #define RCC_RDLSICR_LSIRDY      BIT(1)
 160
 161 /* used for ALL PLLNCR registers */
 162 #define RCC_PLLNCR_PLLON        BIT(0)
 163 #define RCC_PLLNCR_PLLRDY       BIT(1)
 164 #define RCC_PLLNCR_DIVPEN       BIT(4)
 165 #define RCC_PLLNCR_DIVQEN       BIT(5)
 166 #define RCC_PLLNCR_DIVREN       BIT(6)
 167 #define RCC_PLLNCR_DIVEN_SHIFT  4
 168
 169 /* used for ALL PLLNCFGR1 registers */
 170 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 171 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 172 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 173 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 174 /* only for PLL3 and PLL4 */
 175 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 176 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 177
 178 /* used for ALL PLLNCFGR2 registers */
 179 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 180 #define RCC_PLLNCFGR2_DIVP_SHIFT        0
 181 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 182 #define RCC_PLLNCFGR2_DIVQ_SHIFT        8
 183 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 184 #define RCC_PLLNCFGR2_DIVR_SHIFT        16
 185 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 186
 187 /* used for ALL PLLNFRACR registers */
 188 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 189 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 190 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 191
 192 /* used for ALL PLLNCSGR registers */
 193 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 194 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 195 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 196 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 197 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 198 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 199
 200 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 201 #define RCC_OCENR_HSION                 BIT(0)
 202 #define RCC_OCENR_CSION                 BIT(4)
 203 #define RCC_OCENR_HSEON                 BIT(8)
 204 #define RCC_OCENR_HSEBYP                BIT(10)
 205 #define RCC_OCENR_HSECSSON              BIT(11)
 206
 207 /* Fields of RCC_OCRDYR register */
 208 #define RCC_OCRDYR_HSIRDY               BIT(0)
 209 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 210 #define RCC_OCRDYR_CSIRDY               BIT(4)
 211 #define RCC_OCRDYR_HSERDY               BIT(8)
 212
 213 /* Fields of DDRITFCR register */
 214 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 215 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 216 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 217
 218 /* Fields of RCC_HSICFGR register */
 219 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 220
 221 /* used for MCO related operations */
 222 #define RCC_MCOCFG_MCOON                BIT(12)
 223 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 224 #define RCC_MCOCFG_MCODIV_SHIFT         4
 225 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 226
 227 enum stm32mp1_parent_id {
 228 /*
 229  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 230  * they are used as index in osc[] as entry point
 231  */
 232         _HSI,
 233         _HSE,
 234         _CSI,
 235         _LSI,
 236         _LSE,
 237         _I2S_CKIN,
 238         _USB_PHY_48,
 239         NB_OSC,
 240
 241 /* other parent source */
 242         _HSI_KER = NB_OSC,
 243         _HSE_KER,
 244         _HSE_KER_DIV2,
 245         _CSI_KER,
 246         _PLL1_P,
 247         _PLL1_Q,
 248         _PLL1_R,
 249         _PLL2_P,
 250         _PLL2_Q,
 251         _PLL2_R,
 252         _PLL3_P,
 253         _PLL3_Q,
 254         _PLL3_R,
 255         _PLL4_P,
 256         _PLL4_Q,
 257         _PLL4_R,
 258         _ACLK,
 259         _PCLK1,
 260         _PCLK2,
 261         _PCLK3,
 262         _PCLK4,
 263         _PCLK5,
 264         _HCLK6,
 265         _HCLK2,
 266         _CK_PER,
 267         _CK_MPU,
 268         _CK_MCU,
 269         _PARENT_NB,
 270         _UNKNOWN_ID = 0xff,
 271 };
 272
 273 enum stm32mp1_parent_sel {
 274         _I2C12_SEL,
 275         _I2C35_SEL,
 276         _I2C46_SEL,
 277         _UART6_SEL,
 278         _UART24_SEL,
 279         _UART35_SEL,
 280         _UART78_SEL,
 281         _SDMMC12_SEL,
 282         _SDMMC3_SEL,
 283         _ETH_SEL,
 284         _QSPI_SEL,
 285         _FMC_SEL,
 286         _USBPHY_SEL,
 287         _USBO_SEL,
 288         _STGEN_SEL,
 289         _PARENT_SEL_NB,
 290         _UNKNOWN_SEL = 0xff,
 291 };
 292
 293 enum stm32mp1_pll_id {
 294         _PLL1,
 295         _PLL2,
 296         _PLL3,
 297         _PLL4,
 298         _PLL_NB
 299 };
 300
 301 enum stm32mp1_div_id {
 302         _DIV_P,
 303         _DIV_Q,
 304         _DIV_R,
 305         _DIV_NB,
 306 };
 307
 308 enum stm32mp1_clksrc_id {
 309         CLKSRC_MPU,
 310         CLKSRC_AXI,
 311         CLKSRC_MCU,
 312         CLKSRC_PLL12,
 313         CLKSRC_PLL3,
 314         CLKSRC_PLL4,
 315         CLKSRC_RTC,
 316         CLKSRC_MCO1,
 317         CLKSRC_MCO2,
 318         CLKSRC_NB
 319 };
 320
 321 enum stm32mp1_clkdiv_id {
 322         CLKDIV_MPU,
 323         CLKDIV_AXI,
 324         CLKDIV_MCU,
 325         CLKDIV_APB1,
 326         CLKDIV_APB2,
 327         CLKDIV_APB3,
 328         CLKDIV_APB4,
 329         CLKDIV_APB5,
 330         CLKDIV_RTC,
 331         CLKDIV_MCO1,
 332         CLKDIV_MCO2,
 333         CLKDIV_NB
 334 };
 335
 336 enum stm32mp1_pllcfg {
 337         PLLCFG_M,
 338         PLLCFG_N,
 339         PLLCFG_P,
 340         PLLCFG_Q,
 341         PLLCFG_R,
 342         PLLCFG_O,
 343         PLLCFG_NB
 344 };
 345
 346 enum stm32mp1_pllcsg {
 347         PLLCSG_MOD_PER,
 348         PLLCSG_INC_STEP,
 349         PLLCSG_SSCG_MODE,
 350         PLLCSG_NB
 351 };
 352
 353 enum stm32mp1_plltype {
 354         PLL_800,
 355         PLL_1600,
 356         PLL_TYPE_NB
 357 };
 358
 359 struct stm32mp1_pll {
 360         u8 refclk_min;
 361         u8 refclk_max;
 362         u8 divn_max;
 363 };
 364
 365 struct stm32mp1_clk_gate {
 366         u16 offset;
 367         u8 bit;
 368         u8 index;
 369         u8 set_clr;
 370         u8 sel;
 371         u8 fixed;
 372 };
 373
 374 struct stm32mp1_clk_sel {
 375         u16 offset;
 376         u8 src;
 377         u8 msk;
 378         u8 nb_parent;
 379         const u8 *parent;
 380 };
 381
 382 #define REFCLK_SIZE 4
 383 struct stm32mp1_clk_pll {
 384         enum stm32mp1_plltype plltype;
 385         u16 rckxselr;
 386         u16 pllxcfgr1;
 387         u16 pllxcfgr2;
 388         u16 pllxfracr;
 389         u16 pllxcr;
 390         u16 pllxcsgr;
 391         u8 refclk[REFCLK_SIZE];
 392 };
 393
 394 struct stm32mp1_clk_data {
 395         const struct stm32mp1_clk_gate *gate;
 396         const struct stm32mp1_clk_sel *sel;
 397         const struct stm32mp1_clk_pll *pll;
 398         const int nb_gate;
 399 };
 400
 401 struct stm32mp1_clk_priv {
 402         fdt_addr_t base;
 403         const struct stm32mp1_clk_data *data;
 404         ulong osc[NB_OSC];
 405         struct udevice *osc_dev[NB_OSC];
 406 };
 407
 408 #define STM32MP1_CLK(off, b, idx, s)            \
 409         {                                       \
 410                 .offset = (off),                \
 411                 .bit = (b),                     \
 412                 .index = (idx),                 \
 413                 .set_clr = 0,                   \
 414                 .sel = (s),                     \
 415                 .fixed = _UNKNOWN_ID,           \
 416         }
 417
 418 #define STM32MP1_CLK_F(off, b, idx, f)          \
 419         {                                       \
 420                 .offset = (off),                \
 421                 .bit = (b),                     \
 422                 .index = (idx),                 \
 423                 .set_clr = 0,                   \
 424                 .sel = _UNKNOWN_SEL,            \
 425                 .fixed = (f),                   \
 426         }
 427
 428 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 429         {                                       \
 430                 .offset = (off),                \
 431                 .bit = (b),                     \
 432                 .index = (idx),                 \
 433                 .set_clr = 1,                   \
 434                 .sel = (s),                     \
 435                 .fixed = _UNKNOWN_ID,           \
 436         }
 437
 438 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 439         {                                       \
 440                 .offset = (off),                \
 441                 .bit = (b),                     \
 442                 .index = (idx),                 \
 443                 .set_clr = 1,                   \
 444                 .sel = _UNKNOWN_SEL,            \
 445                 .fixed = (f),                   \
 446         }
 447
 448 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 449         [(idx)] = {                             \
 450                 .offset = (off),                \
 451                 .src = (s),                     \
 452                 .msk = (m),                     \
 453                 .parent = (p),                  \
 454                 .nb_parent = ARRAY_SIZE((p))    \
 455         }
 456
 457 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 458                         p1, p2, p3, p4) \
 459         [(idx)] = {                             \
 460                 .plltype = (type),                      \
 461                 .rckxselr = (off1),             \
 462                 .pllxcfgr1 = (off2),            \
 463                 .pllxcfgr2 = (off3),            \
 464                 .pllxfracr = (off4),            \
 465                 .pllxcr = (off5),               \
 466                 .pllxcsgr = (off6),             \
 467                 .refclk[0] = (p1),              \
 468                 .refclk[1] = (p2),              \
 469                 .refclk[2] = (p3),              \
 470                 .refclk[3] = (p4),              \
 471         }
 472
 473 static const u8 stm32mp1_clks[][2] = {
 474         {CK_PER, _CK_PER},
 475         {CK_MPU, _CK_MPU},
 476         {CK_AXI, _ACLK},
 477         {CK_MCU, _CK_MCU},
 478         {CK_HSE, _HSE},
 479         {CK_CSI, _CSI},
 480         {CK_LSI, _LSI},
 481         {CK_LSE, _LSE},
 482         {CK_HSI, _HSI},
 483         {CK_HSE_DIV2, _HSE_KER_DIV2},
 484 };
 485
 486 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 487         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 488         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 489         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 490         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 491         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 492         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 493         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 494         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 495         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 496         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 497         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 498
 499         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 500         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 501         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 502         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 503         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 504         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 505         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 506         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 507         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 508         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 509
 510         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 511
 512         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
 513
 514         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 515         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 516         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 517
 518         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 519         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 520
 521         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 522         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 523
 524         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 525         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 526         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 527         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 528         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 529         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 530         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 531         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 532         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 533         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 534         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 535
 536         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 537
 538         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
 539         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 540         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 541         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
 542         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 543         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 544         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 545         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 546         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 547         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 548
 549         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 550 };
 551
 552 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 553 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 554 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 555 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 556                                         _HSE_KER};
 557 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 558                                          _HSE_KER};
 559 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 560                                          _HSE_KER};
 561 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 562                                          _HSE_KER};
 563 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 564 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 565 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 566 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 567 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 568 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 569 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 570 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 571
 572 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 573         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 574         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 575         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 576         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 577         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 578                             uart24_parents),
 579         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 580                             uart35_parents),
 581         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 582                             uart78_parents),
 583         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 584                             sdmmc12_parents),
 585         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 586                             sdmmc3_parents),
 587         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 588         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
 589         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
 590         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 591         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 592         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 593 };
 594
 595 #ifdef STM32MP1_CLOCK_TREE_INIT
 596 /* define characteristic of PLL according type */
 597 #define DIVN_MIN        24
 598 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 599         [PLL_800] = {
 600                 .refclk_min = 4,
 601                 .refclk_max = 16,
 602                 .divn_max = 99,
 603                 },
 604         [PLL_1600] = {
 605                 .refclk_min = 8,
 606                 .refclk_max = 16,
 607                 .divn_max = 199,
 608                 },
 609 };
 610 #endif /* STM32MP1_CLOCK_TREE_INIT */
 611
 612 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 613         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 614                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 615                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 616                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 617         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 618                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 619                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 620                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 621         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 622                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 623                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 624                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 625         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 626                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 627                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 628                          _HSI, _HSE, _CSI, _I2S_CKIN),
 629 };
 630
 631 /* Prescaler table lookups for clock computation */
 632 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 633 static const u8 stm32mp1_mcu_div[16] = {
 634         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 635 };
 636
 637 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 638 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 639 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 640 static const u8 stm32mp1_mpu_apbx_div[8] = {
 641         0, 1, 2, 3, 4, 4, 4, 4
 642 };
 643
 644 /* div = /1 /2 /3 /4 */
 645 static const u8 stm32mp1_axi_div[8] = {
 646         1, 2, 3, 4, 4, 4, 4, 4
 647 };
 648
 649 #ifdef DEBUG
 650 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 651         [_HSI] = "HSI",
 652         [_HSE] = "HSE",
 653         [_CSI] = "CSI",
 654         [_LSI] = "LSI",
 655         [_LSE] = "LSE",
 656         [_I2S_CKIN] = "I2S_CKIN",
 657         [_HSI_KER] = "HSI_KER",
 658         [_HSE_KER] = "HSE_KER",
 659         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 660         [_CSI_KER] = "CSI_KER",
 661         [_PLL1_P] = "PLL1_P",
 662         [_PLL1_Q] = "PLL1_Q",
 663         [_PLL1_R] = "PLL1_R",
 664         [_PLL2_P] = "PLL2_P",
 665         [_PLL2_Q] = "PLL2_Q",
 666         [_PLL2_R] = "PLL2_R",
 667         [_PLL3_P] = "PLL3_P",
 668         [_PLL3_Q] = "PLL3_Q",
 669         [_PLL3_R] = "PLL3_R",
 670         [_PLL4_P] = "PLL4_P",
 671         [_PLL4_Q] = "PLL4_Q",
 672         [_PLL4_R] = "PLL4_R",
 673         [_ACLK] = "ACLK",
 674         [_PCLK1] = "PCLK1",
 675         [_PCLK2] = "PCLK2",
 676         [_PCLK3] = "PCLK3",
 677         [_PCLK4] = "PCLK4",
 678         [_PCLK5] = "PCLK5",
 679         [_HCLK6] = "KCLK6",
 680         [_HCLK2] = "HCLK2",
 681         [_CK_PER] = "CK_PER",
 682         [_CK_MPU] = "CK_MPU",
 683         [_CK_MCU] = "CK_MCU",
 684         [_USB_PHY_48] = "USB_PHY_48"
 685 };
 686
 687 static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 688         [_I2C12_SEL] = "I2C12",
 689         [_I2C35_SEL] = "I2C35",
 690         [_I2C46_SEL] = "I2C46",
 691         [_UART6_SEL] = "UART6",
 692         [_UART24_SEL] = "UART24",
 693         [_UART35_SEL] = "UART35",
 694         [_UART78_SEL] = "UART78",
 695         [_SDMMC12_SEL] = "SDMMC12",
 696         [_SDMMC3_SEL] = "SDMMC3",
 697         [_ETH_SEL] = "ETH",
 698         [_QSPI_SEL] = "QSPI",
 699         [_FMC_SEL] = "FMC",
 700         [_USBPHY_SEL] = "USBPHY",
 701         [_USBO_SEL] = "USBO",
 702         [_STGEN_SEL] = "STGEN"
 703 };
 704 #endif
 705
 706 static const struct stm32mp1_clk_data stm32mp1_data = {
 707         .gate = stm32mp1_clk_gate,
 708         .sel = stm32mp1_clk_sel,
 709         .pll = stm32mp1_clk_pll,
 710         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 711 };
 712
 713 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 714 {
 715         if (idx >= NB_OSC) {
 716                 debug("%s: clk id %d not found\n", __func__, idx);
 717                 return 0;
 718         }
 719
 720         debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
 721               (u32)priv->osc[idx], priv->osc[idx] / 1000);
 722
 723         return priv->osc[idx];
 724 }
 725
 726 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 727 {
 728         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 729         int i, nb_clks = priv->data->nb_gate;
 730
 731         for (i = 0; i < nb_clks; i++) {
 732                 if (gate[i].index == id)
 733                         break;
 734         }
 735
 736         if (i == nb_clks) {
 737                 printf("%s: clk id %d not found\n", __func__, (u32)id);
 738                 return -EINVAL;
 739         }
 740
 741         return i;
 742 }
 743
 744 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 745                                 int i)
 746 {
 747         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 748
 749         if (gate[i].sel > _PARENT_SEL_NB) {
 750                 printf("%s: parents for clk id %d not found\n",
 751                        __func__, i);
 752                 return -EINVAL;
 753         }
 754
 755         return gate[i].sel;
 756 }
 757
 758 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 759                                          int i)
 760 {
 761         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 762
 763         if (gate[i].fixed == _UNKNOWN_ID)
 764                 return -ENOENT;
 765
 766         return gate[i].fixed;
 767 }
 768
 769 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 770                                    unsigned long id)
 771 {
 772         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 773         int i;
 774         int s, p;
 775
 776         for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
 777                 if (stm32mp1_clks[i][0] == id)
 778                         return stm32mp1_clks[i][1];
 779
 780         i = stm32mp1_clk_get_id(priv, id);
 781         if (i < 0)
 782                 return i;
 783
 784         p = stm32mp1_clk_get_fixed_parent(priv, i);
 785         if (p >= 0 && p < _PARENT_NB)
 786                 return p;
 787
 788         s = stm32mp1_clk_get_sel(priv, i);
 789         if (s < 0)
 790                 return s;
 791
 792         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 793
 794         if (p < sel[s].nb_parent) {
 795 #ifdef DEBUG
 796                 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
 797                       stm32mp1_clk_parent_name[sel[s].parent[p]],
 798                       stm32mp1_clk_parent_sel_name[s],
 799                       (u32)id);
 800 #endif
 801                 return sel[s].parent[p];
 802         }
 803
 804         pr_err("%s: no parents defined for clk id %d\n",
 805                __func__, (u32)id);
 806
 807         return -EINVAL;
 808 }
 809
 810 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 811                                     int pll_id, int div_id)
 812 {
 813         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 814         int divm, divn, divy, src;
 815         ulong refclk, dfout;
 816         u32 selr, cfgr1, cfgr2, fracr;
 817         const u8 shift[_DIV_NB] = {
 818                 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
 819                 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
 820                 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT };
 821
 822         debug("%s(%d, %d)\n", __func__, pll_id, div_id);
 823         if (div_id > _DIV_NB)
 824                 return 0;
 825
 826         selr = readl(priv->base + pll[pll_id].rckxselr);
 827         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 828         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 829         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 830
 831         debug("PLL%d : selr=%x cfgr1=%x cfgr2=%x fracr=%x\n",
 832               pll_id, selr, cfgr1, cfgr2, fracr);
 833
 834         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 835         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 836         divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
 837
 838         debug("        DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
 839
 840         src = selr & RCC_SELR_SRC_MASK;
 841         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 842
 843         debug("        refclk = %d kHz\n", (u32)(refclk / 1000));
 844
 845         /*
 846          * For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
 847          * So same final result than PLL2 et 4
 848          * with FRACV :
 849          *   Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
 850          *               / (DIVM + 1) * (DIVy + 1)
 851          * without FRACV
 852          *   Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1)
 853          */
 854         if (fracr & RCC_PLLNFRACR_FRACLE) {
 855                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 856                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 857                 dfout = (ulong)lldiv((unsigned long long)refclk *
 858                                      (((divn + 1) << 13) + fracv),
 859                                      ((unsigned long long)(divm + 1) *
 860                                       (divy + 1)) << 13);
 861         } else {
 862                 dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1));
 863         }
 864         debug("        => dfout = %d kHz\n", (u32)(dfout / 1000));
 865
 866         return dfout;
 867 }
 868
 869 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 870 {
 871         u32 reg;
 872         ulong clock = 0;
 873
 874         switch (p) {
 875         case _CK_MPU:
 876         /* MPU sub system */
 877                 reg = readl(priv->base + RCC_MPCKSELR);
 878                 switch (reg & RCC_SELR_SRC_MASK) {
 879                 case RCC_MPCKSELR_HSI:
 880                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 881                         break;
 882                 case RCC_MPCKSELR_HSE:
 883                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 884                         break;
 885                 case RCC_MPCKSELR_PLL:
 886                 case RCC_MPCKSELR_PLL_MPUDIV:
 887                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 888                         if (p == RCC_MPCKSELR_PLL_MPUDIV) {
 889                                 reg = readl(priv->base + RCC_MPCKDIVR);
 890                                 clock /= stm32mp1_mpu_div[reg &
 891                                                           RCC_MPUDIV_MASK];
 892                         }
 893                         break;
 894                 }
 895                 break;
 896         /* AXI sub system */
 897         case _ACLK:
 898         case _HCLK2:
 899         case _HCLK6:
 900         case _PCLK4:
 901         case _PCLK5:
 902                 reg = readl(priv->base + RCC_ASSCKSELR);
 903                 switch (reg & RCC_SELR_SRC_MASK) {
 904                 case RCC_ASSCKSELR_HSI:
 905                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 906                         break;
 907                 case RCC_ASSCKSELR_HSE:
 908                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 909                         break;
 910                 case RCC_ASSCKSELR_PLL:
 911                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
 912                         break;
 913                 }
 914
 915                 /* System clock divider */
 916                 reg = readl(priv->base + RCC_AXIDIVR);
 917                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
 918
 919                 switch (p) {
 920                 case _PCLK4:
 921                         reg = readl(priv->base + RCC_APB4DIVR);
 922                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 923                         break;
 924                 case _PCLK5:
 925                         reg = readl(priv->base + RCC_APB5DIVR);
 926                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 927                         break;
 928                 default:
 929                         break;
 930                 }
 931                 break;
 932         /* MCU sub system */
 933         case _CK_MCU:
 934         case _PCLK1:
 935         case _PCLK2:
 936         case _PCLK3:
 937                 reg = readl(priv->base + RCC_MSSCKSELR);
 938                 switch (reg & RCC_SELR_SRC_MASK) {
 939                 case RCC_MSSCKSELR_HSI:
 940                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 941                         break;
 942                 case RCC_MSSCKSELR_HSE:
 943                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 944                         break;
 945                 case RCC_MSSCKSELR_CSI:
 946                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
 947                         break;
 948                 case RCC_MSSCKSELR_PLL:
 949                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
 950                         break;
 951                 }
 952
 953                 /* MCU clock divider */
 954                 reg = readl(priv->base + RCC_MCUDIVR);
 955                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
 956
 957                 switch (p) {
 958                 case _PCLK1:
 959                         reg = readl(priv->base + RCC_APB1DIVR);
 960                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 961                         break;
 962                 case _PCLK2:
 963                         reg = readl(priv->base + RCC_APB2DIVR);
 964                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 965                         break;
 966                 case _PCLK3:
 967                         reg = readl(priv->base + RCC_APB3DIVR);
 968                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 969                         break;
 970                 case _CK_MCU:
 971                 default:
 972                         break;
 973                 }
 974                 break;
 975         case _CK_PER:
 976                 reg = readl(priv->base + RCC_CPERCKSELR);
 977                 switch (reg & RCC_SELR_SRC_MASK) {
 978                 case RCC_CPERCKSELR_HSI:
 979                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 980                         break;
 981                 case RCC_CPERCKSELR_HSE:
 982                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 983                         break;
 984                 case RCC_CPERCKSELR_CSI:
 985                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
 986                         break;
 987                 }
 988                 break;
 989         case _HSI:
 990         case _HSI_KER:
 991                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
 992                 break;
 993         case _CSI:
 994         case _CSI_KER:
 995                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
 996                 break;
 997         case _HSE:
 998         case _HSE_KER:
 999         case _HSE_KER_DIV2:
1000                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1001                 if (p == _HSE_KER_DIV2)
1002                         clock >>= 1;
1003                 break;
1004         case _LSI:
1005                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1006                 break;
1007         case _LSE:
1008                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1009                 break;
1010         /* PLL */
1011         case _PLL1_P:
1012         case _PLL1_Q:
1013         case _PLL1_R:
1014                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1015                 break;
1016         case _PLL2_P:
1017         case _PLL2_Q:
1018         case _PLL2_R:
1019                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1020                 break;
1021         case _PLL3_P:
1022         case _PLL3_Q:
1023         case _PLL3_R:
1024                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1025                 break;
1026         case _PLL4_P:
1027         case _PLL4_Q:
1028         case _PLL4_R:
1029                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1030                 break;
1031         /* other */
1032         case _USB_PHY_48:
1033                 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
1034                 break;
1035
1036         default:
1037                 break;
1038         }
1039
1040         debug("%s(%d) clock = %lx : %ld kHz\n",
1041               __func__, p, clock, clock / 1000);
1042
1043         return clock;
1044 }
1045
1046 static int stm32mp1_clk_enable(struct clk *clk)
1047 {
1048         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1049         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1050         int i = stm32mp1_clk_get_id(priv, clk->id);
1051
1052         if (i < 0)
1053                 return i;
1054
1055         if (gate[i].set_clr)
1056                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1057         else
1058                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1059
1060         debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1061
1062         return 0;
1063 }
1064
1065 static int stm32mp1_clk_disable(struct clk *clk)
1066 {
1067         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1068         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1069         int i = stm32mp1_clk_get_id(priv, clk->id);
1070
1071         if (i < 0)
1072                 return i;
1073
1074         if (gate[i].set_clr)
1075                 writel(BIT(gate[i].bit),
1076                        priv->base + gate[i].offset
1077                        + RCC_MP_ENCLRR_OFFSET);
1078         else
1079                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1080
1081         debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1082
1083         return 0;
1084 }
1085
1086 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1087 {
1088         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1089         int p = stm32mp1_clk_get_parent(priv, clk->id);
1090         ulong rate;
1091
1092         if (p < 0)
1093                 return 0;
1094
1095         rate = stm32mp1_clk_get(priv, p);
1096
1097 #ifdef DEBUG
1098         debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1099               __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1100 #endif
1101         return rate;
1102 }
1103
1104 #ifdef STM32MP1_CLOCK_TREE_INIT
1105 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1106                                 u32 mask_on)
1107 {
1108         u32 address = rcc + offset;
1109
1110         if (enable)
1111                 setbits_le32(address, mask_on);
1112         else
1113                 clrbits_le32(address, mask_on);
1114 }
1115
1116 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1117 {
1118         if (enable)
1119                 setbits_le32(rcc + RCC_OCENSETR, mask_on);
1120         else
1121                 setbits_le32(rcc + RCC_OCENCLRR, mask_on);
1122 }
1123
1124 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1125                              u32 mask_rdy)
1126 {
1127         u32 mask_test = 0;
1128         u32 address = rcc + offset;
1129         u32 val;
1130         int ret;
1131
1132         if (enable)
1133                 mask_test = mask_rdy;
1134
1135         ret = readl_poll_timeout(address, val,
1136                                  (val & mask_rdy) == mask_test,
1137                                  TIMEOUT_1S);
1138
1139         if (ret)
1140                 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1141                        mask_rdy, address, enable, readl(address));
1142
1143         return ret;
1144 }
1145
1146 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
1147 {
1148         u32 value;
1149
1150         if (bypass)
1151                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1152
1153         /*
1154          * warning: not recommended to switch directly from "high drive"
1155          * to "medium low drive", and vice-versa.
1156          */
1157         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1158                 >> RCC_BDCR_LSEDRV_SHIFT;
1159
1160         while (value != lsedrv) {
1161                 if (value > lsedrv)
1162                         value--;
1163                 else
1164                         value++;
1165
1166                 clrsetbits_le32(rcc + RCC_BDCR,
1167                                 RCC_BDCR_LSEDRV_MASK,
1168                                 value << RCC_BDCR_LSEDRV_SHIFT);
1169         }
1170
1171         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1172 }
1173
1174 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1175 {
1176         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1177 }
1178
1179 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1180 {
1181         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1182         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1183 }
1184
1185 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
1186 {
1187         if (bypass)
1188                 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1189
1190         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1191         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1192
1193         if (css)
1194                 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
1195 }
1196
1197 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1198 {
1199         stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
1200         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1201 }
1202
1203 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1204 {
1205         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1206         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1207 }
1208
1209 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1210 {
1211         u32 address = rcc + RCC_OCRDYR;
1212         u32 val;
1213         int ret;
1214
1215         clrsetbits_le32(rcc + RCC_HSICFGR,
1216                         RCC_HSICFGR_HSIDIV_MASK,
1217                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1218
1219         ret = readl_poll_timeout(address, val,
1220                                  val & RCC_OCRDYR_HSIDIVRDY,
1221                                  TIMEOUT_200MS);
1222         if (ret)
1223                 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1224                        address, readl(address));
1225
1226         return ret;
1227 }
1228
1229 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1230 {
1231         u8 hsidiv;
1232         u32 hsidivfreq = MAX_HSI_HZ;
1233
1234         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1235              hsidivfreq = hsidivfreq / 2)
1236                 if (hsidivfreq == hsifreq)
1237                         break;
1238
1239         if (hsidiv == 4) {
1240                 pr_err("clk-hsi frequency invalid");
1241                 return -1;
1242         }
1243
1244         if (hsidiv > 0)
1245                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1246
1247         return 0;
1248 }
1249
1250 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1251 {
1252         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1253
1254         writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
1255 }
1256
1257 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1258 {
1259         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1260         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1261         u32 val;
1262         int ret;
1263
1264         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1265                                  TIMEOUT_200MS);
1266
1267         if (ret) {
1268                 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1269                        pll_id, pllxcr, readl(pllxcr));
1270                 return ret;
1271         }
1272
1273         /* start the requested output */
1274         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1275
1276         return 0;
1277 }
1278
1279 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1280 {
1281         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1282         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1283         u32 val;
1284
1285         /* stop all output */
1286         clrbits_le32(pllxcr,
1287                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1288
1289         /* stop PLL */
1290         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1291
1292         /* wait PLL stopped */
1293         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1294                                   TIMEOUT_200MS);
1295 }
1296
1297 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1298                               int pll_id, u32 *pllcfg)
1299 {
1300         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1301         fdt_addr_t rcc = priv->base;
1302         u32 value;
1303
1304         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1305                 & RCC_PLLNCFGR2_DIVP_MASK;
1306         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1307                  & RCC_PLLNCFGR2_DIVQ_MASK;
1308         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1309                  & RCC_PLLNCFGR2_DIVR_MASK;
1310         writel(value, rcc + pll[pll_id].pllxcfgr2);
1311 }
1312
1313 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1314                       u32 *pllcfg, u32 fracv)
1315 {
1316         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1317         fdt_addr_t rcc = priv->base;
1318         enum stm32mp1_plltype type = pll[pll_id].plltype;
1319         int src;
1320         ulong refclk;
1321         u8 ifrge = 0;
1322         u32 value;
1323
1324         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1325
1326         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1327                  (pllcfg[PLLCFG_M] + 1);
1328
1329         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1330             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1331                 debug("invalid refclk = %x\n", (u32)refclk);
1332                 return -EINVAL;
1333         }
1334         if (type == PLL_800 && refclk >= 8000000)
1335                 ifrge = 1;
1336
1337         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1338                  & RCC_PLLNCFGR1_DIVN_MASK;
1339         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1340                  & RCC_PLLNCFGR1_DIVM_MASK;
1341         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1342                  & RCC_PLLNCFGR1_IFRGE_MASK;
1343         writel(value, rcc + pll[pll_id].pllxcfgr1);
1344
1345         /* fractional configuration: load sigma-delta modulator (SDM) */
1346
1347         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1348         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1349                rcc + pll[pll_id].pllxfracr);
1350
1351         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1352         setbits_le32(rcc + pll[pll_id].pllxfracr,
1353                      RCC_PLLNFRACR_FRACLE);
1354
1355         pll_config_output(priv, pll_id, pllcfg);
1356
1357         return 0;
1358 }
1359
1360 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1361 {
1362         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1363         u32 pllxcsg;
1364
1365         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1366                     RCC_PLLNCSGR_MOD_PER_MASK) |
1367                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1368                     RCC_PLLNCSGR_INC_STEP_MASK) |
1369                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1370                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1371
1372         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1373 }
1374
1375 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1376 {
1377         u32 address = priv->base + (clksrc >> 4);
1378         u32 val;
1379         int ret;
1380
1381         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1382         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1383                                  TIMEOUT_200MS);
1384         if (ret)
1385                 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1386                        clksrc, address, readl(address));
1387
1388         return ret;
1389 }
1390
1391 static void stgen_config(struct stm32mp1_clk_priv *priv)
1392 {
1393         int p;
1394         u32 stgenc, cntfid0;
1395         ulong rate;
1396
1397         stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
1398
1399         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1400         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1401         rate = stm32mp1_clk_get(priv, p);
1402
1403         if (cntfid0 != rate) {
1404                 pr_debug("System Generic Counter (STGEN) update\n");
1405                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1406                 writel(0x0, stgenc + STGENC_CNTCVL);
1407                 writel(0x0, stgenc + STGENC_CNTCVU);
1408                 writel(rate, stgenc + STGENC_CNTFID0);
1409                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1410
1411                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1412
1413                 /* need to update gd->arch.timer_rate_hz with new frequency */
1414                 timer_init();
1415                 pr_debug("gd->arch.timer_rate_hz = %x\n",
1416                          (u32)gd->arch.timer_rate_hz);
1417                 pr_debug("Tick = %x\n", (u32)(get_ticks()));
1418         }
1419 }
1420
1421 static int set_clkdiv(unsigned int clkdiv, u32 address)
1422 {
1423         u32 val;
1424         int ret;
1425
1426         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1427         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1428                                  TIMEOUT_200MS);
1429         if (ret)
1430                 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1431                        clkdiv, address, readl(address));
1432
1433         return ret;
1434 }
1435
1436 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1437                              u32 clksrc, u32 clkdiv)
1438 {
1439         u32 address = priv->base + (clksrc >> 4);
1440
1441         /*
1442          * binding clksrc : bit15-4 offset
1443          *                  bit3:   disable
1444          *                  bit2-0: MCOSEL[2:0]
1445          */
1446         if (clksrc & 0x8) {
1447                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1448         } else {
1449                 clrsetbits_le32(address,
1450                                 RCC_MCOCFG_MCOSRC_MASK,
1451                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1452                 clrsetbits_le32(address,
1453                                 RCC_MCOCFG_MCODIV_MASK,
1454                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1455                 setbits_le32(address, RCC_MCOCFG_MCOON);
1456         }
1457 }
1458
1459 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1460                        unsigned int clksrc,
1461                        int lse_css)
1462 {
1463         u32 address = priv->base + RCC_BDCR;
1464
1465         if (readl(address) & RCC_BDCR_RTCCKEN)
1466                 goto skip_rtc;
1467
1468         if (clksrc == CLK_RTC_DISABLED)
1469                 goto skip_rtc;
1470
1471         clrsetbits_le32(address,
1472                         RCC_BDCR_RTCSRC_MASK,
1473                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1474
1475         setbits_le32(address, RCC_BDCR_RTCCKEN);
1476
1477 skip_rtc:
1478         if (lse_css)
1479                 setbits_le32(address, RCC_BDCR_LSECSSON);
1480 }
1481
1482 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1483 {
1484         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1485         u32 value = pkcs & 0xF;
1486         u32 mask = 0xF;
1487
1488         if (pkcs & BIT(31)) {
1489                 mask <<= 4;
1490                 value <<= 4;
1491         }
1492         clrsetbits_le32(address, mask, value);
1493 }
1494
1495 static int stm32mp1_clktree(struct udevice *dev)
1496 {
1497         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1498         fdt_addr_t rcc = priv->base;
1499         unsigned int clksrc[CLKSRC_NB];
1500         unsigned int clkdiv[CLKDIV_NB];
1501         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1502         ofnode plloff[_PLL_NB];
1503         int ret;
1504         int i, len;
1505         int lse_css = 0;
1506         const u32 *pkcs_cell;
1507
1508         /* check mandatory field */
1509         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1510         if (ret < 0) {
1511                 debug("field st,clksrc invalid: error %d\n", ret);
1512                 return -FDT_ERR_NOTFOUND;
1513         }
1514
1515         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1516         if (ret < 0) {
1517                 debug("field st,clkdiv invalid: error %d\n", ret);
1518                 return -FDT_ERR_NOTFOUND;
1519         }
1520
1521         /* check mandatory field in each pll */
1522         for (i = 0; i < _PLL_NB; i++) {
1523                 char name[12];
1524
1525                 sprintf(name, "st,pll@%d", i);
1526                 plloff[i] = dev_read_subnode(dev, name);
1527                 if (!ofnode_valid(plloff[i]))
1528                         continue;
1529                 ret = ofnode_read_u32_array(plloff[i], "cfg",
1530                                             pllcfg[i], PLLCFG_NB);
1531                 if (ret < 0) {
1532                         debug("field cfg invalid: error %d\n", ret);
1533                         return -FDT_ERR_NOTFOUND;
1534                 }
1535         }
1536
1537         debug("configuration MCO\n");
1538         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1539         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1540
1541         debug("switch ON osillator\n");
1542         /*
1543          * switch ON oscillator found in device-tree,
1544          * HSI already ON after bootrom
1545          */
1546         if (priv->osc[_LSI])
1547                 stm32mp1_lsi_set(rcc, 1);
1548
1549         if (priv->osc[_LSE]) {
1550                 int bypass;
1551                 int lsedrv;
1552                 struct udevice *dev = priv->osc_dev[_LSE];
1553
1554                 bypass = dev_read_bool(dev, "st,bypass");
1555                 lse_css = dev_read_bool(dev, "st,css");
1556                 lsedrv = dev_read_u32_default(dev, "st,drive",
1557                                               LSEDRV_MEDIUM_HIGH);
1558
1559                 stm32mp1_lse_enable(rcc, bypass, lsedrv);
1560         }
1561
1562         if (priv->osc[_HSE]) {
1563                 int bypass, css;
1564                 struct udevice *dev = priv->osc_dev[_HSE];
1565
1566                 bypass = dev_read_bool(dev, "st,bypass");
1567                 css = dev_read_bool(dev, "st,css");
1568
1569                 stm32mp1_hse_enable(rcc, bypass, css);
1570         }
1571         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1572          * => switch on CSI even if node is not present in device tree
1573          */
1574         stm32mp1_csi_set(rcc, 1);
1575
1576         /* come back to HSI */
1577         debug("come back to HSI\n");
1578         set_clksrc(priv, CLK_MPU_HSI);
1579         set_clksrc(priv, CLK_AXI_HSI);
1580         set_clksrc(priv, CLK_MCU_HSI);
1581
1582         debug("pll stop\n");
1583         for (i = 0; i < _PLL_NB; i++)
1584                 pll_stop(priv, i);
1585
1586         /* configure HSIDIV */
1587         debug("configure HSIDIV\n");
1588         if (priv->osc[_HSI]) {
1589                 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1590                 stgen_config(priv);
1591         }
1592
1593         /* select DIV */
1594         debug("select DIV\n");
1595         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1596         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1597         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1598         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1599         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1600         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1601         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1602         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1603         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1604
1605         /* no ready bit for RTC */
1606         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1607
1608         /* configure PLLs source */
1609         debug("configure PLLs source\n");
1610         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1611         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1612         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1613
1614         /* configure and start PLLs */
1615         debug("configure PLLs\n");
1616         for (i = 0; i < _PLL_NB; i++) {
1617                 u32 fracv;
1618                 u32 csg[PLLCSG_NB];
1619
1620                 debug("configure PLL %d @ %d\n", i,
1621                       ofnode_to_offset(plloff[i]));
1622                 if (!ofnode_valid(plloff[i]))
1623                         continue;
1624
1625                 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1626                 pll_config(priv, i, pllcfg[i], fracv);
1627                 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1628                 if (!ret) {
1629                         pll_csg(priv, i, csg);
1630                 } else if (ret != -FDT_ERR_NOTFOUND) {
1631                         debug("invalid csg node for pll@%d res=%d\n", i, ret);
1632                         return ret;
1633                 }
1634                 pll_start(priv, i);
1635         }
1636
1637         /* wait and start PLLs ouptut when ready */
1638         for (i = 0; i < _PLL_NB; i++) {
1639                 if (!ofnode_valid(plloff[i]))
1640                         continue;
1641                 debug("output PLL %d\n", i);
1642                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1643         }
1644
1645         /* wait LSE ready before to use it */
1646         if (priv->osc[_LSE])
1647                 stm32mp1_lse_wait(rcc);
1648
1649         /* configure with expected clock source */
1650         debug("CLKSRC\n");
1651         set_clksrc(priv, clksrc[CLKSRC_MPU]);
1652         set_clksrc(priv, clksrc[CLKSRC_AXI]);
1653         set_clksrc(priv, clksrc[CLKSRC_MCU]);
1654         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1655
1656         /* configure PKCK */
1657         debug("PKCK\n");
1658         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1659         if (pkcs_cell) {
1660                 bool ckper_disabled = false;
1661
1662                 for (i = 0; i < len / sizeof(u32); i++) {
1663                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1664
1665                         if (pkcs == CLK_CKPER_DISABLED) {
1666                                 ckper_disabled = true;
1667                                 continue;
1668                         }
1669                         pkcs_config(priv, pkcs);
1670                 }
1671                 /* CKPER is source for some peripheral clock
1672                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
1673                  * only if previous clock is still ON
1674                  * => deactivated CKPER only after switching clock
1675                  */
1676                 if (ckper_disabled)
1677                         pkcs_config(priv, CLK_CKPER_DISABLED);
1678         }
1679
1680         /* STGEN clock source can change with CLK_STGEN_XXX */
1681         stgen_config(priv);
1682
1683         debug("oscillator off\n");
1684         /* switch OFF HSI if not found in device-tree */
1685         if (!priv->osc[_HSI])
1686                 stm32mp1_hsi_set(rcc, 0);
1687
1688         /* Software Self-Refresh mode (SSR) during DDR initilialization */
1689         clrsetbits_le32(priv->base + RCC_DDRITFCR,
1690                         RCC_DDRITFCR_DDRCKMOD_MASK,
1691                         RCC_DDRITFCR_DDRCKMOD_SSR <<
1692                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
1693
1694         return 0;
1695 }
1696 #endif /* STM32MP1_CLOCK_TREE_INIT */
1697
1698 static void stm32mp1_osc_clk_init(const char *name,
1699                                   struct stm32mp1_clk_priv *priv,
1700                                   int index)
1701 {
1702         struct clk clk;
1703         struct udevice *dev = NULL;
1704
1705         priv->osc[index] = 0;
1706         clk.id = 0;
1707         if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1708                 if (clk_request(dev, &clk))
1709                         pr_err("%s request", name);
1710                 else
1711                         priv->osc[index] = clk_get_rate(&clk);
1712         }
1713         priv->osc_dev[index] = dev;
1714 }
1715
1716 static void stm32mp1_osc_init(struct udevice *dev)
1717 {
1718         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1719         int i;
1720         const char *name[NB_OSC] = {
1721                 [_LSI] = "clk-lsi",
1722                 [_LSE] = "clk-lse",
1723                 [_HSI] = "clk-hsi",
1724                 [_HSE] = "clk-hse",
1725                 [_CSI] = "clk-csi",
1726                 [_I2S_CKIN] = "i2s_ckin",
1727                 [_USB_PHY_48] = "ck_usbo_48m"};
1728
1729         for (i = 0; i < NB_OSC; i++) {
1730                 stm32mp1_osc_clk_init(name[i], priv, i);
1731                 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1732         }
1733 }
1734
1735 static int stm32mp1_clk_probe(struct udevice *dev)
1736 {
1737         int result = 0;
1738         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1739
1740         priv->base = dev_read_addr(dev->parent);
1741         if (priv->base == FDT_ADDR_T_NONE)
1742                 return -EINVAL;
1743
1744         priv->data = (void *)&stm32mp1_data;
1745
1746         if (!priv->data->gate || !priv->data->sel ||
1747             !priv->data->pll)
1748                 return -EINVAL;
1749
1750         stm32mp1_osc_init(dev);
1751
1752 #ifdef STM32MP1_CLOCK_TREE_INIT
1753         /* clock tree init is done only one time, before relocation */
1754         if (!(gd->flags & GD_FLG_RELOC))
1755                 result = stm32mp1_clktree(dev);
1756 #endif
1757
1758         return result;
1759 }
1760
1761 static const struct clk_ops stm32mp1_clk_ops = {
1762         .enable = stm32mp1_clk_enable,
1763         .disable = stm32mp1_clk_disable,
1764         .get_rate = stm32mp1_clk_get_rate,
1765 };
1766
1767 static const struct udevice_id stm32mp1_clk_ids[] = {
1768         { .compatible = "st,stm32mp1-rcc-clk" },
1769         { }
1770 };
1771
1772 U_BOOT_DRIVER(stm32mp1_clock) = {
1773         .name = "stm32mp1_clk",
1774         .id = UCLASS_CLK,
1775         .of_match = stm32mp1_clk_ids,
1776         .ops = &stm32mp1_clk_ops,
1777         .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
1778         .probe = stm32mp1_clk_probe,
1779 };