git.sur5r.net Git - u-boot/blob - drivers/clk/clk_stm32mp1.c

   1 /*
   2  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+        BSD-3-Clause
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <div64.h>
  10 #include <dm.h>
  11 #include <regmap.h>
  12 #include <spl.h>
  13 #include <syscon.h>
  14 #include <linux/io.h>
  15 #include <linux/iopoll.h>
  16 #include <dt-bindings/clock/stm32mp1-clks.h>
  17 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  18
  19 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  20 /* activate clock tree initialization in the driver */
  21 #define STM32MP1_CLOCK_TREE_INIT
  22 #endif
  23
  24 #define MAX_HSI_HZ              64000000
  25
  26 /* TIMEOUT */
  27 #define TIMEOUT_200MS           200000
  28 #define TIMEOUT_1S              1000000
  29
  30 /* STGEN registers */
  31 #define STGENC_CNTCR            0x00
  32 #define STGENC_CNTSR            0x04
  33 #define STGENC_CNTCVL           0x08
  34 #define STGENC_CNTCVU           0x0C
  35 #define STGENC_CNTFID0          0x20
  36
  37 #define STGENC_CNTCR_EN         BIT(0)
  38
  39 /* RCC registers */
  40 #define RCC_OCENSETR            0x0C
  41 #define RCC_OCENCLRR            0x10
  42 #define RCC_HSICFGR             0x18
  43 #define RCC_MPCKSELR            0x20
  44 #define RCC_ASSCKSELR           0x24
  45 #define RCC_RCK12SELR           0x28
  46 #define RCC_MPCKDIVR            0x2C
  47 #define RCC_AXIDIVR             0x30
  48 #define RCC_APB4DIVR            0x3C
  49 #define RCC_APB5DIVR            0x40
  50 #define RCC_RTCDIVR             0x44
  51 #define RCC_MSSCKSELR           0x48
  52 #define RCC_PLL1CR              0x80
  53 #define RCC_PLL1CFGR1           0x84
  54 #define RCC_PLL1CFGR2           0x88
  55 #define RCC_PLL1FRACR           0x8C
  56 #define RCC_PLL1CSGR            0x90
  57 #define RCC_PLL2CR              0x94
  58 #define RCC_PLL2CFGR1           0x98
  59 #define RCC_PLL2CFGR2           0x9C
  60 #define RCC_PLL2FRACR           0xA0
  61 #define RCC_PLL2CSGR            0xA4
  62 #define RCC_I2C46CKSELR         0xC0
  63 #define RCC_CPERCKSELR          0xD0
  64 #define RCC_STGENCKSELR         0xD4
  65 #define RCC_DDRITFCR            0xD8
  66 #define RCC_BDCR                0x140
  67 #define RCC_RDLSICR             0x144
  68 #define RCC_MP_APB4ENSETR       0x200
  69 #define RCC_MP_APB5ENSETR       0x208
  70 #define RCC_MP_AHB5ENSETR       0x210
  71 #define RCC_MP_AHB6ENSETR       0x218
  72 #define RCC_OCRDYR              0x808
  73 #define RCC_DBGCFGR             0x80C
  74 #define RCC_RCK3SELR            0x820
  75 #define RCC_RCK4SELR            0x824
  76 #define RCC_MCUDIVR             0x830
  77 #define RCC_APB1DIVR            0x834
  78 #define RCC_APB2DIVR            0x838
  79 #define RCC_APB3DIVR            0x83C
  80 #define RCC_PLL3CR              0x880
  81 #define RCC_PLL3CFGR1           0x884
  82 #define RCC_PLL3CFGR2           0x888
  83 #define RCC_PLL3FRACR           0x88C
  84 #define RCC_PLL3CSGR            0x890
  85 #define RCC_PLL4CR              0x894
  86 #define RCC_PLL4CFGR1           0x898
  87 #define RCC_PLL4CFGR2           0x89C
  88 #define RCC_PLL4FRACR           0x8A0
  89 #define RCC_PLL4CSGR            0x8A4
  90 #define RCC_I2C12CKSELR         0x8C0
  91 #define RCC_I2C35CKSELR         0x8C4
  92 #define RCC_UART6CKSELR         0x8E4
  93 #define RCC_UART24CKSELR        0x8E8
  94 #define RCC_UART35CKSELR        0x8EC
  95 #define RCC_UART78CKSELR        0x8F0
  96 #define RCC_SDMMC12CKSELR       0x8F4
  97 #define RCC_SDMMC3CKSELR        0x8F8
  98 #define RCC_ETHCKSELR           0x8FC
  99 #define RCC_QSPICKSELR          0x900
 100 #define RCC_FMCCKSELR           0x904
 101 #define RCC_USBCKSELR           0x91C
 102 #define RCC_MP_APB1ENSETR       0xA00
 103 #define RCC_MP_APB2ENSETR       0XA08
 104 #define RCC_MP_AHB2ENSETR       0xA18
 105 #define RCC_MP_AHB4ENSETR       0xA28
 106
 107 /* used for most of SELR register */
 108 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 109 #define RCC_SELR_SRCRDY         BIT(31)
 110
 111 /* Values of RCC_MPCKSELR register */
 112 #define RCC_MPCKSELR_HSI        0
 113 #define RCC_MPCKSELR_HSE        1
 114 #define RCC_MPCKSELR_PLL        2
 115 #define RCC_MPCKSELR_PLL_MPUDIV 3
 116
 117 /* Values of RCC_ASSCKSELR register */
 118 #define RCC_ASSCKSELR_HSI       0
 119 #define RCC_ASSCKSELR_HSE       1
 120 #define RCC_ASSCKSELR_PLL       2
 121
 122 /* Values of RCC_MSSCKSELR register */
 123 #define RCC_MSSCKSELR_HSI       0
 124 #define RCC_MSSCKSELR_HSE       1
 125 #define RCC_MSSCKSELR_CSI       2
 126 #define RCC_MSSCKSELR_PLL       3
 127
 128 /* Values of RCC_CPERCKSELR register */
 129 #define RCC_CPERCKSELR_HSI      0
 130 #define RCC_CPERCKSELR_CSI      1
 131 #define RCC_CPERCKSELR_HSE      2
 132
 133 /* used for most of DIVR register : max div for RTC */
 134 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 135 #define RCC_DIVR_DIVRDY         BIT(31)
 136
 137 /* Masks for specific DIVR registers */
 138 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 139 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 140 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 141 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 142
 143 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 144 #define RCC_MP_ENCLRR_OFFSET    4
 145
 146 /* Fields of RCC_BDCR register */
 147 #define RCC_BDCR_LSEON          BIT(0)
 148 #define RCC_BDCR_LSEBYP         BIT(1)
 149 #define RCC_BDCR_LSERDY         BIT(2)
 150 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 151 #define RCC_BDCR_LSEDRV_SHIFT   4
 152 #define RCC_BDCR_LSECSSON       BIT(8)
 153 #define RCC_BDCR_RTCCKEN        BIT(20)
 154 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 155 #define RCC_BDCR_RTCSRC_SHIFT   16
 156
 157 /* Fields of RCC_RDLSICR register */
 158 #define RCC_RDLSICR_LSION       BIT(0)
 159 #define RCC_RDLSICR_LSIRDY      BIT(1)
 160
 161 /* used for ALL PLLNCR registers */
 162 #define RCC_PLLNCR_PLLON        BIT(0)
 163 #define RCC_PLLNCR_PLLRDY       BIT(1)
 164 #define RCC_PLLNCR_DIVPEN       BIT(4)
 165 #define RCC_PLLNCR_DIVQEN       BIT(5)
 166 #define RCC_PLLNCR_DIVREN       BIT(6)
 167 #define RCC_PLLNCR_DIVEN_SHIFT  4
 168
 169 /* used for ALL PLLNCFGR1 registers */
 170 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 171 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 172 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 173 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 174 /* only for PLL3 and PLL4 */
 175 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 176 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 177
 178 /* used for ALL PLLNCFGR2 registers */
 179 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 180 #define RCC_PLLNCFGR2_DIVP_SHIFT        0
 181 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 182 #define RCC_PLLNCFGR2_DIVQ_SHIFT        8
 183 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 184 #define RCC_PLLNCFGR2_DIVR_SHIFT        16
 185 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 186
 187 /* used for ALL PLLNFRACR registers */
 188 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 189 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 190 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 191
 192 /* used for ALL PLLNCSGR registers */
 193 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 194 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 195 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 196 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 197 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 198 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 199
 200 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 201 #define RCC_OCENR_HSION                 BIT(0)
 202 #define RCC_OCENR_CSION                 BIT(4)
 203 #define RCC_OCENR_HSEON                 BIT(8)
 204 #define RCC_OCENR_HSEBYP                BIT(10)
 205 #define RCC_OCENR_HSECSSON              BIT(11)
 206
 207 /* Fields of RCC_OCRDYR register */
 208 #define RCC_OCRDYR_HSIRDY               BIT(0)
 209 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 210 #define RCC_OCRDYR_CSIRDY               BIT(4)
 211 #define RCC_OCRDYR_HSERDY               BIT(8)
 212
 213 /* Fields of DDRITFCR register */
 214 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 215 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 216 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 217
 218 /* Fields of RCC_HSICFGR register */
 219 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 220
 221 /* used for MCO related operations */
 222 #define RCC_MCOCFG_MCOON                BIT(12)
 223 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 224 #define RCC_MCOCFG_MCODIV_SHIFT         4
 225 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 226
 227 enum stm32mp1_parent_id {
 228 /*
 229  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 230  * they are used as index in osc[] as entry point
 231  */
 232         _HSI,
 233         _HSE,
 234         _CSI,
 235         _LSI,
 236         _LSE,
 237         _I2S_CKIN,
 238         _USB_PHY_48,
 239         NB_OSC,
 240
 241 /* other parent source */
 242         _HSI_KER = NB_OSC,
 243         _HSE_KER,
 244         _HSE_KER_DIV2,
 245         _CSI_KER,
 246         _PLL1_P,
 247         _PLL1_Q,
 248         _PLL1_R,
 249         _PLL2_P,
 250         _PLL2_Q,
 251         _PLL2_R,
 252         _PLL3_P,
 253         _PLL3_Q,
 254         _PLL3_R,
 255         _PLL4_P,
 256         _PLL4_Q,
 257         _PLL4_R,
 258         _ACLK,
 259         _PCLK1,
 260         _PCLK2,
 261         _PCLK3,
 262         _PCLK4,
 263         _PCLK5,
 264         _HCLK6,
 265         _HCLK2,
 266         _CK_PER,
 267         _CK_MPU,
 268         _CK_MCU,
 269         _PARENT_NB,
 270         _UNKNOWN_ID = 0xff,
 271 };
 272
 273 enum stm32mp1_parent_sel {
 274         _I2C12_SEL,
 275         _I2C35_SEL,
 276         _I2C46_SEL,
 277         _UART6_SEL,
 278         _UART24_SEL,
 279         _UART35_SEL,
 280         _UART78_SEL,
 281         _SDMMC12_SEL,
 282         _SDMMC3_SEL,
 283         _ETH_SEL,
 284         _QSPI_SEL,
 285         _FMC_SEL,
 286         _USBPHY_SEL,
 287         _USBO_SEL,
 288         _STGEN_SEL,
 289         _PARENT_SEL_NB,
 290         _UNKNOWN_SEL = 0xff,
 291 };
 292
 293 enum stm32mp1_pll_id {
 294         _PLL1,
 295         _PLL2,
 296         _PLL3,
 297         _PLL4,
 298         _PLL_NB
 299 };
 300
 301 enum stm32mp1_div_id {
 302         _DIV_P,
 303         _DIV_Q,
 304         _DIV_R,
 305         _DIV_NB,
 306 };
 307
 308 enum stm32mp1_clksrc_id {
 309         CLKSRC_MPU,
 310         CLKSRC_AXI,
 311         CLKSRC_MCU,
 312         CLKSRC_PLL12,
 313         CLKSRC_PLL3,
 314         CLKSRC_PLL4,
 315         CLKSRC_RTC,
 316         CLKSRC_MCO1,
 317         CLKSRC_MCO2,
 318         CLKSRC_NB
 319 };
 320
 321 enum stm32mp1_clkdiv_id {
 322         CLKDIV_MPU,
 323         CLKDIV_AXI,
 324         CLKDIV_MCU,
 325         CLKDIV_APB1,
 326         CLKDIV_APB2,
 327         CLKDIV_APB3,
 328         CLKDIV_APB4,
 329         CLKDIV_APB5,
 330         CLKDIV_RTC,
 331         CLKDIV_MCO1,
 332         CLKDIV_MCO2,
 333         CLKDIV_NB
 334 };
 335
 336 enum stm32mp1_pllcfg {
 337         PLLCFG_M,
 338         PLLCFG_N,
 339         PLLCFG_P,
 340         PLLCFG_Q,
 341         PLLCFG_R,
 342         PLLCFG_O,
 343         PLLCFG_NB
 344 };
 345
 346 enum stm32mp1_pllcsg {
 347         PLLCSG_MOD_PER,
 348         PLLCSG_INC_STEP,
 349         PLLCSG_SSCG_MODE,
 350         PLLCSG_NB
 351 };
 352
 353 enum stm32mp1_plltype {
 354         PLL_800,
 355         PLL_1600,
 356         PLL_TYPE_NB
 357 };
 358
 359 struct stm32mp1_pll {
 360         u8 refclk_min;
 361         u8 refclk_max;
 362         u8 divn_max;
 363 };
 364
 365 struct stm32mp1_clk_gate {
 366         u16 offset;
 367         u8 bit;
 368         u8 index;
 369         u8 set_clr;
 370         u8 sel;
 371         u8 fixed;
 372 };
 373
 374 struct stm32mp1_clk_sel {
 375         u16 offset;
 376         u8 src;
 377         u8 msk;
 378         u8 nb_parent;
 379         const u8 *parent;
 380 };
 381
 382 #define REFCLK_SIZE 4
 383 struct stm32mp1_clk_pll {
 384         enum stm32mp1_plltype plltype;
 385         u16 rckxselr;
 386         u16 pllxcfgr1;
 387         u16 pllxcfgr2;
 388         u16 pllxfracr;
 389         u16 pllxcr;
 390         u16 pllxcsgr;
 391         u8 refclk[REFCLK_SIZE];
 392 };
 393
 394 struct stm32mp1_clk_data {
 395         const struct stm32mp1_clk_gate *gate;
 396         const struct stm32mp1_clk_sel *sel;
 397         const struct stm32mp1_clk_pll *pll;
 398         const int nb_gate;
 399 };
 400
 401 struct stm32mp1_clk_priv {
 402         fdt_addr_t base;
 403         const struct stm32mp1_clk_data *data;
 404         ulong osc[NB_OSC];
 405         struct udevice *osc_dev[NB_OSC];
 406 };
 407
 408 #define STM32MP1_CLK(off, b, idx, s)            \
 409         {                                       \
 410                 .offset = (off),                \
 411                 .bit = (b),                     \
 412                 .index = (idx),                 \
 413                 .set_clr = 0,                   \
 414                 .sel = (s),                     \
 415                 .fixed = _UNKNOWN_ID,           \
 416         }
 417
 418 #define STM32MP1_CLK_F(off, b, idx, f)          \
 419         {                                       \
 420                 .offset = (off),                \
 421                 .bit = (b),                     \
 422                 .index = (idx),                 \
 423                 .set_clr = 0,                   \
 424                 .sel = _UNKNOWN_SEL,            \
 425                 .fixed = (f),                   \
 426         }
 427
 428 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 429         {                                       \
 430                 .offset = (off),                \
 431                 .bit = (b),                     \
 432                 .index = (idx),                 \
 433                 .set_clr = 1,                   \
 434                 .sel = (s),                     \
 435                 .fixed = _UNKNOWN_ID,           \
 436         }
 437
 438 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 439         {                                       \
 440                 .offset = (off),                \
 441                 .bit = (b),                     \
 442                 .index = (idx),                 \
 443                 .set_clr = 1,                   \
 444                 .sel = _UNKNOWN_SEL,            \
 445                 .fixed = (f),                   \
 446         }
 447
 448 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 449         [(idx)] = {                             \
 450                 .offset = (off),                \
 451                 .src = (s),                     \
 452                 .msk = (m),                     \
 453                 .parent = (p),                  \
 454                 .nb_parent = ARRAY_SIZE((p))    \
 455         }
 456
 457 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 458                         p1, p2, p3, p4) \
 459         [(idx)] = {                             \
 460                 .plltype = (type),                      \
 461                 .rckxselr = (off1),             \
 462                 .pllxcfgr1 = (off2),            \
 463                 .pllxcfgr2 = (off3),            \
 464                 .pllxfracr = (off4),            \
 465                 .pllxcr = (off5),               \
 466                 .pllxcsgr = (off6),             \
 467                 .refclk[0] = (p1),              \
 468                 .refclk[1] = (p2),              \
 469                 .refclk[2] = (p3),              \
 470                 .refclk[3] = (p4),              \
 471         }
 472
 473 static const u8 stm32mp1_clks[][2] = {
 474         {CK_PER, _CK_PER},
 475         {CK_MPU, _CK_MPU},
 476         {CK_AXI, _ACLK},
 477         {CK_MCU, _CK_MCU},
 478         {CK_HSE, _HSE},
 479         {CK_CSI, _CSI},
 480         {CK_LSI, _LSI},
 481         {CK_LSE, _LSE},
 482         {CK_HSI, _HSI},
 483         {CK_HSE_DIV2, _HSE_KER_DIV2},
 484 };
 485
 486 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 487         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 488         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 489         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 490         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 491         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 492         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 493         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 494         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 495         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 496         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 497         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 498
 499         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 500         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 501         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 502         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 503         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 504         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 505         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 506         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 507         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 508         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 509
 510         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 511
 512         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 513         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 514         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 515
 516         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 517         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 518
 519         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 520         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 521
 522         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 523         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 524         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 525         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 526         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 527         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 528         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 529         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 530         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 531         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 532         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 533
 534         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 535
 536         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
 537         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 538         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 539         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
 540         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 541         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 542         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 543         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 544         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 545         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 546
 547         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 548 };
 549
 550 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 551 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 552 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 553 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 554                                         _HSE_KER};
 555 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 556                                          _HSE_KER};
 557 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 558                                          _HSE_KER};
 559 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 560                                          _HSE_KER};
 561 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 562 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 563 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 564 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 565 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 566 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 567 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 568 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 569
 570 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 571         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 572         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 573         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 574         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 575         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 576                             uart24_parents),
 577         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 578                             uart35_parents),
 579         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 580                             uart78_parents),
 581         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 582                             sdmmc12_parents),
 583         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 584                             sdmmc3_parents),
 585         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 586         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
 587         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
 588         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 589         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 590         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 591 };
 592
 593 #ifdef STM32MP1_CLOCK_TREE_INIT
 594 /* define characteristic of PLL according type */
 595 #define DIVN_MIN        24
 596 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 597         [PLL_800] = {
 598                 .refclk_min = 4,
 599                 .refclk_max = 16,
 600                 .divn_max = 99,
 601                 },
 602         [PLL_1600] = {
 603                 .refclk_min = 8,
 604                 .refclk_max = 16,
 605                 .divn_max = 199,
 606                 },
 607 };
 608 #endif /* STM32MP1_CLOCK_TREE_INIT */
 609
 610 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 611         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 612                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 613                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 614                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 615         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 616                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 617                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 618                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 619         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 620                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 621                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 622                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 623         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 624                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 625                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 626                          _HSI, _HSE, _CSI, _I2S_CKIN),
 627 };
 628
 629 /* Prescaler table lookups for clock computation */
 630 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 631 static const u8 stm32mp1_mcu_div[16] = {
 632         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 633 };
 634
 635 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 636 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 637 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 638 static const u8 stm32mp1_mpu_apbx_div[8] = {
 639         0, 1, 2, 3, 4, 4, 4, 4
 640 };
 641
 642 /* div = /1 /2 /3 /4 */
 643 static const u8 stm32mp1_axi_div[8] = {
 644         1, 2, 3, 4, 4, 4, 4, 4
 645 };
 646
 647 #ifdef DEBUG
 648 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 649         [_HSI] = "HSI",
 650         [_HSE] = "HSE",
 651         [_CSI] = "CSI",
 652         [_LSI] = "LSI",
 653         [_LSE] = "LSE",
 654         [_I2S_CKIN] = "I2S_CKIN",
 655         [_HSI_KER] = "HSI_KER",
 656         [_HSE_KER] = "HSE_KER",
 657         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 658         [_CSI_KER] = "CSI_KER",
 659         [_PLL1_P] = "PLL1_P",
 660         [_PLL1_Q] = "PLL1_Q",
 661         [_PLL1_R] = "PLL1_R",
 662         [_PLL2_P] = "PLL2_P",
 663         [_PLL2_Q] = "PLL2_Q",
 664         [_PLL2_R] = "PLL2_R",
 665         [_PLL3_P] = "PLL3_P",
 666         [_PLL3_Q] = "PLL3_Q",
 667         [_PLL3_R] = "PLL3_R",
 668         [_PLL4_P] = "PLL4_P",
 669         [_PLL4_Q] = "PLL4_Q",
 670         [_PLL4_R] = "PLL4_R",
 671         [_ACLK] = "ACLK",
 672         [_PCLK1] = "PCLK1",
 673         [_PCLK2] = "PCLK2",
 674         [_PCLK3] = "PCLK3",
 675         [_PCLK4] = "PCLK4",
 676         [_PCLK5] = "PCLK5",
 677         [_HCLK6] = "KCLK6",
 678         [_HCLK2] = "HCLK2",
 679         [_CK_PER] = "CK_PER",
 680         [_CK_MPU] = "CK_MPU",
 681         [_CK_MCU] = "CK_MCU",
 682         [_USB_PHY_48] = "USB_PHY_48"
 683 };
 684
 685 static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 686         [_I2C12_SEL] = "I2C12",
 687         [_I2C35_SEL] = "I2C35",
 688         [_I2C46_SEL] = "I2C46",
 689         [_UART6_SEL] = "UART6",
 690         [_UART24_SEL] = "UART24",
 691         [_UART35_SEL] = "UART35",
 692         [_UART78_SEL] = "UART78",
 693         [_SDMMC12_SEL] = "SDMMC12",
 694         [_SDMMC3_SEL] = "SDMMC3",
 695         [_ETH_SEL] = "ETH",
 696         [_QSPI_SEL] = "QSPI",
 697         [_FMC_SEL] = "FMC",
 698         [_USBPHY_SEL] = "USBPHY",
 699         [_USBO_SEL] = "USBO",
 700         [_STGEN_SEL] = "STGEN"
 701 };
 702 #endif
 703
 704 static const struct stm32mp1_clk_data stm32mp1_data = {
 705         .gate = stm32mp1_clk_gate,
 706         .sel = stm32mp1_clk_sel,
 707         .pll = stm32mp1_clk_pll,
 708         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 709 };
 710
 711 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 712 {
 713         if (idx >= NB_OSC) {
 714                 debug("%s: clk id %d not found\n", __func__, idx);
 715                 return 0;
 716         }
 717
 718         debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
 719               (u32)priv->osc[idx], priv->osc[idx] / 1000);
 720
 721         return priv->osc[idx];
 722 }
 723
 724 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 725 {
 726         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 727         int i, nb_clks = priv->data->nb_gate;
 728
 729         for (i = 0; i < nb_clks; i++) {
 730                 if (gate[i].index == id)
 731                         break;
 732         }
 733
 734         if (i == nb_clks) {
 735                 printf("%s: clk id %d not found\n", __func__, (u32)id);
 736                 return -EINVAL;
 737         }
 738
 739         return i;
 740 }
 741
 742 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 743                                 int i)
 744 {
 745         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 746
 747         if (gate[i].sel > _PARENT_SEL_NB) {
 748                 printf("%s: parents for clk id %d not found\n",
 749                        __func__, i);
 750                 return -EINVAL;
 751         }
 752
 753         return gate[i].sel;
 754 }
 755
 756 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 757                                          int i)
 758 {
 759         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 760
 761         if (gate[i].fixed == _UNKNOWN_ID)
 762                 return -ENOENT;
 763
 764         return gate[i].fixed;
 765 }
 766
 767 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 768                                    unsigned long id)
 769 {
 770         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 771         int i;
 772         int s, p;
 773
 774         for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
 775                 if (stm32mp1_clks[i][0] == id)
 776                         return stm32mp1_clks[i][1];
 777
 778         i = stm32mp1_clk_get_id(priv, id);
 779         if (i < 0)
 780                 return i;
 781
 782         p = stm32mp1_clk_get_fixed_parent(priv, i);
 783         if (p >= 0 && p < _PARENT_NB)
 784                 return p;
 785
 786         s = stm32mp1_clk_get_sel(priv, i);
 787         if (s < 0)
 788                 return s;
 789
 790         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 791
 792         if (p < sel[s].nb_parent) {
 793 #ifdef DEBUG
 794                 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
 795                       stm32mp1_clk_parent_name[sel[s].parent[p]],
 796                       stm32mp1_clk_parent_sel_name[s],
 797                       (u32)id);
 798 #endif
 799                 return sel[s].parent[p];
 800         }
 801
 802         pr_err("%s: no parents defined for clk id %d\n",
 803                __func__, (u32)id);
 804
 805         return -EINVAL;
 806 }
 807
 808 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 809                                     int pll_id, int div_id)
 810 {
 811         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 812         int divm, divn, divy, src;
 813         ulong refclk, dfout;
 814         u32 selr, cfgr1, cfgr2, fracr;
 815         const u8 shift[_DIV_NB] = {
 816                 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
 817                 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
 818                 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT };
 819
 820         debug("%s(%d, %d)\n", __func__, pll_id, div_id);
 821         if (div_id > _DIV_NB)
 822                 return 0;
 823
 824         selr = readl(priv->base + pll[pll_id].rckxselr);
 825         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 826         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 827         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 828
 829         debug("PLL%d : selr=%x cfgr1=%x cfgr2=%x fracr=%x\n",
 830               pll_id, selr, cfgr1, cfgr2, fracr);
 831
 832         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 833         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 834         divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
 835
 836         debug("        DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
 837
 838         src = selr & RCC_SELR_SRC_MASK;
 839         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 840
 841         debug("        refclk = %d kHz\n", (u32)(refclk / 1000));
 842
 843         /*
 844          * For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
 845          * So same final result than PLL2 et 4
 846          * with FRACV :
 847          *   Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
 848          *               / (DIVM + 1) * (DIVy + 1)
 849          * without FRACV
 850          *   Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1)
 851          */
 852         if (fracr & RCC_PLLNFRACR_FRACLE) {
 853                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 854                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 855                 dfout = (ulong)lldiv((unsigned long long)refclk *
 856                                      (((divn + 1) << 13) + fracv),
 857                                      ((unsigned long long)(divm + 1) *
 858                                       (divy + 1)) << 13);
 859         } else {
 860                 dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1));
 861         }
 862         debug("        => dfout = %d kHz\n", (u32)(dfout / 1000));
 863
 864         return dfout;
 865 }
 866
 867 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 868 {
 869         u32 reg;
 870         ulong clock = 0;
 871
 872         switch (p) {
 873         case _CK_MPU:
 874         /* MPU sub system */
 875                 reg = readl(priv->base + RCC_MPCKSELR);
 876                 switch (reg & RCC_SELR_SRC_MASK) {
 877                 case RCC_MPCKSELR_HSI:
 878                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 879                         break;
 880                 case RCC_MPCKSELR_HSE:
 881                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 882                         break;
 883                 case RCC_MPCKSELR_PLL:
 884                 case RCC_MPCKSELR_PLL_MPUDIV:
 885                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 886                         if (p == RCC_MPCKSELR_PLL_MPUDIV) {
 887                                 reg = readl(priv->base + RCC_MPCKDIVR);
 888                                 clock /= stm32mp1_mpu_div[reg &
 889                                                           RCC_MPUDIV_MASK];
 890                         }
 891                         break;
 892                 }
 893                 break;
 894         /* AXI sub system */
 895         case _ACLK:
 896         case _HCLK2:
 897         case _HCLK6:
 898         case _PCLK4:
 899         case _PCLK5:
 900                 reg = readl(priv->base + RCC_ASSCKSELR);
 901                 switch (reg & RCC_SELR_SRC_MASK) {
 902                 case RCC_ASSCKSELR_HSI:
 903                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 904                         break;
 905                 case RCC_ASSCKSELR_HSE:
 906                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 907                         break;
 908                 case RCC_ASSCKSELR_PLL:
 909                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
 910                         break;
 911                 }
 912
 913                 /* System clock divider */
 914                 reg = readl(priv->base + RCC_AXIDIVR);
 915                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
 916
 917                 switch (p) {
 918                 case _PCLK4:
 919                         reg = readl(priv->base + RCC_APB4DIVR);
 920                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 921                         break;
 922                 case _PCLK5:
 923                         reg = readl(priv->base + RCC_APB5DIVR);
 924                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 925                         break;
 926                 default:
 927                         break;
 928                 }
 929                 break;
 930         /* MCU sub system */
 931         case _CK_MCU:
 932         case _PCLK1:
 933         case _PCLK2:
 934         case _PCLK3:
 935                 reg = readl(priv->base + RCC_MSSCKSELR);
 936                 switch (reg & RCC_SELR_SRC_MASK) {
 937                 case RCC_MSSCKSELR_HSI:
 938                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 939                         break;
 940                 case RCC_MSSCKSELR_HSE:
 941                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 942                         break;
 943                 case RCC_MSSCKSELR_CSI:
 944                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
 945                         break;
 946                 case RCC_MSSCKSELR_PLL:
 947                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
 948                         break;
 949                 }
 950
 951                 /* MCU clock divider */
 952                 reg = readl(priv->base + RCC_MCUDIVR);
 953                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
 954
 955                 switch (p) {
 956                 case _PCLK1:
 957                         reg = readl(priv->base + RCC_APB1DIVR);
 958                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 959                         break;
 960                 case _PCLK2:
 961                         reg = readl(priv->base + RCC_APB2DIVR);
 962                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 963                         break;
 964                 case _PCLK3:
 965                         reg = readl(priv->base + RCC_APB3DIVR);
 966                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 967                         break;
 968                 case _CK_MCU:
 969                 default:
 970                         break;
 971                 }
 972                 break;
 973         case _CK_PER:
 974                 reg = readl(priv->base + RCC_CPERCKSELR);
 975                 switch (reg & RCC_SELR_SRC_MASK) {
 976                 case RCC_CPERCKSELR_HSI:
 977                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 978                         break;
 979                 case RCC_CPERCKSELR_HSE:
 980                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 981                         break;
 982                 case RCC_CPERCKSELR_CSI:
 983                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
 984                         break;
 985                 }
 986                 break;
 987         case _HSI:
 988         case _HSI_KER:
 989                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
 990                 break;
 991         case _CSI:
 992         case _CSI_KER:
 993                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
 994                 break;
 995         case _HSE:
 996         case _HSE_KER:
 997         case _HSE_KER_DIV2:
 998                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
 999                 if (p == _HSE_KER_DIV2)
1000                         clock >>= 1;
1001                 break;
1002         case _LSI:
1003                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1004                 break;
1005         case _LSE:
1006                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1007                 break;
1008         /* PLL */
1009         case _PLL1_P:
1010         case _PLL1_Q:
1011         case _PLL1_R:
1012                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1013                 break;
1014         case _PLL2_P:
1015         case _PLL2_Q:
1016         case _PLL2_R:
1017                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1018                 break;
1019         case _PLL3_P:
1020         case _PLL3_Q:
1021         case _PLL3_R:
1022                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1023                 break;
1024         case _PLL4_P:
1025         case _PLL4_Q:
1026         case _PLL4_R:
1027                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1028                 break;
1029         /* other */
1030         case _USB_PHY_48:
1031                 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
1032                 break;
1033
1034         default:
1035                 break;
1036         }
1037
1038         debug("%s(%d) clock = %lx : %ld kHz\n",
1039               __func__, p, clock, clock / 1000);
1040
1041         return clock;
1042 }
1043
1044 static int stm32mp1_clk_enable(struct clk *clk)
1045 {
1046         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1047         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1048         int i = stm32mp1_clk_get_id(priv, clk->id);
1049
1050         if (i < 0)
1051                 return i;
1052
1053         if (gate[i].set_clr)
1054                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1055         else
1056                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1057
1058         debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1059
1060         return 0;
1061 }
1062
1063 static int stm32mp1_clk_disable(struct clk *clk)
1064 {
1065         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1066         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1067         int i = stm32mp1_clk_get_id(priv, clk->id);
1068
1069         if (i < 0)
1070                 return i;
1071
1072         if (gate[i].set_clr)
1073                 writel(BIT(gate[i].bit),
1074                        priv->base + gate[i].offset
1075                        + RCC_MP_ENCLRR_OFFSET);
1076         else
1077                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1078
1079         debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1080
1081         return 0;
1082 }
1083
1084 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1085 {
1086         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1087         int p = stm32mp1_clk_get_parent(priv, clk->id);
1088         ulong rate;
1089
1090         if (p < 0)
1091                 return 0;
1092
1093         rate = stm32mp1_clk_get(priv, p);
1094
1095 #ifdef DEBUG
1096         debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1097               __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1098 #endif
1099         return rate;
1100 }
1101
1102 #ifdef STM32MP1_CLOCK_TREE_INIT
1103 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1104                                 u32 mask_on)
1105 {
1106         u32 address = rcc + offset;
1107
1108         if (enable)
1109                 setbits_le32(address, mask_on);
1110         else
1111                 clrbits_le32(address, mask_on);
1112 }
1113
1114 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1115 {
1116         if (enable)
1117                 setbits_le32(rcc + RCC_OCENSETR, mask_on);
1118         else
1119                 setbits_le32(rcc + RCC_OCENCLRR, mask_on);
1120 }
1121
1122 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1123                              u32 mask_rdy)
1124 {
1125         u32 mask_test = 0;
1126         u32 address = rcc + offset;
1127         u32 val;
1128         int ret;
1129
1130         if (enable)
1131                 mask_test = mask_rdy;
1132
1133         ret = readl_poll_timeout(address, val,
1134                                  (val & mask_rdy) == mask_test,
1135                                  TIMEOUT_1S);
1136
1137         if (ret)
1138                 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1139                        mask_rdy, address, enable, readl(address));
1140
1141         return ret;
1142 }
1143
1144 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
1145 {
1146         u32 value;
1147
1148         if (bypass)
1149                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1150
1151         /*
1152          * warning: not recommended to switch directly from "high drive"
1153          * to "medium low drive", and vice-versa.
1154          */
1155         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1156                 >> RCC_BDCR_LSEDRV_SHIFT;
1157
1158         while (value != lsedrv) {
1159                 if (value > lsedrv)
1160                         value--;
1161                 else
1162                         value++;
1163
1164                 clrsetbits_le32(rcc + RCC_BDCR,
1165                                 RCC_BDCR_LSEDRV_MASK,
1166                                 value << RCC_BDCR_LSEDRV_SHIFT);
1167         }
1168
1169         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1170 }
1171
1172 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1173 {
1174         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1175 }
1176
1177 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1178 {
1179         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1180         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1181 }
1182
1183 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
1184 {
1185         if (bypass)
1186                 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1187
1188         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1189         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1190
1191         if (css)
1192                 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
1193 }
1194
1195 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1196 {
1197         stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
1198         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1199 }
1200
1201 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1202 {
1203         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1204         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1205 }
1206
1207 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1208 {
1209         u32 address = rcc + RCC_OCRDYR;
1210         u32 val;
1211         int ret;
1212
1213         clrsetbits_le32(rcc + RCC_HSICFGR,
1214                         RCC_HSICFGR_HSIDIV_MASK,
1215                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1216
1217         ret = readl_poll_timeout(address, val,
1218                                  val & RCC_OCRDYR_HSIDIVRDY,
1219                                  TIMEOUT_200MS);
1220         if (ret)
1221                 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1222                        address, readl(address));
1223
1224         return ret;
1225 }
1226
1227 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1228 {
1229         u8 hsidiv;
1230         u32 hsidivfreq = MAX_HSI_HZ;
1231
1232         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1233              hsidivfreq = hsidivfreq / 2)
1234                 if (hsidivfreq == hsifreq)
1235                         break;
1236
1237         if (hsidiv == 4) {
1238                 pr_err("clk-hsi frequency invalid");
1239                 return -1;
1240         }
1241
1242         if (hsidiv > 0)
1243                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1244
1245         return 0;
1246 }
1247
1248 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1249 {
1250         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1251
1252         writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
1253 }
1254
1255 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1256 {
1257         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1258         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1259         u32 val;
1260         int ret;
1261
1262         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1263                                  TIMEOUT_200MS);
1264
1265         if (ret) {
1266                 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1267                        pll_id, pllxcr, readl(pllxcr));
1268                 return ret;
1269         }
1270
1271         /* start the requested output */
1272         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1273
1274         return 0;
1275 }
1276
1277 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1278 {
1279         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1280         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1281         u32 val;
1282
1283         /* stop all output */
1284         clrbits_le32(pllxcr,
1285                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1286
1287         /* stop PLL */
1288         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1289
1290         /* wait PLL stopped */
1291         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1292                                   TIMEOUT_200MS);
1293 }
1294
1295 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1296                               int pll_id, u32 *pllcfg)
1297 {
1298         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1299         fdt_addr_t rcc = priv->base;
1300         u32 value;
1301
1302         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1303                 & RCC_PLLNCFGR2_DIVP_MASK;
1304         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1305                  & RCC_PLLNCFGR2_DIVQ_MASK;
1306         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1307                  & RCC_PLLNCFGR2_DIVR_MASK;
1308         writel(value, rcc + pll[pll_id].pllxcfgr2);
1309 }
1310
1311 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1312                       u32 *pllcfg, u32 fracv)
1313 {
1314         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1315         fdt_addr_t rcc = priv->base;
1316         enum stm32mp1_plltype type = pll[pll_id].plltype;
1317         int src;
1318         ulong refclk;
1319         u8 ifrge = 0;
1320         u32 value;
1321
1322         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1323
1324         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1325                  (pllcfg[PLLCFG_M] + 1);
1326
1327         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1328             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1329                 debug("invalid refclk = %x\n", (u32)refclk);
1330                 return -EINVAL;
1331         }
1332         if (type == PLL_800 && refclk >= 8000000)
1333                 ifrge = 1;
1334
1335         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1336                  & RCC_PLLNCFGR1_DIVN_MASK;
1337         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1338                  & RCC_PLLNCFGR1_DIVM_MASK;
1339         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1340                  & RCC_PLLNCFGR1_IFRGE_MASK;
1341         writel(value, rcc + pll[pll_id].pllxcfgr1);
1342
1343         /* fractional configuration: load sigma-delta modulator (SDM) */
1344
1345         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1346         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1347                rcc + pll[pll_id].pllxfracr);
1348
1349         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1350         setbits_le32(rcc + pll[pll_id].pllxfracr,
1351                      RCC_PLLNFRACR_FRACLE);
1352
1353         pll_config_output(priv, pll_id, pllcfg);
1354
1355         return 0;
1356 }
1357
1358 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1359 {
1360         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1361         u32 pllxcsg;
1362
1363         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1364                     RCC_PLLNCSGR_MOD_PER_MASK) |
1365                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1366                     RCC_PLLNCSGR_INC_STEP_MASK) |
1367                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1368                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1369
1370         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1371 }
1372
1373 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1374 {
1375         u32 address = priv->base + (clksrc >> 4);
1376         u32 val;
1377         int ret;
1378
1379         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1380         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1381                                  TIMEOUT_200MS);
1382         if (ret)
1383                 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1384                        clksrc, address, readl(address));
1385
1386         return ret;
1387 }
1388
1389 static void stgen_config(struct stm32mp1_clk_priv *priv)
1390 {
1391         int p;
1392         u32 stgenc, cntfid0;
1393         ulong rate;
1394
1395         stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
1396
1397         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1398         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1399         rate = stm32mp1_clk_get(priv, p);
1400
1401         if (cntfid0 != rate) {
1402                 pr_debug("System Generic Counter (STGEN) update\n");
1403                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1404                 writel(0x0, stgenc + STGENC_CNTCVL);
1405                 writel(0x0, stgenc + STGENC_CNTCVU);
1406                 writel(rate, stgenc + STGENC_CNTFID0);
1407                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1408
1409                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1410
1411                 /* need to update gd->arch.timer_rate_hz with new frequency */
1412                 timer_init();
1413                 pr_debug("gd->arch.timer_rate_hz = %x\n",
1414                          (u32)gd->arch.timer_rate_hz);
1415                 pr_debug("Tick = %x\n", (u32)(get_ticks()));
1416         }
1417 }
1418
1419 static int set_clkdiv(unsigned int clkdiv, u32 address)
1420 {
1421         u32 val;
1422         int ret;
1423
1424         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1425         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1426                                  TIMEOUT_200MS);
1427         if (ret)
1428                 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1429                        clkdiv, address, readl(address));
1430
1431         return ret;
1432 }
1433
1434 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1435                              u32 clksrc, u32 clkdiv)
1436 {
1437         u32 address = priv->base + (clksrc >> 4);
1438
1439         /*
1440          * binding clksrc : bit15-4 offset
1441          *                  bit3:   disable
1442          *                  bit2-0: MCOSEL[2:0]
1443          */
1444         if (clksrc & 0x8) {
1445                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1446         } else {
1447                 clrsetbits_le32(address,
1448                                 RCC_MCOCFG_MCOSRC_MASK,
1449                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1450                 clrsetbits_le32(address,
1451                                 RCC_MCOCFG_MCODIV_MASK,
1452                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1453                 setbits_le32(address, RCC_MCOCFG_MCOON);
1454         }
1455 }
1456
1457 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1458                        unsigned int clksrc,
1459                        int lse_css)
1460 {
1461         u32 address = priv->base + RCC_BDCR;
1462
1463         if (readl(address) & RCC_BDCR_RTCCKEN)
1464                 goto skip_rtc;
1465
1466         if (clksrc == CLK_RTC_DISABLED)
1467                 goto skip_rtc;
1468
1469         clrsetbits_le32(address,
1470                         RCC_BDCR_RTCSRC_MASK,
1471                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1472
1473         setbits_le32(address, RCC_BDCR_RTCCKEN);
1474
1475 skip_rtc:
1476         if (lse_css)
1477                 setbits_le32(address, RCC_BDCR_LSECSSON);
1478 }
1479
1480 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1481 {
1482         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1483         u32 value = pkcs & 0xF;
1484         u32 mask = 0xF;
1485
1486         if (pkcs & BIT(31)) {
1487                 mask <<= 4;
1488                 value <<= 4;
1489         }
1490         clrsetbits_le32(address, mask, value);
1491 }
1492
1493 static int stm32mp1_clktree(struct udevice *dev)
1494 {
1495         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1496         fdt_addr_t rcc = priv->base;
1497         unsigned int clksrc[CLKSRC_NB];
1498         unsigned int clkdiv[CLKDIV_NB];
1499         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1500         ofnode plloff[_PLL_NB];
1501         int ret;
1502         int i, len;
1503         int lse_css = 0;
1504         const u32 *pkcs_cell;
1505
1506         /* check mandatory field */
1507         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1508         if (ret < 0) {
1509                 debug("field st,clksrc invalid: error %d\n", ret);
1510                 return -FDT_ERR_NOTFOUND;
1511         }
1512
1513         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1514         if (ret < 0) {
1515                 debug("field st,clkdiv invalid: error %d\n", ret);
1516                 return -FDT_ERR_NOTFOUND;
1517         }
1518
1519         /* check mandatory field in each pll */
1520         for (i = 0; i < _PLL_NB; i++) {
1521                 char name[12];
1522
1523                 sprintf(name, "st,pll@%d", i);
1524                 plloff[i] = dev_read_subnode(dev, name);
1525                 if (!ofnode_valid(plloff[i]))
1526                         continue;
1527                 ret = ofnode_read_u32_array(plloff[i], "cfg",
1528                                             pllcfg[i], PLLCFG_NB);
1529                 if (ret < 0) {
1530                         debug("field cfg invalid: error %d\n", ret);
1531                         return -FDT_ERR_NOTFOUND;
1532                 }
1533         }
1534
1535         debug("configuration MCO\n");
1536         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1537         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1538
1539         debug("switch ON osillator\n");
1540         /*
1541          * switch ON oscillator found in device-tree,
1542          * HSI already ON after bootrom
1543          */
1544         if (priv->osc[_LSI])
1545                 stm32mp1_lsi_set(rcc, 1);
1546
1547         if (priv->osc[_LSE]) {
1548                 int bypass;
1549                 int lsedrv;
1550                 struct udevice *dev = priv->osc_dev[_LSE];
1551
1552                 bypass = dev_read_bool(dev, "st,bypass");
1553                 lse_css = dev_read_bool(dev, "st,css");
1554                 lsedrv = dev_read_u32_default(dev, "st,drive",
1555                                               LSEDRV_MEDIUM_HIGH);
1556
1557                 stm32mp1_lse_enable(rcc, bypass, lsedrv);
1558         }
1559
1560         if (priv->osc[_HSE]) {
1561                 int bypass, css;
1562                 struct udevice *dev = priv->osc_dev[_HSE];
1563
1564                 bypass = dev_read_bool(dev, "st,bypass");
1565                 css = dev_read_bool(dev, "st,css");
1566
1567                 stm32mp1_hse_enable(rcc, bypass, css);
1568         }
1569         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1570          * => switch on CSI even if node is not present in device tree
1571          */
1572         stm32mp1_csi_set(rcc, 1);
1573
1574         /* come back to HSI */
1575         debug("come back to HSI\n");
1576         set_clksrc(priv, CLK_MPU_HSI);
1577         set_clksrc(priv, CLK_AXI_HSI);
1578         set_clksrc(priv, CLK_MCU_HSI);
1579
1580         debug("pll stop\n");
1581         for (i = 0; i < _PLL_NB; i++)
1582                 pll_stop(priv, i);
1583
1584         /* configure HSIDIV */
1585         debug("configure HSIDIV\n");
1586         if (priv->osc[_HSI]) {
1587                 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1588                 stgen_config(priv);
1589         }
1590
1591         /* select DIV */
1592         debug("select DIV\n");
1593         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1594         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1595         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1596         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1597         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1598         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1599         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1600         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1601         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1602
1603         /* no ready bit for RTC */
1604         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1605
1606         /* configure PLLs source */
1607         debug("configure PLLs source\n");
1608         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1609         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1610         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1611
1612         /* configure and start PLLs */
1613         debug("configure PLLs\n");
1614         for (i = 0; i < _PLL_NB; i++) {
1615                 u32 fracv;
1616                 u32 csg[PLLCSG_NB];
1617
1618                 debug("configure PLL %d @ %d\n", i,
1619                       ofnode_to_offset(plloff[i]));
1620                 if (!ofnode_valid(plloff[i]))
1621                         continue;
1622
1623                 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1624                 pll_config(priv, i, pllcfg[i], fracv);
1625                 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1626                 if (!ret) {
1627                         pll_csg(priv, i, csg);
1628                 } else if (ret != -FDT_ERR_NOTFOUND) {
1629                         debug("invalid csg node for pll@%d res=%d\n", i, ret);
1630                         return ret;
1631                 }
1632                 pll_start(priv, i);
1633         }
1634
1635         /* wait and start PLLs ouptut when ready */
1636         for (i = 0; i < _PLL_NB; i++) {
1637                 if (!ofnode_valid(plloff[i]))
1638                         continue;
1639                 debug("output PLL %d\n", i);
1640                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1641         }
1642
1643         /* wait LSE ready before to use it */
1644         if (priv->osc[_LSE])
1645                 stm32mp1_lse_wait(rcc);
1646
1647         /* configure with expected clock source */
1648         debug("CLKSRC\n");
1649         set_clksrc(priv, clksrc[CLKSRC_MPU]);
1650         set_clksrc(priv, clksrc[CLKSRC_AXI]);
1651         set_clksrc(priv, clksrc[CLKSRC_MCU]);
1652         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1653
1654         /* configure PKCK */
1655         debug("PKCK\n");
1656         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1657         if (pkcs_cell) {
1658                 bool ckper_disabled = false;
1659
1660                 for (i = 0; i < len / sizeof(u32); i++) {
1661                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1662
1663                         if (pkcs == CLK_CKPER_DISABLED) {
1664                                 ckper_disabled = true;
1665                                 continue;
1666                         }
1667                         pkcs_config(priv, pkcs);
1668                 }
1669                 /* CKPER is source for some peripheral clock
1670                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
1671                  * only if previous clock is still ON
1672                  * => deactivated CKPER only after switching clock
1673                  */
1674                 if (ckper_disabled)
1675                         pkcs_config(priv, CLK_CKPER_DISABLED);
1676         }
1677
1678         /* STGEN clock source can change with CLK_STGEN_XXX */
1679         stgen_config(priv);
1680
1681         debug("oscillator off\n");
1682         /* switch OFF HSI if not found in device-tree */
1683         if (!priv->osc[_HSI])
1684                 stm32mp1_hsi_set(rcc, 0);
1685
1686         /* Software Self-Refresh mode (SSR) during DDR initilialization */
1687         clrsetbits_le32(priv->base + RCC_DDRITFCR,
1688                         RCC_DDRITFCR_DDRCKMOD_MASK,
1689                         RCC_DDRITFCR_DDRCKMOD_SSR <<
1690                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
1691
1692         return 0;
1693 }
1694 #endif /* STM32MP1_CLOCK_TREE_INIT */
1695
1696 static void stm32mp1_osc_clk_init(const char *name,
1697                                   struct stm32mp1_clk_priv *priv,
1698                                   int index)
1699 {
1700         struct clk clk;
1701         struct udevice *dev = NULL;
1702
1703         priv->osc[index] = 0;
1704         clk.id = 0;
1705         if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1706                 if (clk_request(dev, &clk))
1707                         pr_err("%s request", name);
1708                 else
1709                         priv->osc[index] = clk_get_rate(&clk);
1710         }
1711         priv->osc_dev[index] = dev;
1712 }
1713
1714 static void stm32mp1_osc_init(struct udevice *dev)
1715 {
1716         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1717         int i;
1718         const char *name[NB_OSC] = {
1719                 [_LSI] = "clk-lsi",
1720                 [_LSE] = "clk-lse",
1721                 [_HSI] = "clk-hsi",
1722                 [_HSE] = "clk-hse",
1723                 [_CSI] = "clk-csi",
1724                 [_I2S_CKIN] = "i2s_ckin",
1725                 [_USB_PHY_48] = "ck_usbo_48m"};
1726
1727         for (i = 0; i < NB_OSC; i++) {
1728                 stm32mp1_osc_clk_init(name[i], priv, i);
1729                 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1730         }
1731 }
1732
1733 static int stm32mp1_clk_probe(struct udevice *dev)
1734 {
1735         int result = 0;
1736         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1737
1738         priv->base = dev_read_addr(dev->parent);
1739         if (priv->base == FDT_ADDR_T_NONE)
1740                 return -EINVAL;
1741
1742         priv->data = (void *)&stm32mp1_data;
1743
1744         if (!priv->data->gate || !priv->data->sel ||
1745             !priv->data->pll)
1746                 return -EINVAL;
1747
1748         stm32mp1_osc_init(dev);
1749
1750 #ifdef STM32MP1_CLOCK_TREE_INIT
1751         /* clock tree init is done only one time, before relocation */
1752         if (!(gd->flags & GD_FLG_RELOC))
1753                 result = stm32mp1_clktree(dev);
1754 #endif
1755
1756         return result;
1757 }
1758
1759 static const struct clk_ops stm32mp1_clk_ops = {
1760         .enable = stm32mp1_clk_enable,
1761         .disable = stm32mp1_clk_disable,
1762         .get_rate = stm32mp1_clk_get_rate,
1763 };
1764
1765 static const struct udevice_id stm32mp1_clk_ids[] = {
1766         { .compatible = "st,stm32mp1-rcc-clk" },
1767         { }
1768 };
1769
1770 U_BOOT_DRIVER(stm32mp1_clock) = {
1771         .name = "stm32mp1_clk",
1772         .id = UCLASS_CLK,
1773         .of_match = stm32mp1_clk_ids,
1774         .ops = &stm32mp1_clk_ops,
1775         .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
1776         .probe = stm32mp1_clk_probe,
1777 };