git.sur5r.net Git - u-boot/blob - drivers/clk/rockchip/clk_rk3188.c

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0
   6  */
   7
   8 #include <common.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <errno.h>
  13 #include <mapmem.h>
  14 #include <syscon.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/cru_rk3188.h>
  18 #include <asm/arch/grf_rk3188.h>
  19 #include <asm/arch/hardware.h>
  20 #include <dt-bindings/clock/rk3188-cru.h>
  21 #include <dm/device-internal.h>
  22 #include <dm/lists.h>
  23 #include <dm/uclass-internal.h>
  24 #include <linux/log2.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 enum rk3188_clk_type {
  29         RK3188_CRU,
  30         RK3188A_CRU,
  31 };
  32
  33 struct rk3188_clk_plat {
  34 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  35         struct dtd_rockchip_rk3188_cru dtd;
  36 #endif
  37 };
  38
  39 struct pll_div {
  40         u32 nr;
  41         u32 nf;
  42         u32 no;
  43 };
  44
  45 enum {
  46         VCO_MAX_HZ      = 2200U * 1000000,
  47         VCO_MIN_HZ      = 440 * 1000000,
  48         OUTPUT_MAX_HZ   = 2200U * 1000000,
  49         OUTPUT_MIN_HZ   = 30 * 1000000,
  50         FREF_MAX_HZ     = 2200U * 1000000,
  51         FREF_MIN_HZ     = 30 * 1000,
  52 };
  53
  54 enum {
  55         /* PLL CON0 */
  56         PLL_OD_MASK             = 0x0f,
  57
  58         /* PLL CON1 */
  59         PLL_NF_MASK             = 0x1fff,
  60
  61         /* PLL CON2 */
  62         PLL_BWADJ_MASK          = 0x0fff,
  63
  64         /* PLL CON3 */
  65         PLL_RESET_SHIFT         = 5,
  66
  67         /* GRF_SOC_STATUS0 */
  68         SOCSTS_DPLL_LOCK        = 1 << 5,
  69         SOCSTS_APLL_LOCK        = 1 << 6,
  70         SOCSTS_CPLL_LOCK        = 1 << 7,
  71         SOCSTS_GPLL_LOCK        = 1 << 8,
  72 };
  73
  74 #define RATE_TO_DIV(input_rate, output_rate) \
  75         ((input_rate) / (output_rate) - 1);
  76
  77 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
  78
  79 #define PLL_DIVISORS(hz, _nr, _no) {\
  80         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
  81         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
  82                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
  83                        "divisors on line " __stringify(__LINE__));
  84
  85 /* Keep divisors as low as possible to reduce jitter and power usage */
  86 #ifdef CONFIG_SPL_BUILD
  87 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
  88 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
  89 #endif
  90
  91 static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id,
  92                          const struct pll_div *div, bool has_bwadj)
  93 {
  94         int pll_id = rk_pll_id(clk_id);
  95         struct rk3188_pll *pll = &cru->pll[pll_id];
  96         /* All PLLs have same VCO and output frequency range restrictions. */
  97         uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
  98         uint output_hz = vco_hz / div->no;
  99
 100         debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
 101               (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
 102         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
 103                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
 104                (div->no == 1 || !(div->no % 2)));
 105
 106         /* enter reset */
 107         rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 108
 109         rk_clrsetreg(&pll->con0,
 110                      CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
 111                      ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
 112         rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
 113
 114         if (has_bwadj)
 115                 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
 116
 117         udelay(10);
 118
 119         /* return from reset */
 120         rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 121
 122         return 0;
 123 }
 124
 125 static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf,
 126                                unsigned int hz, bool has_bwadj)
 127 {
 128         static const struct pll_div dpll_cfg[] = {
 129                 {.nf = 25, .nr = 2, .no = 1},
 130                 {.nf = 400, .nr = 9, .no = 2},
 131                 {.nf = 500, .nr = 9, .no = 2},
 132                 {.nf = 100, .nr = 3, .no = 1},
 133         };
 134         int cfg;
 135
 136         switch (hz) {
 137         case 300000000:
 138                 cfg = 0;
 139                 break;
 140         case 533000000: /* actually 533.3P MHz */
 141                 cfg = 1;
 142                 break;
 143         case 666000000: /* actually 666.6P MHz */
 144                 cfg = 2;
 145                 break;
 146         case 800000000:
 147                 cfg = 3;
 148                 break;
 149         default:
 150                 debug("Unsupported SDRAM frequency");
 151                 return -EINVAL;
 152         }
 153
 154         /* pll enter slow-mode */
 155         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 156                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 157
 158         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj);
 159
 160         /* wait for pll lock */
 161         while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK))
 162                 udelay(1);
 163
 164         /* PLL enter normal-mode */
 165         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 166                      DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 167
 168         return 0;
 169 }
 170
 171 static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf,
 172                               unsigned int hz, bool has_bwadj)
 173 {
 174         static const struct pll_div apll_cfg[] = {
 175                 {.nf = 50, .nr = 1, .no = 2},
 176                 {.nf = 67, .nr = 1, .no = 1},
 177         };
 178         int div_core_peri, div_aclk_core, cfg;
 179
 180         /*
 181          * We support two possible frequencies, the safe 600MHz
 182          * which will work with default pmic settings and will
 183          * be set in SPL to get away from the 24MHz default and
 184          * the maximum of 1.6Ghz, which boards can set if they
 185          * were able to get pmic support for it.
 186          */
 187         switch (hz) {
 188         case APLL_SAFE_HZ:
 189                 cfg = 0;
 190                 div_core_peri = 1;
 191                 div_aclk_core = 3;
 192                 break;
 193         case APLL_HZ:
 194                 cfg = 1;
 195                 div_core_peri = 2;
 196                 div_aclk_core = 3;
 197                 break;
 198         default:
 199                 debug("Unsupported ARMCLK frequency");
 200                 return -EINVAL;
 201         }
 202
 203         /* pll enter slow-mode */
 204         rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
 205                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
 206
 207         rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj);
 208
 209         /* waiting for pll lock */
 210         while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
 211                 udelay(1);
 212
 213         /* Set divider for peripherals attached to the cpu core. */
 214         rk_clrsetreg(&cru->cru_clksel_con[0],
 215                 CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
 216                 div_core_peri << CORE_PERI_DIV_SHIFT);
 217
 218         /* set up dependent divisor for aclk_core */
 219         rk_clrsetreg(&cru->cru_clksel_con[1],
 220                 CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT,
 221                 div_aclk_core << CORE_ACLK_DIV_SHIFT);
 222
 223         /* PLL enter normal-mode */
 224         rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
 225                      APLL_MODE_NORMAL << APLL_MODE_SHIFT);
 226
 227         return hz;
 228 }
 229
 230 /* Get pll rate by id */
 231 static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru,
 232                                    enum rk_clk_id clk_id)
 233 {
 234         uint32_t nr, no, nf;
 235         uint32_t con;
 236         int pll_id = rk_pll_id(clk_id);
 237         struct rk3188_pll *pll = &cru->pll[pll_id];
 238         static u8 clk_shift[CLK_COUNT] = {
 239                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 240                 GPLL_MODE_SHIFT
 241         };
 242         uint shift;
 243
 244         con = readl(&cru->cru_mode_con);
 245         shift = clk_shift[clk_id];
 246         switch ((con >> shift) & APLL_MODE_MASK) {
 247         case APLL_MODE_SLOW:
 248                 return OSC_HZ;
 249         case APLL_MODE_NORMAL:
 250                 /* normal mode */
 251                 con = readl(&pll->con0);
 252                 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
 253                 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
 254                 con = readl(&pll->con1);
 255                 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
 256
 257                 return (24 * nf / (nr * no)) * 1000000;
 258         case APLL_MODE_DEEP:
 259         default:
 260                 return 32768;
 261         }
 262 }
 263
 264 static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
 265                                   int periph)
 266 {
 267         uint div;
 268         u32 con;
 269
 270         switch (periph) {
 271         case HCLK_EMMC:
 272         case SCLK_EMMC:
 273                 con = readl(&cru->cru_clksel_con[12]);
 274                 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
 275                 break;
 276         case HCLK_SDMMC:
 277         case SCLK_SDMMC:
 278                 con = readl(&cru->cru_clksel_con[11]);
 279                 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
 280                 break;
 281         case HCLK_SDIO:
 282         case SCLK_SDIO:
 283                 con = readl(&cru->cru_clksel_con[12]);
 284                 div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
 285                 break;
 286         default:
 287                 return -EINVAL;
 288         }
 289
 290         return DIV_TO_RATE(gclk_rate, div) / 2;
 291 }
 292
 293 static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
 294                                   int  periph, uint freq)
 295 {
 296         int src_clk_div;
 297
 298         debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
 299         /* mmc clock defaulg div 2 internal, need provide double in cru */
 300         src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
 301         assert(src_clk_div <= 0x3f);
 302
 303         switch (periph) {
 304         case HCLK_EMMC:
 305         case SCLK_EMMC:
 306                 rk_clrsetreg(&cru->cru_clksel_con[12],
 307                              EMMC_DIV_MASK << EMMC_DIV_SHIFT,
 308                              src_clk_div << EMMC_DIV_SHIFT);
 309                 break;
 310         case HCLK_SDMMC:
 311         case SCLK_SDMMC:
 312                 rk_clrsetreg(&cru->cru_clksel_con[11],
 313                              MMC0_DIV_MASK << MMC0_DIV_SHIFT,
 314                              src_clk_div << MMC0_DIV_SHIFT);
 315                 break;
 316         case HCLK_SDIO:
 317         case SCLK_SDIO:
 318                 rk_clrsetreg(&cru->cru_clksel_con[12],
 319                              SDIO_DIV_MASK << SDIO_DIV_SHIFT,
 320                              src_clk_div << SDIO_DIV_SHIFT);
 321                 break;
 322         default:
 323                 return -EINVAL;
 324         }
 325
 326         return rockchip_mmc_get_clk(cru, gclk_rate, periph);
 327 }
 328
 329 static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
 330                                   int periph)
 331 {
 332         uint div;
 333         u32 con;
 334
 335         switch (periph) {
 336         case SCLK_SPI0:
 337                 con = readl(&cru->cru_clksel_con[25]);
 338                 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
 339                 break;
 340         case SCLK_SPI1:
 341                 con = readl(&cru->cru_clksel_con[25]);
 342                 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
 343                 break;
 344         default:
 345                 return -EINVAL;
 346         }
 347
 348         return DIV_TO_RATE(gclk_rate, div);
 349 }
 350
 351 static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
 352                                   int periph, uint freq)
 353 {
 354         int src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 355
 356         switch (periph) {
 357         case SCLK_SPI0:
 358                 assert(src_clk_div <= SPI0_DIV_MASK);
 359                 rk_clrsetreg(&cru->cru_clksel_con[25],
 360                              SPI0_DIV_MASK << SPI0_DIV_SHIFT,
 361                              src_clk_div << SPI0_DIV_SHIFT);
 362                 break;
 363         case SCLK_SPI1:
 364                 assert(src_clk_div <= SPI1_DIV_MASK);
 365                 rk_clrsetreg(&cru->cru_clksel_con[25],
 366                              SPI1_DIV_MASK << SPI1_DIV_SHIFT,
 367                              src_clk_div << SPI1_DIV_SHIFT);
 368                 break;
 369         default:
 370                 return -EINVAL;
 371         }
 372
 373         return rockchip_spi_get_clk(cru, gclk_rate, periph);
 374 }
 375
 376 #ifdef CONFIG_SPL_BUILD
 377 static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
 378                        bool has_bwadj)
 379 {
 380         u32 aclk_div, hclk_div, pclk_div, h2p_div;
 381
 382         /* pll enter slow-mode */
 383         rk_clrsetreg(&cru->cru_mode_con,
 384                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 385                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 386                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 387                      CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
 388
 389         /* init pll */
 390         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
 391         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);
 392
 393         /* waiting for pll lock */
 394         while ((readl(&grf->soc_status0) &
 395                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
 396                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 397                 udelay(1);
 398
 399         /*
 400          * cpu clock pll source selection and
 401          * reparent aclk_cpu_pre from apll to gpll
 402          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 403          */
 404         aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ);
 405         assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 406
 407         rk_clrsetreg(&cru->cru_clksel_con[0],
 408                      CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |
 409                      A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT,
 410                      CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT |
 411                      aclk_div << A9_CPU_DIV_SHIFT);
 412
 413         hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ);
 414         assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
 415         pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ);
 416         assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
 417         h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ);
 418         assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);
 419
 420         rk_clrsetreg(&cru->cru_clksel_con[1],
 421                      AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT |
 422                      CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT |
 423                      CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
 424                      h2p_div << AHB2APB_DIV_SHIFT |
 425                      pclk_div << CPU_PCLK_DIV_SHIFT |
 426                      hclk_div << CPU_HCLK_DIV_SHIFT);
 427
 428         /*
 429          * peri clock pll source selection and
 430          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 431          */
 432         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 433         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 434
 435         hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 436         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 437                 PERI_ACLK_HZ && (hclk_div < 0x4));
 438
 439         pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 440         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 441                 PERI_ACLK_HZ && (pclk_div < 0x4));
 442
 443         rk_clrsetreg(&cru->cru_clksel_con[10],
 444                      PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
 445                      PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
 446                      PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
 447                      PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
 448                      pclk_div << PERI_PCLK_DIV_SHIFT |
 449                      hclk_div << PERI_HCLK_DIV_SHIFT |
 450                      aclk_div << PERI_ACLK_DIV_SHIFT);
 451
 452         /* PLL enter normal-mode */
 453         rk_clrsetreg(&cru->cru_mode_con,
 454                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 455                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 456                      GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
 457                      CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 458
 459         rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000);
 460 }
 461 #endif
 462
 463 static ulong rk3188_clk_get_rate(struct clk *clk)
 464 {
 465         struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
 466         ulong new_rate, gclk_rate;
 467
 468         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 469         switch (clk->id) {
 470         case 1 ... 4:
 471                 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
 472                 break;
 473         case HCLK_EMMC:
 474         case HCLK_SDMMC:
 475         case HCLK_SDIO:
 476         case SCLK_EMMC:
 477         case SCLK_SDMMC:
 478         case SCLK_SDIO:
 479                 new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
 480                                                 clk->id);
 481                 break;
 482         case SCLK_SPI0:
 483         case SCLK_SPI1:
 484                 new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ,
 485                                                 clk->id);
 486                 break;
 487         case PCLK_I2C0:
 488         case PCLK_I2C1:
 489         case PCLK_I2C2:
 490         case PCLK_I2C3:
 491         case PCLK_I2C4:
 492                 return gclk_rate;
 493         default:
 494                 return -ENOENT;
 495         }
 496
 497         return new_rate;
 498 }
 499
 500 static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
 501 {
 502         struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
 503         struct rk3188_cru *cru = priv->cru;
 504         ulong new_rate;
 505
 506         switch (clk->id) {
 507         case PLL_APLL:
 508                 new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate,
 509                                                priv->has_bwadj);
 510                 break;
 511         case CLK_DDR:
 512                 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate,
 513                                                priv->has_bwadj);
 514                 break;
 515         case HCLK_EMMC:
 516         case HCLK_SDMMC:
 517         case HCLK_SDIO:
 518         case SCLK_EMMC:
 519         case SCLK_SDMMC:
 520         case SCLK_SDIO:
 521                 new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
 522                                                 clk->id, rate);
 523                 break;
 524         case SCLK_SPI0:
 525         case SCLK_SPI1:
 526                 new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ,
 527                                                 clk->id, rate);
 528                 break;
 529         default:
 530                 return -ENOENT;
 531         }
 532
 533         return new_rate;
 534 }
 535
 536 static struct clk_ops rk3188_clk_ops = {
 537         .get_rate       = rk3188_clk_get_rate,
 538         .set_rate       = rk3188_clk_set_rate,
 539 };
 540
 541 static int rk3188_clk_ofdata_to_platdata(struct udevice *dev)
 542 {
 543 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 544         struct rk3188_clk_priv *priv = dev_get_priv(dev);
 545
 546         priv->cru = (struct rk3188_cru *)devfdt_get_addr(dev);
 547 #endif
 548
 549         return 0;
 550 }
 551
 552 static int rk3188_clk_probe(struct udevice *dev)
 553 {
 554         struct rk3188_clk_priv *priv = dev_get_priv(dev);
 555         enum rk3188_clk_type type = dev_get_driver_data(dev);
 556
 557         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 558         if (IS_ERR(priv->grf))
 559                 return PTR_ERR(priv->grf);
 560         priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0;
 561
 562 #ifdef CONFIG_SPL_BUILD
 563 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 564         struct rk3188_clk_plat *plat = dev_get_platdata(dev);
 565
 566         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 567 #endif
 568
 569         rkclk_init(priv->cru, priv->grf, priv->has_bwadj);
 570 #endif
 571
 572         return 0;
 573 }
 574
 575 static int rk3188_clk_bind(struct udevice *dev)
 576 {
 577         int ret;
 578
 579         /* The reset driver does not have a device node, so bind it here */
 580         ret = device_bind_driver(gd->dm_root, "rk3188_sysreset", "reset", &dev);
 581         if (ret)
 582                 debug("Warning: No rk3188 reset driver: ret=%d\n", ret);
 583
 584         return 0;
 585 }
 586
 587 static const struct udevice_id rk3188_clk_ids[] = {
 588         { .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU },
 589         { .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU },
 590         { }
 591 };
 592
 593 U_BOOT_DRIVER(rockchip_rk3188_cru) = {
 594         .name                   = "rockchip_rk3188_cru",
 595         .id                     = UCLASS_CLK,
 596         .of_match               = rk3188_clk_ids,
 597         .priv_auto_alloc_size   = sizeof(struct rk3188_clk_priv),
 598         .platdata_auto_alloc_size = sizeof(struct rk3188_clk_plat),
 599         .ops                    = &rk3188_clk_ops,
 600         .bind                   = rk3188_clk_bind,
 601         .ofdata_to_platdata     = rk3188_clk_ofdata_to_platdata,
 602         .probe                  = rk3188_clk_probe,
 603 };