git.sur5r.net Git - u-boot/blob - drivers/clk/rockchip/clk_rk322x.c

   1 /*
   2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <syscon.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/cru_rk322x.h>
  15 #include <asm/arch/hardware.h>
  16 #include <dm/lists.h>
  17 #include <dt-bindings/clock/rk3228-cru.h>
  18 #include <linux/log2.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 enum {
  23         VCO_MAX_HZ      = 3200U * 1000000,
  24         VCO_MIN_HZ      = 800 * 1000000,
  25         OUTPUT_MAX_HZ   = 3200U * 1000000,
  26         OUTPUT_MIN_HZ   = 24 * 1000000,
  27 };
  28
  29 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
  30
  31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  32         .refdiv = _refdiv,\
  33         .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
  34         .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
  35         _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
  36                          OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
  37                          #hz "Hz cannot be hit with PLL "\
  38                          "divisors on line " __stringify(__LINE__));
  39
  40 /* use integer mode*/
  41 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
  42 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  43
  44 static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
  45                          const struct pll_div *div)
  46 {
  47         int pll_id = rk_pll_id(clk_id);
  48         struct rk322x_pll *pll = &cru->pll[pll_id];
  49
  50         /* All PLLs have same VCO and output frequency range restrictions. */
  51         uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
  52         uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
  53
  54         debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
  55               pll, div->fbdiv, div->refdiv, div->postdiv1,
  56               div->postdiv2, vco_hz, output_hz);
  57         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  58                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
  59
  60         /* use integer mode */
  61         rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
  62         /* Power down */
  63         rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
  64
  65         rk_clrsetreg(&pll->con0,
  66                      PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
  67                      (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
  68         rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
  69                      (div->postdiv2 << PLL_POSTDIV2_SHIFT |
  70                      div->refdiv << PLL_REFDIV_SHIFT));
  71
  72         /* Power Up */
  73         rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
  74
  75         /* waiting for pll lock */
  76         while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
  77                 udelay(1);
  78
  79         return 0;
  80 }
  81
  82 static void rkclk_init(struct rk322x_cru *cru)
  83 {
  84         u32 aclk_div;
  85         u32 hclk_div;
  86         u32 pclk_div;
  87
  88         /* pll enter slow-mode */
  89         rk_clrsetreg(&cru->cru_mode_con,
  90                      GPLL_MODE_MASK | APLL_MODE_MASK,
  91                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
  92                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
  93
  94         /* init pll */
  95         rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
  96         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
  97
  98         /*
  99          * select apll as cpu/core clock pll source and
 100          * set up dependent divisors for PERI and ACLK clocks.
 101          * core hz : apll = 1:1
 102          */
 103         aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
 104         assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
 105
 106         pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
 107         assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
 108
 109         rk_clrsetreg(&cru->cru_clksel_con[0],
 110                      CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
 111                      CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
 112                      0 << CORE_DIV_CON_SHIFT);
 113
 114         rk_clrsetreg(&cru->cru_clksel_con[1],
 115                      CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
 116                      aclk_div << CORE_ACLK_DIV_SHIFT |
 117                      pclk_div << CORE_PERI_DIV_SHIFT);
 118
 119         /*
 120          * select gpll as pd_bus bus clock source and
 121          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 122          */
 123         aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
 124         assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 125
 126         pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
 127         assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
 128
 129         hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
 130         assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
 131
 132         rk_clrsetreg(&cru->cru_clksel_con[0],
 133                      BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
 134                      BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
 135                      aclk_div << BUS_ACLK_DIV_SHIFT);
 136
 137         rk_clrsetreg(&cru->cru_clksel_con[1],
 138                      BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
 139                      pclk_div << BUS_PCLK_DIV_SHIFT |
 140                      hclk_div << BUS_HCLK_DIV_SHIFT);
 141
 142         /*
 143          * select gpll as pd_peri bus clock source and
 144          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 145          */
 146         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 147         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 148
 149         hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 150         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 151                 PERI_ACLK_HZ && (hclk_div < 0x4));
 152
 153         pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 154         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 155                 PERI_ACLK_HZ && pclk_div < 0x8);
 156
 157         rk_clrsetreg(&cru->cru_clksel_con[10],
 158                      PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
 159                      PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
 160                      PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
 161                      pclk_div << PERI_PCLK_DIV_SHIFT |
 162                      hclk_div << PERI_HCLK_DIV_SHIFT |
 163                      aclk_div << PERI_ACLK_DIV_SHIFT);
 164
 165         /* PLL enter normal-mode */
 166         rk_clrsetreg(&cru->cru_mode_con,
 167                      GPLL_MODE_MASK | APLL_MODE_MASK,
 168                      GPLL_MODE_NORM << GPLL_MODE_SHIFT |
 169                      APLL_MODE_NORM << APLL_MODE_SHIFT);
 170 }
 171
 172 /* Get pll rate by id */
 173 static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
 174                                    enum rk_clk_id clk_id)
 175 {
 176         uint32_t refdiv, fbdiv, postdiv1, postdiv2;
 177         uint32_t con;
 178         int pll_id = rk_pll_id(clk_id);
 179         struct rk322x_pll *pll = &cru->pll[pll_id];
 180         static u8 clk_shift[CLK_COUNT] = {
 181                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
 182                 GPLL_MODE_SHIFT, 0xff
 183         };
 184         static u32 clk_mask[CLK_COUNT] = {
 185                 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
 186                 GPLL_MODE_MASK, 0xff
 187         };
 188         uint shift;
 189         uint mask;
 190
 191         con = readl(&cru->cru_mode_con);
 192         shift = clk_shift[clk_id];
 193         mask = clk_mask[clk_id];
 194
 195         switch ((con & mask) >> shift) {
 196         case GPLL_MODE_SLOW:
 197                 return OSC_HZ;
 198         case GPLL_MODE_NORM:
 199
 200                 /* normal mode */
 201                 con = readl(&pll->con0);
 202                 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
 203                 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
 204                 con = readl(&pll->con1);
 205                 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
 206                 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
 207                 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
 208         default:
 209                 return 32768;
 210         }
 211 }
 212
 213 static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
 214                                   int periph)
 215 {
 216         uint src_rate;
 217         uint div, mux;
 218         u32 con;
 219
 220         switch (periph) {
 221         case HCLK_EMMC:
 222         case SCLK_EMMC:
 223                 con = readl(&cru->cru_clksel_con[11]);
 224                 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
 225                 con = readl(&cru->cru_clksel_con[12]);
 226                 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
 227                 break;
 228         case HCLK_SDMMC:
 229         case SCLK_SDMMC:
 230                 con = readl(&cru->cru_clksel_con[11]);
 231                 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
 232                 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
 233                 break;
 234         default:
 235                 return -EINVAL;
 236         }
 237
 238         src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
 239         return DIV_TO_RATE(src_rate, div) / 2;
 240 }
 241
 242 static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
 243 {
 244         ulong ret;
 245
 246         /*
 247          * The gmac clock can be derived either from an external clock
 248          * or can be generated from internally by a divider from SCLK_MAC.
 249          */
 250         if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {
 251                 /* An external clock will always generate the right rate... */
 252                 ret = freq;
 253         } else {
 254                 u32 con = readl(&cru->cru_clksel_con[5]);
 255                 ulong pll_rate;
 256                 u8 div;
 257
 258                 if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
 259                         pll_rate = GPLL_HZ;
 260                 else
 261                         /* CPLL is not set */
 262                         return -EPERM;
 263
 264                 div = DIV_ROUND_UP(pll_rate, freq) - 1;
 265                 if (div <= 0x1f)
 266                         rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,
 267                                      div << CLK_MAC_DIV_SHIFT);
 268                 else
 269                         debug("Unsupported div for gmac:%d\n", div);
 270
 271                 return DIV_TO_RATE(pll_rate, div);
 272         }
 273
 274         return ret;
 275 }
 276
 277 static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
 278                                   int periph, uint freq)
 279 {
 280         int src_clk_div;
 281         int mux;
 282
 283         debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
 284
 285         /* mmc clock defaulg div 2 internal, need provide double in cru */
 286         src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
 287
 288         if (src_clk_div > 128) {
 289                 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
 290                 assert(src_clk_div - 1 < 128);
 291                 mux = EMMC_SEL_24M;
 292         } else {
 293                 mux = EMMC_SEL_GPLL;
 294         }
 295
 296         switch (periph) {
 297         case HCLK_EMMC:
 298         case SCLK_EMMC:
 299                 rk_clrsetreg(&cru->cru_clksel_con[11],
 300                              EMMC_PLL_MASK,
 301                              mux << EMMC_PLL_SHIFT);
 302                 rk_clrsetreg(&cru->cru_clksel_con[12],
 303                              EMMC_DIV_MASK,
 304                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 305                 break;
 306         case HCLK_SDMMC:
 307         case SCLK_SDMMC:
 308                 rk_clrsetreg(&cru->cru_clksel_con[11],
 309                              MMC0_PLL_MASK | MMC0_DIV_MASK,
 310                              mux << MMC0_PLL_SHIFT |
 311                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
 312                 break;
 313         default:
 314                 return -EINVAL;
 315         }
 316
 317         return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
 318 }
 319
 320 static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
 321 {
 322         struct pll_div dpll_cfg;
 323
 324         /*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
 325         switch (set_rate) {
 326         case 400*MHz:
 327                 dpll_cfg = (struct pll_div)
 328                 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
 329                 break;
 330         case 600*MHz:
 331                 dpll_cfg = (struct pll_div)
 332                 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
 333                 break;
 334         case 800*MHz:
 335                 dpll_cfg = (struct pll_div)
 336                 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
 337                 break;
 338         }
 339
 340         /* pll enter slow-mode */
 341         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
 342                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 343         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
 344         /* PLL enter normal-mode */
 345         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
 346                      DPLL_MODE_NORM << DPLL_MODE_SHIFT);
 347
 348         return set_rate;
 349 }
 350 static ulong rk322x_clk_get_rate(struct clk *clk)
 351 {
 352         struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
 353         ulong rate, gclk_rate;
 354
 355         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 356         switch (clk->id) {
 357         case 0 ... 63:
 358                 rate = rkclk_pll_get_rate(priv->cru, clk->id);
 359                 break;
 360         case HCLK_EMMC:
 361         case SCLK_EMMC:
 362         case HCLK_SDMMC:
 363         case SCLK_SDMMC:
 364                 rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
 365                 break;
 366         default:
 367                 return -ENOENT;
 368         }
 369
 370         return rate;
 371 }
 372
 373 static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
 374 {
 375         struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
 376         ulong new_rate, gclk_rate;
 377
 378         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 379         switch (clk->id) {
 380         case HCLK_EMMC:
 381         case SCLK_EMMC:
 382         case HCLK_SDMMC:
 383         case SCLK_SDMMC:
 384                 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
 385                                                 clk->id, rate);
 386                 break;
 387         case CLK_DDR:
 388                 new_rate = rk322x_ddr_set_clk(priv->cru, rate);
 389                 break;
 390         case SCLK_MAC:
 391                 new_rate = rk322x_mac_set_clk(priv->cru, rate);
 392                 break;
 393         case PLL_GPLL:
 394                 return 0;
 395         default:
 396                 return -ENOENT;
 397         }
 398
 399         return new_rate;
 400 }
 401
 402 static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent)
 403 {
 404         struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
 405         struct rk322x_cru *cru = priv->cru;
 406
 407         /*
 408          * If the requested parent is in the same clock-controller and the id
 409          * is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
 410          */
 411         if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
 412                 debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
 413                 rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);
 414                 return 0;
 415         }
 416
 417         /*
 418          * If the requested parent is in the same clock-controller and the id
 419          * is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
 420          */
 421         if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
 422                 debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
 423                 rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));
 424                 return 0;
 425         }
 426
 427         return -EINVAL;
 428 }
 429
 430 static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent)
 431 {
 432         struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
 433         const char *clock_output_name;
 434         struct rk322x_cru *cru = priv->cru;
 435         int ret;
 436
 437         ret = dev_read_string_index(parent->dev, "clock-output-names",
 438                                     parent->id, &clock_output_name);
 439         if (ret < 0)
 440                 return -ENODATA;
 441
 442         if (!strcmp(clock_output_name, "ext_gmac")) {
 443                 debug("%s: switching gmac extclk to ext_gmac\n", __func__);
 444                 rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);
 445                 return 0;
 446         } else if (!strcmp(clock_output_name, "phy_50m_out")) {
 447                 debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
 448                 rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));
 449                 return 0;
 450         }
 451
 452         return -EINVAL;
 453 }
 454
 455 static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
 456 {
 457         switch (clk->id) {
 458         case SCLK_MAC:
 459                 return rk322x_gmac_set_parent(clk, parent);
 460         case SCLK_MAC_EXTCLK:
 461                 return rk322x_gmac_extclk_set_parent(clk, parent);
 462         }
 463
 464         debug("%s: unsupported clk %ld\n", __func__, clk->id);
 465         return -ENOENT;
 466 }
 467
 468 static struct clk_ops rk322x_clk_ops = {
 469         .get_rate       = rk322x_clk_get_rate,
 470         .set_rate       = rk322x_clk_set_rate,
 471         .set_parent     = rk322x_clk_set_parent,
 472 };
 473
 474 static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
 475 {
 476         struct rk322x_clk_priv *priv = dev_get_priv(dev);
 477
 478         priv->cru = (struct rk322x_cru *)devfdt_get_addr(dev);
 479
 480         return 0;
 481 }
 482
 483 static int rk322x_clk_probe(struct udevice *dev)
 484 {
 485         struct rk322x_clk_priv *priv = dev_get_priv(dev);
 486
 487         rkclk_init(priv->cru);
 488
 489         return 0;
 490 }
 491
 492 static int rk322x_clk_bind(struct udevice *dev)
 493 {
 494         int ret;
 495         struct udevice *sys_child;
 496         struct sysreset_reg *priv;
 497
 498         /* The reset driver does not have a device node, so bind it here */
 499         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
 500                                  &sys_child);
 501         if (ret) {
 502                 debug("Warning: No sysreset driver: ret=%d\n", ret);
 503         } else {
 504                 priv = malloc(sizeof(struct sysreset_reg));
 505                 priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
 506                                                     cru_glb_srst_fst_value);
 507                 priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
 508                                                     cru_glb_srst_snd_value);
 509                 sys_child->priv = priv;
 510         }
 511
 512 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
 513         ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
 514         ret = rockchip_reset_bind(dev, ret, 9);
 515         if (ret)
 516                 debug("Warning: software reset driver bind faile\n");
 517 #endif
 518
 519         return 0;
 520 }
 521
 522 static const struct udevice_id rk322x_clk_ids[] = {
 523         { .compatible = "rockchip,rk3228-cru" },
 524         { }
 525 };
 526
 527 U_BOOT_DRIVER(rockchip_rk322x_cru) = {
 528         .name           = "clk_rk322x",
 529         .id             = UCLASS_CLK,
 530         .of_match       = rk322x_clk_ids,
 531         .priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
 532         .ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
 533         .ops            = &rk322x_clk_ops,
 534         .bind           = rk322x_clk_bind,
 535         .probe          = rk322x_clk_probe,
 536 };