1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 * Author: Andy Yan <andy.yan@rock-chips.com>
5 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cru_rk3368.h>
18 #include <asm/arch/hardware.h>
21 #include <dt-bindings/clock/rk3368-cru.h>
23 #if CONFIG_IS_ENABLED(OF_PLATDATA)
24 struct rk3368_clk_plat {
25 struct dtd_rockchip_rk3368_cru dtd;
35 #define OSC_HZ (24 * 1000 * 1000)
36 #define APLL_L_HZ (800 * 1000 * 1000)
37 #define APLL_B_HZ (816 * 1000 * 1000)
38 #define GPLL_HZ (576 * 1000 * 1000)
39 #define CPLL_HZ (400 * 1000 * 1000)
41 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
43 #define PLL_DIVISORS(hz, _nr, _no) { \
44 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
45 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
46 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
47 "divisors on line " __stringify(__LINE__));
49 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
50 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
51 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
52 #if !defined(CONFIG_TPL_BUILD)
53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
58 static ulong rk3368_clk_get_rate(struct clk *clk);
60 /* Get pll rate by id */
61 static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
62 enum rk3368_pll_id pll_id)
66 struct rk3368_pll *pll = &cru->pll[pll_id];
68 con = readl(&pll->con3);
70 switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
74 con = readl(&pll->con0);
75 no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
76 nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
77 con = readl(&pll->con1);
78 nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;
80 return (24 * nf / (nr * no)) * 1000000;
81 case PLL_MODE_DEEP_SLOW:
87 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
88 static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
89 const struct pll_div *div)
91 struct rk3368_pll *pll = &cru->pll[pll_id];
92 /* All PLLs have same VCO and output frequency range restrictions*/
93 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
94 uint output_hz = vco_hz / div->no;
96 debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
97 pll, div->nf, div->nr, div->no, vco_hz, output_hz);
99 /* enter slow mode and reset pll */
100 rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK,
101 PLL_RESET << PLL_RESET_SHIFT);
103 rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK,
104 ((div->nr - 1) << PLL_NR_SHIFT) |
105 ((div->no - 1) << PLL_OD_SHIFT));
106 writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
108 * BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
109 * Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
111 clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
115 /* return from reset */
116 rk_clrreg(&pll->con3, PLL_RESET_MASK);
118 /* waiting for pll lock */
119 while (!(readl(&pll->con1) & PLL_LOCK_STA))
122 rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
123 PLL_MODE_NORMAL << PLL_MODE_SHIFT);
129 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
130 static void rkclk_init(struct rk3368_cru *cru)
132 u32 apllb, aplll, dpll, cpll, gpll;
134 rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
135 rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
136 #if !defined(CONFIG_TPL_BUILD)
138 * If we plan to return to the boot ROM, we can't increase the
139 * GPLL rate from the SPL stage.
141 rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
142 rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
145 apllb = rkclk_pll_get_rate(cru, APLLB);
146 aplll = rkclk_pll_get_rate(cru, APLLL);
147 dpll = rkclk_pll_get_rate(cru, DPLL);
148 cpll = rkclk_pll_get_rate(cru, CPLL);
149 gpll = rkclk_pll_get_rate(cru, GPLL);
151 debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
152 __func__, apllb, aplll, dpll, cpll, gpll);
156 #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
157 static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
159 u32 div, con, con_id, rate;
176 con = readl(&cru->clksel_con[con_id]);
177 switch (con & MMC_PLL_SEL_MASK) {
178 case MMC_PLL_SEL_GPLL:
179 pll_rate = rkclk_pll_get_rate(cru, GPLL);
181 case MMC_PLL_SEL_24M:
184 case MMC_PLL_SEL_CPLL:
185 pll_rate = rkclk_pll_get_rate(cru, CPLL);
187 case MMC_PLL_SEL_USBPHY_480M:
191 div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
192 rate = DIV_TO_RATE(pll_rate, div);
194 debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate);
198 static ulong rk3368_mmc_find_best_rate_and_parent(struct clk *clk,
205 const ulong MHz = 1000000;
210 { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ },
211 { .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ },
212 { .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz }
215 debug("%s: target rate %ld\n", __func__, rate);
216 for (i = 0; i < ARRAY_SIZE(parents); ++i) {
218 * Find the largest rate no larger than the target-rate for
219 * the current parent.
221 ulong parent_rate = parents[i].rate;
222 u32 div = DIV_ROUND_UP(parent_rate, rate);
224 ulong new_rate = parent_rate / adj_div;
226 debug("%s: rate %ld, parent-mux %d, parent-rate %ld, div %d\n",
227 __func__, rate, parents[i].mux, parents[i].rate, div);
229 /* Skip, if not representable */
230 if ((div - 1) > MMC_CLK_DIV_MASK)
233 /* Skip, if we already have a better (or equal) solution */
234 if (new_rate <= best_rate)
237 /* This is our new best rate. */
238 best_rate = new_rate;
239 *best_mux = parents[i].mux;
243 debug("%s: best_mux = %x, best_div = %d, best_rate = %ld\n",
244 __func__, *best_mux, *best_div, best_rate);
249 static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate)
251 struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
252 struct rk3368_cru *cru = priv->cru;
253 ulong clk_id = clk->id;
254 u32 con_id, mux = 0, div = 0;
256 /* Find the best parent and rate */
257 rk3368_mmc_find_best_rate_and_parent(clk, rate << 1, &mux, &div);
273 rk_clrsetreg(&cru->clksel_con[con_id],
274 MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
277 return rk3368_mmc_get_clk(cru, clk_id);
281 #if IS_ENABLED(CONFIG_TPL_BUILD)
282 static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
284 const struct pll_div *dpll_cfg = NULL;
285 const ulong MHz = 1000000;
287 /* Fout = ((Fin /NR) * NF )/ NO */
288 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1);
289 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1);
290 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2);
294 dpll_cfg = &dpll_1200;
297 dpll_cfg = &dpll_1332;
300 dpll_cfg = &dpll_1600;
303 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
305 rkclk_set_pll(cru, DPLL, dpll_cfg);
311 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
312 static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate)
317 * The gmac clock can be derived either from an external clock
318 * or can be generated from internally by a divider from SCLK_MAC.
320 if (readl(&cru->clksel_con[43]) & GMAC_MUX_SEL_EXTCLK) {
321 /* An external clock will always generate the right rate... */
324 u32 con = readl(&cru->clksel_con[43]);
328 if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
329 GMAC_PLL_SELECT_GENERAL)
331 else if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
332 GMAC_PLL_SELECT_CODEC)
335 /* CPLL is not set */
338 div = DIV_ROUND_UP(pll_rate, set_rate) - 1;
340 rk_clrsetreg(&cru->clksel_con[43], GMAC_DIV_CON_MASK,
341 div << GMAC_DIV_CON_SHIFT);
343 debug("Unsupported div for gmac:%d\n", div);
345 return DIV_TO_RATE(pll_rate, div);
353 * RK3368 SPI clocks have a common divider-width (7 bits) and a single bit
354 * to select either CPLL or GPLL as the clock-parent. The location within
355 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
359 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
365 * The entries are numbered relative to their offset from SCLK_SPI0.
367 static const struct spi_clkreg spi_clkregs[] = {
368 [0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
369 [1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
370 [2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
373 static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
375 return (val >> shift) & ((1 << width) - 1);
378 static ulong rk3368_spi_get_clk(struct rk3368_cru *cru, ulong clk_id)
380 const struct spi_clkreg *spiclk = NULL;
384 case SCLK_SPI0 ... SCLK_SPI2:
385 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
389 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
393 val = readl(&cru->clksel_con[spiclk->reg]);
394 div = extract_bits(val, 7, spiclk->div_shift);
396 debug("%s: div 0x%x\n", __func__, div);
397 return DIV_TO_RATE(GPLL_HZ, div);
400 static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz)
402 const struct spi_clkreg *spiclk = NULL;
405 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);
406 assert(src_clk_div < 127);
409 case SCLK_SPI0 ... SCLK_SPI2:
410 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
414 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
418 rk_clrsetreg(&cru->clksel_con[spiclk->reg],
419 ((0x7f << spiclk->div_shift) |
420 (0x1 << spiclk->sel_shift)),
421 ((src_clk_div << spiclk->div_shift) |
422 (1 << spiclk->sel_shift)));
424 return rk3368_spi_get_clk(cru, clk_id);
427 static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru)
431 val = readl(&cru->clksel_con[25]);
432 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
433 CLK_SARADC_DIV_CON_WIDTH);
435 return DIV_TO_RATE(OSC_HZ, div);
438 static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz)
442 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
443 assert(src_clk_div < 128);
445 rk_clrsetreg(&cru->clksel_con[25],
446 CLK_SARADC_DIV_CON_MASK,
447 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
449 return rk3368_saradc_get_clk(cru);
452 static ulong rk3368_clk_get_rate(struct clk *clk)
454 struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
457 debug("%s: id %ld\n", __func__, clk->id);
460 rate = rkclk_pll_get_rate(priv->cru, CPLL);
463 rate = rkclk_pll_get_rate(priv->cru, GPLL);
465 case SCLK_SPI0 ... SCLK_SPI2:
466 rate = rk3368_spi_get_clk(priv->cru, clk->id);
468 #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
471 rate = rk3368_mmc_get_clk(priv->cru, clk->id);
475 rate = rk3368_saradc_get_clk(priv->cru);
484 static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
486 __maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
489 debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
491 case SCLK_SPI0 ... SCLK_SPI2:
492 ret = rk3368_spi_set_clk(priv->cru, clk->id, rate);
494 #if IS_ENABLED(CONFIG_TPL_BUILD)
496 ret = rk3368_ddr_set_clk(priv->cru, rate);
499 #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
502 ret = rk3368_mmc_set_clk(clk, rate);
505 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
507 /* select the external clock */
508 ret = rk3368_gmac_set_clk(priv->cru, rate);
512 ret = rk3368_saradc_set_clk(priv->cru, rate);
521 static int __maybe_unused rk3368_gmac_set_parent(struct clk *clk, struct clk *parent)
523 struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
524 struct rk3368_cru *cru = priv->cru;
525 const char *clock_output_name;
529 * If the requested parent is in the same clock-controller and
530 * the id is SCLK_MAC ("sclk_mac"), switch to the internal
533 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
534 debug("%s: switching GAMC to SCLK_MAC\n", __func__);
535 rk_clrreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
540 * Otherwise, we need to check the clock-output-names of the
541 * requested parent to see if the requested id is "ext_gmac".
543 ret = dev_read_string_index(parent->dev, "clock-output-names",
544 parent->id, &clock_output_name);
548 /* If this is "ext_gmac", switch to the external clock input */
549 if (!strcmp(clock_output_name, "ext_gmac")) {
550 debug("%s: switching GMAC to external clock\n", __func__);
551 rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
558 static int __maybe_unused rk3368_clk_set_parent(struct clk *clk, struct clk *parent)
562 return rk3368_gmac_set_parent(clk, parent);
565 debug("%s: unsupported clk %ld\n", __func__, clk->id);
569 static int rk3368_clk_enable(struct clk *clk)
576 case SCLK_MACREF_OUT:
579 /* Required to successfully probe the Designware GMAC driver */
583 debug("%s: unsupported clk %ld\n", __func__, clk->id);
587 static struct clk_ops rk3368_clk_ops = {
588 .get_rate = rk3368_clk_get_rate,
589 .set_rate = rk3368_clk_set_rate,
590 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
591 .set_parent = rk3368_clk_set_parent,
593 .enable = rk3368_clk_enable,
596 static int rk3368_clk_probe(struct udevice *dev)
598 struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev);
599 #if CONFIG_IS_ENABLED(OF_PLATDATA)
600 struct rk3368_clk_plat *plat = dev_get_platdata(dev);
602 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
604 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
605 rkclk_init(priv->cru);
611 static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
613 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
614 struct rk3368_clk_priv *priv = dev_get_priv(dev);
616 priv->cru = dev_read_addr_ptr(dev);
622 static int rk3368_clk_bind(struct udevice *dev)
625 struct udevice *sys_child;
626 struct sysreset_reg *priv;
628 /* The reset driver does not have a device node, so bind it here */
629 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
632 debug("Warning: No sysreset driver: ret=%d\n", ret);
634 priv = malloc(sizeof(struct sysreset_reg));
635 priv->glb_srst_fst_value = offsetof(struct rk3368_cru,
637 priv->glb_srst_snd_value = offsetof(struct rk3368_cru,
639 sys_child->priv = priv;
642 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
643 ret = offsetof(struct rk3368_cru, softrst_con[0]);
644 ret = rockchip_reset_bind(dev, ret, 15);
646 debug("Warning: software reset driver bind faile\n");
652 static const struct udevice_id rk3368_clk_ids[] = {
653 { .compatible = "rockchip,rk3368-cru" },
657 U_BOOT_DRIVER(rockchip_rk3368_cru) = {
658 .name = "rockchip_rk3368_cru",
660 .of_match = rk3368_clk_ids,
661 .priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
662 #if CONFIG_IS_ENABLED(OF_PLATDATA)
663 .platdata_auto_alloc_size = sizeof(struct rk3368_clk_plat),
665 .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
666 .ops = &rk3368_clk_ops,
667 .bind = rk3368_clk_bind,
668 .probe = rk3368_clk_probe,