git.sur5r.net Git - u-boot/blob - drivers/clk/rockchip/clk_rk3399.c

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  * (C) 2017 Theobroma Systems Design und Consulting GmbH
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0
   6  */
   7
   8 #include <common.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <errno.h>
  13 #include <mapmem.h>
  14 #include <syscon.h>
  15 #include <bitfield.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/cru_rk3399.h>
  19 #include <asm/arch/hardware.h>
  20 #include <dm/lists.h>
  21 #include <dt-bindings/clock/rk3399-cru.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  26 struct rk3399_clk_plat {
  27         struct dtd_rockchip_rk3399_cru dtd;
  28 };
  29
  30 struct rk3399_pmuclk_plat {
  31         struct dtd_rockchip_rk3399_pmucru dtd;
  32 };
  33 #endif
  34
  35 struct pll_div {
  36         u32 refdiv;
  37         u32 fbdiv;
  38         u32 postdiv1;
  39         u32 postdiv2;
  40         u32 frac;
  41 };
  42
  43 #define RATE_TO_DIV(input_rate, output_rate) \
  44         ((input_rate) / (output_rate) - 1);
  45 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
  46
  47 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  48         .refdiv = _refdiv,\
  49         .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  50         .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  51
  52 #if defined(CONFIG_SPL_BUILD)
  53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
  55 #else
  56 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
  57 #endif
  58
  59 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
  60 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
  61
  62 static const struct pll_div *apll_l_cfgs[] = {
  63         [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
  64         [APLL_L_600_MHZ] = &apll_l_600_cfg,
  65 };
  66
  67 enum {
  68         /* PLL_CON0 */
  69         PLL_FBDIV_MASK                  = 0xfff,
  70         PLL_FBDIV_SHIFT                 = 0,
  71
  72         /* PLL_CON1 */
  73         PLL_POSTDIV2_SHIFT              = 12,
  74         PLL_POSTDIV2_MASK               = 0x7 << PLL_POSTDIV2_SHIFT,
  75         PLL_POSTDIV1_SHIFT              = 8,
  76         PLL_POSTDIV1_MASK               = 0x7 << PLL_POSTDIV1_SHIFT,
  77         PLL_REFDIV_MASK                 = 0x3f,
  78         PLL_REFDIV_SHIFT                = 0,
  79
  80         /* PLL_CON2 */
  81         PLL_LOCK_STATUS_SHIFT           = 31,
  82         PLL_LOCK_STATUS_MASK            = 1 << PLL_LOCK_STATUS_SHIFT,
  83         PLL_FRACDIV_MASK                = 0xffffff,
  84         PLL_FRACDIV_SHIFT               = 0,
  85
  86         /* PLL_CON3 */
  87         PLL_MODE_SHIFT                  = 8,
  88         PLL_MODE_MASK                   = 3 << PLL_MODE_SHIFT,
  89         PLL_MODE_SLOW                   = 0,
  90         PLL_MODE_NORM,
  91         PLL_MODE_DEEP,
  92         PLL_DSMPD_SHIFT                 = 3,
  93         PLL_DSMPD_MASK                  = 1 << PLL_DSMPD_SHIFT,
  94         PLL_INTEGER_MODE                = 1,
  95
  96         /* PMUCRU_CLKSEL_CON0 */
  97         PMU_PCLK_DIV_CON_MASK           = 0x1f,
  98         PMU_PCLK_DIV_CON_SHIFT          = 0,
  99
 100         /* PMUCRU_CLKSEL_CON1 */
 101         SPI3_PLL_SEL_SHIFT              = 7,
 102         SPI3_PLL_SEL_MASK               = 1 << SPI3_PLL_SEL_SHIFT,
 103         SPI3_PLL_SEL_24M                = 0,
 104         SPI3_PLL_SEL_PPLL               = 1,
 105         SPI3_DIV_CON_SHIFT              = 0x0,
 106         SPI3_DIV_CON_MASK               = 0x7f,
 107
 108         /* PMUCRU_CLKSEL_CON2 */
 109         I2C_DIV_CON_MASK                = 0x7f,
 110         CLK_I2C8_DIV_CON_SHIFT          = 8,
 111         CLK_I2C0_DIV_CON_SHIFT          = 0,
 112
 113         /* PMUCRU_CLKSEL_CON3 */
 114         CLK_I2C4_DIV_CON_SHIFT          = 0,
 115
 116         /* CLKSEL_CON0 */
 117         ACLKM_CORE_L_DIV_CON_SHIFT      = 8,
 118         ACLKM_CORE_L_DIV_CON_MASK       = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
 119         CLK_CORE_L_PLL_SEL_SHIFT        = 6,
 120         CLK_CORE_L_PLL_SEL_MASK         = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
 121         CLK_CORE_L_PLL_SEL_ALPLL        = 0x0,
 122         CLK_CORE_L_PLL_SEL_ABPLL        = 0x1,
 123         CLK_CORE_L_PLL_SEL_DPLL         = 0x10,
 124         CLK_CORE_L_PLL_SEL_GPLL         = 0x11,
 125         CLK_CORE_L_DIV_MASK             = 0x1f,
 126         CLK_CORE_L_DIV_SHIFT            = 0,
 127
 128         /* CLKSEL_CON1 */
 129         PCLK_DBG_L_DIV_SHIFT            = 0x8,
 130         PCLK_DBG_L_DIV_MASK             = 0x1f << PCLK_DBG_L_DIV_SHIFT,
 131         ATCLK_CORE_L_DIV_SHIFT          = 0,
 132         ATCLK_CORE_L_DIV_MASK           = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
 133
 134         /* CLKSEL_CON14 */
 135         PCLK_PERIHP_DIV_CON_SHIFT       = 12,
 136         PCLK_PERIHP_DIV_CON_MASK        = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
 137         HCLK_PERIHP_DIV_CON_SHIFT       = 8,
 138         HCLK_PERIHP_DIV_CON_MASK        = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
 139         ACLK_PERIHP_PLL_SEL_SHIFT       = 7,
 140         ACLK_PERIHP_PLL_SEL_MASK        = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
 141         ACLK_PERIHP_PLL_SEL_CPLL        = 0,
 142         ACLK_PERIHP_PLL_SEL_GPLL        = 1,
 143         ACLK_PERIHP_DIV_CON_SHIFT       = 0,
 144         ACLK_PERIHP_DIV_CON_MASK        = 0x1f,
 145
 146         /* CLKSEL_CON21 */
 147         ACLK_EMMC_PLL_SEL_SHIFT         = 7,
 148         ACLK_EMMC_PLL_SEL_MASK          = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
 149         ACLK_EMMC_PLL_SEL_GPLL          = 0x1,
 150         ACLK_EMMC_DIV_CON_SHIFT         = 0,
 151         ACLK_EMMC_DIV_CON_MASK          = 0x1f,
 152
 153         /* CLKSEL_CON22 */
 154         CLK_EMMC_PLL_SHIFT              = 8,
 155         CLK_EMMC_PLL_MASK               = 0x7 << CLK_EMMC_PLL_SHIFT,
 156         CLK_EMMC_PLL_SEL_GPLL           = 0x1,
 157         CLK_EMMC_PLL_SEL_24M            = 0x5,
 158         CLK_EMMC_DIV_CON_SHIFT          = 0,
 159         CLK_EMMC_DIV_CON_MASK           = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
 160
 161         /* CLKSEL_CON23 */
 162         PCLK_PERILP0_DIV_CON_SHIFT      = 12,
 163         PCLK_PERILP0_DIV_CON_MASK       = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
 164         HCLK_PERILP0_DIV_CON_SHIFT      = 8,
 165         HCLK_PERILP0_DIV_CON_MASK       = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
 166         ACLK_PERILP0_PLL_SEL_SHIFT      = 7,
 167         ACLK_PERILP0_PLL_SEL_MASK       = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
 168         ACLK_PERILP0_PLL_SEL_CPLL       = 0,
 169         ACLK_PERILP0_PLL_SEL_GPLL       = 1,
 170         ACLK_PERILP0_DIV_CON_SHIFT      = 0,
 171         ACLK_PERILP0_DIV_CON_MASK       = 0x1f,
 172
 173         /* CLKSEL_CON25 */
 174         PCLK_PERILP1_DIV_CON_SHIFT      = 8,
 175         PCLK_PERILP1_DIV_CON_MASK       = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
 176         HCLK_PERILP1_PLL_SEL_SHIFT      = 7,
 177         HCLK_PERILP1_PLL_SEL_MASK       = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
 178         HCLK_PERILP1_PLL_SEL_CPLL       = 0,
 179         HCLK_PERILP1_PLL_SEL_GPLL       = 1,
 180         HCLK_PERILP1_DIV_CON_SHIFT      = 0,
 181         HCLK_PERILP1_DIV_CON_MASK       = 0x1f,
 182
 183         /* CLKSEL_CON26 */
 184         CLK_SARADC_DIV_CON_SHIFT        = 8,
 185         CLK_SARADC_DIV_CON_MASK         = GENMASK(15, 8),
 186         CLK_SARADC_DIV_CON_WIDTH        = 8,
 187
 188         /* CLKSEL_CON27 */
 189         CLK_TSADC_SEL_X24M              = 0x0,
 190         CLK_TSADC_SEL_SHIFT             = 15,
 191         CLK_TSADC_SEL_MASK              = 1 << CLK_TSADC_SEL_SHIFT,
 192         CLK_TSADC_DIV_CON_SHIFT         = 0,
 193         CLK_TSADC_DIV_CON_MASK          = 0x3ff,
 194
 195         /* CLKSEL_CON47 & CLKSEL_CON48 */
 196         ACLK_VOP_PLL_SEL_SHIFT          = 6,
 197         ACLK_VOP_PLL_SEL_MASK           = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
 198         ACLK_VOP_PLL_SEL_CPLL           = 0x1,
 199         ACLK_VOP_DIV_CON_SHIFT          = 0,
 200         ACLK_VOP_DIV_CON_MASK           = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
 201
 202         /* CLKSEL_CON49 & CLKSEL_CON50 */
 203         DCLK_VOP_DCLK_SEL_SHIFT         = 11,
 204         DCLK_VOP_DCLK_SEL_MASK          = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
 205         DCLK_VOP_DCLK_SEL_DIVOUT        = 0,
 206         DCLK_VOP_PLL_SEL_SHIFT          = 8,
 207         DCLK_VOP_PLL_SEL_MASK           = 3 << DCLK_VOP_PLL_SEL_SHIFT,
 208         DCLK_VOP_PLL_SEL_VPLL           = 0,
 209         DCLK_VOP_DIV_CON_MASK           = 0xff,
 210         DCLK_VOP_DIV_CON_SHIFT          = 0,
 211
 212         /* CLKSEL_CON58 */
 213         CLK_SPI_PLL_SEL_WIDTH = 1,
 214         CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
 215         CLK_SPI_PLL_SEL_CPLL = 0,
 216         CLK_SPI_PLL_SEL_GPLL = 1,
 217         CLK_SPI_PLL_DIV_CON_WIDTH = 7,
 218         CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
 219
 220         CLK_SPI5_PLL_DIV_CON_SHIFT      = 8,
 221         CLK_SPI5_PLL_SEL_SHIFT          = 15,
 222
 223         /* CLKSEL_CON59 */
 224         CLK_SPI1_PLL_SEL_SHIFT          = 15,
 225         CLK_SPI1_PLL_DIV_CON_SHIFT      = 8,
 226         CLK_SPI0_PLL_SEL_SHIFT          = 7,
 227         CLK_SPI0_PLL_DIV_CON_SHIFT      = 0,
 228
 229         /* CLKSEL_CON60 */
 230         CLK_SPI4_PLL_SEL_SHIFT          = 15,
 231         CLK_SPI4_PLL_DIV_CON_SHIFT      = 8,
 232         CLK_SPI2_PLL_SEL_SHIFT          = 7,
 233         CLK_SPI2_PLL_DIV_CON_SHIFT      = 0,
 234
 235         /* CLKSEL_CON61 */
 236         CLK_I2C_PLL_SEL_MASK            = 1,
 237         CLK_I2C_PLL_SEL_CPLL            = 0,
 238         CLK_I2C_PLL_SEL_GPLL            = 1,
 239         CLK_I2C5_PLL_SEL_SHIFT          = 15,
 240         CLK_I2C5_DIV_CON_SHIFT          = 8,
 241         CLK_I2C1_PLL_SEL_SHIFT          = 7,
 242         CLK_I2C1_DIV_CON_SHIFT          = 0,
 243
 244         /* CLKSEL_CON62 */
 245         CLK_I2C6_PLL_SEL_SHIFT          = 15,
 246         CLK_I2C6_DIV_CON_SHIFT          = 8,
 247         CLK_I2C2_PLL_SEL_SHIFT          = 7,
 248         CLK_I2C2_DIV_CON_SHIFT          = 0,
 249
 250         /* CLKSEL_CON63 */
 251         CLK_I2C7_PLL_SEL_SHIFT          = 15,
 252         CLK_I2C7_DIV_CON_SHIFT          = 8,
 253         CLK_I2C3_PLL_SEL_SHIFT          = 7,
 254         CLK_I2C3_DIV_CON_SHIFT          = 0,
 255
 256         /* CRU_SOFTRST_CON4 */
 257         RESETN_DDR0_REQ_SHIFT           = 8,
 258         RESETN_DDR0_REQ_MASK            = 1 << RESETN_DDR0_REQ_SHIFT,
 259         RESETN_DDRPHY0_REQ_SHIFT        = 9,
 260         RESETN_DDRPHY0_REQ_MASK         = 1 << RESETN_DDRPHY0_REQ_SHIFT,
 261         RESETN_DDR1_REQ_SHIFT           = 12,
 262         RESETN_DDR1_REQ_MASK            = 1 << RESETN_DDR1_REQ_SHIFT,
 263         RESETN_DDRPHY1_REQ_SHIFT        = 13,
 264         RESETN_DDRPHY1_REQ_MASK         = 1 << RESETN_DDRPHY1_REQ_SHIFT,
 265 };
 266
 267 #define VCO_MAX_KHZ     (3200 * (MHz / KHz))
 268 #define VCO_MIN_KHZ     (800 * (MHz / KHz))
 269 #define OUTPUT_MAX_KHZ  (3200 * (MHz / KHz))
 270 #define OUTPUT_MIN_KHZ  (16 * (MHz / KHz))
 271
 272 /*
 273  *  the div restructions of pll in integer mode, these are defined in
 274  *  * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
 275  */
 276 #define PLL_DIV_MIN     16
 277 #define PLL_DIV_MAX     3200
 278
 279 /*
 280  * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
 281  * Formulas also embedded within the Fractional PLL Verilog model:
 282  * If DSMPD = 1 (DSM is disabled, "integer mode")
 283  * FOUTVCO = FREF / REFDIV * FBDIV
 284  * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
 285  * Where:
 286  * FOUTVCO = Fractional PLL non-divided output frequency
 287  * FOUTPOSTDIV = Fractional PLL divided output frequency
 288  *               (output of second post divider)
 289  * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
 290  * REFDIV = Fractional PLL input reference clock divider
 291  * FBDIV = Integer value programmed into feedback divide
 292  *
 293  */
 294 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
 295 {
 296         /* All 8 PLLs have same VCO and output frequency range restrictions. */
 297         u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
 298         u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
 299
 300         debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
 301                            "postdiv2=%d, vco=%u khz, output=%u khz\n",
 302                            pll_con, div->fbdiv, div->refdiv, div->postdiv1,
 303                            div->postdiv2, vco_khz, output_khz);
 304         assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
 305                output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
 306                div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
 307
 308         /*
 309          * When power on or changing PLL setting,
 310          * we must force PLL into slow mode to ensure output stable clock.
 311          */
 312         rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
 313                      PLL_MODE_SLOW << PLL_MODE_SHIFT);
 314
 315         /* use integer mode */
 316         rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
 317                      PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
 318
 319         rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
 320                      div->fbdiv << PLL_FBDIV_SHIFT);
 321         rk_clrsetreg(&pll_con[1],
 322                      PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
 323                      PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
 324                      (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
 325                      (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
 326                      (div->refdiv << PLL_REFDIV_SHIFT));
 327
 328         /* waiting for pll lock */
 329         while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
 330                 udelay(1);
 331
 332         /* pll enter normal mode */
 333         rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
 334                      PLL_MODE_NORM << PLL_MODE_SHIFT);
 335 }
 336
 337 static int pll_para_config(u32 freq_hz, struct pll_div *div)
 338 {
 339         u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
 340         u32 postdiv1, postdiv2 = 1;
 341         u32 fref_khz;
 342         u32 diff_khz, best_diff_khz;
 343         const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
 344         const u32 max_postdiv1 = 7, max_postdiv2 = 7;
 345         u32 vco_khz;
 346         u32 freq_khz = freq_hz / KHz;
 347
 348         if (!freq_hz) {
 349                 printf("%s: the frequency can't be 0 Hz\n", __func__);
 350                 return -1;
 351         }
 352
 353         postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 354         if (postdiv1 > max_postdiv1) {
 355                 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
 356                 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
 357         }
 358
 359         vco_khz = freq_khz * postdiv1 * postdiv2;
 360
 361         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
 362             postdiv2 > max_postdiv2) {
 363                 printf("%s: Cannot find out a supported VCO"
 364                        " for Frequency (%uHz).\n", __func__, freq_hz);
 365                 return -1;
 366         }
 367
 368         div->postdiv1 = postdiv1;
 369         div->postdiv2 = postdiv2;
 370
 371         best_diff_khz = vco_khz;
 372         for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
 373                 fref_khz = ref_khz / refdiv;
 374
 375                 fbdiv = vco_khz / fref_khz;
 376                 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
 377                         continue;
 378                 diff_khz = vco_khz - fbdiv * fref_khz;
 379                 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
 380                         fbdiv++;
 381                         diff_khz = fref_khz - diff_khz;
 382                 }
 383
 384                 if (diff_khz >= best_diff_khz)
 385                         continue;
 386
 387                 best_diff_khz = diff_khz;
 388                 div->refdiv = refdiv;
 389                 div->fbdiv = fbdiv;
 390         }
 391
 392         if (best_diff_khz > 4 * (MHz/KHz)) {
 393                 printf("%s: Failed to match output frequency %u, "
 394                        "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
 395                        best_diff_khz * KHz);
 396                 return -1;
 397         }
 398         return 0;
 399 }
 400
 401 void rk3399_configure_cpu(struct rk3399_cru *cru,
 402                           enum apll_l_frequencies apll_l_freq)
 403 {
 404         u32 aclkm_div;
 405         u32 pclk_dbg_div;
 406         u32 atclk_div;
 407
 408         rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
 409
 410         aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1;
 411         assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ &&
 412                aclkm_div < 0x1f);
 413
 414         pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1;
 415         assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ &&
 416                pclk_dbg_div < 0x1f);
 417
 418         atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1;
 419         assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ &&
 420                atclk_div < 0x1f);
 421
 422         rk_clrsetreg(&cru->clksel_con[0],
 423                      ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
 424                      CLK_CORE_L_DIV_MASK,
 425                      aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
 426                      CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
 427                      0 << CLK_CORE_L_DIV_SHIFT);
 428
 429         rk_clrsetreg(&cru->clksel_con[1],
 430                      PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
 431                      pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
 432                      atclk_div << ATCLK_CORE_L_DIV_SHIFT);
 433 }
 434 #define I2C_CLK_REG_MASK(bus) \
 435                         (I2C_DIV_CON_MASK << \
 436                         CLK_I2C ##bus## _DIV_CON_SHIFT | \
 437                         CLK_I2C_PLL_SEL_MASK << \
 438                         CLK_I2C ##bus## _PLL_SEL_SHIFT)
 439
 440 #define I2C_CLK_REG_VALUE(bus, clk_div) \
 441                               ((clk_div - 1) << \
 442                                         CLK_I2C ##bus## _DIV_CON_SHIFT | \
 443                               CLK_I2C_PLL_SEL_GPLL << \
 444                                         CLK_I2C ##bus## _PLL_SEL_SHIFT)
 445
 446 #define I2C_CLK_DIV_VALUE(con, bus) \
 447                         (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
 448                                 I2C_DIV_CON_MASK;
 449
 450 #define I2C_PMUCLK_REG_MASK(bus) \
 451                         (I2C_DIV_CON_MASK << \
 452                          CLK_I2C ##bus## _DIV_CON_SHIFT)
 453
 454 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
 455                                 ((clk_div - 1) << \
 456                                 CLK_I2C ##bus## _DIV_CON_SHIFT)
 457
 458 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
 459 {
 460         u32 div, con;
 461
 462         switch (clk_id) {
 463         case SCLK_I2C1:
 464                 con = readl(&cru->clksel_con[61]);
 465                 div = I2C_CLK_DIV_VALUE(con, 1);
 466                 break;
 467         case SCLK_I2C2:
 468                 con = readl(&cru->clksel_con[62]);
 469                 div = I2C_CLK_DIV_VALUE(con, 2);
 470                 break;
 471         case SCLK_I2C3:
 472                 con = readl(&cru->clksel_con[63]);
 473                 div = I2C_CLK_DIV_VALUE(con, 3);
 474                 break;
 475         case SCLK_I2C5:
 476                 con = readl(&cru->clksel_con[61]);
 477                 div = I2C_CLK_DIV_VALUE(con, 5);
 478                 break;
 479         case SCLK_I2C6:
 480                 con = readl(&cru->clksel_con[62]);
 481                 div = I2C_CLK_DIV_VALUE(con, 6);
 482                 break;
 483         case SCLK_I2C7:
 484                 con = readl(&cru->clksel_con[63]);
 485                 div = I2C_CLK_DIV_VALUE(con, 7);
 486                 break;
 487         default:
 488                 printf("do not support this i2c bus\n");
 489                 return -EINVAL;
 490         }
 491
 492         return DIV_TO_RATE(GPLL_HZ, div);
 493 }
 494
 495 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
 496 {
 497         int src_clk_div;
 498
 499         /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
 500         src_clk_div = GPLL_HZ / hz;
 501         assert(src_clk_div - 1 < 127);
 502
 503         switch (clk_id) {
 504         case SCLK_I2C1:
 505                 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
 506                              I2C_CLK_REG_VALUE(1, src_clk_div));
 507                 break;
 508         case SCLK_I2C2:
 509                 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
 510                              I2C_CLK_REG_VALUE(2, src_clk_div));
 511                 break;
 512         case SCLK_I2C3:
 513                 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
 514                              I2C_CLK_REG_VALUE(3, src_clk_div));
 515                 break;
 516         case SCLK_I2C5:
 517                 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
 518                              I2C_CLK_REG_VALUE(5, src_clk_div));
 519                 break;
 520         case SCLK_I2C6:
 521                 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
 522                              I2C_CLK_REG_VALUE(6, src_clk_div));
 523                 break;
 524         case SCLK_I2C7:
 525                 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
 526                              I2C_CLK_REG_VALUE(7, src_clk_div));
 527                 break;
 528         default:
 529                 printf("do not support this i2c bus\n");
 530                 return -EINVAL;
 531         }
 532
 533         return rk3399_i2c_get_clk(cru, clk_id);
 534 }
 535
 536 /*
 537  * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
 538  * to select either CPLL or GPLL as the clock-parent. The location within
 539  * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
 540  */
 541
 542 struct spi_clkreg {
 543         uint8_t reg;  /* CLKSEL_CON[reg] register in CRU */
 544         uint8_t div_shift;
 545         uint8_t sel_shift;
 546 };
 547
 548 /*
 549  * The entries are numbered relative to their offset from SCLK_SPI0.
 550  *
 551  * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
 552  * logic is not supported).
 553  */
 554 static const struct spi_clkreg spi_clkregs[] = {
 555         [0] = { .reg = 59,
 556                 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
 557                 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
 558         [1] = { .reg = 59,
 559                 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
 560                 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
 561         [2] = { .reg = 60,
 562                 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
 563                 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
 564         [3] = { .reg = 60,
 565                 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
 566                 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
 567         [4] = { .reg = 58,
 568                 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
 569                 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
 570 };
 571
 572 static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
 573 {
 574         return (val >> shift) & ((1 << width) - 1);
 575 }
 576
 577 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
 578 {
 579         const struct spi_clkreg *spiclk = NULL;
 580         u32 div, val;
 581
 582         switch (clk_id) {
 583         case SCLK_SPI0 ... SCLK_SPI5:
 584                 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
 585                 break;
 586
 587         default:
 588                 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
 589                 return -EINVAL;
 590         }
 591
 592         val = readl(&cru->clksel_con[spiclk->reg]);
 593         div = extract_bits(val, CLK_SPI_PLL_DIV_CON_WIDTH, spiclk->div_shift);
 594
 595         return DIV_TO_RATE(GPLL_HZ, div);
 596 }
 597
 598 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
 599 {
 600         const struct spi_clkreg *spiclk = NULL;
 601         int src_clk_div;
 602
 603         src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
 604         assert(src_clk_div < 128);
 605
 606         switch (clk_id) {
 607         case SCLK_SPI1 ... SCLK_SPI5:
 608                 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
 609                 break;
 610
 611         default:
 612                 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
 613                 return -EINVAL;
 614         }
 615
 616         rk_clrsetreg(&cru->clksel_con[spiclk->reg],
 617                      ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
 618                        (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
 619                      ((src_clk_div << spiclk->div_shift) |
 620                       (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
 621
 622         return rk3399_spi_get_clk(cru, clk_id);
 623 }
 624
 625 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
 626 {
 627         struct pll_div vpll_config = {0};
 628         int aclk_vop = 198*MHz;
 629         void *aclkreg_addr, *dclkreg_addr;
 630         u32 div;
 631
 632         switch (clk_id) {
 633         case DCLK_VOP0:
 634                 aclkreg_addr = &cru->clksel_con[47];
 635                 dclkreg_addr = &cru->clksel_con[49];
 636                 break;
 637         case DCLK_VOP1:
 638                 aclkreg_addr = &cru->clksel_con[48];
 639                 dclkreg_addr = &cru->clksel_con[50];
 640                 break;
 641         default:
 642                 return -EINVAL;
 643         }
 644         /* vop aclk source clk: cpll */
 645         div = CPLL_HZ / aclk_vop;
 646         assert(div - 1 < 32);
 647
 648         rk_clrsetreg(aclkreg_addr,
 649                      ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
 650                      ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
 651                      (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
 652
 653         /* vop dclk source from vpll, and equals to vpll(means div == 1) */
 654         if (pll_para_config(hz, &vpll_config))
 655                 return -1;
 656
 657         rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
 658
 659         rk_clrsetreg(dclkreg_addr,
 660                      DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK|
 661                      DCLK_VOP_DIV_CON_MASK,
 662                      DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
 663                      DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
 664                      (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
 665
 666         return hz;
 667 }
 668
 669 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
 670 {
 671         u32 div, con;
 672
 673         switch (clk_id) {
 674         case HCLK_SDMMC:
 675         case SCLK_SDMMC:
 676                 con = readl(&cru->clksel_con[16]);
 677                 /* dwmmc controller have internal div 2 */
 678                 div = 2;
 679                 break;
 680         case SCLK_EMMC:
 681                 con = readl(&cru->clksel_con[21]);
 682                 div = 1;
 683                 break;
 684         default:
 685                 return -EINVAL;
 686         }
 687
 688         div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
 689         if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
 690                         == CLK_EMMC_PLL_SEL_24M)
 691                 return DIV_TO_RATE(OSC_HZ, div);
 692         else
 693                 return DIV_TO_RATE(GPLL_HZ, div);
 694 }
 695
 696 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
 697                                 ulong clk_id, ulong set_rate)
 698 {
 699         int src_clk_div;
 700         int aclk_emmc = 198*MHz;
 701
 702         switch (clk_id) {
 703         case HCLK_SDMMC:
 704         case SCLK_SDMMC:
 705                 /* Select clk_sdmmc source from GPLL by default */
 706                 /* mmc clock defaulg div 2 internal, provide double in cru */
 707                 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
 708
 709                 if (src_clk_div > 128) {
 710                         /* use 24MHz source for 400KHz clock */
 711                         src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
 712                         assert(src_clk_div - 1 < 128);
 713                         rk_clrsetreg(&cru->clksel_con[16],
 714                                      CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 715                                      CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
 716                                      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 717                 } else {
 718                         rk_clrsetreg(&cru->clksel_con[16],
 719                                      CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 720                                      CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 721                                      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 722                 }
 723                 break;
 724         case SCLK_EMMC:
 725                 /* Select aclk_emmc source from GPLL */
 726                 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc);
 727                 assert(src_clk_div - 1 < 32);
 728
 729                 rk_clrsetreg(&cru->clksel_con[21],
 730                              ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
 731                              ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
 732                              (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
 733
 734                 /* Select clk_emmc source from GPLL too */
 735                 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
 736                 assert(src_clk_div - 1 < 128);
 737
 738                 rk_clrsetreg(&cru->clksel_con[22],
 739                              CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 740                              CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 741                              (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 742                 break;
 743         default:
 744                 return -EINVAL;
 745         }
 746         return rk3399_mmc_get_clk(cru, clk_id);
 747 }
 748
 749 #define PMUSGRF_DDR_RGN_CON16 0xff330040
 750 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
 751                                 ulong set_rate)
 752 {
 753         struct pll_div dpll_cfg;
 754
 755         /*  IC ECO bug, need to set this register */
 756         writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
 757
 758         /*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
 759         switch (set_rate) {
 760         case 200*MHz:
 761                 dpll_cfg = (struct pll_div)
 762                 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
 763                 break;
 764         case 300*MHz:
 765                 dpll_cfg = (struct pll_div)
 766                 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
 767                 break;
 768         case 666*MHz:
 769                 dpll_cfg = (struct pll_div)
 770                 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
 771                 break;
 772         case 800*MHz:
 773                 dpll_cfg = (struct pll_div)
 774                 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
 775                 break;
 776         case 933*MHz:
 777                 dpll_cfg = (struct pll_div)
 778                 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
 779                 break;
 780         default:
 781                 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
 782         }
 783         rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
 784
 785         return set_rate;
 786 }
 787
 788 static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
 789 {
 790         u32 div, val;
 791
 792         val = readl(&cru->clksel_con[26]);
 793         div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
 794                                CLK_SARADC_DIV_CON_WIDTH);
 795
 796         return DIV_TO_RATE(OSC_HZ, div);
 797 }
 798
 799 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
 800 {
 801         int src_clk_div;
 802
 803         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
 804         assert(src_clk_div < 128);
 805
 806         rk_clrsetreg(&cru->clksel_con[26],
 807                      CLK_SARADC_DIV_CON_MASK,
 808                      src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
 809
 810         return rk3399_saradc_get_clk(cru);
 811 }
 812
 813 static ulong rk3399_clk_get_rate(struct clk *clk)
 814 {
 815         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
 816         ulong rate = 0;
 817
 818         switch (clk->id) {
 819         case 0 ... 63:
 820                 return 0;
 821         case HCLK_SDMMC:
 822         case SCLK_SDMMC:
 823         case SCLK_EMMC:
 824                 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
 825                 break;
 826         case SCLK_I2C1:
 827         case SCLK_I2C2:
 828         case SCLK_I2C3:
 829         case SCLK_I2C5:
 830         case SCLK_I2C6:
 831         case SCLK_I2C7:
 832                 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
 833                 break;
 834         case SCLK_SPI0...SCLK_SPI5:
 835                 rate = rk3399_spi_get_clk(priv->cru, clk->id);
 836                 break;
 837         case SCLK_UART0:
 838         case SCLK_UART2:
 839                 return 24000000;
 840                 break;
 841         case PCLK_HDMI_CTRL:
 842                 break;
 843         case DCLK_VOP0:
 844         case DCLK_VOP1:
 845                 break;
 846         case PCLK_EFUSE1024NS:
 847                 break;
 848         case SCLK_SARADC:
 849                 rate = rk3399_saradc_get_clk(priv->cru);
 850                 break;
 851         default:
 852                 return -ENOENT;
 853         }
 854
 855         return rate;
 856 }
 857
 858 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 859 {
 860         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
 861         ulong ret = 0;
 862
 863         switch (clk->id) {
 864         case 0 ... 63:
 865                 return 0;
 866         case HCLK_SDMMC:
 867         case SCLK_SDMMC:
 868         case SCLK_EMMC:
 869                 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
 870                 break;
 871         case SCLK_MAC:
 872                 /* nothing to do, as this is an external clock */
 873                 ret = rate;
 874                 break;
 875         case SCLK_I2C1:
 876         case SCLK_I2C2:
 877         case SCLK_I2C3:
 878         case SCLK_I2C5:
 879         case SCLK_I2C6:
 880         case SCLK_I2C7:
 881                 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
 882                 break;
 883         case SCLK_SPI0...SCLK_SPI5:
 884                 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
 885                 break;
 886         case PCLK_HDMI_CTRL:
 887         case PCLK_VIO_GRF:
 888                 /* the PCLK gates for video are enabled by default */
 889                 break;
 890         case DCLK_VOP0:
 891         case DCLK_VOP1:
 892                 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
 893                 break;
 894         case SCLK_DDRCLK:
 895                 ret = rk3399_ddr_set_clk(priv->cru, rate);
 896                 break;
 897         case PCLK_EFUSE1024NS:
 898                 break;
 899         case SCLK_SARADC:
 900                 ret = rk3399_saradc_set_clk(priv->cru, rate);
 901                 break;
 902         default:
 903                 return -ENOENT;
 904         }
 905
 906         return ret;
 907 }
 908
 909 static int rk3399_clk_enable(struct clk *clk)
 910 {
 911         switch (clk->id) {
 912         case HCLK_HOST0:
 913         case HCLK_HOST0_ARB:
 914         case HCLK_HOST1:
 915         case HCLK_HOST1_ARB:
 916                 return 0;
 917         }
 918
 919         debug("%s: unsupported clk %ld\n", __func__, clk->id);
 920         return -ENOENT;
 921 }
 922
 923 static struct clk_ops rk3399_clk_ops = {
 924         .get_rate = rk3399_clk_get_rate,
 925         .set_rate = rk3399_clk_set_rate,
 926         .enable = rk3399_clk_enable,
 927 };
 928
 929 #ifdef CONFIG_SPL_BUILD
 930 static void rkclk_init(struct rk3399_cru *cru)
 931 {
 932         u32 aclk_div;
 933         u32 hclk_div;
 934         u32 pclk_div;
 935
 936         rk3399_configure_cpu(cru, APLL_L_600_MHZ);
 937         /*
 938          * some cru registers changed by bootrom, we'd better reset them to
 939          * reset/default values described in TRM to avoid confusion in kernel.
 940          * Please consider these three lines as a fix of bootrom bug.
 941          */
 942         rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
 943         rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
 944         rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
 945
 946         /* configure gpll cpll */
 947         rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
 948         rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
 949
 950         /* configure perihp aclk, hclk, pclk */
 951         aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
 952         assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 953
 954         hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
 955         assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
 956                PERIHP_ACLK_HZ && (hclk_div < 0x4));
 957
 958         pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
 959         assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
 960                PERIHP_ACLK_HZ && (pclk_div < 0x7));
 961
 962         rk_clrsetreg(&cru->clksel_con[14],
 963                      PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
 964                      ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
 965                      pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
 966                      hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
 967                      ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
 968                      aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
 969
 970         /* configure perilp0 aclk, hclk, pclk */
 971         aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
 972         assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 973
 974         hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
 975         assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
 976                PERILP0_ACLK_HZ && (hclk_div < 0x4));
 977
 978         pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
 979         assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
 980                PERILP0_ACLK_HZ && (pclk_div < 0x7));
 981
 982         rk_clrsetreg(&cru->clksel_con[23],
 983                      PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
 984                      ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
 985                      pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
 986                      hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
 987                      ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
 988                      aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
 989
 990         /* perilp1 hclk select gpll as source */
 991         hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
 992         assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
 993                GPLL_HZ && (hclk_div < 0x1f));
 994
 995         pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
 996         assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
 997                PERILP1_HCLK_HZ && (hclk_div < 0x7));
 998
 999         rk_clrsetreg(&cru->clksel_con[25],
1000                      PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
1001                      HCLK_PERILP1_PLL_SEL_MASK,
1002                      pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
1003                      hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1004                      HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1005 }
1006 #endif
1007
1008 static int rk3399_clk_probe(struct udevice *dev)
1009 {
1010 #ifdef CONFIG_SPL_BUILD
1011         struct rk3399_clk_priv *priv = dev_get_priv(dev);
1012
1013 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1014         struct rk3399_clk_plat *plat = dev_get_platdata(dev);
1015
1016         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1017 #endif
1018         rkclk_init(priv->cru);
1019 #endif
1020         return 0;
1021 }
1022
1023 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
1024 {
1025 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1026         struct rk3399_clk_priv *priv = dev_get_priv(dev);
1027
1028         priv->cru = dev_read_addr_ptr(dev);
1029 #endif
1030         return 0;
1031 }
1032
1033 static int rk3399_clk_bind(struct udevice *dev)
1034 {
1035         int ret;
1036
1037         /* The reset driver does not have a device node, so bind it here */
1038         ret = device_bind_driver(gd->dm_root, "rk3399_sysreset", "reset", &dev);
1039         if (ret)
1040                 printf("Warning: No RK3399 reset driver: ret=%d\n", ret);
1041
1042         return 0;
1043 }
1044
1045 static const struct udevice_id rk3399_clk_ids[] = {
1046         { .compatible = "rockchip,rk3399-cru" },
1047         { }
1048 };
1049
1050 U_BOOT_DRIVER(clk_rk3399) = {
1051         .name           = "rockchip_rk3399_cru",
1052         .id             = UCLASS_CLK,
1053         .of_match       = rk3399_clk_ids,
1054         .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
1055         .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
1056         .ops            = &rk3399_clk_ops,
1057         .bind           = rk3399_clk_bind,
1058         .probe          = rk3399_clk_probe,
1059 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1060         .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
1061 #endif
1062 };
1063
1064 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1065 {
1066         u32 div, con;
1067
1068         switch (clk_id) {
1069         case SCLK_I2C0_PMU:
1070                 con = readl(&pmucru->pmucru_clksel[2]);
1071                 div = I2C_CLK_DIV_VALUE(con, 0);
1072                 break;
1073         case SCLK_I2C4_PMU:
1074                 con = readl(&pmucru->pmucru_clksel[3]);
1075                 div = I2C_CLK_DIV_VALUE(con, 4);
1076                 break;
1077         case SCLK_I2C8_PMU:
1078                 con = readl(&pmucru->pmucru_clksel[2]);
1079                 div = I2C_CLK_DIV_VALUE(con, 8);
1080                 break;
1081         default:
1082                 printf("do not support this i2c bus\n");
1083                 return -EINVAL;
1084         }
1085
1086         return DIV_TO_RATE(PPLL_HZ, div);
1087 }
1088
1089 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1090                                    uint hz)
1091 {
1092         int src_clk_div;
1093
1094         src_clk_div = PPLL_HZ / hz;
1095         assert(src_clk_div - 1 < 127);
1096
1097         switch (clk_id) {
1098         case SCLK_I2C0_PMU:
1099                 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1100                              I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1101                 break;
1102         case SCLK_I2C4_PMU:
1103                 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1104                              I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1105                 break;
1106         case SCLK_I2C8_PMU:
1107                 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1108                              I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1109                 break;
1110         default:
1111                 printf("do not support this i2c bus\n");
1112                 return -EINVAL;
1113         }
1114
1115         return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1116 }
1117
1118 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1119 {
1120         u32 div, con;
1121
1122         /* PWM closk rate is same as pclk_pmu */
1123         con = readl(&pmucru->pmucru_clksel[0]);
1124         div = con & PMU_PCLK_DIV_CON_MASK;
1125
1126         return DIV_TO_RATE(PPLL_HZ, div);
1127 }
1128
1129 static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1130 {
1131         struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1132         ulong rate = 0;
1133
1134         switch (clk->id) {
1135         case PCLK_RKPWM_PMU:
1136                 rate = rk3399_pwm_get_clk(priv->pmucru);
1137                 break;
1138         case SCLK_I2C0_PMU:
1139         case SCLK_I2C4_PMU:
1140         case SCLK_I2C8_PMU:
1141                 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1142                 break;
1143         default:
1144                 return -ENOENT;
1145         }
1146
1147         return rate;
1148 }
1149
1150 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1151 {
1152         struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1153         ulong ret = 0;
1154
1155         switch (clk->id) {
1156         case SCLK_I2C0_PMU:
1157         case SCLK_I2C4_PMU:
1158         case SCLK_I2C8_PMU:
1159                 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1160                 break;
1161         default:
1162                 return -ENOENT;
1163         }
1164
1165         return ret;
1166 }
1167
1168 static struct clk_ops rk3399_pmuclk_ops = {
1169         .get_rate = rk3399_pmuclk_get_rate,
1170         .set_rate = rk3399_pmuclk_set_rate,
1171 };
1172
1173 #ifndef CONFIG_SPL_BUILD
1174 static void pmuclk_init(struct rk3399_pmucru *pmucru)
1175 {
1176         u32 pclk_div;
1177
1178         /*  configure pmu pll(ppll) */
1179         rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1180
1181         /*  configure pmu pclk */
1182         pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
1183         rk_clrsetreg(&pmucru->pmucru_clksel[0],
1184                      PMU_PCLK_DIV_CON_MASK,
1185                      pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1186 }
1187 #endif
1188
1189 static int rk3399_pmuclk_probe(struct udevice *dev)
1190 {
1191 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
1192         struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1193 #endif
1194
1195 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1196         struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
1197
1198         priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1199 #endif
1200
1201 #ifndef CONFIG_SPL_BUILD
1202         pmuclk_init(priv->pmucru);
1203 #endif
1204         return 0;
1205 }
1206
1207 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
1208 {
1209 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1210         struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1211
1212         priv->pmucru = dev_read_addr_ptr(dev);
1213 #endif
1214         return 0;
1215 }
1216
1217 static const struct udevice_id rk3399_pmuclk_ids[] = {
1218         { .compatible = "rockchip,rk3399-pmucru" },
1219         { }
1220 };
1221
1222 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
1223         .name           = "rockchip_rk3399_pmucru",
1224         .id             = UCLASS_CLK,
1225         .of_match       = rk3399_pmuclk_ids,
1226         .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
1227         .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
1228         .ops            = &rk3399_pmuclk_ops,
1229         .probe          = rk3399_pmuclk_probe,
1230 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1231         .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
1232 #endif
1233 };