2 * Copyright (c) 2016, NVIDIA CORPORATION.
4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
11 #include <asm/arch-tegra/bpmp_abi.h>
13 static ulong tegra186_clk_get_rate(struct clk *clk)
15 struct mrq_clk_request req;
16 struct mrq_clk_response resp;
19 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
22 req.cmd_and_id = (CMD_CLK_GET_RATE << 24) | clk->id;
24 ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
29 return resp.clk_get_rate.rate;
32 static ulong tegra186_clk_set_rate(struct clk *clk, ulong rate)
34 struct mrq_clk_request req;
35 struct mrq_clk_response resp;
38 debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
41 req.cmd_and_id = (CMD_CLK_SET_RATE << 24) | clk->id;
42 req.clk_set_rate.rate = rate;
44 ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
49 return resp.clk_set_rate.rate;
52 static int tegra186_clk_en_dis(struct clk *clk,
53 enum mrq_reset_commands cmd)
55 struct mrq_clk_request req;
56 struct mrq_clk_response resp;
59 req.cmd_and_id = (cmd << 24) | clk->id;
61 ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
69 static int tegra186_clk_enable(struct clk *clk)
71 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
74 return tegra186_clk_en_dis(clk, CMD_CLK_ENABLE);
77 static int tegra186_clk_disable(struct clk *clk)
79 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
82 return tegra186_clk_en_dis(clk, CMD_CLK_DISABLE);
85 static struct clk_ops tegra186_clk_ops = {
86 .get_rate = tegra186_clk_get_rate,
87 .set_rate = tegra186_clk_set_rate,
88 .enable = tegra186_clk_enable,
89 .disable = tegra186_clk_disable,
92 static int tegra186_clk_probe(struct udevice *dev)
94 debug("%s(dev=%p)\n", __func__, dev);
99 U_BOOT_DRIVER(tegra186_clk) = {
100 .name = "tegra186_clk",
102 .probe = tegra186_clk_probe,
103 .ops = &tegra186_clk_ops,