2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <clk-uclass.h>
11 #include <linux/bitops.h>
13 #include <linux/sizes.h>
15 #include "clk-uniphier.h"
18 * struct uniphier_clk_priv - private data for UniPhier clock driver
20 * @base: base address of the clock provider
21 * @data: SoC specific data
23 struct uniphier_clk_priv {
25 const struct uniphier_clk_data *data;
28 static int uniphier_clk_enable(struct clk *clk)
30 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
31 unsigned long id = clk->id;
32 const struct uniphier_clk_gate_data *p;
34 for (p = priv->data->gate; p->id != UNIPHIER_CLK_ID_END; p++) {
40 val = readl(priv->base + p->reg);
42 writel(val, priv->base + p->reg);
47 dev_err(priv->dev, "clk_id=%lu was not handled\n", id);
51 static const struct uniphier_clk_mux_data *
52 uniphier_clk_get_mux_data(struct uniphier_clk_priv *priv, unsigned long id)
54 const struct uniphier_clk_mux_data *p;
56 for (p = priv->data->mux; p->id != UNIPHIER_CLK_ID_END; p++) {
64 static ulong uniphier_clk_get_rate(struct clk *clk)
66 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
67 const struct uniphier_clk_mux_data *mux;
71 mux = uniphier_clk_get_mux_data(priv, clk->id);
75 if (!mux->nr_muxs) /* fixed-rate */
78 val = readl(priv->base + mux->reg);
80 for (i = 0; i < mux->nr_muxs; i++)
81 if ((mux->masks[i] & val) == mux->vals[i])
87 static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
89 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
90 const struct uniphier_clk_mux_data *mux;
92 int i, best_rate_id = -1;
95 mux = uniphier_clk_get_mux_data(priv, clk->id);
99 if (!mux->nr_muxs) /* fixed-rate */
100 return mux->rates[0];
102 /* first, decide the best match rate */
103 for (i = 0; i < mux->nr_muxs; i++) {
104 if (mux->rates[i] > best_rate && mux->rates[i] <= rate) {
105 best_rate = mux->rates[i];
110 if (best_rate_id < 0)
113 val = readl(priv->base + mux->reg);
114 val &= ~mux->masks[best_rate_id];
115 val |= mux->vals[best_rate_id];
116 writel(val, priv->base + mux->reg);
118 debug("%s: requested rate = %lu, set rate = %lu\n", __func__,
124 const struct clk_ops uniphier_clk_ops = {
125 .enable = uniphier_clk_enable,
126 .get_rate = uniphier_clk_get_rate,
127 .set_rate = uniphier_clk_set_rate,
130 static int uniphier_clk_probe(struct udevice *dev)
132 struct uniphier_clk_priv *priv = dev_get_priv(dev);
135 addr = devfdt_get_addr(dev->parent);
136 if (addr == FDT_ADDR_T_NONE)
139 priv->base = devm_ioremap(dev, addr, SZ_4K);
143 priv->data = (void *)dev_get_driver_data(dev);
148 static const struct udevice_id uniphier_clk_match[] = {
150 .compatible = "socionext,uniphier-sld3-mio-clock",
151 .data = (ulong)&uniphier_mio_clk_data,
154 .compatible = "socionext,uniphier-ld4-mio-clock",
155 .data = (ulong)&uniphier_mio_clk_data,
158 .compatible = "socionext,uniphier-pro4-mio-clock",
159 .data = (ulong)&uniphier_mio_clk_data,
162 .compatible = "socionext,uniphier-sld8-mio-clock",
163 .data = (ulong)&uniphier_mio_clk_data,
166 .compatible = "socionext,uniphier-pro5-sd-clock",
167 .data = (ulong)&uniphier_mio_clk_data,
170 .compatible = "socionext,uniphier-pxs2-sd-clock",
171 .data = (ulong)&uniphier_mio_clk_data,
174 .compatible = "socionext,uniphier-ld11-mio-clock",
175 .data = (ulong)&uniphier_mio_clk_data,
178 .compatible = "socionext,uniphier-ld20-sd-clock",
179 .data = (ulong)&uniphier_mio_clk_data,
184 U_BOOT_DRIVER(uniphier_clk) = {
185 .name = "uniphier-clk",
187 .of_match = uniphier_clk_match,
188 .probe = uniphier_clk_probe,
189 .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
190 .ops = &uniphier_clk_ops,