2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/bitops.h>
11 #include <linux/sizes.h>
12 #include <clk-uclass.h>
13 #include <dm/device.h>
15 #include "clk-uniphier.h"
18 * struct uniphier_clk_priv - private data for UniPhier clock driver
20 * @base: base address of the clock provider
21 * @socdata: SoC specific data
23 struct uniphier_clk_priv {
25 const struct uniphier_clk_soc_data *socdata;
28 int uniphier_clk_probe(struct udevice *dev)
30 struct uniphier_clk_priv *priv = dev_get_priv(dev);
33 addr = dev_get_addr(dev->parent);
34 if (addr == FDT_ADDR_T_NONE)
37 priv->base = devm_ioremap(dev, addr, SZ_4K);
41 priv->socdata = (void *)dev_get_driver_data(dev);
46 static int uniphier_clk_enable(struct clk *clk)
48 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
49 const struct uniphier_clk_gate_data *gate = priv->socdata->gate;
50 unsigned int nr_gate = priv->socdata->nr_gate;
55 for (i = 0; i < nr_gate; i++) {
56 if (gate[i].index != clk->id)
59 reg = priv->base + gate[i].reg;
61 data = gate[i].data & mask;
66 debug("%s: %p: %08x\n", __func__, reg, tmp);
73 static ulong uniphier_clk_get_rate(struct clk *clk)
75 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
76 const struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
77 unsigned int nr_rdata = priv->socdata->nr_rate;
80 ulong matched_rate = 0;
83 for (i = 0; i < nr_rdata; i++) {
84 if (rdata[i].index != clk->id)
87 if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
90 reg = priv->base + rdata[i].reg;
92 data = rdata[i].data & mask;
93 if ((readl(reg) & mask) == data) {
94 if (matched_rate && rdata[i].rate != matched_rate) {
95 printf("failed to get clk rate for insane register values\n");
98 matched_rate = rdata[i].rate;
102 debug("%s: rate = %lu\n", __func__, matched_rate);
107 static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
109 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
110 const struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
111 unsigned int nr_rdata = priv->socdata->nr_rate;
117 /* first, decide the best match rate */
118 for (i = 0; i < nr_rdata; i++) {
119 if (rdata[i].index != clk->id)
122 if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
125 if (rdata[i].rate > best_rate && rdata[i].rate <= rate)
126 best_rate = rdata[i].rate;
132 debug("%s: requested rate = %lu, set rate = %lu\n", __func__,
135 /* second, really set registers */
136 for (i = 0; i < nr_rdata; i++) {
137 if (rdata[i].index != clk->id || rdata[i].rate != best_rate)
140 reg = priv->base + rdata[i].reg;
141 mask = rdata[i].mask;
142 data = rdata[i].data & mask;
147 debug("%s: %p: %08x\n", __func__, reg, tmp);
154 const struct clk_ops uniphier_clk_ops = {
155 .enable = uniphier_clk_enable,
156 .get_rate = uniphier_clk_get_rate,
157 .set_rate = uniphier_clk_set_rate,
160 static const struct udevice_id uniphier_clk_match[] = {
162 .compatible = "socionext,uniphier-sld3-mio-clock",
163 .data = (ulong)&uniphier_mio_clk_data,
166 .compatible = "socionext,uniphier-ld4-mio-clock",
167 .data = (ulong)&uniphier_mio_clk_data,
170 .compatible = "socionext,uniphier-pro4-mio-clock",
171 .data = (ulong)&uniphier_mio_clk_data,
174 .compatible = "socionext,uniphier-sld8-mio-clock",
175 .data = (ulong)&uniphier_mio_clk_data,
178 .compatible = "socionext,uniphier-pro5-mio-clock",
179 .data = (ulong)&uniphier_mio_clk_data,
182 .compatible = "socionext,uniphier-pxs2-mio-clock",
183 .data = (ulong)&uniphier_mio_clk_data,
186 .compatible = "socionext,uniphier-ld11-mio-clock",
187 .data = (ulong)&uniphier_mio_clk_data,
190 .compatible = "socionext,uniphier-ld20-mio-clock",
191 .data = (ulong)&uniphier_mio_clk_data,
196 U_BOOT_DRIVER(uniphier_clk) = {
197 .name = "uniphier-clk",
199 .of_match = uniphier_clk_match,
200 .probe = uniphier_clk_probe,
201 .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
202 .ops = &uniphier_clk_ops,