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Merge git://git.denx.de/u-boot-uniphier
[u-boot] / drivers / clk / uniphier / clk-uniphier-mio.c
1 /*
2  * Copyright (C) 2016 Socionext Inc.
3  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #include "clk-uniphier.h"
9
10 #define UNIPHIER_MIO_CLK_SD_FIXED                                       \
11         UNIPHIER_CLK_RATE(128, 44444444),                               \
12         UNIPHIER_CLK_RATE(129, 33333333),                               \
13         UNIPHIER_CLK_RATE(130, 50000000),                               \
14         UNIPHIER_CLK_RATE(131, 66666667),                               \
15         UNIPHIER_CLK_RATE(132, 100000000),                              \
16         UNIPHIER_CLK_RATE(133, 40000000),                               \
17         UNIPHIER_CLK_RATE(134, 25000000),                               \
18         UNIPHIER_CLK_RATE(135, 22222222)
19
20 #define UNIPHIER_MIO_CLK_SD(_id, ch)                                    \
21         {                                                               \
22                 .type = UNIPHIER_CLK_TYPE_MUX,                          \
23                 .id = (_id) + 32,                                       \
24                 .data.mux = {                                           \
25                         .parent_ids = {                                 \
26                                 128,                                    \
27                                 129,                                    \
28                                 130,                                    \
29                                 131,                                    \
30                                 132,                                    \
31                                 133,                                    \
32                                 134,                                    \
33                                 135,                                    \
34                         },                                              \
35                         .num_parents = 8,                               \
36                         .reg = 0x30 + 0x200 * (ch),                     \
37                         .masks = {                                      \
38                                 0x00031000,                             \
39                                 0x00031000,                             \
40                                 0x00031000,                             \
41                                 0x00031000,                             \
42                                 0x00001300,                             \
43                                 0x00001300,                             \
44                                 0x00001300,                             \
45                                 0x00001300,                             \
46                         },                                              \
47                         .vals = {                                       \
48                                 0x00000000,                             \
49                                 0x00010000,                             \
50                                 0x00020000,                             \
51                                 0x00030000,                             \
52                                 0x00001000,                             \
53                                 0x00001100,                             \
54                                 0x00001200,                             \
55                                 0x00001300,                             \
56                         },                                              \
57                 },                                                      \
58         },                                                              \
59         UNIPHIER_CLK_GATE((_id), (_id) + 32, 0x20 + 0x200 * (ch), 8)
60
61 #define UNIPHIER_MIO_CLK_USB2(id, ch)                                   \
62         UNIPHIER_CLK_GATE_SIMPLE((id), 0x20 + 0x200 * (ch), 28)
63
64 #define UNIPHIER_MIO_CLK_USB2_PHY(id, ch)                               \
65         UNIPHIER_CLK_GATE_SIMPLE((id), 0x20 + 0x200 * (ch), 29)
66
67 #define UNIPHIER_MIO_CLK_DMAC(id)                                       \
68         UNIPHIER_CLK_GATE_SIMPLE((id), 0x20, 25)
69
70 const struct uniphier_clk_data uniphier_mio_clk_data[] = {
71         UNIPHIER_MIO_CLK_SD_FIXED,
72         UNIPHIER_MIO_CLK_SD(0, 0),
73         UNIPHIER_MIO_CLK_SD(1, 1),
74         UNIPHIER_MIO_CLK_SD(2, 2),
75         UNIPHIER_MIO_CLK_DMAC(7),
76         UNIPHIER_MIO_CLK_USB2(8, 0),
77         UNIPHIER_MIO_CLK_USB2(9, 1),
78         UNIPHIER_MIO_CLK_USB2(10, 2),
79         UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
80         UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
81         UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
82         { /* sentinel */ }
83 };