1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
5 * Derived from linux/arch/mips/bcm63xx/cpu.c:
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
16 DECLARE_GLOBAL_DATA_PTR;
18 #define REV_CHIPID_SHIFT 16
19 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
20 #define REV_LONG_CHIPID_SHIFT 12
21 #define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT)
22 #define REV_REVID_SHIFT 0
23 #define REV_REVID_MASK (0xff << REV_REVID_SHIFT)
25 #define REG_BCM6328_OTP 0x62c
26 #define BCM6328_TP1_DISABLED BIT(9)
28 #define REG_BCM6318_STRAP_OVRDBUS 0x900
29 #define OVRDBUS_6318_FREQ_SHIFT 23
30 #define OVRDBUS_6318_FREQ_MASK (0x3 << OVRDBUS_6318_FREQ_SHIFT)
32 #define REG_BCM6328_MISC_STRAPBUS 0x1a40
33 #define STRAPBUS_6328_FCVO_SHIFT 7
34 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
36 #define REG_BCM6348_PERF_MIPSPLLCFG 0x34
37 #define MIPSPLLCFG_6348_M1CPU_SHIFT 6
38 #define MIPSPLLCFG_6348_M1CPU_MASK (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
39 #define MIPSPLLCFG_6348_N2_SHIFT 15
40 #define MIPSPLLCFG_6348_N2_MASK (0x1F << MIPSPLLCFG_6348_N2_SHIFT)
41 #define MIPSPLLCFG_6348_N1_SHIFT 20
42 #define MIPSPLLCFG_6348_N1_MASK (0x7 << MIPSPLLCFG_6348_N1_SHIFT)
44 #define REG_BCM6358_DDR_DMIPSPLLCFG 0x12b8
45 #define DMIPSPLLCFG_6358_M1_SHIFT 0
46 #define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT)
47 #define DMIPSPLLCFG_6358_N1_SHIFT 23
48 #define DMIPSPLLCFG_6358_N1_MASK (0x3f << DMIPSPLLCFG_6358_N1_SHIFT)
49 #define DMIPSPLLCFG_6358_N2_SHIFT 29
50 #define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
52 #define REG_BCM6362_MISC_STRAPBUS 0x1814
53 #define STRAPBUS_6362_FCVO_SHIFT 1
54 #define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT)
56 #define REG_BCM6368_DDR_DMIPSPLLCFG 0x12a0
57 #define DMIPSPLLCFG_6368_P1_SHIFT 0
58 #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
59 #define DMIPSPLLCFG_6368_P2_SHIFT 4
60 #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
61 #define DMIPSPLLCFG_6368_NDIV_SHIFT 16
62 #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
63 #define REG_BCM6368_DDR_DMIPSPLLDIV 0x12a4
64 #define DMIPSPLLDIV_6368_MDIV_SHIFT 0
65 #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
67 #define REG_BCM63268_MISC_STRAPBUS 0x1814
68 #define STRAPBUS_63268_FCVO_SHIFT 21
69 #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
71 struct bmips_cpu_priv;
74 int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size);
75 ulong (*get_cpu_freq)(struct bmips_cpu_priv *);
76 int (*get_cpu_count)(struct bmips_cpu_priv *);
79 struct bmips_cpu_priv {
81 const struct bmips_cpu_hw *hw;
84 /* Specific CPU Ops */
85 static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
88 unsigned short cpu_id;
89 unsigned char cpu_rev;
92 val = readl_be(priv->regs);
93 cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
94 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
96 snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev);
101 static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
105 unsigned char cpu_rev;
108 val = readl_be(priv->regs);
109 cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT;
110 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
112 snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev);
117 static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv)
122 static ulong bcm6318_get_cpu_freq(struct bmips_cpu_priv *priv)
124 unsigned int mips_pll_fcvo;
126 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6318_STRAP_OVRDBUS);
127 mips_pll_fcvo = (mips_pll_fcvo & OVRDBUS_6318_FREQ_MASK)
128 >> OVRDBUS_6318_FREQ_SHIFT;
130 switch (mips_pll_fcvo) {
144 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
146 unsigned int mips_pll_fcvo;
148 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS);
149 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK)
150 >> STRAPBUS_6328_FCVO_SHIFT;
152 switch (mips_pll_fcvo) {
171 static ulong bcm6338_get_cpu_freq(struct bmips_cpu_priv *priv)
176 static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
178 unsigned int tmp, n1, n2, m1;
180 tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
181 n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
182 n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
183 m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
185 return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
188 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
190 unsigned int tmp, n1, n2, m1;
192 tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG);
193 n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT;
194 n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT;
195 m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT;
197 return (16 * 1000000 * n1 * n2) / m1;
200 static ulong bcm6362_get_cpu_freq(struct bmips_cpu_priv *priv)
202 unsigned int mips_pll_fcvo;
204 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6362_MISC_STRAPBUS);
205 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6362_FCVO_MASK)
206 >> STRAPBUS_6362_FCVO_SHIFT;
208 switch (mips_pll_fcvo) {
238 static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv)
240 unsigned int tmp, p1, p2, ndiv, m1;
242 tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLCFG);
243 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> DMIPSPLLCFG_6368_P1_SHIFT;
244 p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> DMIPSPLLCFG_6368_P2_SHIFT;
245 ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
246 DMIPSPLLCFG_6368_NDIV_SHIFT;
248 tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLDIV);
249 m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> DMIPSPLLDIV_6368_MDIV_SHIFT;
251 return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
254 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
256 unsigned int mips_pll_fcvo;
258 mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS);
259 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK)
260 >> STRAPBUS_63268_FCVO_SHIFT;
262 switch (mips_pll_fcvo) {
277 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
279 u32 val = readl_be(priv->regs + REG_BCM6328_OTP);
281 if (val & BCM6328_TP1_DISABLED)
287 static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
292 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
297 static const struct bmips_cpu_hw bmips_cpu_bcm3380 = {
298 .get_cpu_desc = bmips_short_cpu_desc,
299 .get_cpu_freq = bcm3380_get_cpu_freq,
300 .get_cpu_count = bcm6358_get_cpu_count,
303 static const struct bmips_cpu_hw bmips_cpu_bcm6318 = {
304 .get_cpu_desc = bmips_short_cpu_desc,
305 .get_cpu_freq = bcm6318_get_cpu_freq,
306 .get_cpu_count = bcm6345_get_cpu_count,
309 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
310 .get_cpu_desc = bmips_long_cpu_desc,
311 .get_cpu_freq = bcm6328_get_cpu_freq,
312 .get_cpu_count = bcm6328_get_cpu_count,
315 static const struct bmips_cpu_hw bmips_cpu_bcm6338 = {
316 .get_cpu_desc = bmips_short_cpu_desc,
317 .get_cpu_freq = bcm6338_get_cpu_freq,
318 .get_cpu_count = bcm6345_get_cpu_count,
321 static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
322 .get_cpu_desc = bmips_short_cpu_desc,
323 .get_cpu_freq = bcm6348_get_cpu_freq,
324 .get_cpu_count = bcm6345_get_cpu_count,
327 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
328 .get_cpu_desc = bmips_short_cpu_desc,
329 .get_cpu_freq = bcm6358_get_cpu_freq,
330 .get_cpu_count = bcm6358_get_cpu_count,
333 static const struct bmips_cpu_hw bmips_cpu_bcm6362 = {
334 .get_cpu_desc = bmips_short_cpu_desc,
335 .get_cpu_freq = bcm6362_get_cpu_freq,
336 .get_cpu_count = bcm6358_get_cpu_count,
339 static const struct bmips_cpu_hw bmips_cpu_bcm6368 = {
340 .get_cpu_desc = bmips_short_cpu_desc,
341 .get_cpu_freq = bcm6368_get_cpu_freq,
342 .get_cpu_count = bcm6358_get_cpu_count,
345 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
346 .get_cpu_desc = bmips_long_cpu_desc,
347 .get_cpu_freq = bcm63268_get_cpu_freq,
348 .get_cpu_count = bcm6358_get_cpu_count,
351 /* Generic CPU Ops */
352 static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size)
354 struct bmips_cpu_priv *priv = dev_get_priv(dev);
355 const struct bmips_cpu_hw *hw = priv->hw;
357 return hw->get_cpu_desc(priv, buf, size);
360 static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info)
362 struct bmips_cpu_priv *priv = dev_get_priv(dev);
363 const struct bmips_cpu_hw *hw = priv->hw;
365 info->cpu_freq = hw->get_cpu_freq(priv);
366 info->features = BIT(CPU_FEAT_L1_CACHE);
367 info->features |= BIT(CPU_FEAT_MMU);
368 info->features |= BIT(CPU_FEAT_DEVICE_ID);
373 static int bmips_cpu_get_count(struct udevice *dev)
375 struct bmips_cpu_priv *priv = dev_get_priv(dev);
376 const struct bmips_cpu_hw *hw = priv->hw;
378 return hw->get_cpu_count(priv);
381 static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size)
383 snprintf(buf, size, "Broadcom");
388 static const struct cpu_ops bmips_cpu_ops = {
389 .get_desc = bmips_cpu_get_desc,
390 .get_info = bmips_cpu_get_info,
391 .get_count = bmips_cpu_get_count,
392 .get_vendor = bmips_cpu_get_vendor,
395 /* BMIPS CPU driver */
396 int bmips_cpu_bind(struct udevice *dev)
398 struct cpu_platdata *plat = dev_get_parent_platdata(dev);
400 plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
402 plat->device_id = read_c0_prid();
407 int bmips_cpu_probe(struct udevice *dev)
409 struct bmips_cpu_priv *priv = dev_get_priv(dev);
410 const struct bmips_cpu_hw *hw =
411 (const struct bmips_cpu_hw *)dev_get_driver_data(dev);
415 addr = devfdt_get_addr_size_index(dev_get_parent(dev), 0, &size);
416 if (addr == FDT_ADDR_T_NONE)
419 priv->regs = ioremap(addr, size);
425 static const struct udevice_id bmips_cpu_ids[] = {
427 .compatible = "brcm,bcm3380-cpu",
428 .data = (ulong)&bmips_cpu_bcm3380,
430 .compatible = "brcm,bcm6318-cpu",
431 .data = (ulong)&bmips_cpu_bcm6318,
433 .compatible = "brcm,bcm6328-cpu",
434 .data = (ulong)&bmips_cpu_bcm6328,
436 .compatible = "brcm,bcm6338-cpu",
437 .data = (ulong)&bmips_cpu_bcm6338,
439 .compatible = "brcm,bcm6348-cpu",
440 .data = (ulong)&bmips_cpu_bcm6348,
442 .compatible = "brcm,bcm6358-cpu",
443 .data = (ulong)&bmips_cpu_bcm6358,
445 .compatible = "brcm,bcm6362-cpu",
446 .data = (ulong)&bmips_cpu_bcm6362,
448 .compatible = "brcm,bcm6368-cpu",
449 .data = (ulong)&bmips_cpu_bcm6368,
451 .compatible = "brcm,bcm63268-cpu",
452 .data = (ulong)&bmips_cpu_bcm63268,
457 U_BOOT_DRIVER(bmips_cpu_drv) = {
460 .of_match = bmips_cpu_ids,
461 .bind = bmips_cpu_bind,
462 .probe = bmips_cpu_probe,
463 .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv),
464 .ops = &bmips_cpu_ops,
465 .flags = DM_FLAG_PRE_RELOC,
468 #ifdef CONFIG_DISPLAY_CPUINFO
469 int print_cpuinfo(void)
476 err = uclass_get_device(UCLASS_CPU, 0, &dev);
480 err = cpu_get_info(dev, &cpu);
484 err = cpu_get_desc(dev, desc, sizeof(desc));
488 printf("Chip ID: %s, MIPS: ", desc);
489 print_freq(cpu.cpu_freq, "\n");