2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
6 * Based on CAAM driver in drivers/crypto/caam in Linux
14 #include "desc_constr.h"
15 #ifdef CONFIG_FSL_CORENET
16 #include <asm/fsl_pamu.h>
19 #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
20 #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
22 uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
24 #if defined(CONFIG_PPC_C29X)
25 CONFIG_SYS_FSL_SEC_IDX_OFFSET,
26 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
30 #define SEC_ADDR(idx) \
31 ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
33 #define SEC_JR0_ADDR(idx) \
35 (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
37 struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
39 static inline void start_jr0(uint8_t sec_idx)
41 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
42 u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
43 u32 scfgr = sec_in32(&sec->scfgr);
45 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
46 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
47 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
49 if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
50 (!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) &&
51 (scfgr & SEC_SCFGR_VIRT_EN)))
52 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
54 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
55 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
56 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
60 static inline void jr_reset_liodn(uint8_t sec_idx)
62 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
63 sec_out32(&sec->jrliodnr[0].ls, 0);
66 static inline void jr_disable_irq(uint8_t sec_idx)
68 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
69 uint32_t jrcfg = sec_in32(®s->jrcfg1);
71 jrcfg = jrcfg | JR_INTMASK;
73 sec_out32(®s->jrcfg1, jrcfg);
76 static void jr_initregs(uint8_t sec_idx)
78 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
79 struct jobring *jr = &jr0[sec_idx];
80 phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
81 phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);
83 #ifdef CONFIG_PHYS_64BIT
84 sec_out32(®s->irba_h, ip_base >> 32);
86 sec_out32(®s->irba_h, 0x0);
88 sec_out32(®s->irba_l, (uint32_t)ip_base);
89 #ifdef CONFIG_PHYS_64BIT
90 sec_out32(®s->orba_h, op_base >> 32);
92 sec_out32(®s->orba_h, 0x0);
94 sec_out32(®s->orba_l, (uint32_t)op_base);
95 sec_out32(®s->ors, JR_SIZE);
96 sec_out32(®s->irs, JR_SIZE);
99 jr_disable_irq(sec_idx);
102 static int jr_init(uint8_t sec_idx)
104 struct jobring *jr = &jr0[sec_idx];
106 memset(jr, 0, sizeof(struct jobring));
108 jr->jq_id = DEFAULT_JR_ID;
109 jr->irq = DEFAULT_IRQ;
111 #ifdef CONFIG_FSL_CORENET
112 jr->liodn = DEFAULT_JR_LIODN;
115 jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
116 JR_SIZE * sizeof(dma_addr_t));
120 jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
123 (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
124 if (!jr->output_ring)
127 memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
128 memset(jr->output_ring, 0, jr->op_size);
132 jr_initregs(sec_idx);
137 static int jr_sw_cleanup(uint8_t sec_idx)
139 struct jobring *jr = &jr0[sec_idx];
145 memset(jr->info, 0, sizeof(jr->info));
146 memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t));
147 memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
152 static int jr_hw_reset(uint8_t sec_idx)
154 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
155 uint32_t timeout = 100000;
156 uint32_t jrint, jrcr;
158 sec_out32(®s->jrcr, JRCR_RESET);
160 jrint = sec_in32(®s->jrint);
161 } while (((jrint & JRINT_ERR_HALT_MASK) ==
162 JRINT_ERR_HALT_INPROGRESS) && --timeout);
164 jrint = sec_in32(®s->jrint);
165 if (((jrint & JRINT_ERR_HALT_MASK) !=
166 JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
170 sec_out32(®s->jrcr, JRCR_RESET);
172 jrcr = sec_in32(®s->jrcr);
173 } while ((jrcr & JRCR_RESET) && --timeout);
181 /* -1 --- error, can't enqueue -- no space available */
182 static int jr_enqueue(uint32_t *desc_addr,
183 void (*callback)(uint32_t status, void *arg),
184 void *arg, uint8_t sec_idx)
186 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
187 struct jobring *jr = &jr0[sec_idx];
190 int length = desc_len(desc_addr);
192 #ifdef CONFIG_PHYS_64BIT
193 uint32_t *addr_hi, *addr_lo;
196 /* The descriptor must be submitted to SEC block as per endianness
198 * So, if the endianness of Core and SEC block is different, each word
199 * of the descriptor will be byte-swapped.
201 for (i = 0; i < length; i++) {
202 desc_word = desc_addr[i];
203 sec_out32((uint32_t *)&desc_addr[i], desc_word);
206 phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
208 jr->info[head].desc_phys_addr = desc_phys_addr;
209 jr->info[head].callback = (void *)callback;
210 jr->info[head].arg = arg;
211 jr->info[head].op_done = 0;
213 unsigned long start = (unsigned long)&jr->info[head] &
214 ~(ARCH_DMA_MINALIGN - 1);
215 unsigned long end = ALIGN((unsigned long)&jr->info[head] +
216 sizeof(struct jr_info), ARCH_DMA_MINALIGN);
217 flush_dcache_range(start, end);
219 #ifdef CONFIG_PHYS_64BIT
220 /* Write the 64 bit Descriptor address on Input Ring.
221 * The 32 bit hign and low part of the address will
222 * depend on endianness of SEC block.
224 #ifdef CONFIG_SYS_FSL_SEC_LE
225 addr_lo = (uint32_t *)(&jr->input_ring[head]);
226 addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
227 #elif defined(CONFIG_SYS_FSL_SEC_BE)
228 addr_hi = (uint32_t *)(&jr->input_ring[head]);
229 addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
230 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
232 sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
233 sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
236 /* Write the 32 bit Descriptor address on Input Ring. */
237 sec_out32(&jr->input_ring[head], desc_phys_addr);
238 #endif /* ifdef CONFIG_PHYS_64BIT */
240 start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
241 end = ALIGN((unsigned long)&jr->input_ring[head] +
242 sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
243 flush_dcache_range(start, end);
245 jr->head = (head + 1) & (jr->size - 1);
247 /* Invalidate output ring */
248 start = (unsigned long)jr->output_ring &
249 ~(ARCH_DMA_MINALIGN - 1);
250 end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
252 invalidate_dcache_range(start, end);
254 sec_out32(®s->irja, 1);
259 static int jr_dequeue(int sec_idx)
261 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
262 struct jobring *jr = &jr0[sec_idx];
266 void (*callback)(uint32_t status, void *arg);
268 #ifdef CONFIG_PHYS_64BIT
269 uint32_t *addr_hi, *addr_lo;
274 while (sec_in32(®s->orsf) && CIRC_CNT(jr->head, jr->tail,
280 #ifdef CONFIG_PHYS_64BIT
281 /* Read the 64 bit Descriptor address from Output Ring.
282 * The 32 bit hign and low part of the address will
283 * depend on endianness of SEC block.
285 #ifdef CONFIG_SYS_FSL_SEC_LE
286 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
287 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
288 #elif defined(CONFIG_SYS_FSL_SEC_BE)
289 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
290 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
291 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
293 op_desc = ((u64)sec_in32(addr_hi) << 32) |
294 ((u64)sec_in32(addr_lo));
297 /* Read the 32 bit Descriptor address from Output Ring. */
298 addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
299 op_desc = sec_in32(addr);
300 #endif /* ifdef CONFIG_PHYS_64BIT */
302 uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
304 for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
305 idx = (tail + i) & (jr->size - 1);
306 if (op_desc == jr->info[idx].desc_phys_addr) {
312 /* Error condition if match not found */
316 jr->info[idx].op_done = 1;
317 callback = (void *)jr->info[idx].callback;
318 arg = jr->info[idx].arg;
320 /* When the job on tail idx gets done, increment
321 * tail till the point where job completed out of oredr has
322 * been taken into account
326 tail = (tail + 1) & (jr->size - 1);
327 } while (jr->info[tail].op_done);
330 jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
332 sec_out32(®s->orjr, 1);
333 jr->info[idx].op_done = 0;
335 callback(status, arg);
341 static void desc_done(uint32_t status, void *arg)
343 struct result *x = arg;
345 caam_jr_strstatus(status);
349 static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
351 unsigned long long timeval = get_ticks();
352 unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
356 memset(&op, 0, sizeof(op));
358 ret = jr_enqueue(desc, desc_done, &op, sec_idx);
360 debug("Error in SEC enq\n");
365 timeval = get_ticks();
366 timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
367 while (op.done != 1) {
368 ret = jr_dequeue(sec_idx);
370 debug("Error in SEC deq\n");
375 if ((get_ticks() - timeval) > timeout) {
376 debug("SEC Dequeue timed out\n");
383 debug("Error %x\n", op.status);
390 int run_descriptor_jr(uint32_t *desc)
392 return run_descriptor_jr_idx(desc, 0);
395 static inline int jr_reset_sec(uint8_t sec_idx)
397 if (jr_hw_reset(sec_idx) < 0)
400 /* Clean up the jobring structure maintained by software */
401 jr_sw_cleanup(sec_idx);
408 return jr_reset_sec(0);
411 static inline int sec_reset_idx(uint8_t sec_idx)
413 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
414 uint32_t mcfgr = sec_in32(&sec->mcfgr);
415 uint32_t timeout = 100000;
417 mcfgr |= MCFGR_SWRST;
418 sec_out32(&sec->mcfgr, mcfgr);
420 mcfgr |= MCFGR_DMA_RST;
421 sec_out32(&sec->mcfgr, mcfgr);
423 mcfgr = sec_in32(&sec->mcfgr);
424 } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
431 mcfgr = sec_in32(&sec->mcfgr);
432 } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
440 static int instantiate_rng(uint8_t sec_idx)
446 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
447 struct rng4tst __iomem *rng =
448 (struct rng4tst __iomem *)&sec->rng;
450 memset(&op, 0, sizeof(struct result));
452 desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
454 printf("cannot allocate RNG init descriptor memory\n");
458 inline_cnstr_jobdesc_rng_instantiation(desc);
459 int size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
460 flush_dcache_range((unsigned long)desc,
461 (unsigned long)desc + size);
463 ret = run_descriptor_jr_idx(desc, sec_idx);
466 printf("RNG: Instantiation failed with error %x\n", ret);
468 rdsta_val = sec_in32(&rng->rdsta);
469 if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED))
477 return sec_reset_idx(0);
480 static u8 get_rng_vid(uint8_t sec_idx)
482 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
483 u32 cha_vid = sec_in32(&sec->chavid_ls);
485 return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
489 * By default, the TRNG runs for 200 clocks per sample;
490 * 1200 clocks per sample generates better entropy.
492 static void kick_trng(int ent_delay, uint8_t sec_idx)
494 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
495 struct rng4tst __iomem *rng =
496 (struct rng4tst __iomem *)&sec->rng;
499 /* put RNG4 into program mode */
500 sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
501 /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
502 * length (in system clocks) of each Entropy sample taken
504 val = sec_in32(&rng->rtsdctl);
505 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
506 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
507 sec_out32(&rng->rtsdctl, val);
508 /* min. freq. count, equal to 1/4 of the entropy sample length */
509 sec_out32(&rng->rtfreqmin, ent_delay >> 2);
510 /* disable maximum frequency count */
511 sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
513 * select raw sampling in both entropy shifter
514 * and statistical checker
516 sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
517 /* put RNG4 into run mode */
518 sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
521 static int rng_init(uint8_t sec_idx)
523 int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
524 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
525 struct rng4tst __iomem *rng =
526 (struct rng4tst __iomem *)&sec->rng;
528 u32 rdsta = sec_in32(&rng->rdsta);
530 /* Check if RNG state 0 handler is already instantiated */
531 if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED)
536 * If either of the SH's were instantiated by somebody else
537 * then it is assumed that the entropy
538 * parameters are properly set and thus the function
539 * setting these (kick_trng(...)) is skipped.
540 * Also, if a handle was instantiated, do not change
541 * the TRNG parameters.
543 kick_trng(ent_delay, sec_idx);
546 * if instantiate_rng(...) fails, the loop will rerun
547 * and the kick_trng(...) function will modfiy the
548 * upper and lower limits of the entropy sampling
549 * interval, leading to a sucessful initialization of
552 ret = instantiate_rng(sec_idx);
553 } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
555 printf("RNG: Failed to instantiate RNG\n");
559 /* Enable RDB bit so that RNG works faster */
560 sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
565 int sec_init_idx(uint8_t sec_idx)
567 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
568 uint32_t mcr = sec_in32(&sec->mcfgr);
571 #ifdef CONFIG_FSL_CORENET
577 if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
578 printf("SEC initialization failed\n");
583 * Modifying CAAM Read/Write Attributes
585 * For AXI Write - Cacheable, Write Back, Write allocate
586 * For AXI Read - Cacheable, Read allocate
587 * Only For LS2080a, to solve CAAM coherency issues
589 #ifdef CONFIG_LS2080A
590 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
591 mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
593 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
596 #ifdef CONFIG_PHYS_64BIT
597 mcr |= (1 << MCFGR_PS_SHIFT);
599 sec_out32(&sec->mcfgr, mcr);
601 #ifdef CONFIG_FSL_CORENET
602 #ifdef CONFIG_SPL_BUILD
604 * For SPL Build, Set the Liodns in SEC JR0 for
605 * creating PAMU entries corresponding to these.
606 * For normal build, these are set in set_liodns().
608 liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
609 liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
611 liodnr = sec_in32(&sec->jrliodnr[0].ls) &
612 ~(JRNSLIODN_MASK | JRSLIODN_MASK);
614 (liodn_ns << JRNSLIODN_SHIFT) |
615 (liodn_s << JRSLIODN_SHIFT);
616 sec_out32(&sec->jrliodnr[0].ls, liodnr);
618 liodnr = sec_in32(&sec->jrliodnr[0].ls);
619 liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
620 liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
624 ret = jr_init(sec_idx);
626 printf("SEC initialization failed\n");
630 #ifdef CONFIG_FSL_CORENET
631 ret = sec_config_pamu_table(liodn_ns, liodn_s);
638 if (get_rng_vid(sec_idx) >= 4) {
639 if (rng_init(sec_idx) < 0) {
640 printf("SEC%u: RNG instantiation failed\n", sec_idx);
643 printf("SEC%u: RNG instantiated\n", sec_idx);
651 return sec_init_idx(0);