2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
14 /* Timeout currently defined as 90 sec */
15 #define CONFIG_SEC_DEQ_TIMEOUT 90000000U
17 #define DEFAULT_JR_ID 0
18 #define DEFAULT_JR_LIODN 0
19 #define DEFAULT_IRQ 0 /* Interrupts not to be configured */
21 #define MCFGR_SWRST ((uint32_t)(1)<<31) /* Software Reset */
22 #define MCFGR_DMA_RST ((uint32_t)(1)<<28) /* DMA Reset */
23 #define MCFGR_PS_SHIFT 16
24 #define MCFGR_AWCACHE_SHIFT 8
25 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
26 #define JR_INTMASK 0x00000001
27 #define JRCR_RESET 0x01
28 #define JRINT_ERR_HALT_INPROGRESS 0x4
29 #define JRINT_ERR_HALT_MASK 0xc
30 #define JRNSLIODN_SHIFT 16
31 #define JRNSLIODN_MASK 0x0fff0000
32 #define JRSLIODN_SHIFT 0
33 #define JRSLIODN_MASK 0x00000fff
36 #define JQ_DEQ_TO_ERR -2
45 void (*callback)(uint32_t status, void *arg);
46 phys_addr_t desc_phys_addr;
56 /* Head is the index where software would enq the descriptor in
60 /* Tail index would be used by s/w ehile enqueuing to determine if
61 * there is any space left in the s/w maintained i/p rings
63 /* Also in case of deq tail will be incremented only in case of
64 * in-order job completion
67 /* Read index of the output ring. It may not match with tail in case
68 * of out of order completetion
71 /* Write index to input ring. Would be always equal to head */
73 /* Size of the rings. */
75 /* The ip and output rings have to be accessed by SEC. So the
76 * pointers will ahve to point to the housekeeping region provided
79 /*Circular Ring of i/p descriptors */
80 dma_addr_t *input_ring;
81 /* Circular Ring of o/p descriptors */
82 /* Circula Ring containing info regarding descriptors in i/p
85 /* This ring can be on the stack */
86 struct jr_info info[JR_SIZE];
87 struct op_ring *output_ring;
95 void caam_jr_strstatus(u32 status);
96 int run_descriptor_jr(uint32_t *desc);