git.sur5r.net Git - u-boot/blob - drivers/ddr/altera/sdram.c

   1 /*
   2  * Copyright Altera Corporation (C) 2014-2015
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <errno.h>
   8 #include <div64.h>
   9 #include <watchdog.h>
  10 #include <asm/arch/fpga_manager.h>
  11 #include <asm/arch/sdram.h>
  12 #include <asm/arch/system_manager.h>
  13 #include <asm/io.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 struct sdram_prot_rule {
  18         u32     sdram_start;    /* SDRAM start address */
  19         u32     sdram_end;      /* SDRAM end address */
  20         u32     rule;           /* SDRAM protection rule number: 0-19 */
  21         int     valid;          /* Rule valid or not? 1 - valid, 0 not*/
  22
  23         u32     security;
  24         u32     portmask;
  25         u32     result;
  26         u32     lo_prot_id;
  27         u32     hi_prot_id;
  28 };
  29
  30 static struct socfpga_system_manager *sysmgr_regs =
  31         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  32 static struct socfpga_sdr_ctrl *sdr_ctrl =
  33         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  34
  35 /**
  36  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
  37  * @cfg:        SDRAM controller configuration data
  38  *
  39  * SDRAM Failure happens when accessing non-existent memory. Artificially
  40  * increase the number of rows so that the memory controller thinks it has
  41  * 4GB of RAM. This function returns such amount of rows.
  42  */
  43 static int get_errata_rows(const struct socfpga_sdram_config *cfg)
  44 {
  45         /* Define constant for 4G memory - used for SDRAM errata workaround */
  46 #define MEMSIZE_4G      (4ULL * 1024ULL * 1024ULL * 1024ULL)
  47         const unsigned long long memsize = MEMSIZE_4G;
  48         const unsigned int cs =
  49                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
  50                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
  51         const unsigned int rows =
  52                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
  53                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
  54         const unsigned int banks =
  55                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
  56                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
  57         const unsigned int cols =
  58                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
  59                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
  60         const unsigned int width = 8;
  61
  62         unsigned long long newrows;
  63         int bits, inewrowslog2;
  64
  65         debug("workaround rows - memsize %lld\n", memsize);
  66         debug("workaround rows - cs        %d\n", cs);
  67         debug("workaround rows - width     %d\n", width);
  68         debug("workaround rows - rows      %d\n", rows);
  69         debug("workaround rows - banks     %d\n", banks);
  70         debug("workaround rows - cols      %d\n", cols);
  71
  72         newrows = lldiv(memsize, cs * (width / 8));
  73         debug("rows workaround - term1 %lld\n", newrows);
  74
  75         newrows = lldiv(newrows, (1 << banks) * (1 << cols));
  76         debug("rows workaround - term2 %lld\n", newrows);
  77
  78         /*
  79          * Compute the hamming weight - same as number of bits set.
  80          * Need to see if result is ordinal power of 2 before
  81          * attempting log2 of result.
  82          */
  83         bits = generic_hweight32(newrows);
  84
  85         debug("rows workaround - bits %d\n", bits);
  86
  87         if (bits != 1) {
  88                 printf("SDRAM workaround failed, bits set %d\n", bits);
  89                 return rows;
  90         }
  91
  92         if (newrows > UINT_MAX) {
  93                 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
  94                 return rows;
  95         }
  96
  97         inewrowslog2 = __ilog2(newrows);
  98
  99         debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
 100
 101         if (inewrowslog2 == -1) {
 102                 printf("SDRAM workaround failed, newrows %lld\n", newrows);
 103                 return rows;
 104         }
 105
 106         return inewrowslog2;
 107 }
 108
 109 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
 110 static void sdram_set_rule(struct sdram_prot_rule *prule)
 111 {
 112         u32 lo_addr_bits;
 113         u32 hi_addr_bits;
 114         int ruleno = prule->rule;
 115
 116         /* Select the rule */
 117         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 118
 119         /* Obtain the address bits */
 120         lo_addr_bits = prule->sdram_start >> 20ULL;
 121         hi_addr_bits = prule->sdram_end >> 20ULL;
 122
 123         debug("sdram set rule start %x, %d\n", lo_addr_bits,
 124               prule->sdram_start);
 125         debug("sdram set rule end   %x, %d\n", hi_addr_bits,
 126               prule->sdram_end);
 127
 128         /* Set rule addresses */
 129         writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
 130
 131         /* Set rule protection ids */
 132         writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
 133                &sdr_ctrl->prot_rule_id);
 134
 135         /* Set the rule data */
 136         writel(prule->security | (prule->valid << 2) |
 137                (prule->portmask << 3) | (prule->result << 13),
 138                &sdr_ctrl->prot_rule_data);
 139
 140         /* write the rule */
 141         writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
 142
 143         /* Set rule number to 0 by default */
 144         writel(0, &sdr_ctrl->prot_rule_rdwr);
 145 }
 146
 147 static void sdram_get_rule(struct sdram_prot_rule *prule)
 148 {
 149         u32 addr;
 150         u32 id;
 151         u32 data;
 152         int ruleno = prule->rule;
 153
 154         /* Read the rule */
 155         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 156         writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
 157
 158         /* Get the addresses */
 159         addr = readl(&sdr_ctrl->prot_rule_addr);
 160         prule->sdram_start = (addr & 0xFFF) << 20;
 161         prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
 162
 163         /* Get the configured protection IDs */
 164         id = readl(&sdr_ctrl->prot_rule_id);
 165         prule->lo_prot_id = id & 0xFFF;
 166         prule->hi_prot_id = (id >> 12) & 0xFFF;
 167
 168         /* Get protection data */
 169         data = readl(&sdr_ctrl->prot_rule_data);
 170
 171         prule->security = data & 0x3;
 172         prule->valid = (data >> 2) & 0x1;
 173         prule->portmask = (data >> 3) & 0x3FF;
 174         prule->result = (data >> 13) & 0x1;
 175 }
 176
 177 static void
 178 sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
 179 {
 180         struct sdram_prot_rule rule;
 181         int rules;
 182
 183         /* Start with accepting all SDRAM transaction */
 184         writel(0x0, &sdr_ctrl->protport_default);
 185
 186         /* Clear all protection rules for warm boot case */
 187         memset(&rule, 0, sizeof(rule));
 188
 189         for (rules = 0; rules < 20; rules++) {
 190                 rule.rule = rules;
 191                 sdram_set_rule(&rule);
 192         }
 193
 194         /* new rule: accept SDRAM */
 195         rule.sdram_start = sdram_start;
 196         rule.sdram_end = sdram_end;
 197         rule.lo_prot_id = 0x0;
 198         rule.hi_prot_id = 0xFFF;
 199         rule.portmask = 0x3FF;
 200         rule.security = 0x3;
 201         rule.result = 0;
 202         rule.valid = 1;
 203         rule.rule = 0;
 204
 205         /* set new rule */
 206         sdram_set_rule(&rule);
 207
 208         /* default rule: reject everything */
 209         writel(0x3ff, &sdr_ctrl->protport_default);
 210 }
 211
 212 static void sdram_dump_protection_config(void)
 213 {
 214         struct sdram_prot_rule rule;
 215         int rules;
 216
 217         debug("SDRAM Prot rule, default %x\n",
 218               readl(&sdr_ctrl->protport_default));
 219
 220         for (rules = 0; rules < 20; rules++) {
 221                 sdram_get_rule(&rule);
 222                 debug("Rule %d, rules ...\n", rules);
 223                 debug("    sdram start %x\n", rule.sdram_start);
 224                 debug("    sdram end   %x\n", rule.sdram_end);
 225                 debug("    low prot id %d, hi prot id %d\n",
 226                       rule.lo_prot_id,
 227                       rule.hi_prot_id);
 228                 debug("    portmask %x\n", rule.portmask);
 229                 debug("    security %d\n", rule.security);
 230                 debug("    result %d\n", rule.result);
 231                 debug("    valid %d\n", rule.valid);
 232         }
 233 }
 234
 235 /**
 236  * sdram_write_verify() - write to register and verify the write.
 237  * @addr:       Register address
 238  * @val:        Value to be written and verified
 239  *
 240  * This function writes to a register, reads back the value and compares
 241  * the result with the written value to check if the data match.
 242  */
 243 static unsigned sdram_write_verify(const u32 *addr, const u32 val)
 244 {
 245         u32 rval;
 246
 247         debug("   Write - Address 0x%p Data 0x%08x\n", addr, val);
 248         writel(val, addr);
 249
 250         debug("   Read and verify...");
 251         rval = readl(addr);
 252         if (rval != val) {
 253                 debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
 254                       addr, val, rval);
 255                 return -EINVAL;
 256         }
 257
 258         debug("correct!\n");
 259         return 0;
 260 }
 261
 262 /**
 263  * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
 264  * @cfg:        SDRAM controller configuration data
 265  *
 266  * Return the value of DRAM CTRLCFG register.
 267  */
 268 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
 269 {
 270         const u32 csbits =
 271                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 272                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 273         u32 addrorder =
 274                 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
 275                         SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 276
 277         u32 ctrl_cfg = cfg->ctrl_cfg;
 278
 279         /*
 280          * SDRAM Failure When Accessing Non-Existent Memory
 281          * Set the addrorder field of the SDRAM control register
 282          * based on the CSBITs setting.
 283          */
 284         if (csbits == 1) {
 285                 if (addrorder != 0)
 286                         debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
 287                 addrorder = 0;
 288         } else if (csbits == 2) {
 289                 if (addrorder != 2)
 290                         debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
 291                 addrorder = 2;
 292         }
 293
 294         ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
 295         ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 296
 297         return ctrl_cfg;
 298 }
 299
 300 /**
 301  * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
 302  * @cfg:        SDRAM controller configuration data
 303  *
 304  * Return the value of DRAM ADDRW register.
 305  */
 306 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
 307 {
 308         /*
 309          * SDRAM Failure When Accessing Non-Existent Memory
 310          * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
 311          * log2(number of chip select bits). Since there's only
 312          * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
 313          * which is the same as "chip selects" - 1.
 314          */
 315         const int rows = get_errata_rows(cfg);
 316         u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
 317
 318         return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
 319 }
 320
 321 /**
 322  * sdr_load_regs() - Load SDRAM controller registers
 323  * @cfg:        SDRAM controller configuration data
 324  *
 325  * This function loads the register values into the SDRAM controller block.
 326  */
 327 static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
 328 {
 329         const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
 330         const u32 dram_addrw = sdr_get_addr_rw(cfg);
 331
 332         debug("\nConfiguring CTRLCFG\n");
 333         writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
 334
 335         debug("Configuring DRAMTIMING1\n");
 336         writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
 337
 338         debug("Configuring DRAMTIMING2\n");
 339         writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
 340
 341         debug("Configuring DRAMTIMING3\n");
 342         writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
 343
 344         debug("Configuring DRAMTIMING4\n");
 345         writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
 346
 347         debug("Configuring LOWPWRTIMING\n");
 348         writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
 349
 350         debug("Configuring DRAMADDRW\n");
 351         writel(dram_addrw, &sdr_ctrl->dram_addrw);
 352
 353         debug("Configuring DRAMIFWIDTH\n");
 354         writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
 355
 356         debug("Configuring DRAMDEVWIDTH\n");
 357         writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
 358
 359         debug("Configuring LOWPWREQ\n");
 360         writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
 361
 362         debug("Configuring DRAMINTR\n");
 363         writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
 364
 365         debug("Configuring STATICCFG\n");
 366         writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
 367
 368         debug("Configuring CTRLWIDTH\n");
 369         writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
 370
 371         debug("Configuring PORTCFG\n");
 372         writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
 373
 374         debug("Configuring FIFOCFG\n");
 375         writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
 376
 377         debug("Configuring MPPRIORITY\n");
 378         writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
 379
 380         debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
 381         writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
 382         writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
 383         writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
 384         writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
 385
 386         debug("Configuring MPPACING_MPPACING_0\n");
 387         writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
 388         writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
 389         writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
 390         writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
 391
 392         debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
 393         writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
 394         writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
 395         writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
 396
 397         debug("Configuring PHYCTRL_PHYCTRL_0\n");
 398         writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
 399
 400         debug("Configuring CPORTWIDTH\n");
 401         writel(cfg->cport_width, &sdr_ctrl->cport_width);
 402
 403         debug("Configuring CPORTWMAP\n");
 404         writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
 405
 406         debug("Configuring CPORTRMAP\n");
 407         writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
 408
 409         debug("Configuring RFIFOCMAP\n");
 410         writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
 411
 412         debug("Configuring WFIFOCMAP\n");
 413         writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
 414
 415         debug("Configuring CPORTRDWR\n");
 416         writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
 417
 418         debug("Configuring DRAMODT\n");
 419         writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
 420 }
 421
 422 /**
 423  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 424  * @sdr_phy_reg:        Value of the PHY control register 0
 425  *
 426  * Initialize the SDRAM MMR.
 427  */
 428 int sdram_mmr_init_full(unsigned int sdr_phy_reg)
 429 {
 430         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 431         const unsigned int rows =
 432                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 433                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 434         int ret;
 435
 436         writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
 437
 438         sdr_load_regs(cfg);
 439
 440         /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 441         writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
 442
 443         /* only enable if the FPGA is programmed */
 444         if (fpgamgr_test_fpga_ready()) {
 445                 ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
 446                                          cfg->fpgaport_rst);
 447                 if (ret)
 448                         return ret;
 449         }
 450
 451         /* Restore the SDR PHY Register if valid */
 452         if (sdr_phy_reg != 0xffffffff)
 453                 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
 454
 455         /* Final step - apply configuration changes */
 456         debug("Configuring STATICCFG\n");
 457         clrsetbits_le32(&sdr_ctrl->static_cfg,
 458                         SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 459                         1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 460
 461         sdram_set_protection_config(0, sdram_calculate_size() - 1);
 462
 463         sdram_dump_protection_config();
 464
 465         return 0;
 466 }
 467
 468 /**
 469  * sdram_calculate_size() - Calculate SDRAM size
 470  *
 471  * Calculate SDRAM device size based on SDRAM controller parameters.
 472  * Size is specified in bytes.
 473  */
 474 unsigned long sdram_calculate_size(void)
 475 {
 476         unsigned long temp;
 477         unsigned long row, bank, col, cs, width;
 478         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 479         const unsigned int csbits =
 480                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 481                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 482         const unsigned int rowbits =
 483                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 484                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 485
 486         temp = readl(&sdr_ctrl->dram_addrw);
 487         col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 488                 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 489
 490         /*
 491          * SDRAM Failure When Accessing Non-Existent Memory
 492          * Use ROWBITS from Quartus/QSys to calculate SDRAM size
 493          * since the FB specifies we modify ROWBITs to work around SDRAM
 494          * controller issue.
 495          */
 496         row = readl(&sysmgr_regs->iswgrp_handoff[4]);
 497         if (row == 0)
 498                 row = rowbits;
 499         /*
 500          * If the stored handoff value for rows is greater than
 501          * the field width in the sdr.dramaddrw register then
 502          * something is very wrong. Revert to using the the #define
 503          * value handed off by the SOCEDS tool chain instead of
 504          * using a broken value.
 505          */
 506         if (row > 31)
 507                 row = rowbits;
 508
 509         bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 510                 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 511
 512         /*
 513          * SDRAM Failure When Accessing Non-Existent Memory
 514          * Use CSBITs from Quartus/QSys to calculate SDRAM size
 515          * since the FB specifies we modify CSBITs to work around SDRAM
 516          * controller issue.
 517          */
 518         cs = csbits;
 519
 520         width = readl(&sdr_ctrl->dram_if_width);
 521
 522         /* ECC would not be calculated as its not addressible */
 523         if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
 524                 width = 32;
 525         if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
 526                 width = 16;
 527
 528         /* calculate the SDRAM size base on this info */
 529         temp = 1 << (row + bank + col);
 530         temp = temp * cs * (width  / 8);
 531
 532         debug("%s returns %ld\n", __func__, temp);
 533
 534         return temp;
 535 }