2 * Copyright Altera Corporation (C) 2014-2015
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/fpga_manager.h>
10 #include <asm/arch/sdram.h>
11 #include <asm/arch/system_manager.h>
15 * FIXME: This path is temporary until the SDRAM driver gets
16 * a proper thorough cleanup.
18 #include "../../../board/altera/socfpga/qts/sdram_config.h"
20 DECLARE_GLOBAL_DATA_PTR;
22 struct sdram_prot_rule {
23 u64 sdram_start; /* SDRAM start address */
24 u64 sdram_end; /* SDRAM end address */
25 u32 rule; /* SDRAM protection rule number: 0-19 */
26 int valid; /* Rule valid or not? 1 - valid, 0 not*/
35 static struct socfpga_system_manager *sysmgr_regs =
36 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
37 static struct socfpga_sdr_ctrl *sdr_ctrl =
38 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
41 * get_errata_rows() - Up the number of DRAM rows to cover entire address space
43 * SDRAM Failure happens when accessing non-existent memory. Artificially
44 * increase the number of rows so that the memory controller thinks it has
45 * 4GB of RAM. This function returns such amount of rows.
47 static int get_errata_rows(void)
49 /* Define constant for 4G memory - used for SDRAM errata workaround */
50 #define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
51 const unsigned long long memsize = MEMSIZE_4G;
52 const unsigned int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
53 const unsigned int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
54 const unsigned int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS;
55 const unsigned int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS;
56 const unsigned int width = 8;
58 unsigned long long newrows;
59 int bits, inewrowslog2;
61 debug("workaround rows - memsize %lld\n", memsize);
62 debug("workaround rows - cs %d\n", cs);
63 debug("workaround rows - width %d\n", width);
64 debug("workaround rows - rows %d\n", rows);
65 debug("workaround rows - banks %d\n", banks);
66 debug("workaround rows - cols %d\n", cols);
68 newrows = lldiv(memsize, cs * (width / 8));
69 debug("rows workaround - term1 %lld\n", newrows);
71 newrows = lldiv(newrows, (1 << banks) * (1 << cols));
72 debug("rows workaround - term2 %lld\n", newrows);
75 * Compute the hamming weight - same as number of bits set.
76 * Need to see if result is ordinal power of 2 before
77 * attempting log2 of result.
79 bits = generic_hweight32(newrows);
81 debug("rows workaround - bits %d\n", bits);
84 printf("SDRAM workaround failed, bits set %d\n", bits);
88 if (newrows > UINT_MAX) {
89 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
93 inewrowslog2 = __ilog2(newrows);
95 debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
97 if (inewrowslog2 == -1) {
98 printf("SDRAM workaround failed, newrows %lld\n", newrows);
105 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
106 static void sdram_set_rule(struct sdram_prot_rule *prule)
108 uint32_t lo_addr_bits;
109 uint32_t hi_addr_bits;
110 int ruleno = prule->rule;
112 /* Select the rule */
113 writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
115 /* Obtain the address bits */
116 lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF);
117 hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF);
119 debug("sdram set rule start %x, %lld\n", lo_addr_bits,
121 debug("sdram set rule end %x, %lld\n", hi_addr_bits,
124 /* Set rule addresses */
125 writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
127 /* Set rule protection ids */
128 writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
129 &sdr_ctrl->prot_rule_id);
131 /* Set the rule data */
132 writel(prule->security | (prule->valid << 2) |
133 (prule->portmask << 3) | (prule->result << 13),
134 &sdr_ctrl->prot_rule_data);
137 writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr);
139 /* Set rule number to 0 by default */
140 writel(0, &sdr_ctrl->prot_rule_rdwr);
143 static void sdram_get_rule(struct sdram_prot_rule *prule)
148 int ruleno = prule->rule;
151 writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
152 writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr);
154 /* Get the addresses */
155 addr = readl(&sdr_ctrl->prot_rule_addr);
156 prule->sdram_start = (addr & 0xFFF) << 20;
157 prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
159 /* Get the configured protection IDs */
160 id = readl(&sdr_ctrl->prot_rule_id);
161 prule->lo_prot_id = id & 0xFFF;
162 prule->hi_prot_id = (id >> 12) & 0xFFF;
164 /* Get protection data */
165 data = readl(&sdr_ctrl->prot_rule_data);
167 prule->security = data & 0x3;
168 prule->valid = (data >> 2) & 0x1;
169 prule->portmask = (data >> 3) & 0x3FF;
170 prule->result = (data >> 13) & 0x1;
173 static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end)
175 struct sdram_prot_rule rule;
178 /* Start with accepting all SDRAM transaction */
179 writel(0x0, &sdr_ctrl->protport_default);
181 /* Clear all protection rules for warm boot case */
182 memset(&rule, 0, sizeof(struct sdram_prot_rule));
184 for (rules = 0; rules < 20; rules++) {
186 sdram_set_rule(&rule);
189 /* new rule: accept SDRAM */
190 rule.sdram_start = sdram_start;
191 rule.sdram_end = sdram_end;
192 rule.lo_prot_id = 0x0;
193 rule.hi_prot_id = 0xFFF;
194 rule.portmask = 0x3FF;
201 sdram_set_rule(&rule);
203 /* default rule: reject everything */
204 writel(0x3ff, &sdr_ctrl->protport_default);
207 static void sdram_dump_protection_config(void)
209 struct sdram_prot_rule rule;
212 debug("SDRAM Prot rule, default %x\n",
213 readl(&sdr_ctrl->protport_default));
215 for (rules = 0; rules < 20; rules++) {
216 sdram_get_rule(&rule);
217 debug("Rule %d, rules ...\n", rules);
218 debug(" sdram start %llx\n", rule.sdram_start);
219 debug(" sdram end %llx\n", rule.sdram_end);
220 debug(" low prot id %d, hi prot id %d\n",
223 debug(" portmask %x\n", rule.portmask);
224 debug(" security %d\n", rule.security);
225 debug(" result %d\n", rule.result);
226 debug(" valid %d\n", rule.valid);
230 /* Function to write to register and verify the write */
231 static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
233 #ifndef SDRAM_MMR_SKIP_VERIFY
236 debug(" Write - Address ");
237 debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value);
238 /* Write to register */
239 writel(reg_value, addr);
240 #ifndef SDRAM_MMR_SKIP_VERIFY
241 debug(" Read and verify...");
242 /* Read back the wrote value */
243 reg_value1 = readl(addr);
244 /* Indicate failure if value not matched */
245 if (reg_value1 != reg_value) {
246 debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n",
247 (u32)addr, reg_value, reg_value1);
251 #endif /* SDRAM_MMR_SKIP_VERIFY */
255 static void set_sdr_ctrlcfg(void)
259 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
260 SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
261 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
262 SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
263 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
264 SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
265 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
266 SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
267 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
268 SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
269 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
270 SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
271 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
272 SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
273 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
274 SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB);
276 debug("\nConfiguring CTRLCFG\n");
279 * SDRAM Failure When Accessing Non-Existent Memory
280 * Set the addrorder field of the SDRAM control register
281 * based on the CSBITs setting.
283 switch (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) {
285 addrorder = 0; /* chip, row, bank, column */
286 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0)
287 debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
290 addrorder = 2; /* row, chip, bank, column */
291 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2)
292 debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
295 addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER;
299 ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
301 writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
304 static void set_sdr_dram_timing(void)
306 const u32 dram_timing1 =
307 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
308 SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
309 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
310 SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
311 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
312 SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
313 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
314 SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
315 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
316 SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
317 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
318 SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB);
320 const u32 dram_timing2 =
321 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
322 SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
323 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
324 SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
325 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
326 SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
327 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
328 SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
329 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
330 SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB);
332 const u32 dram_timing3 =
333 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
334 SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
335 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
336 SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
337 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
338 SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
339 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
340 SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
341 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
342 SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB);
344 const u32 dram_timing4 =
345 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
346 SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
347 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
348 SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB);
350 const u32 lowpwr_timing =
351 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
352 SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
353 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
354 SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB);
356 debug("Configuring DRAMTIMING1\n");
357 writel(dram_timing1, &sdr_ctrl->dram_timing1);
359 debug("Configuring DRAMTIMING2\n");
360 writel(dram_timing2, &sdr_ctrl->dram_timing2);
362 debug("Configuring DRAMTIMING3\n");
363 writel(dram_timing3, &sdr_ctrl->dram_timing3);
365 debug("Configuring DRAMTIMING4\n");
366 writel(dram_timing4, &sdr_ctrl->dram_timing4);
368 debug("Configuring LOWPWRTIMING\n");
369 writel(lowpwr_timing, &sdr_ctrl->lowpwr_timing);
372 static void set_sdr_addr_rw(void)
375 * SDRAM Failure When Accessing Non-Existent Memory
376 * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
377 * log2(number of chip select bits). Since there's only
378 * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
379 * which is the same as "chip selects" - 1.
381 const int rows = get_errata_rows();
382 const u32 dram_addrw =
383 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
384 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
385 (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
386 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
387 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
388 ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
389 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB);
390 debug("Configuring DRAMADDRW\n");
391 writel(dram_addrw, &sdr_ctrl->dram_addrw);
394 static void set_sdr_static_cfg(void)
396 const u32 static_cfg =
397 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
398 SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
399 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
400 SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB);
402 debug("Configuring STATICCFG\n");
403 writel(static_cfg, &sdr_ctrl->static_cfg);
406 static void set_sdr_fifo_cfg(void)
409 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
410 SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
411 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
412 SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB);
414 debug("Configuring FIFOCFG\n");
415 writel(fifo_cfg, &sdr_ctrl->fifo_cfg);
418 static void set_sdr_mp_weight(void)
420 const u32 mp_weight0 =
421 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
422 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB);
423 const u32 mp_weight1 =
424 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
425 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
426 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
427 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB);
428 const u32 mp_weight2 =
429 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
430 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB);
431 const u32 mp_weight3 =
432 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
433 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB);
435 debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
436 writel(mp_weight0, &sdr_ctrl->mp_weight0);
437 writel(mp_weight1, &sdr_ctrl->mp_weight1);
438 writel(mp_weight2, &sdr_ctrl->mp_weight2);
439 writel(mp_weight3, &sdr_ctrl->mp_weight3);
442 static void set_sdr_mp_pacing(void)
444 const u32 mp_pacing0 =
445 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
446 SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB);
447 const u32 mp_pacing1 =
448 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
449 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
450 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
451 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB);
452 const u32 mp_pacing2 =
453 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
454 SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB);
455 const u32 mp_pacing3 =
456 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
457 SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB);
459 debug("Configuring MPPACING_MPPACING_0\n");
460 writel(mp_pacing0, &sdr_ctrl->mp_pacing0);
461 writel(mp_pacing1, &sdr_ctrl->mp_pacing1);
462 writel(mp_pacing2, &sdr_ctrl->mp_pacing2);
463 writel(mp_pacing3, &sdr_ctrl->mp_pacing3);
466 static void set_sdr_mp_threshold(void)
468 debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
469 clrsetbits_le32(&sdr_ctrl->mp_threshold0,
470 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK,
471 CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
472 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB);
474 clrsetbits_le32(&sdr_ctrl->mp_threshold1,
475 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK,
476 CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
477 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB);
479 clrsetbits_le32(&sdr_ctrl->mp_threshold2,
480 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK,
481 CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
482 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB);
486 /* Function to initialize SDRAM MMR */
487 unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
489 unsigned long reg_value;
490 unsigned long status = 0;
492 #if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) && \
493 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) && \
494 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) && \
495 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) && \
496 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS)
498 writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS,
499 &sysmgr_regs->iswgrp_handoff[4]);
502 set_sdr_dram_timing();
505 debug("Configuring DRAMIFWIDTH\n");
506 clrsetbits_le32(&sdr_ctrl->dram_if_width,
507 SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK,
508 CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
509 SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB);
511 debug("Configuring DRAMDEVWIDTH\n");
512 clrsetbits_le32(&sdr_ctrl->dram_dev_width,
513 SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK,
514 CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
515 SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB);
517 debug("Configuring LOWPWREQ\n");
518 clrsetbits_le32(&sdr_ctrl->lowpwr_eq,
519 SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK,
520 CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
521 SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB);
523 debug("Configuring DRAMINTR\n");
524 clrsetbits_le32(&sdr_ctrl->dram_intr, SDR_CTRLGRP_DRAMINTR_INTREN_MASK,
525 CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
526 SDR_CTRLGRP_DRAMINTR_INTREN_LSB);
528 set_sdr_static_cfg();
530 debug("Configuring CTRLWIDTH\n");
531 clrsetbits_le32(&sdr_ctrl->ctrl_width,
532 SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK,
533 CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
534 SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB);
536 debug("Configuring PORTCFG\n");
537 clrsetbits_le32(&sdr_ctrl->port_cfg, SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK,
538 CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
539 SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB);
543 debug("Configuring MPPRIORITY\n");
544 clrsetbits_le32(&sdr_ctrl->mp_priority,
545 SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK,
546 CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
547 SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB);
551 set_sdr_mp_threshold();
553 debug("Configuring PHYCTRL_PHYCTRL_0\n");
554 setbits_le32(&sdr_ctrl->phy_ctrl0,
555 CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0);
557 debug("Configuring CPORTWIDTH\n");
558 clrsetbits_le32(&sdr_ctrl->cport_width,
559 SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK,
560 CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
561 SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB);
562 debug(" Write - Address ");
563 debug("0x%08x Data 0x%08x\n",
564 (unsigned)(&sdr_ctrl->cport_width),
565 (unsigned)reg_value);
566 reg_value = readl(&sdr_ctrl->cport_width);
567 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
569 debug("Configuring CPORTWMAP\n");
570 clrsetbits_le32(&sdr_ctrl->cport_wmap,
571 SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK,
572 CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
573 SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB);
574 debug(" Write - Address ");
575 debug("0x%08x Data 0x%08x\n",
576 (unsigned)(&sdr_ctrl->cport_wmap),
577 (unsigned)reg_value);
578 reg_value = readl(&sdr_ctrl->cport_wmap);
579 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
581 debug("Configuring CPORTRMAP\n");
582 clrsetbits_le32(&sdr_ctrl->cport_rmap,
583 SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK,
584 CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
585 SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB);
586 debug(" Write - Address ");
587 debug("0x%08x Data 0x%08x\n",
588 (unsigned)(&sdr_ctrl->cport_rmap),
589 (unsigned)reg_value);
590 reg_value = readl(&sdr_ctrl->cport_rmap);
591 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
593 debug("Configuring RFIFOCMAP\n");
594 clrsetbits_le32(&sdr_ctrl->rfifo_cmap,
595 SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK,
596 CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
597 SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB);
598 debug(" Write - Address ");
599 debug("0x%08x Data 0x%08x\n",
600 (unsigned)(&sdr_ctrl->rfifo_cmap),
601 (unsigned)reg_value);
602 reg_value = readl(&sdr_ctrl->rfifo_cmap);
603 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
605 debug("Configuring WFIFOCMAP\n");
606 reg_value = readl(&sdr_ctrl->wfifo_cmap);
607 clrsetbits_le32(&sdr_ctrl->wfifo_cmap,
608 SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK,
609 CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
610 SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB);
611 debug(" Write - Address ");
612 debug("0x%08x Data 0x%08x\n",
613 (unsigned)(&sdr_ctrl->wfifo_cmap),
614 (unsigned)reg_value);
615 reg_value = readl(&sdr_ctrl->wfifo_cmap);
616 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
618 debug("Configuring CPORTRDWR\n");
619 clrsetbits_le32(&sdr_ctrl->cport_rdwr,
620 SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK,
621 CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
622 SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB);
623 debug(" Write - Address ");
624 debug("0x%08x Data 0x%08x\n",
625 (unsigned)(&sdr_ctrl->cport_rdwr),
626 (unsigned)reg_value);
627 reg_value = readl(&sdr_ctrl->cport_rdwr);
628 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
630 debug("Configuring DRAMODT\n");
631 clrsetbits_le32(&sdr_ctrl->dram_odt,
632 SDR_CTRLGRP_DRAMODT_READ_MASK,
633 CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
634 SDR_CTRLGRP_DRAMODT_READ_LSB);
636 clrsetbits_le32(&sdr_ctrl->dram_odt,
637 SDR_CTRLGRP_DRAMODT_WRITE_MASK,
638 CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
639 SDR_CTRLGRP_DRAMODT_WRITE_LSB);
641 /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
642 writel(CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
643 &sysmgr_regs->iswgrp_handoff[3]);
645 /* only enable if the FPGA is programmed */
646 if (fpgamgr_test_fpga_ready()) {
647 if (sdram_write_verify(&sdr_ctrl->fpgaport_rst,
648 CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST) == 1) {
654 /* Restore the SDR PHY Register if valid */
655 if (sdr_phy_reg != 0xffffffff)
656 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
658 /***** Final step - apply configuration changes *****/
659 debug("Configuring STATICCFG_\n");
660 clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
661 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
662 debug(" Write - Address ");
663 debug("0x%08x Data 0x%08x\n",
664 (unsigned)(&sdr_ctrl->static_cfg),
665 (unsigned)reg_value);
666 reg_value = readl(&sdr_ctrl->static_cfg);
667 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
669 sdram_set_protection_config(0, sdram_calculate_size());
671 sdram_dump_protection_config();
677 * To calculate SDRAM device size based on SDRAM controller parameters.
678 * Size is specified in bytes.
681 * This function is compiled and linked into the preloader and
682 * Uboot (there may be others). So if this function changes, the Preloader
683 * and UBoot must be updated simultaneously.
685 unsigned long sdram_calculate_size(void)
688 unsigned long row, bank, col, cs, width;
690 temp = readl(&sdr_ctrl->dram_addrw);
691 col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
692 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
694 /* SDRAM Failure When Accessing Non-Existent Memory
695 * Use ROWBITS from Quartus/QSys to calculate SDRAM size
696 * since the FB specifies we modify ROWBITs to work around SDRAM
699 * If the stored handoff value for rows is 0, it probably means
700 * the preloader is older than UBoot. Use the
701 * #define from the SOCEDS Tools per Crucible review
702 * uboot-socfpga-204. Note that this is not a supported
703 * configuration and is not tested. The customer
704 * should be using preloader and uboot built from the
707 row = readl(&sysmgr_regs->iswgrp_handoff[4]);
709 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
710 /* If the stored handoff value for rows is greater than
711 * the field width in the sdr.dramaddrw register then
712 * something is very wrong. Revert to using the the #define
713 * value handed off by the SOCEDS tool chain instead of
714 * using a broken value.
717 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
719 bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
720 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
722 /* SDRAM Failure When Accessing Non-Existent Memory
723 * Use CSBITs from Quartus/QSys to calculate SDRAM size
724 * since the FB specifies we modify CSBITs to work around SDRAM
727 cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
728 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB;
731 cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
733 width = readl(&sdr_ctrl->dram_if_width);
734 /* ECC would not be calculated as its not addressible */
735 if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
737 if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
740 /* calculate the SDRAM size base on this info */
741 temp = 1 << (row + bank + col);
742 temp = temp * cs * (width / 8);
744 debug("sdram_calculate_memory returns %ld\n", temp);