1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017 Intel Corporation <www.intel.com>
13 #include <asm/arch/fpga_manager.h>
14 #include <asm/arch/misc.h>
15 #include <asm/arch/reset_manager.h>
16 #include <asm/arch/sdram.h>
17 #include <linux/kernel.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 static void sdram_mmr_init(void);
22 static u64 sdram_size_calc(void);
24 /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
25 #define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1)
27 #define ARRIA_DDR_CONFIG(A, B, C, R) \
28 (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
29 #define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config)
30 #define DDR_REG_SEQ2CORE 0xFFD0507C
31 #define DDR_REG_CORE2SEQ 0xFFD05078
32 #define DDR_READ_LATENCY_DELAY 40
33 #define DDR_SIZE_2GB_HEX 0x80000000
34 #define DDR_MAX_TRIES 0x00100000
36 #define IO48_MMR_DRAMSTS 0xFFCFA0EC
37 #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
38 #define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
39 #define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
41 #define SEQ2CORE_MASK 0xF
42 #define CORE2SEQ_INT_REQ 0xF
43 #define SEQ2CORE_INT_RESP_BIT 3
45 static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
46 (void *)SOCFPGA_SDR_ADDRESS;
47 static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
48 (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
49 static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
50 *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
51 (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
52 static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
53 (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
54 static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
55 (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
57 /* The following are the supported configurations */
58 static u32 ddr_config[] = {
59 /* Chip - Row - Bank - Column Style */
61 ARRIA_DDR_CONFIG(0, 3, 10, 12),
62 ARRIA_DDR_CONFIG(0, 3, 10, 13),
63 ARRIA_DDR_CONFIG(0, 3, 10, 14),
64 ARRIA_DDR_CONFIG(0, 3, 10, 15),
65 ARRIA_DDR_CONFIG(0, 3, 10, 16),
66 ARRIA_DDR_CONFIG(0, 3, 10, 17),
68 ARRIA_DDR_CONFIG(0, 3, 11, 14),
69 ARRIA_DDR_CONFIG(0, 3, 11, 15),
70 ARRIA_DDR_CONFIG(0, 3, 11, 16),
71 ARRIA_DDR_CONFIG(0, 3, 12, 15),
73 ARRIA_DDR_CONFIG(0, 4, 10, 14),
74 ARRIA_DDR_CONFIG(0, 4, 10, 15),
75 ARRIA_DDR_CONFIG(0, 4, 10, 16),
76 ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
77 /* Chip - Bank - Row - Column Style */
78 ARRIA_DDR_CONFIG(1, 3, 10, 12),
79 ARRIA_DDR_CONFIG(1, 3, 10, 13),
80 ARRIA_DDR_CONFIG(1, 3, 10, 14),
81 ARRIA_DDR_CONFIG(1, 3, 10, 15),
82 ARRIA_DDR_CONFIG(1, 3, 10, 16),
83 ARRIA_DDR_CONFIG(1, 3, 10, 17),
84 ARRIA_DDR_CONFIG(1, 3, 11, 14),
85 ARRIA_DDR_CONFIG(1, 3, 11, 15),
86 ARRIA_DDR_CONFIG(1, 3, 11, 16),
87 ARRIA_DDR_CONFIG(1, 3, 12, 15),
89 ARRIA_DDR_CONFIG(1, 4, 10, 14),
90 ARRIA_DDR_CONFIG(1, 4, 10, 15),
91 ARRIA_DDR_CONFIG(1, 4, 10, 16),
92 ARRIA_DDR_CONFIG(1, 4, 10, 17),
95 static int match_ddr_conf(u32 ddr_conf)
99 for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
100 if (ddr_conf == ddr_config[i])
106 /* Check whether SDRAM is successfully Calibrated */
107 static int is_sdram_cal_success(void)
109 return readl(&socfpga_ecc_hmc_base->ddrcalstat);
112 static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
114 u32 reg = readl(ereg);
116 return (reg & BIT(bit)) ? 1 : 0;
119 static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
120 u32 expected, u32 timeout_usec)
124 for (tmr = 0; tmr < timeout_usec; tmr += 100) {
127 if (ddr_get_bit(ereg, bit) == expected)
134 static int emif_clear(void)
136 u32 i = DDR_MAX_TRIES;
139 writel(0, DDR_REG_CORE2SEQ);
142 ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
143 SEQ2CORE_MASK, 1, 50, 0);
144 } while (ret && (--i > 0));
149 static int emif_reset(void)
153 c2s = readl(DDR_REG_CORE2SEQ);
154 s2c = readl(DDR_REG_SEQ2CORE);
156 debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
157 c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
158 readl(IO48_MMR_NIOS2_RESERVE1),
159 readl(IO48_MMR_NIOS2_RESERVE2),
160 readl(IO48_MMR_DRAMSTS));
162 if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
163 debug("failed emif_clear()\n");
167 writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
169 if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
170 debug("emif_reset failed to see interrupt acknowledge\n");
173 debug("emif_reset interrupt acknowledged\n");
177 debug("emif_clear() failed\n");
180 debug("emif_reset interrupt cleared\n");
182 debug("nr0=%08x nr1=%08x nr2=%08x\n",
183 readl(IO48_MMR_NIOS2_RESERVE0),
184 readl(IO48_MMR_NIOS2_RESERVE1),
185 readl(IO48_MMR_NIOS2_RESERVE2));
190 static int ddr_setup(void)
192 int i, j, ddr_setup_complete = 0;
194 /* Try 3 times to do a calibration */
195 for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
198 /* A delay to wait for calibration bit to set */
199 for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
201 ddr_setup_complete = is_sdram_cal_success();
204 if (!ddr_setup_complete)
206 puts("Error: Failed to reset EMIF\n");
209 /* After 3 times trying calibration */
210 if (!ddr_setup_complete) {
211 puts("Error: Could Not Calibrate SDRAM\n");
218 static int sdram_is_ecc_enabled(void)
220 return !!(readl(&socfpga_ecc_hmc_base->eccctrl) &
221 ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK);
224 /* Initialize SDRAM ECC bits to avoid false DBE */
225 static void sdram_init_ecc_bits(u32 size)
229 memset(0, 0, 0x8000);
230 gd->arch.tlb_addr = 0x4000;
231 gd->arch.tlb_size = PGTABLE_SIZE;
235 printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20);
236 memset((void *)0x8000, 0, size - 0x8000);
238 printf("DDRCAL: Scrubbing ECC RAM done.\n");
242 /* Function to startup the SDRAM*/
243 static int sdram_startup(void)
245 /* Release NOC ddr scheduler from reset */
246 socfpga_reset_deassert_noc_ddr_scheduler();
248 /* Bringup the DDR (calibration and configuration) */
252 static u64 sdram_size_calc(void)
254 u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
256 u64 size = BIT(((dramaddrw &
257 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
258 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
260 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
261 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
263 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
264 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
266 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
267 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
268 (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
270 size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
271 ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
273 debug("SDRAM size=%llu", size);
278 /* Function to initialize SDRAM MMR and NOC DDR scheduler*/
279 static void sdram_mmr_init(void)
281 u32 update_value, io48_value;
282 u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
283 u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
284 u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
285 u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
286 u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
287 u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
288 u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
289 u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
290 u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
294 * Configure the DDR IO size [0xFFCFB008]
295 * niosreserve0: Used to indicate DDR width &
296 * bit[7:0] = Number of data bits (0x20 for 32bit)
297 * bit[8] = 1 if user-mode OCT is present
298 * bit[9] = 1 if warm reset compiled into EMIF Cal Code
299 * bit[10] = 1 if warm reset is on during generation in EMIF Cal
300 * niosreserve1: IP ADCDS version encoded as 16 bit value
301 * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
302 * 3=EAP, 4-6 are reserved)
303 * bit[5:3] = Service Pack # (e.g. 1)
304 * bit[9:6] = Minor Release #
305 * bit[14:10] = Major Release #
307 if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
308 update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
309 writel(((update_value & 0xFF) >> 5),
310 &socfpga_ecc_hmc_base->ddrioctrl);
313 ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
315 /* Set the DDR Configuration [0xFFD12400] */
316 io48_value = ARRIA_DDR_CONFIG(
318 IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
319 IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
321 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
322 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
324 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
325 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
327 IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
329 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
330 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
332 update_value = match_ddr_conf(io48_value);
335 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
338 * Configure DDR timing [0xFFD1240C]
339 * RDTOMISS = tRTP + tRP + tRCD - BL/2
340 * WRTOMISS = WL + tWR + tRP + tRCD and
341 * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...
342 * First part of equation is in memory clock units so divide by 2
343 * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
344 * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
346 u32 ctrlcfg0_cfg_ctrl_burst_len =
347 (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
348 IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
350 u32 caltim0_cfg_act_to_rdwr = caltim0 &
351 IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
353 u32 caltim0_cfg_act_to_act =
354 (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
355 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
357 u32 caltim0_cfg_act_to_act_db =
359 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
360 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
362 u32 caltim1_cfg_rd_to_wr =
363 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
364 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
366 u32 caltim1_cfg_rd_to_rd_dc =
367 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
368 IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
370 u32 caltim1_cfg_rd_to_wr_dc =
371 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
372 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
374 u32 caltim2_cfg_rd_to_pch =
375 (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
376 IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
378 u32 caltim3_cfg_wr_to_rd =
379 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
380 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
382 u32 caltim3_cfg_wr_to_rd_dc =
383 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
384 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
386 u32 caltim4_cfg_pch_to_valid =
387 (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
388 IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
390 u32 caltim9_cfg_4_act_to_act = caltim9 &
391 IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
393 update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid +
394 caltim0_cfg_act_to_rdwr -
395 (ctrlcfg0_cfg_ctrl_burst_len >> 2));
397 io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
398 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
399 (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
400 /* Up to here was in memory cycles so divide by 2 */
401 caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
402 caltim4_cfg_pch_to_valid);
404 writel(((caltim0_cfg_act_to_act <<
405 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
407 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
409 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
410 ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
411 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
412 (caltim1_cfg_rd_to_wr <<
413 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
414 (caltim3_cfg_wr_to_rd <<
415 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
416 (((ddrioctl == 1) ? 1 : 0) <<
417 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
418 &socfpga_noc_ddr_scheduler_base->
419 ddr_t_main_scheduler_ddrtiming);
421 /* Configure DDR mode [0xFFD12410] [precharge = 0] */
422 writel(((ddrioctl ? 0 : 1) <<
423 ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
424 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
426 /* Configure the read latency [0xFFD12414] */
427 writel(((socfpga_io48_mmr_base->dramtiming0 &
428 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
429 DDR_READ_LATENCY_DELAY,
430 &socfpga_noc_ddr_scheduler_base->
431 ddr_t_main_scheduler_readlatency);
434 * Configuring timing values concerning activate commands
435 * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
437 writel(((caltim0_cfg_act_to_act_db <<
438 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
439 (caltim9_cfg_4_act_to_act <<
440 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
441 (ARRIA10_SDR_ACTIVATE_FAWBANK <<
442 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
443 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
446 * Configuring timing values concerning device to device data bus
447 * ownership change [0xFFD1243C]
449 writel(((caltim1_cfg_rd_to_rd_dc <<
450 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
451 (caltim1_cfg_rd_to_wr_dc <<
452 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
453 (caltim3_cfg_wr_to_rd_dc <<
454 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
455 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
457 /* Enable or disable the SDRAM ECC */
458 if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
459 setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
460 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
461 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
462 ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
463 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
464 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
465 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
466 setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
467 (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
468 ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
470 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
471 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
472 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
473 ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
474 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
475 (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
476 ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
480 struct firewall_entry {
481 const char *prop_name;
486 #define FW_MPU_FPGA_ADDRESS \
487 ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
488 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
490 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
491 (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
492 offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
494 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
495 (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
496 offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
498 const struct firewall_entry firewall_table[] = {
501 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
502 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
503 ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
507 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
508 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
509 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
510 ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
514 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
515 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
516 ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
520 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
521 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
522 ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
526 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
527 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
528 ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
532 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
533 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
534 ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
538 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
539 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
540 ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
544 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
545 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
546 ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
550 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
551 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
552 ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
556 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
557 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
558 ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
562 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
563 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
564 ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
568 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
569 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
570 ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
574 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
575 (fpga2sdram0region0addr),
576 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
577 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
581 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
582 (fpga2sdram0region1addr),
583 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
584 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
588 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
589 (fpga2sdram0region2addr),
590 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
591 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
595 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
596 (fpga2sdram0region3addr),
597 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
598 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
602 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
603 (fpga2sdram1region0addr),
604 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
605 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
609 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
610 (fpga2sdram1region1addr),
611 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
612 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
616 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
617 (fpga2sdram1region2addr),
618 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
619 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
623 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
624 (fpga2sdram1region3addr),
625 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
626 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
630 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
631 (fpga2sdram2region0addr),
632 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
633 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
637 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
638 (fpga2sdram2region1addr),
639 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
640 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
644 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
645 (fpga2sdram2region2addr),
646 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
647 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
651 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
652 (fpga2sdram2region3addr),
653 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
654 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
659 static int of_sdram_firewall_setup(const void *blob)
661 int child, i, node, ret;
665 node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
669 child = fdt_first_subnode(blob, node);
673 /* set to default state */
674 writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
675 writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
678 for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
679 sprintf(name, "%s", firewall_table[i].prop_name);
680 ret = fdtdec_get_int_array(blob, child, name,
683 sprintf(name, "altr,%s", firewall_table[i].prop_name);
684 ret = fdtdec_get_int_array(blob, child, name,
690 writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
691 (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
692 firewall_table[i].cfg_addr);
693 setbits_le32(firewall_table[i].en_addr,
694 firewall_table[i].en_bit);
700 int ddr_calibration_sequence(void)
704 /* Check to see if SDRAM cal was success */
705 if (sdram_startup()) {
706 puts("DDRCAL: Failed\n");
710 puts("DDRCAL: Success\n");
714 /* initialize the MMR register */
717 /* assigning the SDRAM size */
718 u64 size = sdram_size_calc();
721 * If size is less than zero, this is invalid/weird value from
722 * calculation, use default Config size.
723 * Up to 2GB is supported, 2GB would be used if more than that.
726 gd->ram_size = PHYS_SDRAM_1_SIZE;
727 else if (DDR_SIZE_2GB_HEX <= size)
728 gd->ram_size = DDR_SIZE_2GB_HEX;
730 gd->ram_size = (u32)size;
732 /* setup the dram info within bd */
733 dram_init_banksize();
735 if (of_sdram_firewall_setup(gd->fdt_blob))
736 puts("FW: Error Configuring Firewall\n");
738 if (sdram_is_ecc_enabled())
739 sdram_init_ecc_bits(gd->ram_size);