git.sur5r.net Git - u-boot/blob - drivers/ddr/altera/sdram_arria10.c

   1 /*
   2  * Copyright (C) 2017 Intel Corporation <www.intel.com>
   3  *
   4  * SPDX-License-Identifier:    GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <fdtdec.h>
  10 #include <malloc.h>
  11 #include <wait_bit.h>
  12 #include <watchdog.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/fpga_manager.h>
  15 #include <asm/arch/misc.h>
  16 #include <asm/arch/reset_manager.h>
  17 #include <asm/arch/sdram.h>
  18 #include <linux/kernel.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 static void sdram_mmr_init(void);
  23 static u64 sdram_size_calc(void);
  24
  25 /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
  26 #define ARRIA10_SDR_ACTIVATE_FAWBANK    (0x1)
  27
  28 #define ARRIA_DDR_CONFIG(A, B, C, R) \
  29         (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  30 #define DDR_CONFIG_ELEMENTS     ARRAY_SIZE(ddr_config)
  31 #define DDR_REG_SEQ2CORE        0xFFD0507C
  32 #define DDR_REG_CORE2SEQ        0xFFD05078
  33 #define DDR_READ_LATENCY_DELAY  40
  34 #define DDR_SIZE_2GB_HEX        0x80000000
  35 #define DDR_MAX_TRIES           0x00100000
  36
  37 #define IO48_MMR_DRAMSTS        0xFFCFA0EC
  38 #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
  39 #define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
  40 #define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
  41
  42 #define SEQ2CORE_MASK           0xF
  43 #define CORE2SEQ_INT_REQ        0xF
  44 #define SEQ2CORE_INT_RESP_BIT   3
  45
  46 static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
  47                 (void *)SOCFPGA_SDR_ADDRESS;
  48 static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
  49                 (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
  50 static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
  51                 *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
  52                 (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
  53 static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
  54                 (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
  55 static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
  56                 (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
  57
  58 /* The following are the supported configurations */
  59 static u32 ddr_config[] = {
  60         /* Chip - Row - Bank - Column Style */
  61         /* All Types */
  62         ARRIA_DDR_CONFIG(0, 3, 10, 12),
  63         ARRIA_DDR_CONFIG(0, 3, 10, 13),
  64         ARRIA_DDR_CONFIG(0, 3, 10, 14),
  65         ARRIA_DDR_CONFIG(0, 3, 10, 15),
  66         ARRIA_DDR_CONFIG(0, 3, 10, 16),
  67         ARRIA_DDR_CONFIG(0, 3, 10, 17),
  68         /* LPDDR x16 */
  69         ARRIA_DDR_CONFIG(0, 3, 11, 14),
  70         ARRIA_DDR_CONFIG(0, 3, 11, 15),
  71         ARRIA_DDR_CONFIG(0, 3, 11, 16),
  72         ARRIA_DDR_CONFIG(0, 3, 12, 15),
  73         /* DDR4 Only */
  74         ARRIA_DDR_CONFIG(0, 4, 10, 14),
  75         ARRIA_DDR_CONFIG(0, 4, 10, 15),
  76         ARRIA_DDR_CONFIG(0, 4, 10, 16),
  77         ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
  78         /* Chip - Bank - Row - Column Style */
  79         ARRIA_DDR_CONFIG(1, 3, 10, 12),
  80         ARRIA_DDR_CONFIG(1, 3, 10, 13),
  81         ARRIA_DDR_CONFIG(1, 3, 10, 14),
  82         ARRIA_DDR_CONFIG(1, 3, 10, 15),
  83         ARRIA_DDR_CONFIG(1, 3, 10, 16),
  84         ARRIA_DDR_CONFIG(1, 3, 10, 17),
  85         ARRIA_DDR_CONFIG(1, 3, 11, 14),
  86         ARRIA_DDR_CONFIG(1, 3, 11, 15),
  87         ARRIA_DDR_CONFIG(1, 3, 11, 16),
  88         ARRIA_DDR_CONFIG(1, 3, 12, 15),
  89         /* DDR4 Only */
  90         ARRIA_DDR_CONFIG(1, 4, 10, 14),
  91         ARRIA_DDR_CONFIG(1, 4, 10, 15),
  92         ARRIA_DDR_CONFIG(1, 4, 10, 16),
  93         ARRIA_DDR_CONFIG(1, 4, 10, 17),
  94 };
  95
  96 static int match_ddr_conf(u32 ddr_conf)
  97 {
  98         int i;
  99
 100         for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
 101                 if (ddr_conf == ddr_config[i])
 102                         return i;
 103         }
 104         return 0;
 105 }
 106
 107 /* Check whether SDRAM is successfully Calibrated */
 108 static int is_sdram_cal_success(void)
 109 {
 110         return readl(&socfpga_ecc_hmc_base->ddrcalstat);
 111 }
 112
 113 static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
 114 {
 115         u32 reg = readl(ereg);
 116
 117         return (reg & BIT(bit)) ? 1 : 0;
 118 }
 119
 120 static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
 121                            u32 expected, u32 timeout_usec)
 122 {
 123         u32 tmr;
 124
 125         for (tmr = 0; tmr < timeout_usec; tmr += 100) {
 126                 udelay(100);
 127                 WATCHDOG_RESET();
 128                 if (ddr_get_bit(ereg, bit) == expected)
 129                         return 0;
 130         }
 131
 132         return 1;
 133 }
 134
 135 static int emif_clear(void)
 136 {
 137         u32 i = DDR_MAX_TRIES;
 138         u8 ret = 0;
 139
 140         writel(0, DDR_REG_CORE2SEQ);
 141
 142         do {
 143                 ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
 144                                    SEQ2CORE_MASK, 1, 50, 0);
 145         } while (ret && (--i > 0));
 146
 147         return !i;
 148 }
 149
 150 static int emif_reset(void)
 151 {
 152         u32 c2s, s2c;
 153
 154         c2s = readl(DDR_REG_CORE2SEQ);
 155         s2c = readl(DDR_REG_SEQ2CORE);
 156
 157         debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
 158              c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
 159              readl(IO48_MMR_NIOS2_RESERVE1),
 160              readl(IO48_MMR_NIOS2_RESERVE2),
 161              readl(IO48_MMR_DRAMSTS));
 162
 163         if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
 164                 debug("failed emif_clear()\n");
 165                 return -EPERM;
 166         }
 167
 168         writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
 169
 170         if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
 171                 debug("emif_reset failed to see interrupt acknowledge\n");
 172                 return -EPERM;
 173         } else {
 174                 debug("emif_reset interrupt acknowledged\n");
 175         }
 176
 177         if (emif_clear()) {
 178                 debug("emif_clear() failed\n");
 179                 return -EPERM;
 180         }
 181         debug("emif_reset interrupt cleared\n");
 182
 183         debug("nr0=%08x nr1=%08x nr2=%08x\n",
 184              readl(IO48_MMR_NIOS2_RESERVE0),
 185              readl(IO48_MMR_NIOS2_RESERVE1),
 186              readl(IO48_MMR_NIOS2_RESERVE2));
 187
 188         return 0;
 189 }
 190
 191 static int ddr_setup(void)
 192 {
 193         int i, j, ddr_setup_complete = 0;
 194
 195         /* Try 3 times to do a calibration */
 196         for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
 197                 WATCHDOG_RESET();
 198
 199                 /* A delay to wait for calibration bit to set */
 200                 for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
 201                         mdelay(500);
 202                         ddr_setup_complete = is_sdram_cal_success();
 203                 }
 204
 205                 if (!ddr_setup_complete)
 206                         if (emif_reset())
 207                                 puts("Error: Failed to reset EMIF\n");
 208         }
 209
 210         /* After 3 times trying calibration */
 211         if (!ddr_setup_complete) {
 212                 puts("Error: Could Not Calibrate SDRAM\n");
 213                 return -EPERM;
 214         }
 215
 216         return 0;
 217 }
 218
 219 /* Function to startup the SDRAM*/
 220 static int sdram_startup(void)
 221 {
 222         /* Release NOC ddr scheduler from reset */
 223         socfpga_reset_deassert_noc_ddr_scheduler();
 224
 225         /* Bringup the DDR (calibration and configuration) */
 226         return ddr_setup();
 227 }
 228
 229 static u64 sdram_size_calc(void)
 230 {
 231         u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
 232
 233         u64 size = BIT(((dramaddrw &
 234                 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
 235                 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
 236                 ((dramaddrw &
 237                 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
 238                 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
 239                 ((dramaddrw &
 240                 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
 241                 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
 242                 ((dramaddrw &
 243                 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
 244                 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
 245                 (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
 246
 247         size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
 248                        ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
 249
 250         debug("SDRAM size=%llu", size);
 251
 252         return size;
 253 }
 254
 255 /* Function to initialize SDRAM MMR and NOC DDR scheduler*/
 256 static void sdram_mmr_init(void)
 257 {
 258         u32 update_value, io48_value;
 259         u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
 260         u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
 261         u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
 262         u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
 263         u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
 264         u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
 265         u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
 266         u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
 267         u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
 268         u32 ddrioctl;
 269
 270         /*
 271          * Configure the DDR IO size [0xFFCFB008]
 272          * niosreserve0: Used to indicate DDR width &
 273          *      bit[7:0] = Number of data bits (0x20 for 32bit)
 274          *      bit[8]   = 1 if user-mode OCT is present
 275          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
 276          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
 277          * niosreserve1: IP ADCDS version encoded as 16 bit value
 278          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
 279          *                          3=EAP, 4-6 are reserved)
 280          *      bit[5:3] = Service Pack # (e.g. 1)
 281          *      bit[9:6] = Minor Release #
 282          *      bit[14:10] = Major Release #
 283          */
 284         if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
 285                 update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
 286                 writel(((update_value & 0xFF) >> 5),
 287                        &socfpga_ecc_hmc_base->ddrioctrl);
 288         }
 289
 290         ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
 291
 292         /* Set the DDR Configuration [0xFFD12400] */
 293         io48_value = ARRIA_DDR_CONFIG(
 294                         ((ctrlcfg1 &
 295                         IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
 296                         IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
 297                         ((dramaddrw &
 298                         IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
 299                         IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
 300                         ((dramaddrw &
 301                         IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
 302                         IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
 303                         (dramaddrw &
 304                         IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
 305                         ((dramaddrw &
 306                         IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
 307                         IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
 308
 309         update_value = match_ddr_conf(io48_value);
 310         if (update_value)
 311                 writel(update_value,
 312                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
 313
 314         /*
 315          * Configure DDR timing [0xFFD1240C]
 316          *  RDTOMISS = tRTP + tRP + tRCD - BL/2
 317          *  WRTOMISS = WL + tWR + tRP + tRCD and
 318          *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
 319          *  First part of equation is in memory clock units so divide by 2
 320          *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
 321          *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
 322          */
 323         u32 ctrlcfg0_cfg_ctrl_burst_len =
 324                 (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
 325                 IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
 326
 327         u32 caltim0_cfg_act_to_rdwr = caltim0 &
 328                 IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
 329
 330         u32 caltim0_cfg_act_to_act =
 331                 (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
 332                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
 333
 334         u32 caltim0_cfg_act_to_act_db =
 335                 (caltim0 &
 336                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
 337                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
 338
 339         u32 caltim1_cfg_rd_to_wr =
 340                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
 341                 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
 342
 343         u32 caltim1_cfg_rd_to_rd_dc =
 344                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
 345                 IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
 346
 347         u32 caltim1_cfg_rd_to_wr_dc =
 348                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
 349                 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
 350
 351         u32 caltim2_cfg_rd_to_pch =
 352                 (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
 353                 IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
 354
 355         u32 caltim3_cfg_wr_to_rd =
 356                 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
 357                 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
 358
 359         u32 caltim3_cfg_wr_to_rd_dc =
 360                 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
 361                 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
 362
 363         u32 caltim4_cfg_pch_to_valid =
 364                 (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
 365                 IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
 366
 367         u32 caltim9_cfg_4_act_to_act = caltim9 &
 368                 IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
 369
 370         update_value = (caltim2_cfg_rd_to_pch +  caltim4_cfg_pch_to_valid +
 371                         caltim0_cfg_act_to_rdwr -
 372                         (ctrlcfg0_cfg_ctrl_burst_len >> 2));
 373
 374         io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
 375                       ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
 376                       (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
 377                       /* Up to here was in memory cycles so divide by 2 */
 378                       caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
 379                       caltim4_cfg_pch_to_valid);
 380
 381         writel(((caltim0_cfg_act_to_act <<
 382                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
 383                 (update_value <<
 384                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
 385                 (io48_value <<
 386                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
 387                 ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
 388                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
 389                 (caltim1_cfg_rd_to_wr <<
 390                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
 391                 (caltim3_cfg_wr_to_rd <<
 392                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
 393                 (((ddrioctl == 1) ? 1 : 0) <<
 394                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
 395                 &socfpga_noc_ddr_scheduler_base->
 396                         ddr_t_main_scheduler_ddrtiming);
 397
 398         /* Configure DDR mode [0xFFD12410] [precharge = 0] */
 399         writel(((ddrioctl ? 0 : 1) <<
 400                 ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
 401                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
 402
 403         /* Configure the read latency [0xFFD12414] */
 404         writel(((socfpga_io48_mmr_base->dramtiming0 &
 405                 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
 406                 DDR_READ_LATENCY_DELAY,
 407                 &socfpga_noc_ddr_scheduler_base->
 408                         ddr_t_main_scheduler_readlatency);
 409
 410         /*
 411          * Configuring timing values concerning activate commands
 412          * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
 413          */
 414         writel(((caltim0_cfg_act_to_act_db <<
 415                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
 416                 (caltim9_cfg_4_act_to_act <<
 417                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
 418                 (ARRIA10_SDR_ACTIVATE_FAWBANK <<
 419                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
 420                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
 421
 422         /*
 423          * Configuring timing values concerning device to device data bus
 424          * ownership change [0xFFD1243C]
 425          */
 426         writel(((caltim1_cfg_rd_to_rd_dc <<
 427                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
 428                 (caltim1_cfg_rd_to_wr_dc <<
 429                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
 430                 (caltim3_cfg_wr_to_rd_dc <<
 431                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
 432                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
 433
 434         /* Enable or disable the SDRAM ECC */
 435         if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
 436                 setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 437                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 438                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
 439                               ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
 440                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 441                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 442                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
 443                 setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
 444                              (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
 445                               ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
 446         } else {
 447                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 448                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 449                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
 450                               ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
 451                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
 452                              (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
 453                               ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
 454         }
 455 }
 456
 457 struct firewall_entry {
 458         const char *prop_name;
 459         const u32 cfg_addr;
 460         const u32 en_addr;
 461         const u32 en_bit;
 462 };
 463 #define FW_MPU_FPGA_ADDRESS \
 464         ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
 465         SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
 466
 467 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
 468                 (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
 469                 offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
 470
 471 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
 472                 (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
 473                 offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
 474
 475 const struct firewall_entry firewall_table[] = {
 476         {
 477                 "mpu0",
 478                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
 479                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 480                 ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
 481         },
 482         {
 483                 "mpu1",
 484                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
 485                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
 486                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 487                 ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
 488         },
 489         {
 490                 "mpu2",
 491                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
 492                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 493                 ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
 494         },
 495         {
 496                 "mpu3",
 497                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
 498                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 499                 ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
 500         },
 501         {
 502                 "l3-0",
 503                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
 504                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 505                 ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
 506         },
 507         {
 508                 "l3-1",
 509                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
 510                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 511                 ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
 512         },
 513         {
 514                 "l3-2",
 515                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
 516                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 517                 ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
 518         },
 519         {
 520                 "l3-3",
 521                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
 522                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 523                 ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
 524         },
 525         {
 526                 "l3-4",
 527                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
 528                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 529                 ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
 530         },
 531         {
 532                 "l3-5",
 533                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
 534                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 535                 ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
 536         },
 537         {
 538                 "l3-6",
 539                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
 540                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 541                 ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
 542         },
 543         {
 544                 "l3-7",
 545                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
 546                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 547                 ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
 548         },
 549         {
 550                 "fpga2sdram0-0",
 551                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 552                 (fpga2sdram0region0addr),
 553                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 554                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
 555         },
 556         {
 557                 "fpga2sdram0-1",
 558                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 559                 (fpga2sdram0region1addr),
 560                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 561                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
 562         },
 563         {
 564                 "fpga2sdram0-2",
 565                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 566                 (fpga2sdram0region2addr),
 567                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 568                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
 569         },
 570         {
 571                 "fpga2sdram0-3",
 572                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 573                 (fpga2sdram0region3addr),
 574                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 575                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
 576         },
 577         {
 578                 "fpga2sdram1-0",
 579                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 580                 (fpga2sdram1region0addr),
 581                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 582                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
 583         },
 584         {
 585                 "fpga2sdram1-1",
 586                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 587                 (fpga2sdram1region1addr),
 588                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 589                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
 590         },
 591         {
 592                 "fpga2sdram1-2",
 593                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 594                 (fpga2sdram1region2addr),
 595                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 596                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
 597         },
 598         {
 599                 "fpga2sdram1-3",
 600                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 601                 (fpga2sdram1region3addr),
 602                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 603                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
 604         },
 605         {
 606                 "fpga2sdram2-0",
 607                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 608                 (fpga2sdram2region0addr),
 609                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 610                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
 611         },
 612         {
 613                 "fpga2sdram2-1",
 614                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 615                 (fpga2sdram2region1addr),
 616                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 617                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
 618         },
 619         {
 620                 "fpga2sdram2-2",
 621                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 622                 (fpga2sdram2region2addr),
 623                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 624                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
 625         },
 626         {
 627                 "fpga2sdram2-3",
 628                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 629                 (fpga2sdram2region3addr),
 630                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 631                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
 632         },
 633
 634 };
 635
 636 static int of_sdram_firewall_setup(const void *blob)
 637 {
 638         int child, i, node, ret;
 639         u32 start_end[2];
 640         char name[32];
 641
 642         node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
 643         if (node < 0)
 644                 return -ENXIO;
 645
 646         child = fdt_first_subnode(blob, node);
 647         if (child < 0)
 648                 return -ENXIO;
 649
 650         /* set to default state */
 651         writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
 652         writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
 653
 654
 655         for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
 656                 sprintf(name, "%s", firewall_table[i].prop_name);
 657                 ret = fdtdec_get_int_array(blob, child, name,
 658                                            start_end, 2);
 659                 if (ret) {
 660                         sprintf(name, "altr,%s", firewall_table[i].prop_name);
 661                         ret = fdtdec_get_int_array(blob, child, name,
 662                                                    start_end, 2);
 663                         if (ret)
 664                                 continue;
 665                 }
 666
 667                 writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
 668                        (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
 669                        firewall_table[i].cfg_addr);
 670                 setbits_le32(firewall_table[i].en_addr,
 671                              firewall_table[i].en_bit);
 672         }
 673
 674         return 0;
 675 }
 676
 677 int ddr_calibration_sequence(void)
 678 {
 679         WATCHDOG_RESET();
 680
 681         /* Check to see if SDRAM cal was success */
 682         if (sdram_startup()) {
 683                 puts("DDRCAL: Failed\n");
 684                 return -EPERM;
 685         }
 686
 687         puts("DDRCAL: Success\n");
 688
 689         WATCHDOG_RESET();
 690
 691         /* initialize the MMR register */
 692         sdram_mmr_init();
 693
 694         /* assigning the SDRAM size */
 695         u64 size = sdram_size_calc();
 696
 697         /*
 698          * If size is less than zero, this is invalid/weird value from
 699          * calculation, use default Config size.
 700          * Up to 2GB is supported, 2GB would be used if more than that.
 701          */
 702         if (size <= 0)
 703                 gd->ram_size = PHYS_SDRAM_1_SIZE;
 704         else if (DDR_SIZE_2GB_HEX <= size)
 705                 gd->ram_size = DDR_SIZE_2GB_HEX;
 706         else
 707                 gd->ram_size = (u32)size;
 708
 709         /* setup the dram info within bd */
 710         dram_init_banksize();
 711
 712         if (of_sdram_firewall_setup(gd->fdt_blob))
 713                 puts("FW: Error Configuring Firewall\n");
 714
 715         return 0;
 716 }
 717
 718 void dram_bank_mmu_setup(int bank)
 719 {
 720         bd_t *bd = gd->bd;
 721         int     i;
 722
 723         debug("%s: bank: %d\n", __func__, bank);
 724         for (i = bd->bi_dram[bank].start >> 20;
 725              i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
 726              i++) {
 727 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
 728                 set_section_dcache(i, DCACHE_WRITETHROUGH);
 729 #else
 730                 set_section_dcache(i, DCACHE_WRITEBACK);
 731 #endif
 732         }
 733
 734         /* same as above but just that we would want cacheable for ocram too */
 735         i = CONFIG_SYS_INIT_RAM_ADDR >> 20;
 736 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
 737         set_section_dcache(i, DCACHE_WRITETHROUGH);
 738 #else
 739         set_section_dcache(i, DCACHE_WRITEBACK);
 740 #endif
 741 }