2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
10 #include "sequencer.h"
11 #include "sequencer_auto.h"
12 #include "sequencer_auto_ac_init.h"
13 #include "sequencer_auto_inst_init.h"
14 #include "sequencer_defines.h"
16 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
17 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
19 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
20 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
22 static struct socfpga_sdr_reg_file *sdr_reg_file =
23 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
25 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
26 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
28 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
29 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
31 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
32 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
34 static struct socfpga_data_mgr *data_mgr =
35 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
37 static struct socfpga_sdr_ctrl *sdr_ctrl =
38 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
43 * In order to reduce ROM size, most of the selectable calibration steps are
44 * decided at compile time based on the user's calibration mode selection,
45 * as captured by the STATIC_CALIB_STEPS selection below.
47 * However, to support simulation-time selection of fast simulation mode, where
48 * we skip everything except the bare minimum, we need a few of the steps to
49 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
50 * check, which is based on the rtl-supplied value, or we dynamically compute
51 * the value to use based on the dynamically-chosen calibration mode
55 #define STATIC_IN_RTL_SIM 0
56 #define STATIC_SKIP_DELAY_LOOPS 0
58 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
59 STATIC_SKIP_DELAY_LOOPS)
61 /* calibration steps requested by the rtl */
62 uint16_t dyn_calib_steps;
65 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
66 * instead of static, we use boolean logic to select between
67 * non-skip and skip values
69 * The mask is set to include all bits when not-skipping, but is
73 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
75 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
76 ((non_skip_value) & skip_delay_mask)
79 struct param_type *param;
80 uint32_t curr_shadow_reg;
82 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
83 uint32_t write_group, uint32_t use_dm,
84 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
86 static void set_failing_group_stage(uint32_t group, uint32_t stage,
90 * Only set the global stage if there was not been any other
93 if (gbl->error_stage == CAL_STAGE_NIL) {
94 gbl->error_substage = substage;
95 gbl->error_stage = stage;
96 gbl->error_group = group;
100 static void reg_file_set_group(u16 set_group)
102 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
105 static void reg_file_set_stage(u8 set_stage)
107 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
110 static void reg_file_set_sub_stage(u8 set_sub_stage)
112 set_sub_stage &= 0xff;
113 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
116 static void initialize(void)
118 debug("%s:%d\n", __func__, __LINE__);
119 /* USER calibration has control over path to memory */
121 * In Hard PHY this is a 2-bit control:
125 writel(0x3, &phy_mgr_cfg->mux_sel);
127 /* USER memory clock is not stable we begin initialization */
128 writel(0, &phy_mgr_cfg->reset_mem_stbl);
130 /* USER calibration status all set to zero */
131 writel(0, &phy_mgr_cfg->cal_status);
133 writel(0, &phy_mgr_cfg->cal_debug_info);
135 if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
136 param->read_correct_mask_vg = ((uint32_t)1 <<
137 (RW_MGR_MEM_DQ_PER_READ_DQS /
138 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
139 param->write_correct_mask_vg = ((uint32_t)1 <<
140 (RW_MGR_MEM_DQ_PER_READ_DQS /
141 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
142 param->read_correct_mask = ((uint32_t)1 <<
143 RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
144 param->write_correct_mask = ((uint32_t)1 <<
145 RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
146 param->dm_correct_mask = ((uint32_t)1 <<
147 (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH))
152 static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
154 uint32_t odt_mask_0 = 0;
155 uint32_t odt_mask_1 = 0;
156 uint32_t cs_and_odt_mask;
158 if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
159 if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
167 } else if (RW_MGR_MEM_NUMBER_OF_RANKS == 2) {
169 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
170 /* - Dual-Slot , Single-Rank
171 * (1 chip-select per DIMM)
173 * - RDIMM, 4 total CS (2 CS per DIMM)
175 * Since MEM_NUMBER_OF_RANKS is 2 they are
177 * with 2 CS each (special for RDIMM)
178 * Read: Turn on ODT on the opposite rank
179 * Write: Turn on ODT on all ranks
181 odt_mask_0 = 0x3 & ~(1 << rank);
185 * USER - Single-Slot , Dual-rank DIMMs
186 * (2 chip-selects per DIMM)
187 * USER Read: Turn on ODT off on all ranks
188 * USER Write: Turn on ODT on active rank
191 odt_mask_1 = 0x3 & (1 << rank);
196 * ----------+-----------------------+
199 * Read From +-----------------------+
200 * Rank | 3 | 2 | 1 | 0 |
201 * ----------+-----+-----+-----+-----+
202 * 0 | 0 | 1 | 0 | 0 |
203 * 1 | 1 | 0 | 0 | 0 |
204 * 2 | 0 | 0 | 0 | 1 |
205 * 3 | 0 | 0 | 1 | 0 |
206 * ----------+-----+-----+-----+-----+
209 * ----------+-----------------------+
212 * Write To +-----------------------+
213 * Rank | 3 | 2 | 1 | 0 |
214 * ----------+-----+-----+-----+-----+
215 * 0 | 0 | 1 | 0 | 1 |
216 * 1 | 1 | 0 | 1 | 0 |
217 * 2 | 0 | 1 | 0 | 1 |
218 * 3 | 1 | 0 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
246 (0xFF & ~(1 << rank)) |
247 ((0xFF & odt_mask_0) << 8) |
248 ((0xFF & odt_mask_1) << 16);
249 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
250 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
254 * scc_mgr_set() - Set SCC Manager register
255 * @off: Base offset in SCC Manager space
256 * @grp: Read/Write group
257 * @val: Value to be set
259 * This function sets the SCC Manager (Scan Chain Control Manager) register.
261 static void scc_mgr_set(u32 off, u32 grp, u32 val)
263 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
267 * scc_mgr_initialize() - Initialize SCC Manager registers
269 * Initialize SCC Manager registers.
271 static void scc_mgr_initialize(void)
274 * Clear register file for HPS. 16 (2^4) is the size of the
275 * full register file in the scc mgr:
276 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
277 * MEM_IF_READ_DQS_WIDTH - 1);
281 for (i = 0; i < 16; i++) {
282 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
283 __func__, __LINE__, i);
284 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
288 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
290 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
293 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
295 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
298 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
300 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
303 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
305 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
308 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
310 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
314 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
316 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
319 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
321 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
324 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
326 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
330 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
332 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
333 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
337 /* load up dqs config settings */
338 static void scc_mgr_load_dqs(uint32_t dqs)
340 writel(dqs, &sdr_scc_mgr->dqs_ena);
343 /* load up dqs io config settings */
344 static void scc_mgr_load_dqs_io(void)
346 writel(0, &sdr_scc_mgr->dqs_io_ena);
349 /* load up dq config settings */
350 static void scc_mgr_load_dq(uint32_t dq_in_group)
352 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
355 /* load up dm config settings */
356 static void scc_mgr_load_dm(uint32_t dm)
358 writel(dm, &sdr_scc_mgr->dm_ena);
362 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
363 * @off: Base offset in SCC Manager space
364 * @grp: Read/Write group
365 * @val: Value to be set
366 * @update: If non-zero, trigger SCC Manager update for all ranks
368 * This function sets the SCC Manager (Scan Chain Control Manager) register
369 * and optionally triggers the SCC update for all ranks.
371 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
376 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
377 r += NUM_RANKS_PER_SHADOW_REG) {
378 scc_mgr_set(off, grp, val);
380 if (update || (r == 0)) {
381 writel(grp, &sdr_scc_mgr->dqs_ena);
382 writel(0, &sdr_scc_mgr->update);
387 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
390 * USER although the h/w doesn't support different phases per
391 * shadow register, for simplicity our scc manager modeling
392 * keeps different phase settings per shadow reg, and it's
393 * important for us to keep them in sync to match h/w.
394 * for efficiency, the scan chain update should occur only
397 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
398 read_group, phase, 0);
401 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
405 * USER although the h/w doesn't support different phases per
406 * shadow register, for simplicity our scc manager modeling
407 * keeps different phase settings per shadow reg, and it's
408 * important for us to keep them in sync to match h/w.
409 * for efficiency, the scan chain update should occur only
412 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
413 write_group, phase, 0);
416 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
420 * In shadow register mode, the T11 settings are stored in
421 * registers in the core, which are updated by the DQS_ENA
422 * signals. Not issuing the SCC_MGR_UPD command allows us to
423 * save lots of rank switching overhead, by calling
424 * select_shadow_regs_for_update with update_scan_chains
427 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
428 read_group, delay, 1);
429 writel(0, &sdr_scc_mgr->update);
433 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
434 * @write_group: Write group
435 * @delay: Delay value
437 * This function sets the OCT output delay in SCC manager.
439 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
441 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
442 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
443 const int base = write_group * ratio;
446 * Load the setting in the SCC manager
447 * Although OCT affects only write data, the OCT delay is controlled
448 * by the DQS logic block which is instantiated once per read group.
449 * For protocols where a write group consists of multiple read groups,
450 * the setting must be set multiple times.
452 for (i = 0; i < ratio; i++)
453 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
457 * scc_mgr_set_hhp_extras() - Set HHP extras.
459 * Load the fixed setting in the SCC manager HHP extras.
461 static void scc_mgr_set_hhp_extras(void)
464 * Load the fixed setting in the SCC manager
465 * bits: 0:0 = 1'b1 - DQS bypass
466 * bits: 1:1 = 1'b1 - DQ bypass
467 * bits: 4:2 = 3'b001 - rfifo_mode
468 * bits: 6:5 = 2'b01 - rfifo clock_select
469 * bits: 7:7 = 1'b0 - separate gating from ungating setting
470 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
472 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
473 (1 << 2) | (1 << 1) | (1 << 0);
474 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
475 SCC_MGR_HHP_GLOBALS_OFFSET |
476 SCC_MGR_HHP_EXTRAS_OFFSET;
478 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
481 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
486 * scc_mgr_zero_all() - Zero all DQS config
488 * Zero all DQS config.
490 static void scc_mgr_zero_all(void)
495 * USER Zero all DQS config settings, across all groups and all
498 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
499 r += NUM_RANKS_PER_SHADOW_REG) {
500 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
502 * The phases actually don't exist on a per-rank basis,
503 * but there's no harm updating them several times, so
504 * let's keep the code simple.
506 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
507 scc_mgr_set_dqs_en_phase(i, 0);
508 scc_mgr_set_dqs_en_delay(i, 0);
511 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
512 scc_mgr_set_dqdqs_output_phase(i, 0);
513 /* Arria V/Cyclone V don't have out2. */
514 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
518 /* Multicast to all DQS group enables. */
519 writel(0xff, &sdr_scc_mgr->dqs_ena);
520 writel(0, &sdr_scc_mgr->update);
524 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
525 * @write_group: Write group
527 * Set bypass mode and trigger SCC update.
529 static void scc_set_bypass_mode(const u32 write_group)
531 /* Multicast to all DQ enables. */
532 writel(0xff, &sdr_scc_mgr->dq_ena);
533 writel(0xff, &sdr_scc_mgr->dm_ena);
535 /* Update current DQS IO enable. */
536 writel(0, &sdr_scc_mgr->dqs_io_ena);
538 /* Update the DQS logic. */
539 writel(write_group, &sdr_scc_mgr->dqs_ena);
542 writel(0, &sdr_scc_mgr->update);
546 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
547 * @write_group: Write group
549 * Load DQS settings for Write Group, do not trigger SCC update.
551 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
553 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
554 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
555 const int base = write_group * ratio;
558 * Load the setting in the SCC manager
559 * Although OCT affects only write data, the OCT delay is controlled
560 * by the DQS logic block which is instantiated once per read group.
561 * For protocols where a write group consists of multiple read groups,
562 * the setting must be set multiple times.
564 for (i = 0; i < ratio; i++)
565 writel(base + i, &sdr_scc_mgr->dqs_ena);
569 * scc_mgr_zero_group() - Zero all configs for a group
571 * Zero DQ, DM, DQS and OCT configs for a group.
573 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
577 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
578 r += NUM_RANKS_PER_SHADOW_REG) {
579 /* Zero all DQ config settings. */
580 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
581 scc_mgr_set_dq_out1_delay(i, 0);
583 scc_mgr_set_dq_in_delay(i, 0);
586 /* Multicast to all DQ enables. */
587 writel(0xff, &sdr_scc_mgr->dq_ena);
589 /* Zero all DM config settings. */
590 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
591 scc_mgr_set_dm_out1_delay(i, 0);
593 /* Multicast to all DM enables. */
594 writel(0xff, &sdr_scc_mgr->dm_ena);
596 /* Zero all DQS IO settings. */
598 scc_mgr_set_dqs_io_in_delay(0);
600 /* Arria V/Cyclone V don't have out2. */
601 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
602 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
603 scc_mgr_load_dqs_for_write_group(write_group);
605 /* Multicast to all DQS IO enables (only 1 in total). */
606 writel(0, &sdr_scc_mgr->dqs_io_ena);
608 /* Hit update to zero everything. */
609 writel(0, &sdr_scc_mgr->update);
614 * apply and load a particular input delay for the DQ pins in a group
615 * group_bgn is the index of the first dq pin (in the write group)
617 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
621 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
622 scc_mgr_set_dq_in_delay(p, delay);
628 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
629 * @delay: Delay value
631 * Apply and load a particular output delay for the DQ pins in a group.
633 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
637 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
638 scc_mgr_set_dq_out1_delay(i, delay);
643 /* apply and load a particular output delay for the DM pins in a group */
644 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
648 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
649 scc_mgr_set_dm_out1_delay(i, delay1);
655 /* apply and load delay on both DQS and OCT out1 */
656 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
659 scc_mgr_set_dqs_out1_delay(delay);
660 scc_mgr_load_dqs_io();
662 scc_mgr_set_oct_out1_delay(write_group, delay);
663 scc_mgr_load_dqs_for_write_group(write_group);
667 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
668 * @write_group: Write group
669 * @delay: Delay value
671 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
673 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
679 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
683 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
687 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
688 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
689 debug_cond(DLEVEL == 1,
690 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
691 __func__, __LINE__, write_group, delay, new_delay,
692 IO_IO_OUT2_DELAY_MAX,
693 new_delay - IO_IO_OUT2_DELAY_MAX);
694 new_delay -= IO_IO_OUT2_DELAY_MAX;
695 scc_mgr_set_dqs_out1_delay(new_delay);
698 scc_mgr_load_dqs_io();
701 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
702 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
703 debug_cond(DLEVEL == 1,
704 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
705 __func__, __LINE__, write_group, delay,
706 new_delay, IO_IO_OUT2_DELAY_MAX,
707 new_delay - IO_IO_OUT2_DELAY_MAX);
708 new_delay -= IO_IO_OUT2_DELAY_MAX;
709 scc_mgr_set_oct_out1_delay(write_group, new_delay);
712 scc_mgr_load_dqs_for_write_group(write_group);
716 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
717 * @write_group: Write group
718 * @delay: Delay value
720 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
723 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
728 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
729 r += NUM_RANKS_PER_SHADOW_REG) {
730 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
731 writel(0, &sdr_scc_mgr->update);
735 /* optimization used to recover some slots in ddr3 inst_rom */
736 /* could be applied to other protocols if we wanted to */
737 static void set_jump_as_return(void)
740 * to save space, we replace return with jump to special shared
741 * RETURN instruction so we set the counter to large value so that
744 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
745 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
749 * should always use constants as argument to ensure all computations are
750 * performed at compile time
752 static void delay_for_n_mem_clocks(const uint32_t clocks)
759 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
762 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
763 /* scale (rounding up) to get afi clocks */
766 * Note, we don't bother accounting for being off a little bit
767 * because of a few extra instructions in outer loops
768 * Note, the loops have a test at the end, and do the test before
769 * the decrement, and so always perform the loop
770 * 1 time more than the counter value
772 if (afi_clocks == 0) {
774 } else if (afi_clocks <= 0x100) {
775 inner = afi_clocks-1;
778 } else if (afi_clocks <= 0x10000) {
780 outer = (afi_clocks-1) >> 8;
785 c_loop = (afi_clocks-1) >> 16;
789 * rom instructions are structured as follows:
791 * IDLE_LOOP2: jnz cntr0, TARGET_A
792 * IDLE_LOOP1: jnz cntr1, TARGET_B
795 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
796 * TARGET_B is set to IDLE_LOOP2 as well
798 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
799 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
801 * a little confusing, but it helps save precious space in the inst_rom
802 * and sequencer rom and keeps the delays more accurate and reduces
805 if (afi_clocks <= 0x100) {
806 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
807 &sdr_rw_load_mgr_regs->load_cntr1);
809 writel(RW_MGR_IDLE_LOOP1,
810 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
812 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
813 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
815 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
816 &sdr_rw_load_mgr_regs->load_cntr0);
818 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
819 &sdr_rw_load_mgr_regs->load_cntr1);
821 writel(RW_MGR_IDLE_LOOP2,
822 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
824 writel(RW_MGR_IDLE_LOOP2,
825 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
827 /* hack to get around compiler not being smart enough */
828 if (afi_clocks <= 0x10000) {
829 /* only need to run once */
830 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
831 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
834 writel(RW_MGR_IDLE_LOOP2,
835 SDR_PHYGRP_RWMGRGRP_ADDRESS |
836 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
837 } while (c_loop-- != 0);
840 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
844 * rw_mgr_mem_init_load_regs() - Load instruction registers
845 * @cntr0: Counter 0 value
846 * @cntr1: Counter 1 value
847 * @cntr2: Counter 2 value
848 * @jump: Jump instruction value
850 * Load instruction registers.
852 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
854 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
855 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
858 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
859 &sdr_rw_load_mgr_regs->load_cntr0);
860 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
861 &sdr_rw_load_mgr_regs->load_cntr1);
862 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
863 &sdr_rw_load_mgr_regs->load_cntr2);
865 /* Load jump address */
866 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
867 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
868 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
870 /* Execute count instruction */
871 writel(jump, grpaddr);
875 * rw_mgr_mem_load_user() - Load user calibration values
876 * @fin1: Final instruction 1
877 * @fin2: Final instruction 2
878 * @precharge: If 1, precharge the banks at the end
880 * Load user calibration values and optionally precharge the banks.
882 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
885 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
886 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
889 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
890 if (param->skip_ranks[r]) {
891 /* request to skip the rank */
896 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
898 /* precharge all banks ... */
900 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
903 * USER Use Mirror-ed commands for odd ranks if address
906 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
907 set_jump_as_return();
908 writel(RW_MGR_MRS2_MIRR, grpaddr);
909 delay_for_n_mem_clocks(4);
910 set_jump_as_return();
911 writel(RW_MGR_MRS3_MIRR, grpaddr);
912 delay_for_n_mem_clocks(4);
913 set_jump_as_return();
914 writel(RW_MGR_MRS1_MIRR, grpaddr);
915 delay_for_n_mem_clocks(4);
916 set_jump_as_return();
917 writel(fin1, grpaddr);
919 set_jump_as_return();
920 writel(RW_MGR_MRS2, grpaddr);
921 delay_for_n_mem_clocks(4);
922 set_jump_as_return();
923 writel(RW_MGR_MRS3, grpaddr);
924 delay_for_n_mem_clocks(4);
925 set_jump_as_return();
926 writel(RW_MGR_MRS1, grpaddr);
927 set_jump_as_return();
928 writel(fin2, grpaddr);
934 set_jump_as_return();
935 writel(RW_MGR_ZQCL, grpaddr);
937 /* tZQinit = tDLLK = 512 ck cycles */
938 delay_for_n_mem_clocks(512);
942 static void rw_mgr_mem_initialize(void)
944 debug("%s:%d\n", __func__, __LINE__);
946 /* The reset / cke part of initialization is broadcasted to all ranks */
947 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
948 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
951 * Here's how you load register for a loop
952 * Counters are located @ 0x800
953 * Jump address are located @ 0xC00
954 * For both, registers 0 to 3 are selected using bits 3 and 2, like
955 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
956 * I know this ain't pretty, but Avalon bus throws away the 2 least
960 /* start with memory RESET activated */
965 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
966 * If a and b are the number of iteration in 2 nested loops
967 * it takes the following number of cycles to complete the operation:
968 * number_of_cycles = ((2 + n) * a + 2) * b
969 * where n is the number of instruction in the inner loop
970 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
973 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
975 RW_MGR_INIT_RESET_0_CKE_0);
977 /* indicate that memory is stable */
978 writel(1, &phy_mgr_cfg->reset_mem_stbl);
981 * transition the RESET to high
986 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
987 * If a and b are the number of iteration in 2 nested loops
988 * it takes the following number of cycles to complete the operation
989 * number_of_cycles = ((2 + n) * a + 2) * b
990 * where n is the number of instruction in the inner loop
991 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
994 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
995 SEQ_TRESET_CNTR2_VAL,
996 RW_MGR_INIT_RESET_1_CKE_0);
998 /* bring up clock enable */
1000 /* tXRP < 250 ck cycles */
1001 delay_for_n_mem_clocks(250);
1003 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1008 * At the end of calibration we have to program the user settings in, and
1009 * USER hand off the memory to the user.
1011 static void rw_mgr_mem_handoff(void)
1013 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1015 * USER need to wait tMOD (12CK or 15ns) time before issuing
1016 * other commands, but we will have plenty of NIOS cycles before
1017 * actual handoff so its okay.
1022 * performs a guaranteed read on the patterns we are going to use during a
1023 * read test to ensure memory works
1025 static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
1026 uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
1030 uint32_t correct_mask_vg;
1031 uint32_t tmp_bit_chk;
1032 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1033 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1035 uint32_t base_rw_mgr;
1037 *bit_chk = param->read_correct_mask;
1038 correct_mask_vg = param->read_correct_mask_vg;
1040 for (r = rank_bgn; r < rank_end; r++) {
1041 if (param->skip_ranks[r])
1042 /* request to skip the rank */
1046 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1048 /* Load up a constant bursts of read commands */
1049 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1050 writel(RW_MGR_GUARANTEED_READ,
1051 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1053 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1054 writel(RW_MGR_GUARANTEED_READ_CONT,
1055 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1058 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1059 /* reset the fifos to get pointers to known state */
1061 writel(0, &phy_mgr_cmd->fifo_reset);
1062 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1063 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1065 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1066 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1068 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1069 writel(RW_MGR_GUARANTEED_READ, addr +
1070 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1073 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1074 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
1079 *bit_chk &= tmp_bit_chk;
1082 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1083 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1085 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1086 debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
1087 %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
1088 (long unsigned int)(*bit_chk == param->read_correct_mask));
1089 return *bit_chk == param->read_correct_mask;
1092 static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
1093 (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
1095 return rw_mgr_mem_calibrate_read_test_patterns(0, group,
1096 num_tries, bit_chk, 1);
1099 /* load up the patterns we are going to use during a read test */
1100 static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
1104 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1105 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1107 debug("%s:%d\n", __func__, __LINE__);
1108 for (r = rank_bgn; r < rank_end; r++) {
1109 if (param->skip_ranks[r])
1110 /* request to skip the rank */
1114 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1116 /* Load up a constant bursts */
1117 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1119 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1120 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1122 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1124 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1125 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1127 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1129 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1130 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1132 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1134 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1135 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1137 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1138 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1141 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1145 * try a read and see if it returns correct data back. has dummy reads
1146 * inserted into the mix used to align dqs enable. has more thorough checks
1147 * than the regular read test.
1149 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1150 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1151 uint32_t all_groups, uint32_t all_ranks)
1154 uint32_t correct_mask_vg;
1155 uint32_t tmp_bit_chk;
1156 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1157 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1159 uint32_t base_rw_mgr;
1161 *bit_chk = param->read_correct_mask;
1162 correct_mask_vg = param->read_correct_mask_vg;
1164 uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1165 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1167 for (r = rank_bgn; r < rank_end; r++) {
1168 if (param->skip_ranks[r])
1169 /* request to skip the rank */
1173 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1175 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1177 writel(RW_MGR_READ_B2B_WAIT1,
1178 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1180 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1181 writel(RW_MGR_READ_B2B_WAIT2,
1182 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1184 if (quick_read_mode)
1185 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1186 /* need at least two (1+1) reads to capture failures */
1187 else if (all_groups)
1188 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1190 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1192 writel(RW_MGR_READ_B2B,
1193 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1195 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1196 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1197 &sdr_rw_load_mgr_regs->load_cntr3);
1199 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1201 writel(RW_MGR_READ_B2B,
1202 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1205 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1206 /* reset the fifos to get pointers to known state */
1207 writel(0, &phy_mgr_cmd->fifo_reset);
1208 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1209 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1211 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1212 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1215 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1217 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1219 writel(RW_MGR_READ_B2B, addr +
1220 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1223 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1224 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1229 *bit_chk &= tmp_bit_chk;
1232 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1233 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1236 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1237 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1238 (%u == %u) => %lu", __func__, __LINE__, group,
1239 all_groups, *bit_chk, param->read_correct_mask,
1240 (long unsigned int)(*bit_chk ==
1241 param->read_correct_mask));
1242 return *bit_chk == param->read_correct_mask;
1244 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1245 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1246 (%u != %lu) => %lu\n", __func__, __LINE__,
1247 group, all_groups, *bit_chk, (long unsigned int)0,
1248 (long unsigned int)(*bit_chk != 0x00));
1249 return *bit_chk != 0x00;
1253 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1254 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1255 uint32_t all_groups)
1257 return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1258 bit_chk, all_groups, 1);
1261 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1263 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1267 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1271 for (i = 0; i < VFIFO_SIZE-1; i++)
1272 rw_mgr_incr_vfifo(grp, v);
1275 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1278 uint32_t fail_cnt = 0;
1279 uint32_t test_status;
1281 for (v = 0; v < VFIFO_SIZE; ) {
1282 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1283 __func__, __LINE__, v);
1284 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1285 (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1293 /* fiddle with FIFO */
1294 rw_mgr_incr_vfifo(grp, &v);
1297 if (v >= VFIFO_SIZE) {
1298 /* no failing read found!! Something must have gone wrong */
1299 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1300 __func__, __LINE__);
1307 static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
1308 uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1309 uint32_t *v, uint32_t *d, uint32_t *p,
1310 uint32_t *i, uint32_t *max_working_cnt)
1312 uint32_t found_begin = 0;
1313 uint32_t tmp_delay = 0;
1314 uint32_t test_status;
1316 for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1317 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1318 *work_bgn = tmp_delay;
1319 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1321 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1322 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1323 IO_DELAY_PER_OPA_TAP) {
1324 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1327 rw_mgr_mem_calibrate_read_test_all_ranks
1328 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1331 *max_working_cnt = 1;
1340 if (*p > IO_DQS_EN_PHASE_MAX)
1341 /* fiddle with FIFO */
1342 rw_mgr_incr_vfifo(*grp, v);
1349 if (*i >= VFIFO_SIZE) {
1350 /* cannot find working solution */
1351 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1352 ptap/dtap\n", __func__, __LINE__);
1359 static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1360 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1361 uint32_t *p, uint32_t *max_working_cnt)
1363 uint32_t found_begin = 0;
1366 /* Special case code for backing up a phase */
1368 *p = IO_DQS_EN_PHASE_MAX;
1369 rw_mgr_decr_vfifo(*grp, v);
1373 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1374 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1376 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1377 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1378 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1380 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1384 *work_bgn = tmp_delay;
1389 /* We have found a working dtap before the ptap found above */
1390 if (found_begin == 1)
1391 (*max_working_cnt)++;
1394 * Restore VFIFO to old state before we decremented it
1398 if (*p > IO_DQS_EN_PHASE_MAX) {
1400 rw_mgr_incr_vfifo(*grp, v);
1403 scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1406 static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1407 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1408 uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1411 uint32_t found_end = 0;
1414 *work_end += IO_DELAY_PER_OPA_TAP;
1415 if (*p > IO_DQS_EN_PHASE_MAX) {
1416 /* fiddle with FIFO */
1418 rw_mgr_incr_vfifo(*grp, v);
1421 for (; *i < VFIFO_SIZE + 1; (*i)++) {
1422 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1423 += IO_DELAY_PER_OPA_TAP) {
1424 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1426 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1427 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1431 (*max_working_cnt)++;
1438 if (*p > IO_DQS_EN_PHASE_MAX) {
1439 /* fiddle with FIFO */
1440 rw_mgr_incr_vfifo(*grp, v);
1445 if (*i >= VFIFO_SIZE + 1) {
1446 /* cannot see edge of failing read */
1447 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1448 failed\n", __func__, __LINE__);
1455 static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
1456 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1457 uint32_t *p, uint32_t *work_mid,
1463 *work_mid = (*work_bgn + *work_end) / 2;
1465 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1466 *work_bgn, *work_end, *work_mid);
1467 /* Get the middle delay to be less than a VFIFO delay */
1468 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
1469 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1471 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1472 while (*work_mid > tmp_delay)
1473 *work_mid -= tmp_delay;
1474 debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
1477 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
1478 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1480 tmp_delay -= IO_DELAY_PER_OPA_TAP;
1481 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
1482 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
1483 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
1485 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
1487 scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
1488 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1491 * push vfifo until we can successfully calibrate. We can do this
1492 * because the largest possible margin in 1 VFIFO cycle.
1494 for (i = 0; i < VFIFO_SIZE; i++) {
1495 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1497 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1503 /* fiddle with FIFO */
1504 rw_mgr_incr_vfifo(*grp, v);
1507 if (i >= VFIFO_SIZE) {
1508 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
1509 failed\n", __func__, __LINE__);
1516 /* find a good dqs enable to use */
1517 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1519 uint32_t v, d, p, i;
1520 uint32_t max_working_cnt;
1522 uint32_t dtaps_per_ptap;
1523 uint32_t work_bgn, work_mid, work_end;
1524 uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1526 debug("%s:%d %u\n", __func__, __LINE__, grp);
1528 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1530 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1531 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1533 /* ************************************************************** */
1534 /* * Step 0 : Determine number of delay taps for each phase tap * */
1535 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1537 /* ********************************************************* */
1538 /* * Step 1 : First push vfifo until we get a failing read * */
1539 v = find_vfifo_read(grp, &bit_chk);
1541 max_working_cnt = 0;
1543 /* ******************************************************** */
1544 /* * step 2: find first working phase, increment in ptaps * */
1546 if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1547 &p, &i, &max_working_cnt) == 0)
1550 work_end = work_bgn;
1553 * If d is 0 then the working window covers a phase tap and
1554 * we can follow the old procedure otherwise, we've found the beginning,
1555 * and we need to increment the dtaps until we find the end.
1558 /* ********************************************************* */
1559 /* * step 3a: if we have room, back off by one and
1560 increment in dtaps * */
1562 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1565 /* ********************************************************* */
1566 /* * step 4a: go forward from working phase to non working
1567 phase, increment in ptaps * */
1568 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1569 &i, &max_working_cnt, &work_end) == 0)
1572 /* ********************************************************* */
1573 /* * step 5a: back off one from last, increment in dtaps * */
1575 /* Special case code for backing up a phase */
1577 p = IO_DQS_EN_PHASE_MAX;
1578 rw_mgr_decr_vfifo(grp, &v);
1583 work_end -= IO_DELAY_PER_OPA_TAP;
1584 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1586 /* * The actual increment of dtaps is done outside of
1587 the if/else loop to share code */
1590 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1591 vfifo=%u ptap=%u\n", __func__, __LINE__,
1594 /* ******************************************************* */
1595 /* * step 3-5b: Find the right edge of the window using
1597 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1598 ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1601 work_end = work_bgn;
1603 /* * The actual increment of dtaps is done outside of the
1604 if/else loop to share code */
1606 /* Only here to counterbalance a subtract later on which is
1607 not needed if this branch of the algorithm is taken */
1611 /* The dtap increment to find the failing edge is done here */
1612 for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1613 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1614 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1615 end-2: dtap=%u\n", __func__, __LINE__, d);
1616 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1618 if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1625 /* Go back to working dtap */
1627 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1629 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1630 ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1631 v, p, d-1, work_end);
1633 if (work_end < work_bgn) {
1635 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1636 failed\n", __func__, __LINE__);
1640 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1641 __func__, __LINE__, work_bgn, work_end);
1643 /* *************************************************************** */
1645 * * We need to calculate the number of dtaps that equal a ptap
1646 * * To do that we'll back up a ptap and re-find the edge of the
1647 * * window using dtaps
1650 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1651 for tracking\n", __func__, __LINE__);
1653 /* Special case code for backing up a phase */
1655 p = IO_DQS_EN_PHASE_MAX;
1656 rw_mgr_decr_vfifo(grp, &v);
1657 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1658 cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1662 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1663 phase only: v=%u p=%u", __func__, __LINE__,
1667 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1670 * Increase dtap until we first see a passing read (in case the
1671 * window is smaller than a ptap),
1672 * and then a failing read to mark the edge of the window again
1675 /* Find a passing read */
1676 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1677 __func__, __LINE__);
1678 found_passing_read = 0;
1679 found_failing_read = 0;
1680 initial_failing_dtap = d;
1681 for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1682 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1683 read d=%u\n", __func__, __LINE__, d);
1684 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1686 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1689 found_passing_read = 1;
1694 if (found_passing_read) {
1695 /* Find a failing read */
1696 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1697 read\n", __func__, __LINE__);
1698 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1699 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1700 testing read d=%u\n", __func__, __LINE__, d);
1701 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1703 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1704 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1705 found_failing_read = 1;
1710 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1711 calculate dtaps", __func__, __LINE__);
1712 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1716 * The dynamically calculated dtaps_per_ptap is only valid if we
1717 * found a passing/failing read. If we didn't, it means d hit the max
1718 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1719 * statically calculated value.
1721 if (found_passing_read && found_failing_read)
1722 dtaps_per_ptap = d - initial_failing_dtap;
1724 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1725 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1726 - %u = %u", __func__, __LINE__, d,
1727 initial_failing_dtap, dtaps_per_ptap);
1729 /* ******************************************** */
1730 /* * step 6: Find the centre of the window * */
1731 if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1732 &work_mid, &work_end) == 0)
1735 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
1736 vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
1742 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1743 * dq_in_delay values
1746 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1747 (uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
1755 const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
1756 (RW_MGR_MEM_DQ_PER_READ_DQS-1);
1757 /* we start at zero, so have one less dq to devide among */
1759 debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
1762 /* try different dq_in_delays since the dq path is shorter than dqs */
1764 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1765 r += NUM_RANKS_PER_SHADOW_REG) {
1766 for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++, d += delay_step) {
1767 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
1768 vfifo_find_dqs_", __func__, __LINE__);
1769 debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
1770 write_group, read_group);
1771 debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
1772 scc_mgr_set_dq_in_delay(p, d);
1775 writel(0, &sdr_scc_mgr->update);
1778 found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
1780 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
1781 en_phase_sweep_dq", __func__, __LINE__);
1782 debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
1783 chain to zero\n", write_group, read_group, found);
1785 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1786 r += NUM_RANKS_PER_SHADOW_REG) {
1787 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1789 scc_mgr_set_dq_in_delay(p, 0);
1792 writel(0, &sdr_scc_mgr->update);
1798 /* per-bit deskew DQ and center */
1799 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1800 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1801 uint32_t use_read_test, uint32_t update_fom)
1803 uint32_t i, p, d, min_index;
1805 * Store these as signed since there are comparisons with
1809 uint32_t sticky_bit_chk;
1810 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1811 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1812 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1814 int32_t orig_mid_min, mid_min;
1815 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1817 int32_t dq_margin, dqs_margin;
1819 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1822 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1824 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1825 start_dqs = readl(addr + (read_group << 2));
1826 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1827 start_dqs_en = readl(addr + ((read_group << 2)
1828 - IO_DQS_EN_DELAY_OFFSET));
1830 /* set the left and right edge of each bit to an illegal value */
1831 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1833 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1834 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1835 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1838 /* Search for the left edge of the window for each bit */
1839 for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1840 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1842 writel(0, &sdr_scc_mgr->update);
1845 * Stop searching when the read test doesn't pass AND when
1846 * we've seen a passing read on every bit.
1848 if (use_read_test) {
1849 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1850 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1853 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1856 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1857 (read_group - (write_group *
1858 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1859 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1860 stop = (bit_chk == 0);
1862 sticky_bit_chk = sticky_bit_chk | bit_chk;
1863 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1864 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1865 && %u", __func__, __LINE__, d,
1867 param->read_correct_mask, stop);
1872 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1874 /* Remember a passing test as the
1878 /* If a left edge has not been seen yet,
1879 then a future passing test will mark
1880 this edge as the right edge */
1882 IO_IO_IN_DELAY_MAX + 1) {
1883 right_edge[i] = -(d + 1);
1886 bit_chk = bit_chk >> 1;
1891 /* Reset DQ delay chains to 0 */
1892 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1894 for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1895 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1896 %d right_edge[%u]: %d\n", __func__, __LINE__,
1897 i, left_edge[i], i, right_edge[i]);
1900 * Check for cases where we haven't found the left edge,
1901 * which makes our assignment of the the right edge invalid.
1902 * Reset it to the illegal value.
1904 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1905 right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1906 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1907 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1908 right_edge[%u]: %d\n", __func__, __LINE__,
1913 * Reset sticky bit (except for bits where we have seen
1914 * both the left and right edge).
1916 sticky_bit_chk = sticky_bit_chk << 1;
1917 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1918 (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1919 sticky_bit_chk = sticky_bit_chk | 1;
1926 /* Search for the right edge of the window for each bit */
1927 for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1928 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1929 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1930 uint32_t delay = d + start_dqs_en;
1931 if (delay > IO_DQS_EN_DELAY_MAX)
1932 delay = IO_DQS_EN_DELAY_MAX;
1933 scc_mgr_set_dqs_en_delay(read_group, delay);
1935 scc_mgr_load_dqs(read_group);
1937 writel(0, &sdr_scc_mgr->update);
1940 * Stop searching when the read test doesn't pass AND when
1941 * we've seen a passing read on every bit.
1943 if (use_read_test) {
1944 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1945 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1948 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1951 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1952 (read_group - (write_group *
1953 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1954 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1955 stop = (bit_chk == 0);
1957 sticky_bit_chk = sticky_bit_chk | bit_chk;
1958 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1960 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1961 %u && %u", __func__, __LINE__, d,
1962 sticky_bit_chk, param->read_correct_mask, stop);
1967 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1969 /* Remember a passing test as
1974 /* If a right edge has not been
1975 seen yet, then a future passing
1976 test will mark this edge as the
1978 if (right_edge[i] ==
1979 IO_IO_IN_DELAY_MAX + 1) {
1980 left_edge[i] = -(d + 1);
1983 /* d = 0 failed, but it passed
1984 when testing the left edge,
1985 so it must be marginal,
1987 if (right_edge[i] ==
1988 IO_IO_IN_DELAY_MAX + 1 &&
1994 /* If a right edge has not been
1995 seen yet, then a future passing
1996 test will mark this edge as the
1998 else if (right_edge[i] ==
1999 IO_IO_IN_DELAY_MAX +
2001 left_edge[i] = -(d + 1);
2006 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
2007 d=%u]: ", __func__, __LINE__, d);
2008 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
2009 (int)(bit_chk & 1), i, left_edge[i]);
2010 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2012 bit_chk = bit_chk >> 1;
2017 /* Check that all bits have a window */
2018 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2019 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2020 %d right_edge[%u]: %d", __func__, __LINE__,
2021 i, left_edge[i], i, right_edge[i]);
2022 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2023 == IO_IO_IN_DELAY_MAX + 1)) {
2025 * Restore delay chain settings before letting the loop
2026 * in rw_mgr_mem_calibrate_vfifo to retry different
2027 * dqs/ck relationships.
2029 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2030 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2031 scc_mgr_set_dqs_en_delay(read_group,
2034 scc_mgr_load_dqs(read_group);
2035 writel(0, &sdr_scc_mgr->update);
2037 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2038 find edge [%u]: %d %d", __func__, __LINE__,
2039 i, left_edge[i], right_edge[i]);
2040 if (use_read_test) {
2041 set_failing_group_stage(read_group *
2042 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2044 CAL_SUBSTAGE_VFIFO_CENTER);
2046 set_failing_group_stage(read_group *
2047 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2048 CAL_STAGE_VFIFO_AFTER_WRITES,
2049 CAL_SUBSTAGE_VFIFO_CENTER);
2055 /* Find middle of window for each DQ bit */
2056 mid_min = left_edge[0] - right_edge[0];
2058 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2059 mid = left_edge[i] - right_edge[i];
2060 if (mid < mid_min) {
2067 * -mid_min/2 represents the amount that we need to move DQS.
2068 * If mid_min is odd and positive we'll need to add one to
2069 * make sure the rounding in further calculations is correct
2070 * (always bias to the right), so just add 1 for all positive values.
2075 mid_min = mid_min / 2;
2077 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2078 __func__, __LINE__, mid_min, min_index);
2080 /* Determine the amount we can change DQS (which is -mid_min) */
2081 orig_mid_min = mid_min;
2082 new_dqs = start_dqs - mid_min;
2083 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2084 new_dqs = IO_DQS_IN_DELAY_MAX;
2085 else if (new_dqs < 0)
2088 mid_min = start_dqs - new_dqs;
2089 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2092 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2093 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2094 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2095 else if (start_dqs_en - mid_min < 0)
2096 mid_min += start_dqs_en - mid_min;
2098 new_dqs = start_dqs - mid_min;
2100 debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2101 new_dqs=%d mid_min=%d\n", start_dqs,
2102 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2105 /* Initialize data for export structures */
2106 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2107 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2109 /* add delay to bring centre of all DQ windows to the same "level" */
2110 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2111 /* Use values before divide by 2 to reduce round off error */
2112 shift_dq = (left_edge[i] - right_edge[i] -
2113 (left_edge[min_index] - right_edge[min_index]))/2 +
2114 (orig_mid_min - mid_min);
2116 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2117 shift_dq[%u]=%d\n", i, shift_dq);
2119 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2120 temp_dq_in_delay1 = readl(addr + (p << 2));
2121 temp_dq_in_delay2 = readl(addr + (i << 2));
2123 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2124 (int32_t)IO_IO_IN_DELAY_MAX) {
2125 shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2126 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2127 shift_dq = -(int32_t)temp_dq_in_delay1;
2129 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2130 shift_dq[%u]=%d\n", i, shift_dq);
2131 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2132 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2135 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2136 left_edge[i] - shift_dq + (-mid_min),
2137 right_edge[i] + shift_dq - (-mid_min));
2138 /* To determine values for export structures */
2139 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2140 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2142 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2143 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2146 final_dqs = new_dqs;
2147 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2148 final_dqs_en = start_dqs_en - mid_min;
2151 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2152 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2153 scc_mgr_load_dqs(read_group);
2157 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2158 scc_mgr_load_dqs(read_group);
2159 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2160 dqs_margin=%d", __func__, __LINE__,
2161 dq_margin, dqs_margin);
2164 * Do not remove this line as it makes sure all of our decisions
2165 * have been applied. Apply the update bit.
2167 writel(0, &sdr_scc_mgr->update);
2169 return (dq_margin >= 0) && (dqs_margin >= 0);
2173 * calibrate the read valid prediction FIFO.
2175 * - read valid prediction will consist of finding a good DQS enable phase,
2176 * DQS enable delay, DQS input phase, and DQS input delay.
2177 * - we also do a per-bit deskew on the DQ lines.
2179 static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
2182 uint32_t p, d, rank_bgn, sr;
2183 uint32_t dtaps_per_ptap;
2186 uint32_t grp_calibrated;
2187 uint32_t write_group, write_test_bgn;
2188 uint32_t failed_substage;
2190 debug("%s:%d: %u %u\n", __func__, __LINE__, read_group, test_bgn);
2192 /* update info for sims */
2193 reg_file_set_stage(CAL_STAGE_VFIFO);
2195 write_group = read_group;
2196 write_test_bgn = test_bgn;
2198 /* USER Determine number of delay taps for each phase tap */
2201 while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
2203 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
2208 /* update info for sims */
2209 reg_file_set_group(read_group);
2213 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2214 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2216 for (d = 0; d <= dtaps_per_ptap && grp_calibrated == 0; d += 2) {
2218 * In RLDRAMX we may be messing the delay of pins in
2219 * the same write group but outside of the current read
2220 * the group, but that's ok because we haven't
2221 * calibrated output side yet.
2224 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2228 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
2230 /* set a particular dqdqs phase */
2231 scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
2233 debug_cond(DLEVEL == 1, "%s:%d calibrate_vfifo: g=%u \
2234 p=%u d=%u\n", __func__, __LINE__,
2238 * Load up the patterns used by read calibration
2239 * using current DQDQS phase.
2241 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2242 if (!(gbl->phy_debug_mode_flags &
2243 PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
2244 if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
2245 (read_group, 1, &bit_chk)) {
2246 debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:",
2247 __func__, __LINE__);
2248 debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
2256 if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
2257 (write_group, read_group, test_bgn)) {
2259 * USER Read per-bit deskew can be done on a
2260 * per shadow register basis.
2262 for (rank_bgn = 0, sr = 0;
2263 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2264 rank_bgn += NUM_RANKS_PER_SHADOW_REG,
2267 * Determine if this set of ranks
2268 * should be skipped entirely.
2270 if (!param->skip_shadow_regs[sr]) {
2272 * If doing read after write
2273 * calibration, do not update
2274 * FOM, now - do it then.
2276 if (!rw_mgr_mem_calibrate_vfifo_center
2277 (rank_bgn, write_group,
2278 read_group, test_bgn, 1, 0)) {
2281 CAL_SUBSTAGE_VFIFO_CENTER;
2287 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2292 if (grp_calibrated == 0) {
2293 set_failing_group_stage(write_group, CAL_STAGE_VFIFO,
2299 * Reset the delay chains back to zero if they have moved > 1
2300 * (check for > 1 because loop will increase d even when pass in
2304 scc_mgr_zero_group(write_group, 1);
2309 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2310 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2313 uint32_t rank_bgn, sr;
2314 uint32_t grp_calibrated;
2315 uint32_t write_group;
2317 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2319 /* update info for sims */
2321 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2322 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2324 write_group = read_group;
2326 /* update info for sims */
2327 reg_file_set_group(read_group);
2330 /* Read per-bit deskew can be done on a per shadow register basis */
2331 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2332 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2333 /* Determine if this set of ranks should be skipped entirely */
2334 if (!param->skip_shadow_regs[sr]) {
2335 /* This is the last calibration round, update FOM here */
2336 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2347 if (grp_calibrated == 0) {
2348 set_failing_group_stage(write_group,
2349 CAL_STAGE_VFIFO_AFTER_WRITES,
2350 CAL_SUBSTAGE_VFIFO_CENTER);
2357 /* Calibrate LFIFO to find smallest read latency */
2358 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2363 debug("%s:%d\n", __func__, __LINE__);
2365 /* update info for sims */
2366 reg_file_set_stage(CAL_STAGE_LFIFO);
2367 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2369 /* Load up the patterns used by read calibration for all ranks */
2370 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2374 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2375 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2376 __func__, __LINE__, gbl->curr_read_lat);
2378 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2386 /* reduce read latency and see if things are working */
2388 gbl->curr_read_lat--;
2389 } while (gbl->curr_read_lat > 0);
2391 /* reset the fifos to get pointers to known state */
2393 writel(0, &phy_mgr_cmd->fifo_reset);
2396 /* add a fudge factor to the read latency that was determined */
2397 gbl->curr_read_lat += 2;
2398 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2399 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2400 read_lat=%u\n", __func__, __LINE__,
2401 gbl->curr_read_lat);
2404 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2405 CAL_SUBSTAGE_READ_LATENCY);
2407 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2408 read_lat=%u\n", __func__, __LINE__,
2409 gbl->curr_read_lat);
2415 * issue write test command.
2416 * two variants are provided. one that just tests a write pattern and
2417 * another that tests datamask functionality.
2419 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2422 uint32_t mcc_instruction;
2423 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2424 ENABLE_SUPER_QUICK_CALIBRATION);
2425 uint32_t rw_wl_nop_cycles;
2429 * Set counter and jump addresses for the right
2430 * number of NOP cycles.
2431 * The number of supported NOP cycles can range from -1 to infinity
2432 * Three different cases are handled:
2434 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2435 * mechanism will be used to insert the right number of NOPs
2437 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2438 * issuing the write command will jump straight to the
2439 * micro-instruction that turns on DQS (for DDRx), or outputs write
2440 * data (for RLD), skipping
2441 * the NOP micro-instruction all together
2443 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2444 * turned on in the same micro-instruction that issues the write
2445 * command. Then we need
2446 * to directly jump to the micro-instruction that sends out the data
2448 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2449 * (2 and 3). One jump-counter (0) is used to perform multiple
2450 * write-read operations.
2451 * one counter left to issue this command in "multiple-group" mode
2454 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2456 if (rw_wl_nop_cycles == -1) {
2458 * CNTR 2 - We want to execute the special write operation that
2459 * turns on DQS right away and then skip directly to the
2460 * instruction that sends out the data. We set the counter to a
2461 * large number so that the jump is always taken.
2463 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2465 /* CNTR 3 - Not used */
2467 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2468 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2469 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2470 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2471 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2473 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2474 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2475 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2476 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2477 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2479 } else if (rw_wl_nop_cycles == 0) {
2481 * CNTR 2 - We want to skip the NOP operation and go straight
2482 * to the DQS enable instruction. We set the counter to a large
2483 * number so that the jump is always taken.
2485 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2487 /* CNTR 3 - Not used */
2489 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2490 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2491 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2493 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2494 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2495 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2499 * CNTR 2 - In this case we want to execute the next instruction
2500 * and NOT take the jump. So we set the counter to 0. The jump
2501 * address doesn't count.
2503 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2504 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2507 * CNTR 3 - Set the nop counter to the number of cycles we
2508 * need to loop for, minus 1.
2510 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2512 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2513 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2514 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2516 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2517 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2518 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2522 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2523 RW_MGR_RESET_READ_DATAPATH_OFFSET);
2525 if (quick_write_mode)
2526 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2528 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2530 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2533 * CNTR 1 - This is used to ensure enough time elapses
2534 * for read data to come back.
2536 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2539 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2540 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2542 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2543 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2546 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2547 writel(mcc_instruction, addr + (group << 2));
2550 /* Test writes, can check for a single bit pass or multiple bit pass */
2551 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2552 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2553 uint32_t *bit_chk, uint32_t all_ranks)
2556 uint32_t correct_mask_vg;
2557 uint32_t tmp_bit_chk;
2559 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2560 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2561 uint32_t addr_rw_mgr;
2562 uint32_t base_rw_mgr;
2564 *bit_chk = param->write_correct_mask;
2565 correct_mask_vg = param->write_correct_mask_vg;
2567 for (r = rank_bgn; r < rank_end; r++) {
2568 if (param->skip_ranks[r]) {
2569 /* request to skip the rank */
2574 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2577 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2578 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2579 /* reset the fifos to get pointers to known state */
2580 writel(0, &phy_mgr_cmd->fifo_reset);
2582 tmp_bit_chk = tmp_bit_chk <<
2583 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2584 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2585 rw_mgr_mem_calibrate_write_test_issue(write_group *
2586 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2589 base_rw_mgr = readl(addr_rw_mgr);
2590 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2594 *bit_chk &= tmp_bit_chk;
2598 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2599 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2600 %u => %lu", write_group, use_dm,
2601 *bit_chk, param->write_correct_mask,
2602 (long unsigned int)(*bit_chk ==
2603 param->write_correct_mask));
2604 return *bit_chk == param->write_correct_mask;
2606 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2607 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2608 write_group, use_dm, *bit_chk);
2609 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2610 (long unsigned int)(*bit_chk != 0));
2611 return *bit_chk != 0x00;
2616 * center all windows. do per-bit-deskew to possibly increase size of
2619 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2620 uint32_t write_group, uint32_t test_bgn)
2622 uint32_t i, p, min_index;
2625 * Store these as signed since there are comparisons with
2629 uint32_t sticky_bit_chk;
2630 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2631 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2633 int32_t mid_min, orig_mid_min;
2634 int32_t new_dqs, start_dqs, shift_dq;
2635 int32_t dq_margin, dqs_margin, dm_margin;
2637 uint32_t temp_dq_out1_delay;
2640 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2644 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2645 start_dqs = readl(addr +
2646 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2648 /* per-bit deskew */
2651 * set the left and right edge of each bit to an illegal value
2652 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2655 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2656 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2657 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2660 /* Search for the left edge of the window for each bit */
2661 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2662 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2664 writel(0, &sdr_scc_mgr->update);
2667 * Stop searching when the read test doesn't pass AND when
2668 * we've seen a passing read on every bit.
2670 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2671 0, PASS_ONE_BIT, &bit_chk, 0);
2672 sticky_bit_chk = sticky_bit_chk | bit_chk;
2673 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2674 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2675 == %u && %u [bit_chk= %u ]\n",
2676 d, sticky_bit_chk, param->write_correct_mask,
2682 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2685 * Remember a passing test as the
2691 * If a left edge has not been seen
2692 * yet, then a future passing test will
2693 * mark this edge as the right edge.
2696 IO_IO_OUT1_DELAY_MAX + 1) {
2697 right_edge[i] = -(d + 1);
2700 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2701 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2702 (int)(bit_chk & 1), i, left_edge[i]);
2703 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2705 bit_chk = bit_chk >> 1;
2710 /* Reset DQ delay chains to 0 */
2711 scc_mgr_apply_group_dq_out1_delay(0);
2713 for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2714 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2715 %d right_edge[%u]: %d\n", __func__, __LINE__,
2716 i, left_edge[i], i, right_edge[i]);
2719 * Check for cases where we haven't found the left edge,
2720 * which makes our assignment of the the right edge invalid.
2721 * Reset it to the illegal value.
2723 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2724 (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2725 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2726 debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2727 right_edge[%u]: %d\n", __func__, __LINE__,
2732 * Reset sticky bit (except for bits where we have
2733 * seen the left edge).
2735 sticky_bit_chk = sticky_bit_chk << 1;
2736 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2737 sticky_bit_chk = sticky_bit_chk | 1;
2743 /* Search for the right edge of the window for each bit */
2744 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2745 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2748 writel(0, &sdr_scc_mgr->update);
2751 * Stop searching when the read test doesn't pass AND when
2752 * we've seen a passing read on every bit.
2754 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2755 0, PASS_ONE_BIT, &bit_chk, 0);
2757 sticky_bit_chk = sticky_bit_chk | bit_chk;
2758 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2760 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2761 %u && %u\n", d, sticky_bit_chk,
2762 param->write_correct_mask, stop);
2766 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2768 /* d = 0 failed, but it passed when
2769 testing the left edge, so it must be
2770 marginal, set it to -1 */
2771 if (right_edge[i] ==
2772 IO_IO_OUT1_DELAY_MAX + 1 &&
2774 IO_IO_OUT1_DELAY_MAX + 1) {
2781 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2784 * Remember a passing test as
2791 * If a right edge has not
2792 * been seen yet, then a future
2793 * passing test will mark this
2794 * edge as the left edge.
2796 if (right_edge[i] ==
2797 IO_IO_OUT1_DELAY_MAX + 1)
2798 left_edge[i] = -(d + 1);
2801 * d = 0 failed, but it passed
2802 * when testing the left edge,
2803 * so it must be marginal, set
2806 if (right_edge[i] ==
2807 IO_IO_OUT1_DELAY_MAX + 1 &&
2809 IO_IO_OUT1_DELAY_MAX + 1)
2812 * If a right edge has not been
2813 * seen yet, then a future
2814 * passing test will mark this
2815 * edge as the left edge.
2817 else if (right_edge[i] ==
2818 IO_IO_OUT1_DELAY_MAX +
2820 left_edge[i] = -(d + 1);
2823 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2824 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2825 (int)(bit_chk & 1), i, left_edge[i]);
2826 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2828 bit_chk = bit_chk >> 1;
2833 /* Check that all bits have a window */
2834 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2835 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2836 %d right_edge[%u]: %d", __func__, __LINE__,
2837 i, left_edge[i], i, right_edge[i]);
2838 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2839 (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2840 set_failing_group_stage(test_bgn + i,
2842 CAL_SUBSTAGE_WRITES_CENTER);
2847 /* Find middle of window for each DQ bit */
2848 mid_min = left_edge[0] - right_edge[0];
2850 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2851 mid = left_edge[i] - right_edge[i];
2852 if (mid < mid_min) {
2859 * -mid_min/2 represents the amount that we need to move DQS.
2860 * If mid_min is odd and positive we'll need to add one to
2861 * make sure the rounding in further calculations is correct
2862 * (always bias to the right), so just add 1 for all positive values.
2866 mid_min = mid_min / 2;
2867 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2870 /* Determine the amount we can change DQS (which is -mid_min) */
2871 orig_mid_min = mid_min;
2872 new_dqs = start_dqs;
2874 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2875 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2876 /* Initialize data for export structures */
2877 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2878 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2880 /* add delay to bring centre of all DQ windows to the same "level" */
2881 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2882 /* Use values before divide by 2 to reduce round off error */
2883 shift_dq = (left_edge[i] - right_edge[i] -
2884 (left_edge[min_index] - right_edge[min_index]))/2 +
2885 (orig_mid_min - mid_min);
2887 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2888 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2890 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2891 temp_dq_out1_delay = readl(addr + (i << 2));
2892 if (shift_dq + (int32_t)temp_dq_out1_delay >
2893 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2894 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2895 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2896 shift_dq = -(int32_t)temp_dq_out1_delay;
2898 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2900 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2903 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2904 left_edge[i] - shift_dq + (-mid_min),
2905 right_edge[i] + shift_dq - (-mid_min));
2906 /* To determine values for export structures */
2907 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2908 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2910 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2911 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2915 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2916 writel(0, &sdr_scc_mgr->update);
2919 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2922 * set the left and right edge of each bit to an illegal value,
2923 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2925 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2926 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2927 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2928 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2929 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2930 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2931 int32_t win_best = 0;
2933 /* Search for the/part of the window with DM shift */
2934 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
2935 scc_mgr_apply_group_dm_out1_delay(d);
2936 writel(0, &sdr_scc_mgr->update);
2938 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2939 PASS_ALL_BITS, &bit_chk,
2941 /* USE Set current end of the window */
2944 * If a starting edge of our window has not been seen
2945 * this is our current start of the DM window.
2947 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
2951 * If current window is bigger than best seen.
2952 * Set best seen to be current window.
2954 if ((end_curr-bgn_curr+1) > win_best) {
2955 win_best = end_curr-bgn_curr+1;
2956 bgn_best = bgn_curr;
2957 end_best = end_curr;
2960 /* We just saw a failing test. Reset temp edge */
2961 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2962 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2967 /* Reset DM delay chains to 0 */
2968 scc_mgr_apply_group_dm_out1_delay(0);
2971 * Check to see if the current window nudges up aganist 0 delay.
2972 * If so we need to continue the search by shifting DQS otherwise DQS
2973 * search begins as a new search. */
2974 if (end_curr != 0) {
2975 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2976 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2979 /* Search for the/part of the window with DQS shifts */
2980 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
2982 * Note: This only shifts DQS, so are we limiting ourselve to
2983 * width of DQ unnecessarily.
2985 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2988 writel(0, &sdr_scc_mgr->update);
2989 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2990 PASS_ALL_BITS, &bit_chk,
2992 /* USE Set current end of the window */
2995 * If a beginning edge of our window has not been seen
2996 * this is our current begin of the DM window.
2998 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3002 * If current window is bigger than best seen. Set best
3003 * seen to be current window.
3005 if ((end_curr-bgn_curr+1) > win_best) {
3006 win_best = end_curr-bgn_curr+1;
3007 bgn_best = bgn_curr;
3008 end_best = end_curr;
3011 /* We just saw a failing test. Reset temp edge */
3012 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3013 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3015 /* Early exit optimization: if ther remaining delay
3016 chain space is less than already seen largest window
3019 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3025 /* assign left and right edge for cal and reporting; */
3026 left_edge[0] = -1*bgn_best;
3027 right_edge[0] = end_best;
3029 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3030 __LINE__, left_edge[0], right_edge[0]);
3032 /* Move DQS (back to orig) */
3033 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3037 /* Find middle of window for the DM bit */
3038 mid = (left_edge[0] - right_edge[0]) / 2;
3040 /* only move right, since we are not moving DQS/DQ */
3044 /* dm_marign should fail if we never find a window */
3048 dm_margin = left_edge[0] - mid;
3050 scc_mgr_apply_group_dm_out1_delay(mid);
3051 writel(0, &sdr_scc_mgr->update);
3053 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3054 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3055 right_edge[0], mid, dm_margin);
3057 gbl->fom_out += dq_margin + dqs_margin;
3059 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3060 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3061 dq_margin, dqs_margin, dm_margin);
3064 * Do not remove this line as it makes sure all of our
3065 * decisions have been applied.
3067 writel(0, &sdr_scc_mgr->update);
3068 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3071 /* calibrate the write operations */
3072 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3075 /* update info for sims */
3076 debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3078 reg_file_set_stage(CAL_STAGE_WRITES);
3079 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3081 reg_file_set_group(g);
3083 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3084 set_failing_group_stage(g, CAL_STAGE_WRITES,
3085 CAL_SUBSTAGE_WRITES_CENTER);
3092 /* precharge all banks and activate row 0 in bank "000..." and bank "111..." */
3093 static void mem_precharge_and_activate(void)
3097 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3098 if (param->skip_ranks[r]) {
3099 /* request to skip the rank */
3104 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3106 /* precharge all banks ... */
3107 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3108 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3110 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3111 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3112 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3114 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3115 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3116 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3119 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3120 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3124 /* Configure various memory related parameters. */
3125 static void mem_config(void)
3127 uint32_t rlat, wlat;
3128 uint32_t rw_wl_nop_cycles;
3129 uint32_t max_latency;
3131 debug("%s:%d\n", __func__, __LINE__);
3132 /* read in write and read latency */
3133 wlat = readl(&data_mgr->t_wl_add);
3134 wlat += readl(&data_mgr->mem_t_add);
3136 /* WL for hard phy does not include additive latency */
3139 * add addtional write latency to offset the address/command extra
3140 * clock cycle. We change the AC mux setting causing AC to be delayed
3141 * by one mem clock cycle. Only do this for DDR3
3145 rlat = readl(&data_mgr->t_rl_add);
3147 rw_wl_nop_cycles = wlat - 2;
3148 gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
3151 * For AV/CV, lfifo is hardened and always runs at full rate so
3152 * max latency in AFI clocks, used here, is correspondingly smaller.
3154 max_latency = (1<<MAX_LATENCY_COUNT_WIDTH)/1 - 1;
3155 /* configure for a burst length of 8 */
3158 /* Adjust Write Latency for Hard PHY */
3161 /* set a pretty high read latency initially */
3162 gbl->curr_read_lat = rlat + 16;
3164 if (gbl->curr_read_lat > max_latency)
3165 gbl->curr_read_lat = max_latency;
3167 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3169 /* advertise write latency */
3170 gbl->curr_write_lat = wlat;
3171 writel(wlat - 2, &phy_mgr_cfg->afi_wlat);
3173 /* initialize bit slips */
3174 mem_precharge_and_activate();
3177 /* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */
3178 static void mem_skip_calibrate(void)
3180 uint32_t vfifo_offset;
3183 debug("%s:%d\n", __func__, __LINE__);
3184 /* Need to update every shadow register set used by the interface */
3185 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3186 r += NUM_RANKS_PER_SHADOW_REG) {
3188 * Set output phase alignment settings appropriate for
3191 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3192 scc_mgr_set_dqs_en_phase(i, 0);
3193 #if IO_DLL_CHAIN_LENGTH == 6
3194 scc_mgr_set_dqdqs_output_phase(i, 6);
3196 scc_mgr_set_dqdqs_output_phase(i, 7);
3201 * Write data arrives to the I/O two cycles before write
3202 * latency is reached (720 deg).
3203 * -> due to bit-slip in a/c bus
3204 * -> to allow board skew where dqs is longer than ck
3205 * -> how often can this happen!?
3206 * -> can claim back some ptaps for high freq
3207 * support if we can relax this, but i digress...
3209 * The write_clk leads mem_ck by 90 deg
3210 * The minimum ptap of the OPA is 180 deg
3211 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3212 * The write_clk is always delayed by 2 ptaps
3214 * Hence, to make DQS aligned to CK, we need to delay
3216 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3218 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3219 * gives us the number of ptaps, which simplies to:
3221 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3223 scc_mgr_set_dqdqs_output_phase(i, (1.25 *
3224 IO_DLL_CHAIN_LENGTH - 2));
3226 writel(0xff, &sdr_scc_mgr->dqs_ena);
3227 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3229 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3230 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3231 SCC_MGR_GROUP_COUNTER_OFFSET);
3233 writel(0xff, &sdr_scc_mgr->dq_ena);
3234 writel(0xff, &sdr_scc_mgr->dm_ena);
3235 writel(0, &sdr_scc_mgr->update);
3238 /* Compensate for simulation model behaviour */
3239 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3240 scc_mgr_set_dqs_bus_in_delay(i, 10);
3241 scc_mgr_load_dqs(i);
3243 writel(0, &sdr_scc_mgr->update);
3246 * ArriaV has hard FIFOs that can only be initialized by incrementing
3249 vfifo_offset = CALIB_VFIFO_OFFSET;
3250 for (j = 0; j < vfifo_offset; j++) {
3251 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3253 writel(0, &phy_mgr_cmd->fifo_reset);
3256 * For ACV with hard lfifo, we get the skip-cal setting from
3257 * generation-time constant.
3259 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3260 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3263 /* Memory calibration entry point */
3264 static uint32_t mem_calibrate(void)
3267 uint32_t rank_bgn, sr;
3268 uint32_t write_group, write_test_bgn;
3269 uint32_t read_group, read_test_bgn;
3270 uint32_t run_groups, current_run;
3271 uint32_t failing_groups = 0;
3272 uint32_t group_failed = 0;
3273 uint32_t sr_failed = 0;
3275 debug("%s:%d\n", __func__, __LINE__);
3276 /* Initialize the data settings */
3278 gbl->error_substage = CAL_SUBSTAGE_NIL;
3279 gbl->error_stage = CAL_STAGE_NIL;
3280 gbl->error_group = 0xff;
3286 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3287 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3288 SCC_MGR_GROUP_COUNTER_OFFSET);
3289 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3291 scc_mgr_set_hhp_extras();
3293 scc_set_bypass_mode(i);
3296 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3298 * Set VFIFO and LFIFO to instant-on settings in skip
3301 mem_skip_calibrate();
3303 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3305 * Zero all delay chain/phase settings for all
3306 * groups and all shadow register sets.
3310 run_groups = ~param->skip_groups;
3312 for (write_group = 0, write_test_bgn = 0; write_group
3313 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3314 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3315 /* Initialized the group failure */
3318 current_run = run_groups & ((1 <<
3319 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3320 run_groups = run_groups >>
3321 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3323 if (current_run == 0)
3326 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3327 SCC_MGR_GROUP_COUNTER_OFFSET);
3328 scc_mgr_zero_group(write_group, 0);
3330 for (read_group = write_group *
3331 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3332 RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3334 read_group < (write_group + 1) *
3335 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3336 RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3338 read_group++, read_test_bgn +=
3339 RW_MGR_MEM_DQ_PER_READ_DQS) {
3340 /* Calibrate the VFIFO */
3341 if (!((STATIC_CALIB_STEPS) &
3342 CALIB_SKIP_VFIFO)) {
3343 if (!rw_mgr_mem_calibrate_vfifo
3349 phy_debug_mode_flags &
3350 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3357 /* Calibrate the output side */
3358 if (group_failed == 0) {
3359 for (rank_bgn = 0, sr = 0; rank_bgn
3360 < RW_MGR_MEM_NUMBER_OF_RANKS;
3362 NUM_RANKS_PER_SHADOW_REG,
3365 if (!((STATIC_CALIB_STEPS) &
3366 CALIB_SKIP_WRITES)) {
3367 if ((STATIC_CALIB_STEPS)
3368 & CALIB_SKIP_DELAY_SWEEPS) {
3369 /* not needed in quick mode! */
3372 * Determine if this set of
3373 * ranks should be skipped
3376 if (!param->skip_shadow_regs[sr]) {
3377 if (!rw_mgr_mem_calibrate_writes
3378 (rank_bgn, write_group,
3382 phy_debug_mode_flags &
3383 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3395 if (group_failed == 0) {
3396 for (read_group = write_group *
3397 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3398 RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3400 read_group < (write_group + 1)
3401 * RW_MGR_MEM_IF_READ_DQS_WIDTH
3402 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3404 read_group++, read_test_bgn +=
3405 RW_MGR_MEM_DQ_PER_READ_DQS) {
3406 if (!((STATIC_CALIB_STEPS) &
3407 CALIB_SKIP_WRITES)) {
3408 if (!rw_mgr_mem_calibrate_vfifo_end
3409 (read_group, read_test_bgn)) {
3412 if (!(gbl->phy_debug_mode_flags
3413 & PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3421 if (group_failed != 0)
3426 * USER If there are any failing groups then report
3429 if (failing_groups != 0)
3432 /* Calibrate the LFIFO */
3433 if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) {
3435 * If we're skipping groups as part of debug,
3436 * don't calibrate LFIFO.
3438 if (param->skip_groups == 0) {
3439 if (!rw_mgr_mem_calibrate_lfifo())
3447 * Do not remove this line as it makes sure all of our decisions
3448 * have been applied.
3450 writel(0, &sdr_scc_mgr->update);
3454 static uint32_t run_mem_calibrate(void)
3457 uint32_t debug_info;
3459 debug("%s:%d\n", __func__, __LINE__);
3461 /* Reset pass/fail status shown on afi_cal_success/fail */
3462 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3464 /* stop tracking manger */
3465 uint32_t ctrlcfg = readl(&sdr_ctrl->ctrl_cfg);
3467 writel(ctrlcfg & 0xFFBFFFFF, &sdr_ctrl->ctrl_cfg);
3470 rw_mgr_mem_initialize();
3472 pass = mem_calibrate();
3474 mem_precharge_and_activate();
3475 writel(0, &phy_mgr_cmd->fifo_reset);
3479 * Don't return control of the PHY back to AFI when in debug mode.
3481 if ((gbl->phy_debug_mode_flags & PHY_DEBUG_IN_DEBUG_MODE) == 0) {
3482 rw_mgr_mem_handoff();
3484 * In Hard PHY this is a 2-bit control:
3486 * 1: DDIO Mux Select
3488 writel(0x2, &phy_mgr_cfg->mux_sel);
3491 writel(ctrlcfg, &sdr_ctrl->ctrl_cfg);
3494 printf("%s: CALIBRATION PASSED\n", __FILE__);
3499 if (gbl->fom_in > 0xff)
3502 if (gbl->fom_out > 0xff)
3503 gbl->fom_out = 0xff;
3505 /* Update the FOM in the register file */
3506 debug_info = gbl->fom_in;
3507 debug_info |= gbl->fom_out << 8;
3508 writel(debug_info, &sdr_reg_file->fom);
3510 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3511 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3513 printf("%s: CALIBRATION FAILED\n", __FILE__);
3515 debug_info = gbl->error_stage;
3516 debug_info |= gbl->error_substage << 8;
3517 debug_info |= gbl->error_group << 16;
3519 writel(debug_info, &sdr_reg_file->failing_stage);
3520 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3521 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3523 /* Update the failing group/stage in the register file */
3524 debug_info = gbl->error_stage;
3525 debug_info |= gbl->error_substage << 8;
3526 debug_info |= gbl->error_group << 16;
3527 writel(debug_info, &sdr_reg_file->failing_stage);
3534 * hc_initialize_rom_data() - Initialize ROM data
3536 * Initialize ROM data.
3538 static void hc_initialize_rom_data(void)
3542 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3543 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3544 writel(inst_rom_init[i], addr + (i << 2));
3546 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3547 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3548 writel(ac_rom_init[i], addr + (i << 2));
3552 * initialize_reg_file() - Initialize SDR register file
3554 * Initialize SDR register file.
3556 static void initialize_reg_file(void)
3558 /* Initialize the register file with the correct data */
3559 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3560 writel(0, &sdr_reg_file->debug_data_addr);
3561 writel(0, &sdr_reg_file->cur_stage);
3562 writel(0, &sdr_reg_file->fom);
3563 writel(0, &sdr_reg_file->failing_stage);
3564 writel(0, &sdr_reg_file->debug1);
3565 writel(0, &sdr_reg_file->debug2);
3569 * initialize_hps_phy() - Initialize HPS PHY
3571 * Initialize HPS PHY.
3573 static void initialize_hps_phy(void)
3577 * Tracking also gets configured here because it's in the
3580 uint32_t trk_sample_count = 7500;
3581 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3583 * Format is number of outer loops in the 16 MSB, sample
3588 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3589 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3590 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3591 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3592 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3593 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3595 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3596 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3598 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3599 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3601 writel(reg, &sdr_ctrl->phy_ctrl0);
3604 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3606 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3607 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3608 trk_long_idle_sample_count);
3609 writel(reg, &sdr_ctrl->phy_ctrl1);
3612 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3613 trk_long_idle_sample_count >>
3614 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3615 writel(reg, &sdr_ctrl->phy_ctrl2);
3618 static void initialize_tracking(void)
3620 uint32_t concatenated_longidle = 0x0;
3621 uint32_t concatenated_delays = 0x0;
3622 uint32_t concatenated_rw_addr = 0x0;
3623 uint32_t concatenated_refresh = 0x0;
3624 uint32_t trk_sample_count = 7500;
3625 uint32_t dtaps_per_ptap;
3629 * compute usable version of value in case we skip full
3634 while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
3636 tmp_delay += IO_DELAY_PER_DCHAIN_TAP;
3640 concatenated_longidle = concatenated_longidle ^ 10;
3641 /*longidle outer loop */
3642 concatenated_longidle = concatenated_longidle << 16;
3643 concatenated_longidle = concatenated_longidle ^ 100;
3644 /*longidle sample count */
3645 concatenated_delays = concatenated_delays ^ 243;
3646 /* trfc, worst case of 933Mhz 4Gb */
3647 concatenated_delays = concatenated_delays << 8;
3648 concatenated_delays = concatenated_delays ^ 14;
3649 /* trcd, worst case */
3650 concatenated_delays = concatenated_delays << 8;
3651 concatenated_delays = concatenated_delays ^ 10;
3653 concatenated_delays = concatenated_delays << 8;
3654 concatenated_delays = concatenated_delays ^ 4;
3657 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_IDLE;
3658 concatenated_rw_addr = concatenated_rw_addr << 8;
3659 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_ACTIVATE_1;
3660 concatenated_rw_addr = concatenated_rw_addr << 8;
3661 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_SGLE_READ;
3662 concatenated_rw_addr = concatenated_rw_addr << 8;
3663 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_PRECHARGE_ALL;
3665 concatenated_refresh = concatenated_refresh ^ RW_MGR_REFRESH_ALL;
3666 concatenated_refresh = concatenated_refresh << 24;
3667 concatenated_refresh = concatenated_refresh ^ 1000; /* trefi */
3669 /* Initialize the register file with the correct data */
3670 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
3671 writel(trk_sample_count, &sdr_reg_file->trk_sample_count);
3672 writel(concatenated_longidle, &sdr_reg_file->trk_longidle);
3673 writel(concatenated_delays, &sdr_reg_file->delays);
3674 writel(concatenated_rw_addr, &sdr_reg_file->trk_rw_mgr_addr);
3675 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, &sdr_reg_file->trk_read_dqs_width);
3676 writel(concatenated_refresh, &sdr_reg_file->trk_rfsh);
3679 int sdram_calibration_full(void)
3681 struct param_type my_param;
3682 struct gbl_type my_gbl;
3689 /* Initialize the debug mode flags */
3690 gbl->phy_debug_mode_flags = 0;
3691 /* Set the calibration enabled by default */
3692 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3694 * Only sweep all groups (regardless of fail state) by default
3695 * Set enabled read test by default.
3697 #if DISABLE_GUARANTEED_READ
3698 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3700 /* Initialize the register file */
3701 initialize_reg_file();
3703 /* Initialize any PHY CSR */
3704 initialize_hps_phy();
3706 scc_mgr_initialize();
3708 initialize_tracking();
3710 /* USER Enable all ranks, groups */
3711 for (i = 0; i < RW_MGR_MEM_NUMBER_OF_RANKS; i++)
3712 param->skip_ranks[i] = 0;
3713 for (i = 0; i < NUM_SHADOW_REGS; ++i)
3714 param->skip_shadow_regs[i] = 0;
3715 param->skip_groups = 0;
3717 printf("%s: Preparing to start memory calibration\n", __FILE__);
3719 debug("%s:%d\n", __func__, __LINE__);
3720 debug_cond(DLEVEL == 1,
3721 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3722 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3723 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3724 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3725 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3726 debug_cond(DLEVEL == 1,
3727 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3728 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3729 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3730 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3731 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3732 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3733 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3734 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3735 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3736 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3737 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3738 IO_IO_OUT2_DELAY_MAX);
3739 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3740 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3742 hc_initialize_rom_data();
3744 /* update info for sims */
3745 reg_file_set_stage(CAL_STAGE_NIL);
3746 reg_file_set_group(0);
3749 * Load global needed for those actions that require
3750 * some dynamic calibration support.
3752 dyn_calib_steps = STATIC_CALIB_STEPS;
3754 * Load global to allow dynamic selection of delay loop settings
3755 * based on calibration mode.
3757 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3758 skip_delay_mask = 0xff;
3760 skip_delay_mask = 0x0;
3762 pass = run_mem_calibrate();
3764 printf("%s: Calibration complete\n", __FILE__);