1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright Altera Corporation (C) 2012-2015
8 #include <asm/arch/sdram.h>
10 #include "sequencer.h"
12 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
13 (struct socfpga_sdr_rw_load_manager *)
14 (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
15 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
16 (struct socfpga_sdr_rw_load_jump_manager *)
17 (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
18 static struct socfpga_sdr_reg_file *sdr_reg_file =
19 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
20 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
21 (struct socfpga_sdr_scc_mgr *)
22 (SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
23 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
24 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
25 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
26 (struct socfpga_phy_mgr_cfg *)
27 (SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
28 static struct socfpga_data_mgr *data_mgr =
29 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
30 static struct socfpga_sdr_ctrl *sdr_ctrl =
31 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
33 const struct socfpga_sdram_rw_mgr_config *rwcfg;
34 const struct socfpga_sdram_io_config *iocfg;
35 const struct socfpga_sdram_misc_config *misccfg;
40 * In order to reduce ROM size, most of the selectable calibration steps are
41 * decided at compile time based on the user's calibration mode selection,
42 * as captured by the STATIC_CALIB_STEPS selection below.
44 * However, to support simulation-time selection of fast simulation mode, where
45 * we skip everything except the bare minimum, we need a few of the steps to
46 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
47 * check, which is based on the rtl-supplied value, or we dynamically compute
48 * the value to use based on the dynamically-chosen calibration mode
52 #define STATIC_IN_RTL_SIM 0
53 #define STATIC_SKIP_DELAY_LOOPS 0
55 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
56 STATIC_SKIP_DELAY_LOOPS)
58 /* calibration steps requested by the rtl */
59 static u16 dyn_calib_steps;
62 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
63 * instead of static, we use boolean logic to select between
64 * non-skip and skip values
66 * The mask is set to include all bits when not-skipping, but is
70 static u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
72 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
73 ((non_skip_value) & skip_delay_mask)
75 static struct gbl_type *gbl;
76 static struct param_type *param;
78 static void set_failing_group_stage(u32 group, u32 stage,
82 * Only set the global stage if there was not been any other
85 if (gbl->error_stage == CAL_STAGE_NIL) {
86 gbl->error_substage = substage;
87 gbl->error_stage = stage;
88 gbl->error_group = group;
92 static void reg_file_set_group(u16 set_group)
94 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
97 static void reg_file_set_stage(u8 set_stage)
99 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
102 static void reg_file_set_sub_stage(u8 set_sub_stage)
104 set_sub_stage &= 0xff;
105 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
109 * phy_mgr_initialize() - Initialize PHY Manager
111 * Initialize PHY Manager.
113 static void phy_mgr_initialize(void)
117 debug("%s:%d\n", __func__, __LINE__);
118 /* Calibration has control over path to memory */
120 * In Hard PHY this is a 2-bit control:
124 writel(0x3, &phy_mgr_cfg->mux_sel);
126 /* USER memory clock is not stable we begin initialization */
127 writel(0, &phy_mgr_cfg->reset_mem_stbl);
129 /* USER calibration status all set to zero */
130 writel(0, &phy_mgr_cfg->cal_status);
132 writel(0, &phy_mgr_cfg->cal_debug_info);
134 /* Init params only if we do NOT skip calibration. */
135 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
138 ratio = rwcfg->mem_dq_per_read_dqs /
139 rwcfg->mem_virtual_groups_per_read_dqs;
140 param->read_correct_mask_vg = (1 << ratio) - 1;
141 param->write_correct_mask_vg = (1 << ratio) - 1;
142 param->read_correct_mask = (1 << rwcfg->mem_dq_per_read_dqs) - 1;
143 param->write_correct_mask = (1 << rwcfg->mem_dq_per_write_dqs) - 1;
147 * set_rank_and_odt_mask() - Set Rank and ODT mask
149 * @odt_mode: ODT mode, OFF or READ_WRITE
151 * Set Rank and ODT mask (On-Die Termination).
153 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
159 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
162 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
163 switch (rwcfg->mem_number_of_ranks) {
165 /* Read: ODT = 0 ; Write: ODT = 1 */
169 case 2: /* 2 Ranks */
170 if (rwcfg->mem_number_of_cs_per_dimm == 1) {
172 * - Dual-Slot , Single-Rank (1 CS per DIMM)
174 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
176 * Since MEM_NUMBER_OF_RANKS is 2, they
177 * are both single rank with 2 CS each
178 * (special for RDIMM).
180 * Read: Turn on ODT on the opposite rank
181 * Write: Turn on ODT on all ranks
183 odt_mask_0 = 0x3 & ~(1 << rank);
187 * - Single-Slot , Dual-Rank (2 CS per DIMM)
189 * Read: Turn on ODT off on all ranks
190 * Write: Turn on ODT on active rank
193 odt_mask_1 = 0x3 & (1 << rank);
196 case 4: /* 4 Ranks */
198 * ----------+-----------------------+
200 * Read From +-----------------------+
201 * Rank | 3 | 2 | 1 | 0 |
202 * ----------+-----+-----+-----+-----+
203 * 0 | 0 | 1 | 0 | 0 |
204 * 1 | 1 | 0 | 0 | 0 |
205 * 2 | 0 | 0 | 0 | 1 |
206 * 3 | 0 | 0 | 1 | 0 |
207 * ----------+-----+-----+-----+-----+
210 * ----------+-----------------------+
212 * Write To +-----------------------+
213 * Rank | 3 | 2 | 1 | 0 |
214 * ----------+-----+-----+-----+-----+
215 * 0 | 0 | 1 | 0 | 1 |
216 * 1 | 1 | 0 | 1 | 0 |
217 * 2 | 0 | 1 | 0 | 1 |
218 * 3 | 1 | 0 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
243 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
244 ((0xFF & odt_mask_0) << 8) |
245 ((0xFF & odt_mask_1) << 16);
246 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
247 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
251 * scc_mgr_set() - Set SCC Manager register
252 * @off: Base offset in SCC Manager space
253 * @grp: Read/Write group
254 * @val: Value to be set
256 * This function sets the SCC Manager (Scan Chain Control Manager) register.
258 static void scc_mgr_set(u32 off, u32 grp, u32 val)
260 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
264 * scc_mgr_initialize() - Initialize SCC Manager registers
266 * Initialize SCC Manager registers.
268 static void scc_mgr_initialize(void)
271 * Clear register file for HPS. 16 (2^4) is the size of the
272 * full register file in the scc mgr:
273 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
274 * MEM_IF_READ_DQS_WIDTH - 1);
278 for (i = 0; i < 16; i++) {
279 debug_cond(DLEVEL >= 1, "%s:%d: Clearing SCC RFILE index %u\n",
280 __func__, __LINE__, i);
281 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0);
285 static void scc_mgr_set_dqdqs_output_phase(u32 write_group, u32 phase)
287 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
290 static void scc_mgr_set_dqs_bus_in_delay(u32 read_group, u32 delay)
292 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
295 static void scc_mgr_set_dqs_en_phase(u32 read_group, u32 phase)
297 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
300 static void scc_mgr_set_dqs_en_delay(u32 read_group, u32 delay)
302 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
305 static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
307 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
310 static void scc_mgr_set_dqs_io_in_delay(u32 delay)
312 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
316 static void scc_mgr_set_dm_in_delay(u32 dm, u32 delay)
318 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET,
319 rwcfg->mem_dq_per_write_dqs + 1 + dm,
323 static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay)
325 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
328 static void scc_mgr_set_dqs_out1_delay(u32 delay)
330 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
334 static void scc_mgr_set_dm_out1_delay(u32 dm, u32 delay)
336 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
337 rwcfg->mem_dq_per_write_dqs + 1 + dm,
341 /* load up dqs config settings */
342 static void scc_mgr_load_dqs(u32 dqs)
344 writel(dqs, &sdr_scc_mgr->dqs_ena);
347 /* load up dqs io config settings */
348 static void scc_mgr_load_dqs_io(void)
350 writel(0, &sdr_scc_mgr->dqs_io_ena);
353 /* load up dq config settings */
354 static void scc_mgr_load_dq(u32 dq_in_group)
356 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
359 /* load up dm config settings */
360 static void scc_mgr_load_dm(u32 dm)
362 writel(dm, &sdr_scc_mgr->dm_ena);
366 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
367 * @off: Base offset in SCC Manager space
368 * @grp: Read/Write group
369 * @val: Value to be set
370 * @update: If non-zero, trigger SCC Manager update for all ranks
372 * This function sets the SCC Manager (Scan Chain Control Manager) register
373 * and optionally triggers the SCC update for all ranks.
375 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
380 for (r = 0; r < rwcfg->mem_number_of_ranks;
381 r += NUM_RANKS_PER_SHADOW_REG) {
382 scc_mgr_set(off, grp, val);
384 if (update || (r == 0)) {
385 writel(grp, &sdr_scc_mgr->dqs_ena);
386 writel(0, &sdr_scc_mgr->update);
391 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
394 * USER although the h/w doesn't support different phases per
395 * shadow register, for simplicity our scc manager modeling
396 * keeps different phase settings per shadow reg, and it's
397 * important for us to keep them in sync to match h/w.
398 * for efficiency, the scan chain update should occur only
401 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
402 read_group, phase, 0);
405 static void scc_mgr_set_dqdqs_output_phase_all_ranks(u32 write_group,
409 * USER although the h/w doesn't support different phases per
410 * shadow register, for simplicity our scc manager modeling
411 * keeps different phase settings per shadow reg, and it's
412 * important for us to keep them in sync to match h/w.
413 * for efficiency, the scan chain update should occur only
416 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
417 write_group, phase, 0);
420 static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group,
424 * In shadow register mode, the T11 settings are stored in
425 * registers in the core, which are updated by the DQS_ENA
426 * signals. Not issuing the SCC_MGR_UPD command allows us to
427 * save lots of rank switching overhead, by calling
428 * select_shadow_regs_for_update with update_scan_chains
431 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
432 read_group, delay, 1);
436 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
437 * @write_group: Write group
438 * @delay: Delay value
440 * This function sets the OCT output delay in SCC manager.
442 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
444 const int ratio = rwcfg->mem_if_read_dqs_width /
445 rwcfg->mem_if_write_dqs_width;
446 const int base = write_group * ratio;
449 * Load the setting in the SCC manager
450 * Although OCT affects only write data, the OCT delay is controlled
451 * by the DQS logic block which is instantiated once per read group.
452 * For protocols where a write group consists of multiple read groups,
453 * the setting must be set multiple times.
455 for (i = 0; i < ratio; i++)
456 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
460 * scc_mgr_set_hhp_extras() - Set HHP extras.
462 * Load the fixed setting in the SCC manager HHP extras.
464 static void scc_mgr_set_hhp_extras(void)
467 * Load the fixed setting in the SCC manager
468 * bits: 0:0 = 1'b1 - DQS bypass
469 * bits: 1:1 = 1'b1 - DQ bypass
470 * bits: 4:2 = 3'b001 - rfifo_mode
471 * bits: 6:5 = 2'b01 - rfifo clock_select
472 * bits: 7:7 = 1'b0 - separate gating from ungating setting
473 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
475 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
476 (1 << 2) | (1 << 1) | (1 << 0);
477 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
478 SCC_MGR_HHP_GLOBALS_OFFSET |
479 SCC_MGR_HHP_EXTRAS_OFFSET;
481 debug_cond(DLEVEL >= 1, "%s:%d Setting HHP Extras\n",
484 debug_cond(DLEVEL >= 1, "%s:%d Done Setting HHP Extras\n",
489 * scc_mgr_zero_all() - Zero all DQS config
491 * Zero all DQS config.
493 static void scc_mgr_zero_all(void)
498 * USER Zero all DQS config settings, across all groups and all
501 for (r = 0; r < rwcfg->mem_number_of_ranks;
502 r += NUM_RANKS_PER_SHADOW_REG) {
503 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
505 * The phases actually don't exist on a per-rank basis,
506 * but there's no harm updating them several times, so
507 * let's keep the code simple.
509 scc_mgr_set_dqs_bus_in_delay(i, iocfg->dqs_in_reserve);
510 scc_mgr_set_dqs_en_phase(i, 0);
511 scc_mgr_set_dqs_en_delay(i, 0);
514 for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) {
515 scc_mgr_set_dqdqs_output_phase(i, 0);
516 /* Arria V/Cyclone V don't have out2. */
517 scc_mgr_set_oct_out1_delay(i, iocfg->dqs_out_reserve);
521 /* Multicast to all DQS group enables. */
522 writel(0xff, &sdr_scc_mgr->dqs_ena);
523 writel(0, &sdr_scc_mgr->update);
527 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
528 * @write_group: Write group
530 * Set bypass mode and trigger SCC update.
532 static void scc_set_bypass_mode(const u32 write_group)
534 /* Multicast to all DQ enables. */
535 writel(0xff, &sdr_scc_mgr->dq_ena);
536 writel(0xff, &sdr_scc_mgr->dm_ena);
538 /* Update current DQS IO enable. */
539 writel(0, &sdr_scc_mgr->dqs_io_ena);
541 /* Update the DQS logic. */
542 writel(write_group, &sdr_scc_mgr->dqs_ena);
545 writel(0, &sdr_scc_mgr->update);
549 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
550 * @write_group: Write group
552 * Load DQS settings for Write Group, do not trigger SCC update.
554 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
556 const int ratio = rwcfg->mem_if_read_dqs_width /
557 rwcfg->mem_if_write_dqs_width;
558 const int base = write_group * ratio;
561 * Load the setting in the SCC manager
562 * Although OCT affects only write data, the OCT delay is controlled
563 * by the DQS logic block which is instantiated once per read group.
564 * For protocols where a write group consists of multiple read groups,
565 * the setting must be set multiple times.
567 for (i = 0; i < ratio; i++)
568 writel(base + i, &sdr_scc_mgr->dqs_ena);
572 * scc_mgr_zero_group() - Zero all configs for a group
574 * Zero DQ, DM, DQS and OCT configs for a group.
576 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
580 for (r = 0; r < rwcfg->mem_number_of_ranks;
581 r += NUM_RANKS_PER_SHADOW_REG) {
582 /* Zero all DQ config settings. */
583 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
584 scc_mgr_set_dq_out1_delay(i, 0);
586 scc_mgr_set_dq_in_delay(i, 0);
589 /* Multicast to all DQ enables. */
590 writel(0xff, &sdr_scc_mgr->dq_ena);
592 /* Zero all DM config settings. */
593 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
595 scc_mgr_set_dm_in_delay(i, 0);
596 scc_mgr_set_dm_out1_delay(i, 0);
599 /* Multicast to all DM enables. */
600 writel(0xff, &sdr_scc_mgr->dm_ena);
602 /* Zero all DQS IO settings. */
604 scc_mgr_set_dqs_io_in_delay(0);
606 /* Arria V/Cyclone V don't have out2. */
607 scc_mgr_set_dqs_out1_delay(iocfg->dqs_out_reserve);
608 scc_mgr_set_oct_out1_delay(write_group, iocfg->dqs_out_reserve);
609 scc_mgr_load_dqs_for_write_group(write_group);
611 /* Multicast to all DQS IO enables (only 1 in total). */
612 writel(0, &sdr_scc_mgr->dqs_io_ena);
614 /* Hit update to zero everything. */
615 writel(0, &sdr_scc_mgr->update);
620 * apply and load a particular input delay for the DQ pins in a group
621 * group_bgn is the index of the first dq pin (in the write group)
623 static void scc_mgr_apply_group_dq_in_delay(u32 group_bgn, u32 delay)
627 for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) {
628 scc_mgr_set_dq_in_delay(p, delay);
634 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
635 * @delay: Delay value
637 * Apply and load a particular output delay for the DQ pins in a group.
639 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
643 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
644 scc_mgr_set_dq_out1_delay(i, delay);
649 /* apply and load a particular output delay for the DM pins in a group */
650 static void scc_mgr_apply_group_dm_out1_delay(u32 delay1)
654 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
655 scc_mgr_set_dm_out1_delay(i, delay1);
661 /* apply and load delay on both DQS and OCT out1 */
662 static void scc_mgr_apply_group_dqs_io_and_oct_out1(u32 write_group,
665 scc_mgr_set_dqs_out1_delay(delay);
666 scc_mgr_load_dqs_io();
668 scc_mgr_set_oct_out1_delay(write_group, delay);
669 scc_mgr_load_dqs_for_write_group(write_group);
673 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
674 * @write_group: Write group
675 * @delay: Delay value
677 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
679 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
685 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++)
689 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
693 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
694 if (new_delay > iocfg->io_out2_delay_max) {
695 debug_cond(DLEVEL >= 1,
696 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
697 __func__, __LINE__, write_group, delay, new_delay,
698 iocfg->io_out2_delay_max,
699 new_delay - iocfg->io_out2_delay_max);
700 new_delay -= iocfg->io_out2_delay_max;
701 scc_mgr_set_dqs_out1_delay(new_delay);
704 scc_mgr_load_dqs_io();
707 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
708 if (new_delay > iocfg->io_out2_delay_max) {
709 debug_cond(DLEVEL >= 1,
710 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
711 __func__, __LINE__, write_group, delay,
712 new_delay, iocfg->io_out2_delay_max,
713 new_delay - iocfg->io_out2_delay_max);
714 new_delay -= iocfg->io_out2_delay_max;
715 scc_mgr_set_oct_out1_delay(write_group, new_delay);
718 scc_mgr_load_dqs_for_write_group(write_group);
722 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
723 * @write_group: Write group
724 * @delay: Delay value
726 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
729 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
734 for (r = 0; r < rwcfg->mem_number_of_ranks;
735 r += NUM_RANKS_PER_SHADOW_REG) {
736 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
737 writel(0, &sdr_scc_mgr->update);
742 * set_jump_as_return() - Return instruction optimization
744 * Optimization used to recover some slots in ddr3 inst_rom could be
745 * applied to other protocols if we wanted to
747 static void set_jump_as_return(void)
750 * To save space, we replace return with jump to special shared
751 * RETURN instruction so we set the counter to large value so that
754 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
755 writel(rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
759 * delay_for_n_mem_clocks() - Delay for N memory clocks
760 * @clocks: Length of the delay
762 * Delay for N memory clocks.
764 static void delay_for_n_mem_clocks(const u32 clocks)
771 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
773 /* Scale (rounding up) to get afi clocks. */
774 afi_clocks = DIV_ROUND_UP(clocks, misccfg->afi_rate_ratio);
775 if (afi_clocks) /* Temporary underflow protection */
779 * Note, we don't bother accounting for being off a little
780 * bit because of a few extra instructions in outer loops.
781 * Note, the loops have a test at the end, and do the test
782 * before the decrement, and so always perform the loop
783 * 1 time more than the counter value
785 c_loop = afi_clocks >> 16;
786 outer = c_loop ? 0xff : (afi_clocks >> 8);
787 inner = outer ? 0xff : afi_clocks;
790 * rom instructions are structured as follows:
792 * IDLE_LOOP2: jnz cntr0, TARGET_A
793 * IDLE_LOOP1: jnz cntr1, TARGET_B
796 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
797 * TARGET_B is set to IDLE_LOOP2 as well
799 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
800 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
802 * a little confusing, but it helps save precious space in the inst_rom
803 * and sequencer rom and keeps the delays more accurate and reduces
806 if (afi_clocks < 0x100) {
807 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
808 &sdr_rw_load_mgr_regs->load_cntr1);
810 writel(rwcfg->idle_loop1,
811 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
813 writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
814 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
816 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
817 &sdr_rw_load_mgr_regs->load_cntr0);
819 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
820 &sdr_rw_load_mgr_regs->load_cntr1);
822 writel(rwcfg->idle_loop2,
823 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
825 writel(rwcfg->idle_loop2,
826 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
829 writel(rwcfg->idle_loop2,
830 SDR_PHYGRP_RWMGRGRP_ADDRESS |
831 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
832 } while (c_loop-- != 0);
834 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
838 * rw_mgr_mem_init_load_regs() - Load instruction registers
839 * @cntr0: Counter 0 value
840 * @cntr1: Counter 1 value
841 * @cntr2: Counter 2 value
842 * @jump: Jump instruction value
844 * Load instruction registers.
846 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
848 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
849 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
852 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
853 &sdr_rw_load_mgr_regs->load_cntr0);
854 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
855 &sdr_rw_load_mgr_regs->load_cntr1);
856 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
857 &sdr_rw_load_mgr_regs->load_cntr2);
859 /* Load jump address */
860 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
861 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
862 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
864 /* Execute count instruction */
865 writel(jump, grpaddr);
869 * rw_mgr_mem_load_user() - Load user calibration values
870 * @fin1: Final instruction 1
871 * @fin2: Final instruction 2
872 * @precharge: If 1, precharge the banks at the end
874 * Load user calibration values and optionally precharge the banks.
876 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
879 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
880 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
883 for (r = 0; r < rwcfg->mem_number_of_ranks; r++) {
885 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
887 /* precharge all banks ... */
889 writel(rwcfg->precharge_all, grpaddr);
892 * USER Use Mirror-ed commands for odd ranks if address
895 if ((rwcfg->mem_address_mirroring >> r) & 0x1) {
896 set_jump_as_return();
897 writel(rwcfg->mrs2_mirr, grpaddr);
898 delay_for_n_mem_clocks(4);
899 set_jump_as_return();
900 writel(rwcfg->mrs3_mirr, grpaddr);
901 delay_for_n_mem_clocks(4);
902 set_jump_as_return();
903 writel(rwcfg->mrs1_mirr, grpaddr);
904 delay_for_n_mem_clocks(4);
905 set_jump_as_return();
906 writel(fin1, grpaddr);
908 set_jump_as_return();
909 writel(rwcfg->mrs2, grpaddr);
910 delay_for_n_mem_clocks(4);
911 set_jump_as_return();
912 writel(rwcfg->mrs3, grpaddr);
913 delay_for_n_mem_clocks(4);
914 set_jump_as_return();
915 writel(rwcfg->mrs1, grpaddr);
916 set_jump_as_return();
917 writel(fin2, grpaddr);
923 set_jump_as_return();
924 writel(rwcfg->zqcl, grpaddr);
926 /* tZQinit = tDLLK = 512 ck cycles */
927 delay_for_n_mem_clocks(512);
932 * rw_mgr_mem_initialize() - Initialize RW Manager
934 * Initialize RW Manager.
936 static void rw_mgr_mem_initialize(void)
938 debug("%s:%d\n", __func__, __LINE__);
940 /* The reset / cke part of initialization is broadcasted to all ranks */
941 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
942 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
945 * Here's how you load register for a loop
946 * Counters are located @ 0x800
947 * Jump address are located @ 0xC00
948 * For both, registers 0 to 3 are selected using bits 3 and 2, like
949 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
950 * I know this ain't pretty, but Avalon bus throws away the 2 least
954 /* Start with memory RESET activated */
959 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
960 * If a and b are the number of iteration in 2 nested loops
961 * it takes the following number of cycles to complete the operation:
962 * number_of_cycles = ((2 + n) * a + 2) * b
963 * where n is the number of instruction in the inner loop
964 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
967 rw_mgr_mem_init_load_regs(misccfg->tinit_cntr0_val,
968 misccfg->tinit_cntr1_val,
969 misccfg->tinit_cntr2_val,
970 rwcfg->init_reset_0_cke_0);
972 /* Indicate that memory is stable. */
973 writel(1, &phy_mgr_cfg->reset_mem_stbl);
976 * transition the RESET to high
981 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
982 * If a and b are the number of iteration in 2 nested loops
983 * it takes the following number of cycles to complete the operation
984 * number_of_cycles = ((2 + n) * a + 2) * b
985 * where n is the number of instruction in the inner loop
986 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
989 rw_mgr_mem_init_load_regs(misccfg->treset_cntr0_val,
990 misccfg->treset_cntr1_val,
991 misccfg->treset_cntr2_val,
992 rwcfg->init_reset_1_cke_0);
994 /* Bring up clock enable. */
996 /* tXRP < 250 ck cycles */
997 delay_for_n_mem_clocks(250);
999 rw_mgr_mem_load_user(rwcfg->mrs0_dll_reset_mirr, rwcfg->mrs0_dll_reset,
1004 * rw_mgr_mem_handoff() - Hand off the memory to user
1006 * At the end of calibration we have to program the user settings in
1007 * and hand off the memory to the user.
1009 static void rw_mgr_mem_handoff(void)
1011 rw_mgr_mem_load_user(rwcfg->mrs0_user_mirr, rwcfg->mrs0_user, 1);
1013 * Need to wait tMOD (12CK or 15ns) time before issuing other
1014 * commands, but we will have plenty of NIOS cycles before actual
1015 * handoff so its okay.
1020 * rw_mgr_mem_calibrate_write_test_issue() - Issue write test command
1021 * @group: Write Group
1024 * Issue write test command. Two variants are provided, one that just tests
1025 * a write pattern and another that tests datamask functionality.
1027 static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
1030 const u32 quick_write_mode =
1031 (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) &&
1032 misccfg->enable_super_quick_calibration;
1033 u32 mcc_instruction;
1034 u32 rw_wl_nop_cycles;
1037 * Set counter and jump addresses for the right
1038 * number of NOP cycles.
1039 * The number of supported NOP cycles can range from -1 to infinity
1040 * Three different cases are handled:
1042 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
1043 * mechanism will be used to insert the right number of NOPs
1045 * 2. For a number of NOP cycles equals to 0, the micro-instruction
1046 * issuing the write command will jump straight to the
1047 * micro-instruction that turns on DQS (for DDRx), or outputs write
1048 * data (for RLD), skipping
1049 * the NOP micro-instruction all together
1051 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
1052 * turned on in the same micro-instruction that issues the write
1053 * command. Then we need
1054 * to directly jump to the micro-instruction that sends out the data
1056 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
1057 * (2 and 3). One jump-counter (0) is used to perform multiple
1058 * write-read operations.
1059 * one counter left to issue this command in "multiple-group" mode
1062 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
1064 if (rw_wl_nop_cycles == -1) {
1066 * CNTR 2 - We want to execute the special write operation that
1067 * turns on DQS right away and then skip directly to the
1068 * instruction that sends out the data. We set the counter to a
1069 * large number so that the jump is always taken.
1071 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
1073 /* CNTR 3 - Not used */
1075 mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0_wl_1;
1076 writel(rwcfg->lfsr_wr_rd_dm_bank_0_data,
1077 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1078 writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop,
1079 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1081 mcc_instruction = rwcfg->lfsr_wr_rd_bank_0_wl_1;
1082 writel(rwcfg->lfsr_wr_rd_bank_0_data,
1083 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1084 writel(rwcfg->lfsr_wr_rd_bank_0_nop,
1085 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1087 } else if (rw_wl_nop_cycles == 0) {
1089 * CNTR 2 - We want to skip the NOP operation and go straight
1090 * to the DQS enable instruction. We set the counter to a large
1091 * number so that the jump is always taken.
1093 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
1095 /* CNTR 3 - Not used */
1097 mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0;
1098 writel(rwcfg->lfsr_wr_rd_dm_bank_0_dqs,
1099 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1101 mcc_instruction = rwcfg->lfsr_wr_rd_bank_0;
1102 writel(rwcfg->lfsr_wr_rd_bank_0_dqs,
1103 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1107 * CNTR 2 - In this case we want to execute the next instruction
1108 * and NOT take the jump. So we set the counter to 0. The jump
1109 * address doesn't count.
1111 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
1112 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1115 * CNTR 3 - Set the nop counter to the number of cycles we
1116 * need to loop for, minus 1.
1118 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
1120 mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0;
1121 writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop,
1122 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1124 mcc_instruction = rwcfg->lfsr_wr_rd_bank_0;
1125 writel(rwcfg->lfsr_wr_rd_bank_0_nop,
1126 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1130 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1131 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1133 if (quick_write_mode)
1134 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
1136 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
1138 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1141 * CNTR 1 - This is used to ensure enough time elapses
1142 * for read data to come back.
1144 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
1147 writel(rwcfg->lfsr_wr_rd_dm_bank_0_wait,
1148 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1150 writel(rwcfg->lfsr_wr_rd_bank_0_wait,
1151 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1154 writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS |
1155 RW_MGR_RUN_SINGLE_GROUP_OFFSET) +
1160 * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple pass
1161 * @rank_bgn: Rank number
1162 * @write_group: Write Group
1164 * @all_correct: All bits must be correct in the mask
1165 * @bit_chk: Resulting bit mask after the test
1166 * @all_ranks: Test all ranks
1168 * Test writes, can check for a single bit pass or multiple bit pass.
1171 rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
1172 const u32 use_dm, const u32 all_correct,
1173 u32 *bit_chk, const u32 all_ranks)
1175 const u32 rank_end = all_ranks ?
1176 rwcfg->mem_number_of_ranks :
1177 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1178 const u32 shift_ratio = rwcfg->mem_dq_per_write_dqs /
1179 rwcfg->mem_virtual_groups_per_write_dqs;
1180 const u32 correct_mask_vg = param->write_correct_mask_vg;
1182 u32 tmp_bit_chk, base_rw_mgr;
1185 *bit_chk = param->write_correct_mask;
1187 for (r = rank_bgn; r < rank_end; r++) {
1189 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1192 for (vg = rwcfg->mem_virtual_groups_per_write_dqs - 1;
1194 /* Reset the FIFOs to get pointers to known state. */
1195 writel(0, &phy_mgr_cmd->fifo_reset);
1197 rw_mgr_mem_calibrate_write_test_issue(
1199 rwcfg->mem_virtual_groups_per_write_dqs + vg,
1202 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1203 tmp_bit_chk <<= shift_ratio;
1204 tmp_bit_chk |= (correct_mask_vg & ~(base_rw_mgr));
1207 *bit_chk &= tmp_bit_chk;
1210 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1212 debug_cond(DLEVEL >= 2,
1213 "write_test(%u,%u,ALL) : %u == %u => %i\n",
1214 write_group, use_dm, *bit_chk,
1215 param->write_correct_mask,
1216 *bit_chk == param->write_correct_mask);
1217 return *bit_chk == param->write_correct_mask;
1219 debug_cond(DLEVEL >= 2,
1220 "write_test(%u,%u,ONE) : %u != %i => %i\n",
1221 write_group, use_dm, *bit_chk, 0, *bit_chk != 0);
1222 return *bit_chk != 0x00;
1227 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1228 * @rank_bgn: Rank number
1229 * @group: Read/Write Group
1230 * @all_ranks: Test all ranks
1232 * Performs a guaranteed read on the patterns we are going to use during a
1233 * read test to ensure memory works.
1236 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1237 const u32 all_ranks)
1239 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1240 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1241 const u32 addr_offset =
1242 (group * rwcfg->mem_virtual_groups_per_read_dqs) << 2;
1243 const u32 rank_end = all_ranks ?
1244 rwcfg->mem_number_of_ranks :
1245 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1246 const u32 shift_ratio = rwcfg->mem_dq_per_read_dqs /
1247 rwcfg->mem_virtual_groups_per_read_dqs;
1248 const u32 correct_mask_vg = param->read_correct_mask_vg;
1250 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1254 bit_chk = param->read_correct_mask;
1256 for (r = rank_bgn; r < rank_end; r++) {
1258 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1260 /* Load up a constant bursts of read commands */
1261 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1262 writel(rwcfg->guaranteed_read,
1263 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1265 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1266 writel(rwcfg->guaranteed_read_cont,
1267 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1270 for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1;
1272 /* Reset the FIFOs to get pointers to known state. */
1273 writel(0, &phy_mgr_cmd->fifo_reset);
1274 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1275 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1276 writel(rwcfg->guaranteed_read,
1277 addr + addr_offset + (vg << 2));
1279 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1280 tmp_bit_chk <<= shift_ratio;
1281 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1284 bit_chk &= tmp_bit_chk;
1287 writel(rwcfg->clear_dqs_enable, addr + (group << 2));
1289 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1291 if (bit_chk != param->read_correct_mask)
1294 debug_cond(DLEVEL >= 1,
1295 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1296 __func__, __LINE__, group, bit_chk,
1297 param->read_correct_mask, ret);
1303 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1304 * @rank_bgn: Rank number
1305 * @all_ranks: Test all ranks
1307 * Load up the patterns we are going to use during a read test.
1309 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1310 const int all_ranks)
1312 const u32 rank_end = all_ranks ?
1313 rwcfg->mem_number_of_ranks :
1314 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1317 debug("%s:%d\n", __func__, __LINE__);
1319 for (r = rank_bgn; r < rank_end; r++) {
1321 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1323 /* Load up a constant bursts */
1324 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1326 writel(rwcfg->guaranteed_write_wait0,
1327 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1329 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1331 writel(rwcfg->guaranteed_write_wait1,
1332 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1334 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1336 writel(rwcfg->guaranteed_write_wait2,
1337 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1339 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1341 writel(rwcfg->guaranteed_write_wait3,
1342 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1344 writel(rwcfg->guaranteed_write, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1345 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1348 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1352 * rw_mgr_mem_calibrate_read_test() - Perform READ test on single rank
1353 * @rank_bgn: Rank number
1354 * @group: Read/Write group
1355 * @num_tries: Number of retries of the test
1356 * @all_correct: All bits must be correct in the mask
1357 * @bit_chk: Resulting bit mask after the test
1358 * @all_groups: Test all R/W groups
1359 * @all_ranks: Test all ranks
1361 * Try a read and see if it returns correct data back. Test has dummy reads
1362 * inserted into the mix used to align DQS enable. Test has more thorough
1363 * checks than the regular read test.
1366 rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
1367 const u32 num_tries, const u32 all_correct,
1369 const u32 all_groups, const u32 all_ranks)
1371 const u32 rank_end = all_ranks ? rwcfg->mem_number_of_ranks :
1372 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1373 const u32 quick_read_mode =
1374 ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
1375 misccfg->enable_super_quick_calibration);
1376 u32 correct_mask_vg = param->read_correct_mask_vg;
1383 *bit_chk = param->read_correct_mask;
1385 for (r = rank_bgn; r < rank_end; r++) {
1387 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1389 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1391 writel(rwcfg->read_b2b_wait1,
1392 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1394 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1395 writel(rwcfg->read_b2b_wait2,
1396 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1398 if (quick_read_mode)
1399 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1400 /* need at least two (1+1) reads to capture failures */
1401 else if (all_groups)
1402 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1404 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1406 writel(rwcfg->read_b2b,
1407 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1409 writel(rwcfg->mem_if_read_dqs_width *
1410 rwcfg->mem_virtual_groups_per_read_dqs - 1,
1411 &sdr_rw_load_mgr_regs->load_cntr3);
1413 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1415 writel(rwcfg->read_b2b,
1416 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1419 for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0;
1421 /* Reset the FIFOs to get pointers to known state. */
1422 writel(0, &phy_mgr_cmd->fifo_reset);
1423 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1424 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1427 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1428 RW_MGR_RUN_ALL_GROUPS_OFFSET;
1430 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1431 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1434 writel(rwcfg->read_b2b, addr +
1436 rwcfg->mem_virtual_groups_per_read_dqs +
1439 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1440 tmp_bit_chk <<= rwcfg->mem_dq_per_read_dqs /
1441 rwcfg->mem_virtual_groups_per_read_dqs;
1442 tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
1445 *bit_chk &= tmp_bit_chk;
1448 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1449 writel(rwcfg->clear_dqs_enable, addr + (group << 2));
1451 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1454 ret = (*bit_chk == param->read_correct_mask);
1455 debug_cond(DLEVEL >= 2,
1456 "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1457 __func__, __LINE__, group, all_groups, *bit_chk,
1458 param->read_correct_mask, ret);
1460 ret = (*bit_chk != 0x00);
1461 debug_cond(DLEVEL >= 2,
1462 "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1463 __func__, __LINE__, group, all_groups, *bit_chk,
1471 * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
1472 * @grp: Read/Write group
1473 * @num_tries: Number of retries of the test
1474 * @all_correct: All bits must be correct in the mask
1475 * @all_groups: Test all R/W groups
1477 * Perform a READ test across all memory ranks.
1480 rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries,
1481 const u32 all_correct,
1482 const u32 all_groups)
1485 return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct,
1486 &bit_chk, all_groups, 1);
1490 * rw_mgr_incr_vfifo() - Increase VFIFO value
1491 * @grp: Read/Write group
1493 * Increase VFIFO value.
1495 static void rw_mgr_incr_vfifo(const u32 grp)
1497 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1501 * rw_mgr_decr_vfifo() - Decrease VFIFO value
1502 * @grp: Read/Write group
1504 * Decrease VFIFO value.
1506 static void rw_mgr_decr_vfifo(const u32 grp)
1510 for (i = 0; i < misccfg->read_valid_fifo_size - 1; i++)
1511 rw_mgr_incr_vfifo(grp);
1515 * find_vfifo_failing_read() - Push VFIFO to get a failing read
1516 * @grp: Read/Write group
1518 * Push VFIFO until a failing read happens.
1520 static int find_vfifo_failing_read(const u32 grp)
1522 u32 v, ret, fail_cnt = 0;
1524 for (v = 0; v < misccfg->read_valid_fifo_size; v++) {
1525 debug_cond(DLEVEL >= 2, "%s:%d: vfifo %u\n",
1526 __func__, __LINE__, v);
1527 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1536 /* Fiddle with FIFO. */
1537 rw_mgr_incr_vfifo(grp);
1540 /* No failing read found! Something must have gone wrong. */
1541 debug_cond(DLEVEL >= 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
1546 * sdr_find_phase_delay() - Find DQS enable phase or delay
1547 * @working: If 1, look for working phase/delay, if 0, look for non-working
1548 * @delay: If 1, look for delay, if 0, look for phase
1549 * @grp: Read/Write group
1550 * @work: Working window position
1551 * @work_inc: Working window increment
1552 * @pd: DQS Phase/Delay Iterator
1554 * Find working or non-working DQS enable phase setting.
1556 static int sdr_find_phase_delay(int working, int delay, const u32 grp,
1557 u32 *work, const u32 work_inc, u32 *pd)
1559 const u32 max = delay ? iocfg->dqs_en_delay_max :
1560 iocfg->dqs_en_phase_max;
1563 for (; *pd <= max; (*pd)++) {
1565 scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd);
1567 scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd);
1569 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1584 * sdr_find_phase() - Find DQS enable phase
1585 * @working: If 1, look for working phase, if 0, look for non-working phase
1586 * @grp: Read/Write group
1587 * @work: Working window position
1589 * @p: DQS Phase Iterator
1591 * Find working or non-working DQS enable phase setting.
1593 static int sdr_find_phase(int working, const u32 grp, u32 *work,
1596 const u32 end = misccfg->read_valid_fifo_size + (working ? 0 : 1);
1599 for (; *i < end; (*i)++) {
1603 ret = sdr_find_phase_delay(working, 0, grp, work,
1604 iocfg->delay_per_opa_tap, p);
1608 if (*p > iocfg->dqs_en_phase_max) {
1609 /* Fiddle with FIFO. */
1610 rw_mgr_incr_vfifo(grp);
1620 * sdr_working_phase() - Find working DQS enable phase
1621 * @grp: Read/Write group
1622 * @work_bgn: Working window start position
1623 * @d: dtaps output value
1624 * @p: DQS Phase Iterator
1627 * Find working DQS enable phase setting.
1629 static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
1632 const u32 dtaps_per_ptap = iocfg->delay_per_opa_tap /
1633 iocfg->delay_per_dqs_en_dchain_tap;
1638 for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1640 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1641 ret = sdr_find_phase(1, grp, work_bgn, i, p);
1644 *work_bgn += iocfg->delay_per_dqs_en_dchain_tap;
1647 /* Cannot find working solution */
1648 debug_cond(DLEVEL >= 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1649 __func__, __LINE__);
1654 * sdr_backup_phase() - Find DQS enable backup phase
1655 * @grp: Read/Write group
1656 * @work_bgn: Working window start position
1657 * @p: DQS Phase Iterator
1659 * Find DQS enable backup phase setting.
1661 static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
1666 /* Special case code for backing up a phase */
1668 *p = iocfg->dqs_en_phase_max;
1669 rw_mgr_decr_vfifo(grp);
1673 tmp_delay = *work_bgn - iocfg->delay_per_opa_tap;
1674 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1676 for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn;
1678 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1680 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1683 *work_bgn = tmp_delay;
1687 tmp_delay += iocfg->delay_per_dqs_en_dchain_tap;
1690 /* Restore VFIFO to old state before we decremented it (if needed). */
1692 if (*p > iocfg->dqs_en_phase_max) {
1694 rw_mgr_incr_vfifo(grp);
1697 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1701 * sdr_nonworking_phase() - Find non-working DQS enable phase
1702 * @grp: Read/Write group
1703 * @work_end: Working window end position
1704 * @p: DQS Phase Iterator
1707 * Find non-working DQS enable phase setting.
1709 static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
1714 *work_end += iocfg->delay_per_opa_tap;
1715 if (*p > iocfg->dqs_en_phase_max) {
1716 /* Fiddle with FIFO. */
1718 rw_mgr_incr_vfifo(grp);
1721 ret = sdr_find_phase(0, grp, work_end, i, p);
1723 /* Cannot see edge of failing read. */
1724 debug_cond(DLEVEL >= 2, "%s:%d: end: failed\n",
1725 __func__, __LINE__);
1732 * sdr_find_window_center() - Find center of the working DQS window.
1733 * @grp: Read/Write group
1734 * @work_bgn: First working settings
1735 * @work_end: Last working settings
1737 * Find center of the working DQS enable window.
1739 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1746 work_mid = (work_bgn + work_end) / 2;
1748 debug_cond(DLEVEL >= 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1749 work_bgn, work_end, work_mid);
1750 /* Get the middle delay to be less than a VFIFO delay */
1751 tmp_delay = (iocfg->dqs_en_phase_max + 1) * iocfg->delay_per_opa_tap;
1753 debug_cond(DLEVEL >= 2, "vfifo ptap delay %d\n", tmp_delay);
1754 work_mid %= tmp_delay;
1755 debug_cond(DLEVEL >= 2, "new work_mid %d\n", work_mid);
1757 tmp_delay = rounddown(work_mid, iocfg->delay_per_opa_tap);
1758 if (tmp_delay > iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap)
1759 tmp_delay = iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap;
1760 p = tmp_delay / iocfg->delay_per_opa_tap;
1762 debug_cond(DLEVEL >= 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1764 d = DIV_ROUND_UP(work_mid - tmp_delay,
1765 iocfg->delay_per_dqs_en_dchain_tap);
1766 if (d > iocfg->dqs_en_delay_max)
1767 d = iocfg->dqs_en_delay_max;
1768 tmp_delay += d * iocfg->delay_per_dqs_en_dchain_tap;
1770 debug_cond(DLEVEL >= 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1772 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1773 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1776 * push vfifo until we can successfully calibrate. We can do this
1777 * because the largest possible margin in 1 VFIFO cycle.
1779 for (i = 0; i < misccfg->read_valid_fifo_size; i++) {
1780 debug_cond(DLEVEL >= 2, "find_dqs_en_phase: center\n");
1781 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1784 debug_cond(DLEVEL >= 2,
1785 "%s:%d center: found: ptap=%u dtap=%u\n",
1786 __func__, __LINE__, p, d);
1790 /* Fiddle with FIFO. */
1791 rw_mgr_incr_vfifo(grp);
1794 debug_cond(DLEVEL >= 2, "%s:%d center: failed.\n",
1795 __func__, __LINE__);
1800 * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
1801 * @grp: Read/Write Group
1803 * Find a good DQS enable to use.
1805 static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
1809 u32 work_bgn, work_end;
1810 u32 found_passing_read, found_failing_read = 0, initial_failing_dtap;
1813 debug("%s:%d %u\n", __func__, __LINE__, grp);
1815 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1817 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1818 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1820 /* Step 0: Determine number of delay taps for each phase tap. */
1821 dtaps_per_ptap = iocfg->delay_per_opa_tap /
1822 iocfg->delay_per_dqs_en_dchain_tap;
1824 /* Step 1: First push vfifo until we get a failing read. */
1825 find_vfifo_failing_read(grp);
1827 /* Step 2: Find first working phase, increment in ptaps. */
1829 ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i);
1833 work_end = work_bgn;
1836 * If d is 0 then the working window covers a phase tap and we can
1837 * follow the old procedure. Otherwise, we've found the beginning
1838 * and we need to increment the dtaps until we find the end.
1842 * Step 3a: If we have room, back off by one and
1843 * increment in dtaps.
1845 sdr_backup_phase(grp, &work_bgn, &p);
1848 * Step 4a: go forward from working phase to non working
1849 * phase, increment in ptaps.
1851 ret = sdr_nonworking_phase(grp, &work_end, &p, &i);
1855 /* Step 5a: Back off one from last, increment in dtaps. */
1857 /* Special case code for backing up a phase */
1859 p = iocfg->dqs_en_phase_max;
1860 rw_mgr_decr_vfifo(grp);
1865 work_end -= iocfg->delay_per_opa_tap;
1866 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1870 debug_cond(DLEVEL >= 2, "%s:%d p: ptap=%u\n",
1871 __func__, __LINE__, p);
1874 /* The dtap increment to find the failing edge is done here. */
1875 sdr_find_phase_delay(0, 1, grp, &work_end,
1876 iocfg->delay_per_dqs_en_dchain_tap, &d);
1878 /* Go back to working dtap */
1880 work_end -= iocfg->delay_per_dqs_en_dchain_tap;
1882 debug_cond(DLEVEL >= 2,
1883 "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
1884 __func__, __LINE__, p, d - 1, work_end);
1886 if (work_end < work_bgn) {
1888 debug_cond(DLEVEL >= 2, "%s:%d end-2: failed\n",
1889 __func__, __LINE__);
1893 debug_cond(DLEVEL >= 2, "%s:%d found range [%u,%u]\n",
1894 __func__, __LINE__, work_bgn, work_end);
1897 * We need to calculate the number of dtaps that equal a ptap.
1898 * To do that we'll back up a ptap and re-find the edge of the
1899 * window using dtaps
1901 debug_cond(DLEVEL >= 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
1902 __func__, __LINE__);
1904 /* Special case code for backing up a phase */
1906 p = iocfg->dqs_en_phase_max;
1907 rw_mgr_decr_vfifo(grp);
1908 debug_cond(DLEVEL >= 2, "%s:%d backedup cycle/phase: p=%u\n",
1909 __func__, __LINE__, p);
1912 debug_cond(DLEVEL >= 2, "%s:%d backedup phase only: p=%u",
1913 __func__, __LINE__, p);
1916 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1919 * Increase dtap until we first see a passing read (in case the
1920 * window is smaller than a ptap), and then a failing read to
1921 * mark the edge of the window again.
1924 /* Find a passing read. */
1925 debug_cond(DLEVEL >= 2, "%s:%d find passing read\n",
1926 __func__, __LINE__);
1928 initial_failing_dtap = d;
1930 found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
1931 if (found_passing_read) {
1932 /* Find a failing read. */
1933 debug_cond(DLEVEL >= 2, "%s:%d find failing read\n",
1934 __func__, __LINE__);
1936 found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
1939 debug_cond(DLEVEL >= 1,
1940 "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
1941 __func__, __LINE__);
1945 * The dynamically calculated dtaps_per_ptap is only valid if we
1946 * found a passing/failing read. If we didn't, it means d hit the max
1947 * (iocfg->dqs_en_delay_max). Otherwise, dtaps_per_ptap retains its
1948 * statically calculated value.
1950 if (found_passing_read && found_failing_read)
1951 dtaps_per_ptap = d - initial_failing_dtap;
1953 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1954 debug_cond(DLEVEL >= 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
1955 __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
1957 /* Step 6: Find the centre of the window. */
1958 ret = sdr_find_window_center(grp, work_bgn, work_end);
1964 * search_stop_check() - Check if the detected edge is valid
1965 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1967 * @rank_bgn: Rank number
1968 * @write_group: Write Group
1969 * @read_group: Read Group
1970 * @bit_chk: Resulting bit mask after the test
1971 * @sticky_bit_chk: Resulting sticky bit mask after the test
1972 * @use_read_test: Perform read test
1974 * Test if the found edge is valid.
1976 static u32 search_stop_check(const int write, const int d, const int rank_bgn,
1977 const u32 write_group, const u32 read_group,
1978 u32 *bit_chk, u32 *sticky_bit_chk,
1979 const u32 use_read_test)
1981 const u32 ratio = rwcfg->mem_if_read_dqs_width /
1982 rwcfg->mem_if_write_dqs_width;
1983 const u32 correct_mask = write ? param->write_correct_mask :
1984 param->read_correct_mask;
1985 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
1986 rwcfg->mem_dq_per_read_dqs;
1989 * Stop searching when the read test doesn't pass AND when
1990 * we've seen a passing read on every bit.
1992 if (write) { /* WRITE-ONLY */
1993 ret = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1996 } else if (use_read_test) { /* READ-ONLY */
1997 ret = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group,
1999 PASS_ONE_BIT, bit_chk,
2001 } else { /* READ-ONLY */
2002 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0,
2003 PASS_ONE_BIT, bit_chk, 0);
2004 *bit_chk = *bit_chk >> (per_dqs *
2005 (read_group - (write_group * ratio)));
2006 ret = (*bit_chk == 0);
2008 *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
2009 ret = ret && (*sticky_bit_chk == correct_mask);
2010 debug_cond(DLEVEL >= 2,
2011 "%s:%d center(left): dtap=%u => %u == %u && %u",
2012 __func__, __LINE__, d,
2013 *sticky_bit_chk, correct_mask, ret);
2018 * search_left_edge() - Find left edge of DQ/DQS working phase
2019 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2020 * @rank_bgn: Rank number
2021 * @write_group: Write Group
2022 * @read_group: Read Group
2023 * @test_bgn: Rank number to begin the test
2024 * @sticky_bit_chk: Resulting sticky bit mask after the test
2025 * @left_edge: Left edge of the DQ/DQS phase
2026 * @right_edge: Right edge of the DQ/DQS phase
2027 * @use_read_test: Perform read test
2029 * Find left edge of DQ/DQS working phase.
2031 static void search_left_edge(const int write, const int rank_bgn,
2032 const u32 write_group, const u32 read_group, const u32 test_bgn,
2033 u32 *sticky_bit_chk,
2034 int *left_edge, int *right_edge, const u32 use_read_test)
2036 const u32 delay_max = write ? iocfg->io_out1_delay_max :
2037 iocfg->io_in_delay_max;
2038 const u32 dqs_max = write ? iocfg->io_out1_delay_max :
2039 iocfg->dqs_in_delay_max;
2040 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
2041 rwcfg->mem_dq_per_read_dqs;
2045 for (d = 0; d <= dqs_max; d++) {
2047 scc_mgr_apply_group_dq_out1_delay(d);
2049 scc_mgr_apply_group_dq_in_delay(test_bgn, d);
2051 writel(0, &sdr_scc_mgr->update);
2053 stop = search_stop_check(write, d, rank_bgn, write_group,
2054 read_group, &bit_chk, sticky_bit_chk,
2060 for (i = 0; i < per_dqs; i++) {
2063 * Remember a passing test as
2069 * If a left edge has not been seen
2070 * yet, then a future passing test
2071 * will mark this edge as the right
2074 if (left_edge[i] == delay_max + 1)
2075 right_edge[i] = -(d + 1);
2081 /* Reset DQ delay chains to 0 */
2083 scc_mgr_apply_group_dq_out1_delay(0);
2085 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2087 *sticky_bit_chk = 0;
2088 for (i = per_dqs - 1; i >= 0; i--) {
2089 debug_cond(DLEVEL >= 2,
2090 "%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
2091 __func__, __LINE__, i, left_edge[i],
2095 * Check for cases where we haven't found the left edge,
2096 * which makes our assignment of the the right edge invalid.
2097 * Reset it to the illegal value.
2099 if ((left_edge[i] == delay_max + 1) &&
2100 (right_edge[i] != delay_max + 1)) {
2101 right_edge[i] = delay_max + 1;
2102 debug_cond(DLEVEL >= 2,
2103 "%s:%d vfifo_center: reset right_edge[%u]: %d\n",
2104 __func__, __LINE__, i, right_edge[i]);
2109 * READ: except for bits where we have seen both
2110 * the left and right edge.
2111 * WRITE: except for bits where we have seen the
2114 *sticky_bit_chk <<= 1;
2116 if (left_edge[i] != delay_max + 1)
2117 *sticky_bit_chk |= 1;
2119 if ((left_edge[i] != delay_max + 1) &&
2120 (right_edge[i] != delay_max + 1))
2121 *sticky_bit_chk |= 1;
2127 * search_right_edge() - Find right edge of DQ/DQS working phase
2128 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2129 * @rank_bgn: Rank number
2130 * @write_group: Write Group
2131 * @read_group: Read Group
2132 * @start_dqs: DQS start phase
2133 * @start_dqs_en: DQS enable start phase
2134 * @sticky_bit_chk: Resulting sticky bit mask after the test
2135 * @left_edge: Left edge of the DQ/DQS phase
2136 * @right_edge: Right edge of the DQ/DQS phase
2137 * @use_read_test: Perform read test
2139 * Find right edge of DQ/DQS working phase.
2141 static int search_right_edge(const int write, const int rank_bgn,
2142 const u32 write_group, const u32 read_group,
2143 const int start_dqs, const int start_dqs_en,
2144 u32 *sticky_bit_chk,
2145 int *left_edge, int *right_edge, const u32 use_read_test)
2147 const u32 delay_max = write ? iocfg->io_out1_delay_max :
2148 iocfg->io_in_delay_max;
2149 const u32 dqs_max = write ? iocfg->io_out1_delay_max :
2150 iocfg->dqs_in_delay_max;
2151 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
2152 rwcfg->mem_dq_per_read_dqs;
2156 for (d = 0; d <= dqs_max - start_dqs; d++) {
2157 if (write) { /* WRITE-ONLY */
2158 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2160 } else { /* READ-ONLY */
2161 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
2162 if (iocfg->shift_dqs_en_when_shift_dqs) {
2163 u32 delay = d + start_dqs_en;
2164 if (delay > iocfg->dqs_en_delay_max)
2165 delay = iocfg->dqs_en_delay_max;
2166 scc_mgr_set_dqs_en_delay(read_group, delay);
2168 scc_mgr_load_dqs(read_group);
2171 writel(0, &sdr_scc_mgr->update);
2173 stop = search_stop_check(write, d, rank_bgn, write_group,
2174 read_group, &bit_chk, sticky_bit_chk,
2177 if (write && (d == 0)) { /* WRITE-ONLY */
2178 for (i = 0; i < rwcfg->mem_dq_per_write_dqs;
2181 * d = 0 failed, but it passed when
2182 * testing the left edge, so it must be
2183 * marginal, set it to -1
2185 if (right_edge[i] == delay_max + 1 &&
2186 left_edge[i] != delay_max + 1)
2194 for (i = 0; i < per_dqs; i++) {
2197 * Remember a passing test as
2204 * If a right edge has not
2205 * been seen yet, then a future
2206 * passing test will mark this
2207 * edge as the left edge.
2209 if (right_edge[i] == delay_max + 1)
2210 left_edge[i] = -(d + 1);
2213 * d = 0 failed, but it passed
2214 * when testing the left edge,
2215 * so it must be marginal, set
2218 if (right_edge[i] == delay_max + 1 &&
2219 left_edge[i] != delay_max + 1)
2222 * If a right edge has not been
2223 * seen yet, then a future
2224 * passing test will mark this
2225 * edge as the left edge.
2227 else if (right_edge[i] == delay_max + 1)
2228 left_edge[i] = -(d + 1);
2232 debug_cond(DLEVEL >= 2, "%s:%d center[r,d=%u]: ",
2233 __func__, __LINE__, d);
2234 debug_cond(DLEVEL >= 2,
2235 "bit_chk_test=%i left_edge[%u]: %d ",
2236 bit_chk & 1, i, left_edge[i]);
2237 debug_cond(DLEVEL >= 2, "right_edge[%u]: %d\n", i,
2243 /* Check that all bits have a window */
2244 for (i = 0; i < per_dqs; i++) {
2245 debug_cond(DLEVEL >= 2,
2246 "%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
2247 __func__, __LINE__, i, left_edge[i],
2249 if ((left_edge[i] == dqs_max + 1) ||
2250 (right_edge[i] == dqs_max + 1))
2251 return i + 1; /* FIXME: If we fail, retval > 0 */
2258 * get_window_mid_index() - Find the best middle setting of DQ/DQS phase
2259 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2260 * @left_edge: Left edge of the DQ/DQS phase
2261 * @right_edge: Right edge of the DQ/DQS phase
2262 * @mid_min: Best DQ/DQS phase middle setting
2264 * Find index and value of the middle of the DQ/DQS working phase.
2266 static int get_window_mid_index(const int write, int *left_edge,
2267 int *right_edge, int *mid_min)
2269 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
2270 rwcfg->mem_dq_per_read_dqs;
2271 int i, mid, min_index;
2273 /* Find middle of window for each DQ bit */
2274 *mid_min = left_edge[0] - right_edge[0];
2276 for (i = 1; i < per_dqs; i++) {
2277 mid = left_edge[i] - right_edge[i];
2278 if (mid < *mid_min) {
2285 * -mid_min/2 represents the amount that we need to move DQS.
2286 * If mid_min is odd and positive we'll need to add one to make
2287 * sure the rounding in further calculations is correct (always
2288 * bias to the right), so just add 1 for all positive values.
2292 *mid_min = *mid_min / 2;
2294 debug_cond(DLEVEL >= 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
2295 __func__, __LINE__, *mid_min, min_index);
2300 * center_dq_windows() - Center the DQ/DQS windows
2301 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2302 * @left_edge: Left edge of the DQ/DQS phase
2303 * @right_edge: Right edge of the DQ/DQS phase
2304 * @mid_min: Adjusted DQ/DQS phase middle setting
2305 * @orig_mid_min: Original DQ/DQS phase middle setting
2306 * @min_index: DQ/DQS phase middle setting index
2307 * @test_bgn: Rank number to begin the test
2308 * @dq_margin: Amount of shift for the DQ
2309 * @dqs_margin: Amount of shift for the DQS
2311 * Align the DQ/DQS windows in each group.
2313 static void center_dq_windows(const int write, int *left_edge, int *right_edge,
2314 const int mid_min, const int orig_mid_min,
2315 const int min_index, const int test_bgn,
2316 int *dq_margin, int *dqs_margin)
2318 const s32 delay_max = write ? iocfg->io_out1_delay_max :
2319 iocfg->io_in_delay_max;
2320 const s32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
2321 rwcfg->mem_dq_per_read_dqs;
2322 const s32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
2323 SCC_MGR_IO_IN_DELAY_OFFSET;
2324 const s32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
2326 s32 temp_dq_io_delay1;
2329 /* Initialize data for export structures */
2330 *dqs_margin = delay_max + 1;
2331 *dq_margin = delay_max + 1;
2333 /* add delay to bring centre of all DQ windows to the same "level" */
2334 for (i = 0, p = test_bgn; i < per_dqs; i++, p++) {
2335 /* Use values before divide by 2 to reduce round off error */
2336 shift_dq = (left_edge[i] - right_edge[i] -
2337 (left_edge[min_index] - right_edge[min_index]))/2 +
2338 (orig_mid_min - mid_min);
2340 debug_cond(DLEVEL >= 2,
2341 "vfifo_center: before: shift_dq[%u]=%d\n",
2344 temp_dq_io_delay1 = readl(addr + (i << 2));
2346 if (shift_dq + temp_dq_io_delay1 > delay_max)
2347 shift_dq = delay_max - temp_dq_io_delay1;
2348 else if (shift_dq + temp_dq_io_delay1 < 0)
2349 shift_dq = -temp_dq_io_delay1;
2351 debug_cond(DLEVEL >= 2,
2352 "vfifo_center: after: shift_dq[%u]=%d\n",
2356 scc_mgr_set_dq_out1_delay(i,
2357 temp_dq_io_delay1 + shift_dq);
2359 scc_mgr_set_dq_in_delay(p,
2360 temp_dq_io_delay1 + shift_dq);
2364 debug_cond(DLEVEL >= 2,
2365 "vfifo_center: margin[%u]=[%d,%d]\n", i,
2366 left_edge[i] - shift_dq + (-mid_min),
2367 right_edge[i] + shift_dq - (-mid_min));
2369 /* To determine values for export structures */
2370 if (left_edge[i] - shift_dq + (-mid_min) < *dq_margin)
2371 *dq_margin = left_edge[i] - shift_dq + (-mid_min);
2373 if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin)
2374 *dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2379 * rw_mgr_mem_calibrate_vfifo_center() - Per-bit deskew DQ and centering
2380 * @rank_bgn: Rank number
2381 * @rw_group: Read/Write Group
2382 * @test_bgn: Rank at which the test begins
2383 * @use_read_test: Perform a read test
2384 * @update_fom: Update FOM
2386 * Per-bit deskew DQ and centering.
2388 static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
2389 const u32 rw_group, const u32 test_bgn,
2390 const int use_read_test, const int update_fom)
2393 SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET +
2396 * Store these as signed since there are comparisons with
2400 int32_t left_edge[rwcfg->mem_dq_per_read_dqs];
2401 int32_t right_edge[rwcfg->mem_dq_per_read_dqs];
2402 int32_t orig_mid_min, mid_min;
2403 int32_t new_dqs, start_dqs, start_dqs_en = 0, final_dqs_en;
2404 int32_t dq_margin, dqs_margin;
2408 debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn);
2410 start_dqs = readl(addr);
2411 if (iocfg->shift_dqs_en_when_shift_dqs)
2412 start_dqs_en = readl(addr - iocfg->dqs_en_delay_offset);
2414 /* set the left and right edge of each bit to an illegal value */
2415 /* use (iocfg->io_in_delay_max + 1) as an illegal value */
2417 for (i = 0; i < rwcfg->mem_dq_per_read_dqs; i++) {
2418 left_edge[i] = iocfg->io_in_delay_max + 1;
2419 right_edge[i] = iocfg->io_in_delay_max + 1;
2422 /* Search for the left edge of the window for each bit */
2423 search_left_edge(0, rank_bgn, rw_group, rw_group, test_bgn,
2425 left_edge, right_edge, use_read_test);
2428 /* Search for the right edge of the window for each bit */
2429 ret = search_right_edge(0, rank_bgn, rw_group, rw_group,
2430 start_dqs, start_dqs_en,
2432 left_edge, right_edge, use_read_test);
2435 * Restore delay chain settings before letting the loop
2436 * in rw_mgr_mem_calibrate_vfifo to retry different
2437 * dqs/ck relationships.
2439 scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs);
2440 if (iocfg->shift_dqs_en_when_shift_dqs)
2441 scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en);
2443 scc_mgr_load_dqs(rw_group);
2444 writel(0, &sdr_scc_mgr->update);
2446 debug_cond(DLEVEL >= 1,
2447 "%s:%d vfifo_center: failed to find edge [%u]: %d %d",
2448 __func__, __LINE__, i, left_edge[i], right_edge[i]);
2449 if (use_read_test) {
2450 set_failing_group_stage(rw_group *
2451 rwcfg->mem_dq_per_read_dqs + i,
2453 CAL_SUBSTAGE_VFIFO_CENTER);
2455 set_failing_group_stage(rw_group *
2456 rwcfg->mem_dq_per_read_dqs + i,
2457 CAL_STAGE_VFIFO_AFTER_WRITES,
2458 CAL_SUBSTAGE_VFIFO_CENTER);
2463 min_index = get_window_mid_index(0, left_edge, right_edge, &mid_min);
2465 /* Determine the amount we can change DQS (which is -mid_min) */
2466 orig_mid_min = mid_min;
2467 new_dqs = start_dqs - mid_min;
2468 if (new_dqs > iocfg->dqs_in_delay_max)
2469 new_dqs = iocfg->dqs_in_delay_max;
2470 else if (new_dqs < 0)
2473 mid_min = start_dqs - new_dqs;
2474 debug_cond(DLEVEL >= 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2477 if (iocfg->shift_dqs_en_when_shift_dqs) {
2478 if (start_dqs_en - mid_min > iocfg->dqs_en_delay_max)
2479 mid_min += start_dqs_en - mid_min -
2480 iocfg->dqs_en_delay_max;
2481 else if (start_dqs_en - mid_min < 0)
2482 mid_min += start_dqs_en - mid_min;
2484 new_dqs = start_dqs - mid_min;
2486 debug_cond(DLEVEL >= 1,
2487 "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
2489 iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1,
2492 /* Add delay to bring centre of all DQ windows to the same "level". */
2493 center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min,
2494 min_index, test_bgn, &dq_margin, &dqs_margin);
2497 if (iocfg->shift_dqs_en_when_shift_dqs) {
2498 final_dqs_en = start_dqs_en - mid_min;
2499 scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en);
2500 scc_mgr_load_dqs(rw_group);
2504 scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs);
2505 scc_mgr_load_dqs(rw_group);
2506 debug_cond(DLEVEL >= 2,
2507 "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
2508 __func__, __LINE__, dq_margin, dqs_margin);
2511 * Do not remove this line as it makes sure all of our decisions
2512 * have been applied. Apply the update bit.
2514 writel(0, &sdr_scc_mgr->update);
2516 if ((dq_margin < 0) || (dqs_margin < 0))
2523 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2524 * @rw_group: Read/Write Group
2525 * @phase: DQ/DQS phase
2527 * Because initially no communication ca be reliably performed with the memory
2528 * device, the sequencer uses a guaranteed write mechanism to write data into
2529 * the memory device.
2531 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2536 /* Set a particular DQ/DQS phase. */
2537 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2539 debug_cond(DLEVEL >= 1, "%s:%d guaranteed write: g=%u p=%u\n",
2540 __func__, __LINE__, rw_group, phase);
2543 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2544 * Load up the patterns used by read calibration using the
2545 * current DQDQS phase.
2547 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2549 if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2553 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2554 * Back-to-Back reads of the patterns used for calibration.
2556 ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2558 debug_cond(DLEVEL >= 1,
2559 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2560 __func__, __LINE__, rw_group, phase);
2565 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2566 * @rw_group: Read/Write Group
2567 * @test_bgn: Rank at which the test begins
2569 * DQS enable calibration ensures reliable capture of the DQ signal without
2570 * glitches on the DQS line.
2572 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2576 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2577 * DQS and DQS Eanble Signal Relationships.
2580 /* We start at zero, so have one less dq to devide among */
2581 const u32 delay_step = iocfg->io_in_delay_max /
2582 (rwcfg->mem_dq_per_read_dqs - 1);
2586 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2588 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2589 for (r = 0; r < rwcfg->mem_number_of_ranks;
2590 r += NUM_RANKS_PER_SHADOW_REG) {
2591 for (i = 0, p = test_bgn, d = 0;
2592 i < rwcfg->mem_dq_per_read_dqs;
2593 i++, p++, d += delay_step) {
2594 debug_cond(DLEVEL >= 1,
2595 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2596 __func__, __LINE__, rw_group, r, i, p, d);
2598 scc_mgr_set_dq_in_delay(p, d);
2602 writel(0, &sdr_scc_mgr->update);
2606 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2607 * dq_in_delay values
2609 ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2611 debug_cond(DLEVEL >= 1,
2612 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2613 __func__, __LINE__, rw_group, !ret);
2615 for (r = 0; r < rwcfg->mem_number_of_ranks;
2616 r += NUM_RANKS_PER_SHADOW_REG) {
2617 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2618 writel(0, &sdr_scc_mgr->update);
2625 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2626 * @rw_group: Read/Write Group
2627 * @test_bgn: Rank at which the test begins
2628 * @use_read_test: Perform a read test
2629 * @update_fom: Update FOM
2631 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2635 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2636 const int use_read_test,
2637 const int update_fom)
2640 int ret, grp_calibrated;
2644 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2645 * Read per-bit deskew can be done on a per shadow register basis.
2648 for (rank_bgn = 0, sr = 0;
2649 rank_bgn < rwcfg->mem_number_of_ranks;
2650 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2651 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2661 if (!grp_calibrated)
2668 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2669 * @rw_group: Read/Write Group
2670 * @test_bgn: Rank at which the test begins
2672 * Stage 1: Calibrate the read valid prediction FIFO.
2674 * This function implements UniPHY calibration Stage 1, as explained in
2675 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2677 * - read valid prediction will consist of finding:
2678 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2679 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2680 * - we also do a per-bit deskew on the DQ lines.
2682 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2686 u32 failed_substage;
2690 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2692 /* Update info for sims */
2693 reg_file_set_group(rw_group);
2694 reg_file_set_stage(CAL_STAGE_VFIFO);
2695 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2697 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2699 /* USER Determine number of delay taps for each phase tap. */
2700 dtaps_per_ptap = DIV_ROUND_UP(iocfg->delay_per_opa_tap,
2701 iocfg->delay_per_dqs_en_dchain_tap) - 1;
2703 for (d = 0; d <= dtaps_per_ptap; d += 2) {
2705 * In RLDRAMX we may be messing the delay of pins in
2706 * the same write rw_group but outside of the current read
2707 * the rw_group, but that's ok because we haven't calibrated
2711 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2715 for (p = 0; p <= iocfg->dqdqs_out_phase_max; p++) {
2716 /* 1) Guaranteed Write */
2717 ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2721 /* 2) DQS Enable Calibration */
2722 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2725 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2729 /* 3) Centering DQ/DQS */
2731 * If doing read after write calibration, do not update
2732 * FOM now. Do it then.
2734 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2737 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2746 /* Calibration Stage 1 failed. */
2747 set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2750 /* Calibration Stage 1 completed OK. */
2753 * Reset the delay chains back to zero if they have moved > 1
2754 * (check for > 1 because loop will increase d even when pass in
2758 scc_mgr_zero_group(rw_group, 1);
2764 * rw_mgr_mem_calibrate_vfifo_end() - DQ/DQS Centering.
2765 * @rw_group: Read/Write Group
2766 * @test_bgn: Rank at which the test begins
2768 * Stage 3: DQ/DQS Centering.
2770 * This function implements UniPHY calibration Stage 3, as explained in
2771 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2773 static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group,
2778 debug("%s:%d %u %u", __func__, __LINE__, rw_group, test_bgn);
2780 /* Update info for sims. */
2781 reg_file_set_group(rw_group);
2782 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2783 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2785 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, test_bgn, 0, 1);
2787 set_failing_group_stage(rw_group,
2788 CAL_STAGE_VFIFO_AFTER_WRITES,
2789 CAL_SUBSTAGE_VFIFO_CENTER);
2794 * rw_mgr_mem_calibrate_lfifo() - Minimize latency
2796 * Stage 4: Minimize latency.
2798 * This function implements UniPHY calibration Stage 4, as explained in
2799 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2800 * Calibrate LFIFO to find smallest read latency.
2802 static u32 rw_mgr_mem_calibrate_lfifo(void)
2806 debug("%s:%d\n", __func__, __LINE__);
2808 /* Update info for sims. */
2809 reg_file_set_stage(CAL_STAGE_LFIFO);
2810 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2812 /* Load up the patterns used by read calibration for all ranks */
2813 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2816 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2817 debug_cond(DLEVEL >= 2, "%s:%d lfifo: read_lat=%u",
2818 __func__, __LINE__, gbl->curr_read_lat);
2820 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS,
2826 * Reduce read latency and see if things are
2827 * working correctly.
2829 gbl->curr_read_lat--;
2830 } while (gbl->curr_read_lat > 0);
2832 /* Reset the fifos to get pointers to known state. */
2833 writel(0, &phy_mgr_cmd->fifo_reset);
2836 /* Add a fudge factor to the read latency that was determined */
2837 gbl->curr_read_lat += 2;
2838 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2839 debug_cond(DLEVEL >= 2,
2840 "%s:%d lfifo: success: using read_lat=%u\n",
2841 __func__, __LINE__, gbl->curr_read_lat);
2843 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2844 CAL_SUBSTAGE_READ_LATENCY);
2846 debug_cond(DLEVEL >= 2,
2847 "%s:%d lfifo: failed at initial read_lat=%u\n",
2848 __func__, __LINE__, gbl->curr_read_lat);
2855 * search_window() - Search for the/part of the window with DM/DQS shift
2856 * @search_dm: If 1, search for the DM shift, if 0, search for DQS shift
2857 * @rank_bgn: Rank number
2858 * @write_group: Write Group
2859 * @bgn_curr: Current window begin
2860 * @end_curr: Current window end
2861 * @bgn_best: Current best window begin
2862 * @end_best: Current best window end
2863 * @win_best: Size of the best window
2864 * @new_dqs: New DQS value (only applicable if search_dm = 0).
2866 * Search for the/part of the window with DM/DQS shift.
2868 static void search_window(const int search_dm,
2869 const u32 rank_bgn, const u32 write_group,
2870 int *bgn_curr, int *end_curr, int *bgn_best,
2871 int *end_best, int *win_best, int new_dqs)
2874 const int max = iocfg->io_out1_delay_max - new_dqs;
2877 /* Search for the/part of the window with DM/DQS shift. */
2878 for (di = max; di >= 0; di -= DELTA_D) {
2881 scc_mgr_apply_group_dm_out1_delay(d);
2883 /* For DQS, we go from 0...max */
2886 * Note: This only shifts DQS, so are we limiting
2887 * ourselves to width of DQ unnecessarily.
2889 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2893 writel(0, &sdr_scc_mgr->update);
2895 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2896 PASS_ALL_BITS, &bit_chk,
2898 /* Set current end of the window. */
2899 *end_curr = search_dm ? -d : d;
2902 * If a starting edge of our window has not been seen
2903 * this is our current start of the DM window.
2905 if (*bgn_curr == iocfg->io_out1_delay_max + 1)
2906 *bgn_curr = search_dm ? -d : d;
2909 * If current window is bigger than best seen.
2910 * Set best seen to be current window.
2912 if ((*end_curr - *bgn_curr + 1) > *win_best) {
2913 *win_best = *end_curr - *bgn_curr + 1;
2914 *bgn_best = *bgn_curr;
2915 *end_best = *end_curr;
2918 /* We just saw a failing test. Reset temp edge. */
2919 *bgn_curr = iocfg->io_out1_delay_max + 1;
2920 *end_curr = iocfg->io_out1_delay_max + 1;
2922 /* Early exit is only applicable to DQS. */
2927 * Early exit optimization: if the remaining delay
2928 * chain space is less than already seen largest
2929 * window we can exit.
2931 if (*win_best - 1 > iocfg->io_out1_delay_max - new_dqs - d)
2938 * rw_mgr_mem_calibrate_writes_center() - Center all windows
2939 * @rank_bgn: Rank number
2940 * @write_group: Write group
2941 * @test_bgn: Rank at which the test begins
2943 * Center all windows. Do per-bit-deskew to possibly increase size of
2947 rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
2953 int left_edge[rwcfg->mem_dq_per_write_dqs];
2954 int right_edge[rwcfg->mem_dq_per_write_dqs];
2956 int mid_min, orig_mid_min;
2957 int new_dqs, start_dqs;
2958 int dq_margin, dqs_margin, dm_margin;
2959 int bgn_curr = iocfg->io_out1_delay_max + 1;
2960 int end_curr = iocfg->io_out1_delay_max + 1;
2961 int bgn_best = iocfg->io_out1_delay_max + 1;
2962 int end_best = iocfg->io_out1_delay_max + 1;
2967 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2971 start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS |
2972 SCC_MGR_IO_OUT1_DELAY_OFFSET) +
2973 (rwcfg->mem_dq_per_write_dqs << 2));
2975 /* Per-bit deskew. */
2978 * Set the left and right edge of each bit to an illegal value.
2979 * Use (iocfg->io_out1_delay_max + 1) as an illegal value.
2982 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
2983 left_edge[i] = iocfg->io_out1_delay_max + 1;
2984 right_edge[i] = iocfg->io_out1_delay_max + 1;
2987 /* Search for the left edge of the window for each bit. */
2988 search_left_edge(1, rank_bgn, write_group, 0, test_bgn,
2990 left_edge, right_edge, 0);
2992 /* Search for the right edge of the window for each bit. */
2993 ret = search_right_edge(1, rank_bgn, write_group, 0,
2996 left_edge, right_edge, 0);
2998 set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
2999 CAL_SUBSTAGE_WRITES_CENTER);
3003 min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min);
3005 /* Determine the amount we can change DQS (which is -mid_min). */
3006 orig_mid_min = mid_min;
3007 new_dqs = start_dqs;
3009 debug_cond(DLEVEL >= 1,
3010 "%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n",
3011 __func__, __LINE__, start_dqs, new_dqs, mid_min);
3013 /* Add delay to bring centre of all DQ windows to the same "level". */
3014 center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min,
3015 min_index, 0, &dq_margin, &dqs_margin);
3018 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3019 writel(0, &sdr_scc_mgr->update);
3022 debug_cond(DLEVEL >= 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3025 * Set the left and right edge of each bit to an illegal value.
3026 * Use (iocfg->io_out1_delay_max + 1) as an illegal value.
3028 left_edge[0] = iocfg->io_out1_delay_max + 1;
3029 right_edge[0] = iocfg->io_out1_delay_max + 1;
3031 /* Search for the/part of the window with DM shift. */
3032 search_window(1, rank_bgn, write_group, &bgn_curr, &end_curr,
3033 &bgn_best, &end_best, &win_best, 0);
3035 /* Reset DM delay chains to 0. */
3036 scc_mgr_apply_group_dm_out1_delay(0);
3039 * Check to see if the current window nudges up aganist 0 delay.
3040 * If so we need to continue the search by shifting DQS otherwise DQS
3041 * search begins as a new search.
3043 if (end_curr != 0) {
3044 bgn_curr = iocfg->io_out1_delay_max + 1;
3045 end_curr = iocfg->io_out1_delay_max + 1;
3048 /* Search for the/part of the window with DQS shifts. */
3049 search_window(0, rank_bgn, write_group, &bgn_curr, &end_curr,
3050 &bgn_best, &end_best, &win_best, new_dqs);
3052 /* Assign left and right edge for cal and reporting. */
3053 left_edge[0] = -1 * bgn_best;
3054 right_edge[0] = end_best;
3056 debug_cond(DLEVEL >= 2, "%s:%d dm_calib: left=%d right=%d\n",
3057 __func__, __LINE__, left_edge[0], right_edge[0]);
3059 /* Move DQS (back to orig). */
3060 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3064 /* Find middle of window for the DM bit. */
3065 mid = (left_edge[0] - right_edge[0]) / 2;
3067 /* Only move right, since we are not moving DQS/DQ. */
3071 /* dm_marign should fail if we never find a window. */
3075 dm_margin = left_edge[0] - mid;
3077 scc_mgr_apply_group_dm_out1_delay(mid);
3078 writel(0, &sdr_scc_mgr->update);
3080 debug_cond(DLEVEL >= 2,
3081 "%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
3082 __func__, __LINE__, left_edge[0], right_edge[0],
3084 /* Export values. */
3085 gbl->fom_out += dq_margin + dqs_margin;
3087 debug_cond(DLEVEL >= 2,
3088 "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
3089 __func__, __LINE__, dq_margin, dqs_margin, dm_margin);
3092 * Do not remove this line as it makes sure all of our
3093 * decisions have been applied.
3095 writel(0, &sdr_scc_mgr->update);
3097 if ((dq_margin < 0) || (dqs_margin < 0) || (dm_margin < 0))
3104 * rw_mgr_mem_calibrate_writes() - Write Calibration Part One
3105 * @rank_bgn: Rank number
3106 * @group: Read/Write Group
3107 * @test_bgn: Rank at which the test begins
3109 * Stage 2: Write Calibration Part One.
3111 * This function implements UniPHY calibration Stage 2, as explained in
3112 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
3114 static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group,
3119 /* Update info for sims */
3120 debug("%s:%d %u %u\n", __func__, __LINE__, group, test_bgn);
3122 reg_file_set_group(group);
3123 reg_file_set_stage(CAL_STAGE_WRITES);
3124 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3126 ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn);
3128 set_failing_group_stage(group, CAL_STAGE_WRITES,
3129 CAL_SUBSTAGE_WRITES_CENTER);
3135 * mem_precharge_and_activate() - Precharge all banks and activate
3137 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3139 static void mem_precharge_and_activate(void)
3143 for (r = 0; r < rwcfg->mem_number_of_ranks; r++) {
3145 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3147 /* Precharge all banks. */
3148 writel(rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3149 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3151 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3152 writel(rwcfg->activate_0_and_1_wait1,
3153 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3155 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3156 writel(rwcfg->activate_0_and_1_wait2,
3157 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3159 /* Activate rows. */
3160 writel(rwcfg->activate_0_and_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3161 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3166 * mem_init_latency() - Configure memory RLAT and WLAT settings
3168 * Configure memory RLAT and WLAT parameters.
3170 static void mem_init_latency(void)
3173 * For AV/CV, LFIFO is hardened and always runs at full rate
3174 * so max latency in AFI clocks, used here, is correspondingly
3177 const u32 max_latency = (1 << misccfg->max_latency_count_width) - 1;
3180 debug("%s:%d\n", __func__, __LINE__);
3183 * Read in write latency.
3184 * WL for Hard PHY does not include additive latency.
3186 wlat = readl(&data_mgr->t_wl_add);
3187 wlat += readl(&data_mgr->mem_t_add);
3189 gbl->rw_wl_nop_cycles = wlat - 1;
3191 /* Read in readl latency. */
3192 rlat = readl(&data_mgr->t_rl_add);
3194 /* Set a pretty high read latency initially. */
3195 gbl->curr_read_lat = rlat + 16;
3196 if (gbl->curr_read_lat > max_latency)
3197 gbl->curr_read_lat = max_latency;
3199 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3201 /* Advertise write latency. */
3202 writel(wlat, &phy_mgr_cfg->afi_wlat);
3206 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3208 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3210 static void mem_skip_calibrate(void)
3215 debug("%s:%d\n", __func__, __LINE__);
3216 /* Need to update every shadow register set used by the interface */
3217 for (r = 0; r < rwcfg->mem_number_of_ranks;
3218 r += NUM_RANKS_PER_SHADOW_REG) {
3220 * Set output phase alignment settings appropriate for
3223 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
3224 scc_mgr_set_dqs_en_phase(i, 0);
3225 if (iocfg->dll_chain_length == 6)
3226 scc_mgr_set_dqdqs_output_phase(i, 6);
3228 scc_mgr_set_dqdqs_output_phase(i, 7);
3232 * Write data arrives to the I/O two cycles before write
3233 * latency is reached (720 deg).
3234 * -> due to bit-slip in a/c bus
3235 * -> to allow board skew where dqs is longer than ck
3236 * -> how often can this happen!?
3237 * -> can claim back some ptaps for high freq
3238 * support if we can relax this, but i digress...
3240 * The write_clk leads mem_ck by 90 deg
3241 * The minimum ptap of the OPA is 180 deg
3242 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3243 * The write_clk is always delayed by 2 ptaps
3245 * Hence, to make DQS aligned to CK, we need to delay
3247 * (720 - 90 - 180 - 2) *
3248 * (360 / iocfg->dll_chain_length)
3250 * Dividing the above by (360 / iocfg->dll_chain_length)
3251 * gives us the number of ptaps, which simplies to:
3253 * (1.25 * iocfg->dll_chain_length - 2)
3255 scc_mgr_set_dqdqs_output_phase(i,
3256 ((125 * iocfg->dll_chain_length) / 100) - 2);
3258 writel(0xff, &sdr_scc_mgr->dqs_ena);
3259 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3261 for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) {
3262 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3263 SCC_MGR_GROUP_COUNTER_OFFSET);
3265 writel(0xff, &sdr_scc_mgr->dq_ena);
3266 writel(0xff, &sdr_scc_mgr->dm_ena);
3267 writel(0, &sdr_scc_mgr->update);
3270 /* Compensate for simulation model behaviour */
3271 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
3272 scc_mgr_set_dqs_bus_in_delay(i, 10);
3273 scc_mgr_load_dqs(i);
3275 writel(0, &sdr_scc_mgr->update);
3278 * ArriaV has hard FIFOs that can only be initialized by incrementing
3281 vfifo_offset = misccfg->calib_vfifo_offset;
3282 for (j = 0; j < vfifo_offset; j++)
3283 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3284 writel(0, &phy_mgr_cmd->fifo_reset);
3287 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3288 * setting from generation-time constant.
3290 gbl->curr_read_lat = misccfg->calib_lfifo_offset;
3291 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3295 * mem_calibrate() - Memory calibration entry point.
3297 * Perform memory calibration.
3299 static u32 mem_calibrate(void)
3303 u32 write_group, write_test_bgn;
3304 u32 read_group, read_test_bgn;
3305 u32 run_groups, current_run;
3306 u32 failing_groups = 0;
3307 u32 group_failed = 0;
3309 const u32 rwdqs_ratio = rwcfg->mem_if_read_dqs_width /
3310 rwcfg->mem_if_write_dqs_width;
3312 debug("%s:%d\n", __func__, __LINE__);
3314 /* Initialize the data settings */
3315 gbl->error_substage = CAL_SUBSTAGE_NIL;
3316 gbl->error_stage = CAL_STAGE_NIL;
3317 gbl->error_group = 0xff;
3321 /* Initialize WLAT and RLAT. */
3324 /* Initialize bit slips. */
3325 mem_precharge_and_activate();
3327 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
3328 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3329 SCC_MGR_GROUP_COUNTER_OFFSET);
3330 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3332 scc_mgr_set_hhp_extras();
3334 scc_set_bypass_mode(i);
3337 /* Calibration is skipped. */
3338 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3340 * Set VFIFO and LFIFO to instant-on settings in skip
3343 mem_skip_calibrate();
3346 * Do not remove this line as it makes sure all of our
3347 * decisions have been applied.
3349 writel(0, &sdr_scc_mgr->update);
3353 /* Calibration is not skipped. */
3354 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3356 * Zero all delay chain/phase settings for all
3357 * groups and all shadow register sets.
3363 for (write_group = 0, write_test_bgn = 0; write_group
3364 < rwcfg->mem_if_write_dqs_width; write_group++,
3365 write_test_bgn += rwcfg->mem_dq_per_write_dqs) {
3366 /* Initialize the group failure */
3369 current_run = run_groups & ((1 <<
3370 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3371 run_groups = run_groups >>
3372 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3374 if (current_run == 0)
3377 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3378 SCC_MGR_GROUP_COUNTER_OFFSET);
3379 scc_mgr_zero_group(write_group, 0);
3381 for (read_group = write_group * rwdqs_ratio,
3383 read_group < (write_group + 1) * rwdqs_ratio;
3385 read_test_bgn += rwcfg->mem_dq_per_read_dqs) {
3386 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3389 /* Calibrate the VFIFO */
3390 if (rw_mgr_mem_calibrate_vfifo(read_group,
3394 if (!(gbl->phy_debug_mode_flags &
3395 PHY_DEBUG_SWEEP_ALL_GROUPS))
3398 /* The group failed, we're done. */
3402 /* Calibrate the output side */
3403 for (rank_bgn = 0, sr = 0;
3404 rank_bgn < rwcfg->mem_number_of_ranks;
3405 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3406 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3409 /* Not needed in quick mode! */
3410 if (STATIC_CALIB_STEPS &
3411 CALIB_SKIP_DELAY_SWEEPS)
3414 /* Calibrate WRITEs */
3415 if (!rw_mgr_mem_calibrate_writes(rank_bgn,
3421 if (!(gbl->phy_debug_mode_flags &
3422 PHY_DEBUG_SWEEP_ALL_GROUPS))
3426 /* Some group failed, we're done. */
3430 for (read_group = write_group * rwdqs_ratio,
3432 read_group < (write_group + 1) * rwdqs_ratio;
3434 read_test_bgn += rwcfg->mem_dq_per_read_dqs) {
3435 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3438 if (!rw_mgr_mem_calibrate_vfifo_end(read_group,
3442 if (!(gbl->phy_debug_mode_flags &
3443 PHY_DEBUG_SWEEP_ALL_GROUPS))
3446 /* The group failed, we're done. */
3450 /* No group failed, continue as usual. */
3453 grp_failed: /* A group failed, increment the counter. */
3458 * USER If there are any failing groups then report
3461 if (failing_groups != 0)
3464 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3467 /* Calibrate the LFIFO */
3468 if (!rw_mgr_mem_calibrate_lfifo())
3473 * Do not remove this line as it makes sure all of our decisions
3474 * have been applied.
3476 writel(0, &sdr_scc_mgr->update);
3481 * run_mem_calibrate() - Perform memory calibration
3483 * This function triggers the entire memory calibration procedure.
3485 static int run_mem_calibrate(void)
3490 debug("%s:%d\n", __func__, __LINE__);
3492 /* Reset pass/fail status shown on afi_cal_success/fail */
3493 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3495 /* Stop tracking manager. */
3496 ctrl_cfg = readl(&sdr_ctrl->ctrl_cfg);
3497 writel(ctrl_cfg & ~SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
3498 &sdr_ctrl->ctrl_cfg);
3500 phy_mgr_initialize();
3501 rw_mgr_mem_initialize();
3503 /* Perform the actual memory calibration. */
3504 pass = mem_calibrate();
3506 mem_precharge_and_activate();
3507 writel(0, &phy_mgr_cmd->fifo_reset);
3510 rw_mgr_mem_handoff();
3512 * In Hard PHY this is a 2-bit control:
3514 * 1: DDIO Mux Select
3516 writel(0x2, &phy_mgr_cfg->mux_sel);
3518 /* Start tracking manager. */
3519 writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
3525 * debug_mem_calibrate() - Report result of memory calibration
3526 * @pass: Value indicating whether calibration passed or failed
3528 * This function reports the results of the memory calibration
3529 * and writes debug information into the register file.
3531 static void debug_mem_calibrate(int pass)
3536 debug("%s: CALIBRATION PASSED\n", __FILE__);
3541 if (gbl->fom_in > 0xff)
3544 if (gbl->fom_out > 0xff)
3545 gbl->fom_out = 0xff;
3547 /* Update the FOM in the register file */
3548 debug_info = gbl->fom_in;
3549 debug_info |= gbl->fom_out << 8;
3550 writel(debug_info, &sdr_reg_file->fom);
3552 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3553 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3555 debug("%s: CALIBRATION FAILED\n", __FILE__);
3557 debug_info = gbl->error_stage;
3558 debug_info |= gbl->error_substage << 8;
3559 debug_info |= gbl->error_group << 16;
3561 writel(debug_info, &sdr_reg_file->failing_stage);
3562 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3563 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3565 /* Update the failing group/stage in the register file */
3566 debug_info = gbl->error_stage;
3567 debug_info |= gbl->error_substage << 8;
3568 debug_info |= gbl->error_group << 16;
3569 writel(debug_info, &sdr_reg_file->failing_stage);
3572 debug("%s: Calibration complete\n", __FILE__);
3576 * hc_initialize_rom_data() - Initialize ROM data
3578 * Initialize ROM data.
3580 static void hc_initialize_rom_data(void)
3582 unsigned int nelem = 0;
3583 const u32 *rom_init;
3586 socfpga_get_seq_inst_init(&rom_init, &nelem);
3587 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3588 for (i = 0; i < nelem; i++)
3589 writel(rom_init[i], addr + (i << 2));
3591 socfpga_get_seq_ac_init(&rom_init, &nelem);
3592 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3593 for (i = 0; i < nelem; i++)
3594 writel(rom_init[i], addr + (i << 2));
3598 * initialize_reg_file() - Initialize SDR register file
3600 * Initialize SDR register file.
3602 static void initialize_reg_file(void)
3604 /* Initialize the register file with the correct data */
3605 writel(misccfg->reg_file_init_seq_signature, &sdr_reg_file->signature);
3606 writel(0, &sdr_reg_file->debug_data_addr);
3607 writel(0, &sdr_reg_file->cur_stage);
3608 writel(0, &sdr_reg_file->fom);
3609 writel(0, &sdr_reg_file->failing_stage);
3610 writel(0, &sdr_reg_file->debug1);
3611 writel(0, &sdr_reg_file->debug2);
3615 * initialize_hps_phy() - Initialize HPS PHY
3617 * Initialize HPS PHY.
3619 static void initialize_hps_phy(void)
3623 * Tracking also gets configured here because it's in the
3626 u32 trk_sample_count = 7500;
3627 u32 trk_long_idle_sample_count = (10 << 16) | 100;
3629 * Format is number of outer loops in the 16 MSB, sample
3634 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3635 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3636 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3637 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3638 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3639 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3641 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3642 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3644 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3645 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3647 writel(reg, &sdr_ctrl->phy_ctrl0);
3650 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3652 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3653 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3654 trk_long_idle_sample_count);
3655 writel(reg, &sdr_ctrl->phy_ctrl1);
3658 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3659 trk_long_idle_sample_count >>
3660 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3661 writel(reg, &sdr_ctrl->phy_ctrl2);
3665 * initialize_tracking() - Initialize tracking
3667 * Initialize the register file with usable initial data.
3669 static void initialize_tracking(void)
3672 * Initialize the register file with the correct data.
3673 * Compute usable version of value in case we skip full
3674 * computation later.
3676 writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap,
3677 iocfg->delay_per_dchain_tap) - 1,
3678 &sdr_reg_file->dtaps_per_ptap);
3680 /* trk_sample_count */
3681 writel(7500, &sdr_reg_file->trk_sample_count);
3683 /* longidle outer loop [15:0] */
3684 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3687 * longidle sample count [31:24]
3688 * trfc, worst case of 933Mhz 4Gb [23:16]
3689 * trcd, worst case [15:8]
3692 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3693 &sdr_reg_file->delays);
3696 writel((rwcfg->idle << 24) | (rwcfg->activate_1 << 16) |
3697 (rwcfg->sgle_read << 8) | (rwcfg->precharge_all << 0),
3698 &sdr_reg_file->trk_rw_mgr_addr);
3700 writel(rwcfg->mem_if_read_dqs_width,
3701 &sdr_reg_file->trk_read_dqs_width);
3704 writel((rwcfg->refresh_all << 24) | (1000 << 0),
3705 &sdr_reg_file->trk_rfsh);
3708 int sdram_calibration_full(void)
3710 struct param_type my_param;
3711 struct gbl_type my_gbl;
3714 memset(&my_param, 0, sizeof(my_param));
3715 memset(&my_gbl, 0, sizeof(my_gbl));
3720 rwcfg = socfpga_get_sdram_rwmgr_config();
3721 iocfg = socfpga_get_sdram_io_config();
3722 misccfg = socfpga_get_sdram_misc_config();
3724 /* Set the calibration enabled by default */
3725 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3727 * Only sweep all groups (regardless of fail state) by default
3728 * Set enabled read test by default.
3730 #if DISABLE_GUARANTEED_READ
3731 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3733 /* Initialize the register file */
3734 initialize_reg_file();
3736 /* Initialize any PHY CSR */
3737 initialize_hps_phy();
3739 scc_mgr_initialize();
3741 initialize_tracking();
3743 debug("%s: Preparing to start memory calibration\n", __FILE__);
3745 debug("%s:%d\n", __func__, __LINE__);
3746 debug_cond(DLEVEL >= 1,
3747 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3748 rwcfg->mem_number_of_ranks, rwcfg->mem_number_of_cs_per_dimm,
3749 rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs,
3750 rwcfg->mem_virtual_groups_per_read_dqs,
3751 rwcfg->mem_virtual_groups_per_write_dqs);
3752 debug_cond(DLEVEL >= 1,
3753 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3754 rwcfg->mem_if_read_dqs_width, rwcfg->mem_if_write_dqs_width,
3755 rwcfg->mem_data_width, rwcfg->mem_data_mask_width,
3756 iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap);
3757 debug_cond(DLEVEL >= 1, "dtap_dqsen_delay=%u, dll=%u",
3758 iocfg->delay_per_dqs_en_dchain_tap, iocfg->dll_chain_length);
3759 debug_cond(DLEVEL >= 1,
3760 "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3761 iocfg->dqs_en_phase_max, iocfg->dqdqs_out_phase_max,
3762 iocfg->dqs_en_delay_max, iocfg->dqs_in_delay_max);
3763 debug_cond(DLEVEL >= 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3764 iocfg->io_in_delay_max, iocfg->io_out1_delay_max,
3765 iocfg->io_out2_delay_max);
3766 debug_cond(DLEVEL >= 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3767 iocfg->dqs_in_reserve, iocfg->dqs_out_reserve);
3769 hc_initialize_rom_data();
3771 /* update info for sims */
3772 reg_file_set_stage(CAL_STAGE_NIL);
3773 reg_file_set_group(0);
3776 * Load global needed for those actions that require
3777 * some dynamic calibration support.
3779 dyn_calib_steps = STATIC_CALIB_STEPS;
3781 * Load global to allow dynamic selection of delay loop settings
3782 * based on calibration mode.
3784 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3785 skip_delay_mask = 0xff;
3787 skip_delay_mask = 0x0;
3789 pass = run_mem_calibrate();
3790 debug_mem_calibrate(pass);