git.sur5r.net Git - u-boot/blob - drivers/ddr/altera/sequencer.c

   1 /*
   2  * Copyright Altera Corporation (C) 2012-2015
   3  *
   4  * SPDX-License-Identifier:    BSD-3-Clause
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/sdram.h>
  10 #include "sequencer.h"
  11 #include "sequencer_auto.h"
  12 #include "sequencer_auto_ac_init.h"
  13 #include "sequencer_auto_inst_init.h"
  14 #include "sequencer_defines.h"
  15
  16 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
  17         (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
  18
  19 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
  20         (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
  21
  22 static struct socfpga_sdr_reg_file *sdr_reg_file =
  23         (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
  24
  25 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
  26         (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
  27
  28 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
  29         (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
  30
  31 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
  32         (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
  33
  34 static struct socfpga_data_mgr *data_mgr =
  35         (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
  36
  37 static struct socfpga_sdr_ctrl *sdr_ctrl =
  38         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  39
  40 #define DELTA_D         1
  41
  42 /*
  43  * In order to reduce ROM size, most of the selectable calibration steps are
  44  * decided at compile time based on the user's calibration mode selection,
  45  * as captured by the STATIC_CALIB_STEPS selection below.
  46  *
  47  * However, to support simulation-time selection of fast simulation mode, where
  48  * we skip everything except the bare minimum, we need a few of the steps to
  49  * be dynamic.  In those cases, we either use the DYNAMIC_CALIB_STEPS for the
  50  * check, which is based on the rtl-supplied value, or we dynamically compute
  51  * the value to use based on the dynamically-chosen calibration mode
  52  */
  53
  54 #define DLEVEL 0
  55 #define STATIC_IN_RTL_SIM 0
  56 #define STATIC_SKIP_DELAY_LOOPS 0
  57
  58 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
  59         STATIC_SKIP_DELAY_LOOPS)
  60
  61 /* calibration steps requested by the rtl */
  62 uint16_t dyn_calib_steps;
  63
  64 /*
  65  * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
  66  * instead of static, we use boolean logic to select between
  67  * non-skip and skip values
  68  *
  69  * The mask is set to include all bits when not-skipping, but is
  70  * zero when skipping
  71  */
  72
  73 uint16_t skip_delay_mask;       /* mask off bits when skipping/not-skipping */
  74
  75 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
  76         ((non_skip_value) & skip_delay_mask)
  77
  78 struct gbl_type *gbl;
  79 struct param_type *param;
  80 uint32_t curr_shadow_reg;
  81
  82 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
  83         uint32_t write_group, uint32_t use_dm,
  84         uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
  85
  86 static void set_failing_group_stage(uint32_t group, uint32_t stage,
  87         uint32_t substage)
  88 {
  89         /*
  90          * Only set the global stage if there was not been any other
  91          * failing group
  92          */
  93         if (gbl->error_stage == CAL_STAGE_NIL)  {
  94                 gbl->error_substage = substage;
  95                 gbl->error_stage = stage;
  96                 gbl->error_group = group;
  97         }
  98 }
  99
 100 static void reg_file_set_group(u16 set_group)
 101 {
 102         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
 103 }
 104
 105 static void reg_file_set_stage(u8 set_stage)
 106 {
 107         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
 108 }
 109
 110 static void reg_file_set_sub_stage(u8 set_sub_stage)
 111 {
 112         set_sub_stage &= 0xff;
 113         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
 114 }
 115
 116 /**
 117  * phy_mgr_initialize() - Initialize PHY Manager
 118  *
 119  * Initialize PHY Manager.
 120  */
 121 static void phy_mgr_initialize(void)
 122 {
 123         u32 ratio;
 124
 125         debug("%s:%d\n", __func__, __LINE__);
 126         /* Calibration has control over path to memory */
 127         /*
 128          * In Hard PHY this is a 2-bit control:
 129          * 0: AFI Mux Select
 130          * 1: DDIO Mux Select
 131          */
 132         writel(0x3, &phy_mgr_cfg->mux_sel);
 133
 134         /* USER memory clock is not stable we begin initialization  */
 135         writel(0, &phy_mgr_cfg->reset_mem_stbl);
 136
 137         /* USER calibration status all set to zero */
 138         writel(0, &phy_mgr_cfg->cal_status);
 139
 140         writel(0, &phy_mgr_cfg->cal_debug_info);
 141
 142         /* Init params only if we do NOT skip calibration. */
 143         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
 144                 return;
 145
 146         ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
 147                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
 148         param->read_correct_mask_vg = (1 << ratio) - 1;
 149         param->write_correct_mask_vg = (1 << ratio) - 1;
 150         param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
 151         param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
 152         ratio = RW_MGR_MEM_DATA_WIDTH /
 153                 RW_MGR_MEM_DATA_MASK_WIDTH;
 154         param->dm_correct_mask = (1 << ratio) - 1;
 155 }
 156
 157 static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
 158 {
 159         uint32_t odt_mask_0 = 0;
 160         uint32_t odt_mask_1 = 0;
 161         uint32_t cs_and_odt_mask;
 162
 163         if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
 164                 if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
 165                         /*
 166                          * 1 Rank
 167                          * Read: ODT = 0
 168                          * Write: ODT = 1
 169                          */
 170                         odt_mask_0 = 0x0;
 171                         odt_mask_1 = 0x1;
 172                 } else if (RW_MGR_MEM_NUMBER_OF_RANKS == 2) {
 173                         /* 2 Ranks */
 174                         if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
 175                                 /* - Dual-Slot , Single-Rank
 176                                  * (1 chip-select per DIMM)
 177                                  * OR
 178                                  * - RDIMM, 4 total CS (2 CS per DIMM)
 179                                  * means 2 DIMM
 180                                  * Since MEM_NUMBER_OF_RANKS is 2 they are
 181                                  * both single rank
 182                                  * with 2 CS each (special for RDIMM)
 183                                  * Read: Turn on ODT on the opposite rank
 184                                  * Write: Turn on ODT on all ranks
 185                                  */
 186                                 odt_mask_0 = 0x3 & ~(1 << rank);
 187                                 odt_mask_1 = 0x3;
 188                         } else {
 189                                 /*
 190                                  * USER - Single-Slot , Dual-rank DIMMs
 191                                  * (2 chip-selects per DIMM)
 192                                  * USER Read: Turn on ODT off on all ranks
 193                                  * USER Write: Turn on ODT on active rank
 194                                  */
 195                                 odt_mask_0 = 0x0;
 196                                 odt_mask_1 = 0x3 & (1 << rank);
 197                         }
 198                 } else {
 199                         /* 4 Ranks
 200                          * Read:
 201                          * ----------+-----------------------+
 202                          *           |                       |
 203                          *           |         ODT           |
 204                          * Read From +-----------------------+
 205                          *   Rank    |  3  |  2  |  1  |  0  |
 206                          * ----------+-----+-----+-----+-----+
 207                          *     0     |  0  |  1  |  0  |  0  |
 208                          *     1     |  1  |  0  |  0  |  0  |
 209                          *     2     |  0  |  0  |  0  |  1  |
 210                          *     3     |  0  |  0  |  1  |  0  |
 211                          * ----------+-----+-----+-----+-----+
 212                          *
 213                          * Write:
 214                          * ----------+-----------------------+
 215                          *           |                       |
 216                          *           |         ODT           |
 217                          * Write To  +-----------------------+
 218                          *   Rank    |  3  |  2  |  1  |  0  |
 219                          * ----------+-----+-----+-----+-----+
 220                          *     0     |  0  |  1  |  0  |  1  |
 221                          *     1     |  1  |  0  |  1  |  0  |
 222                          *     2     |  0  |  1  |  0  |  1  |
 223                          *     3     |  1  |  0  |  1  |  0  |
 224                          * ----------+-----+-----+-----+-----+
 225                          */
 226                         switch (rank) {
 227                         case 0:
 228                                 odt_mask_0 = 0x4;
 229                                 odt_mask_1 = 0x5;
 230                                 break;
 231                         case 1:
 232                                 odt_mask_0 = 0x8;
 233                                 odt_mask_1 = 0xA;
 234                                 break;
 235                         case 2:
 236                                 odt_mask_0 = 0x1;
 237                                 odt_mask_1 = 0x5;
 238                                 break;
 239                         case 3:
 240                                 odt_mask_0 = 0x2;
 241                                 odt_mask_1 = 0xA;
 242                                 break;
 243                         }
 244                 }
 245         } else {
 246                 odt_mask_0 = 0x0;
 247                 odt_mask_1 = 0x0;
 248         }
 249
 250         cs_and_odt_mask =
 251                 (0xFF & ~(1 << rank)) |
 252                 ((0xFF & odt_mask_0) << 8) |
 253                 ((0xFF & odt_mask_1) << 16);
 254         writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 255                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 256 }
 257
 258 /**
 259  * scc_mgr_set() - Set SCC Manager register
 260  * @off:        Base offset in SCC Manager space
 261  * @grp:        Read/Write group
 262  * @val:        Value to be set
 263  *
 264  * This function sets the SCC Manager (Scan Chain Control Manager) register.
 265  */
 266 static void scc_mgr_set(u32 off, u32 grp, u32 val)
 267 {
 268         writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
 269 }
 270
 271 /**
 272  * scc_mgr_initialize() - Initialize SCC Manager registers
 273  *
 274  * Initialize SCC Manager registers.
 275  */
 276 static void scc_mgr_initialize(void)
 277 {
 278         /*
 279          * Clear register file for HPS. 16 (2^4) is the size of the
 280          * full register file in the scc mgr:
 281          *      RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
 282          *                             MEM_IF_READ_DQS_WIDTH - 1);
 283          */
 284         int i;
 285
 286         for (i = 0; i < 16; i++) {
 287                 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
 288                            __func__, __LINE__, i);
 289                 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
 290         }
 291 }
 292
 293 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
 294 {
 295         scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
 296 }
 297
 298 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
 299 {
 300         scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
 301 }
 302
 303 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
 304 {
 305         scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
 306 }
 307
 308 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
 309 {
 310         scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
 311 }
 312
 313 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
 314 {
 315         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 316                     delay);
 317 }
 318
 319 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
 320 {
 321         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
 322 }
 323
 324 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
 325 {
 326         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
 327 }
 328
 329 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
 330 {
 331         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 332                     delay);
 333 }
 334
 335 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
 336 {
 337         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
 338                     RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
 339                     delay);
 340 }
 341
 342 /* load up dqs config settings */
 343 static void scc_mgr_load_dqs(uint32_t dqs)
 344 {
 345         writel(dqs, &sdr_scc_mgr->dqs_ena);
 346 }
 347
 348 /* load up dqs io config settings */
 349 static void scc_mgr_load_dqs_io(void)
 350 {
 351         writel(0, &sdr_scc_mgr->dqs_io_ena);
 352 }
 353
 354 /* load up dq config settings */
 355 static void scc_mgr_load_dq(uint32_t dq_in_group)
 356 {
 357         writel(dq_in_group, &sdr_scc_mgr->dq_ena);
 358 }
 359
 360 /* load up dm config settings */
 361 static void scc_mgr_load_dm(uint32_t dm)
 362 {
 363         writel(dm, &sdr_scc_mgr->dm_ena);
 364 }
 365
 366 /**
 367  * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
 368  * @off:        Base offset in SCC Manager space
 369  * @grp:        Read/Write group
 370  * @val:        Value to be set
 371  * @update:     If non-zero, trigger SCC Manager update for all ranks
 372  *
 373  * This function sets the SCC Manager (Scan Chain Control Manager) register
 374  * and optionally triggers the SCC update for all ranks.
 375  */
 376 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
 377                                   const int update)
 378 {
 379         u32 r;
 380
 381         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 382              r += NUM_RANKS_PER_SHADOW_REG) {
 383                 scc_mgr_set(off, grp, val);
 384
 385                 if (update || (r == 0)) {
 386                         writel(grp, &sdr_scc_mgr->dqs_ena);
 387                         writel(0, &sdr_scc_mgr->update);
 388                 }
 389         }
 390 }
 391
 392 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
 393 {
 394         /*
 395          * USER although the h/w doesn't support different phases per
 396          * shadow register, for simplicity our scc manager modeling
 397          * keeps different phase settings per shadow reg, and it's
 398          * important for us to keep them in sync to match h/w.
 399          * for efficiency, the scan chain update should occur only
 400          * once to sr0.
 401          */
 402         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
 403                               read_group, phase, 0);
 404 }
 405
 406 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
 407                                                      uint32_t phase)
 408 {
 409         /*
 410          * USER although the h/w doesn't support different phases per
 411          * shadow register, for simplicity our scc manager modeling
 412          * keeps different phase settings per shadow reg, and it's
 413          * important for us to keep them in sync to match h/w.
 414          * for efficiency, the scan chain update should occur only
 415          * once to sr0.
 416          */
 417         scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
 418                               write_group, phase, 0);
 419 }
 420
 421 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
 422                                                uint32_t delay)
 423 {
 424         /*
 425          * In shadow register mode, the T11 settings are stored in
 426          * registers in the core, which are updated by the DQS_ENA
 427          * signals. Not issuing the SCC_MGR_UPD command allows us to
 428          * save lots of rank switching overhead, by calling
 429          * select_shadow_regs_for_update with update_scan_chains
 430          * set to 0.
 431          */
 432         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
 433                               read_group, delay, 1);
 434         writel(0, &sdr_scc_mgr->update);
 435 }
 436
 437 /**
 438  * scc_mgr_set_oct_out1_delay() - Set OCT output delay
 439  * @write_group:        Write group
 440  * @delay:              Delay value
 441  *
 442  * This function sets the OCT output delay in SCC manager.
 443  */
 444 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
 445 {
 446         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 447                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 448         const int base = write_group * ratio;
 449         int i;
 450         /*
 451          * Load the setting in the SCC manager
 452          * Although OCT affects only write data, the OCT delay is controlled
 453          * by the DQS logic block which is instantiated once per read group.
 454          * For protocols where a write group consists of multiple read groups,
 455          * the setting must be set multiple times.
 456          */
 457         for (i = 0; i < ratio; i++)
 458                 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
 459 }
 460
 461 /**
 462  * scc_mgr_set_hhp_extras() - Set HHP extras.
 463  *
 464  * Load the fixed setting in the SCC manager HHP extras.
 465  */
 466 static void scc_mgr_set_hhp_extras(void)
 467 {
 468         /*
 469          * Load the fixed setting in the SCC manager
 470          * bits: 0:0 = 1'b1     - DQS bypass
 471          * bits: 1:1 = 1'b1     - DQ bypass
 472          * bits: 4:2 = 3'b001   - rfifo_mode
 473          * bits: 6:5 = 2'b01    - rfifo clock_select
 474          * bits: 7:7 = 1'b0     - separate gating from ungating setting
 475          * bits: 8:8 = 1'b0     - separate OE from Output delay setting
 476          */
 477         const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
 478                           (1 << 2) | (1 << 1) | (1 << 0);
 479         const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
 480                          SCC_MGR_HHP_GLOBALS_OFFSET |
 481                          SCC_MGR_HHP_EXTRAS_OFFSET;
 482
 483         debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
 484                    __func__, __LINE__);
 485         writel(value, addr);
 486         debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
 487                    __func__, __LINE__);
 488 }
 489
 490 /**
 491  * scc_mgr_zero_all() - Zero all DQS config
 492  *
 493  * Zero all DQS config.
 494  */
 495 static void scc_mgr_zero_all(void)
 496 {
 497         int i, r;
 498
 499         /*
 500          * USER Zero all DQS config settings, across all groups and all
 501          * shadow registers
 502          */
 503         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 504              r += NUM_RANKS_PER_SHADOW_REG) {
 505                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
 506                         /*
 507                          * The phases actually don't exist on a per-rank basis,
 508                          * but there's no harm updating them several times, so
 509                          * let's keep the code simple.
 510                          */
 511                         scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
 512                         scc_mgr_set_dqs_en_phase(i, 0);
 513                         scc_mgr_set_dqs_en_delay(i, 0);
 514                 }
 515
 516                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
 517                         scc_mgr_set_dqdqs_output_phase(i, 0);
 518                         /* Arria V/Cyclone V don't have out2. */
 519                         scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
 520                 }
 521         }
 522
 523         /* Multicast to all DQS group enables. */
 524         writel(0xff, &sdr_scc_mgr->dqs_ena);
 525         writel(0, &sdr_scc_mgr->update);
 526 }
 527
 528 /**
 529  * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
 530  * @write_group:        Write group
 531  *
 532  * Set bypass mode and trigger SCC update.
 533  */
 534 static void scc_set_bypass_mode(const u32 write_group)
 535 {
 536         /* Multicast to all DQ enables. */
 537         writel(0xff, &sdr_scc_mgr->dq_ena);
 538         writel(0xff, &sdr_scc_mgr->dm_ena);
 539
 540         /* Update current DQS IO enable. */
 541         writel(0, &sdr_scc_mgr->dqs_io_ena);
 542
 543         /* Update the DQS logic. */
 544         writel(write_group, &sdr_scc_mgr->dqs_ena);
 545
 546         /* Hit update. */
 547         writel(0, &sdr_scc_mgr->update);
 548 }
 549
 550 /**
 551  * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
 552  * @write_group:        Write group
 553  *
 554  * Load DQS settings for Write Group, do not trigger SCC update.
 555  */
 556 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
 557 {
 558         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 559                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 560         const int base = write_group * ratio;
 561         int i;
 562         /*
 563          * Load the setting in the SCC manager
 564          * Although OCT affects only write data, the OCT delay is controlled
 565          * by the DQS logic block which is instantiated once per read group.
 566          * For protocols where a write group consists of multiple read groups,
 567          * the setting must be set multiple times.
 568          */
 569         for (i = 0; i < ratio; i++)
 570                 writel(base + i, &sdr_scc_mgr->dqs_ena);
 571 }
 572
 573 /**
 574  * scc_mgr_zero_group() - Zero all configs for a group
 575  *
 576  * Zero DQ, DM, DQS and OCT configs for a group.
 577  */
 578 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
 579 {
 580         int i, r;
 581
 582         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 583              r += NUM_RANKS_PER_SHADOW_REG) {
 584                 /* Zero all DQ config settings. */
 585                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 586                         scc_mgr_set_dq_out1_delay(i, 0);
 587                         if (!out_only)
 588                                 scc_mgr_set_dq_in_delay(i, 0);
 589                 }
 590
 591                 /* Multicast to all DQ enables. */
 592                 writel(0xff, &sdr_scc_mgr->dq_ena);
 593
 594                 /* Zero all DM config settings. */
 595                 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 596                         scc_mgr_set_dm_out1_delay(i, 0);
 597
 598                 /* Multicast to all DM enables. */
 599                 writel(0xff, &sdr_scc_mgr->dm_ena);
 600
 601                 /* Zero all DQS IO settings. */
 602                 if (!out_only)
 603                         scc_mgr_set_dqs_io_in_delay(0);
 604
 605                 /* Arria V/Cyclone V don't have out2. */
 606                 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
 607                 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
 608                 scc_mgr_load_dqs_for_write_group(write_group);
 609
 610                 /* Multicast to all DQS IO enables (only 1 in total). */
 611                 writel(0, &sdr_scc_mgr->dqs_io_ena);
 612
 613                 /* Hit update to zero everything. */
 614                 writel(0, &sdr_scc_mgr->update);
 615         }
 616 }
 617
 618 /*
 619  * apply and load a particular input delay for the DQ pins in a group
 620  * group_bgn is the index of the first dq pin (in the write group)
 621  */
 622 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
 623 {
 624         uint32_t i, p;
 625
 626         for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
 627                 scc_mgr_set_dq_in_delay(p, delay);
 628                 scc_mgr_load_dq(p);
 629         }
 630 }
 631
 632 /**
 633  * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
 634  * @delay:              Delay value
 635  *
 636  * Apply and load a particular output delay for the DQ pins in a group.
 637  */
 638 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
 639 {
 640         int i;
 641
 642         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 643                 scc_mgr_set_dq_out1_delay(i, delay);
 644                 scc_mgr_load_dq(i);
 645         }
 646 }
 647
 648 /* apply and load a particular output delay for the DM pins in a group */
 649 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
 650 {
 651         uint32_t i;
 652
 653         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
 654                 scc_mgr_set_dm_out1_delay(i, delay1);
 655                 scc_mgr_load_dm(i);
 656         }
 657 }
 658
 659
 660 /* apply and load delay on both DQS and OCT out1 */
 661 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
 662                                                     uint32_t delay)
 663 {
 664         scc_mgr_set_dqs_out1_delay(delay);
 665         scc_mgr_load_dqs_io();
 666
 667         scc_mgr_set_oct_out1_delay(write_group, delay);
 668         scc_mgr_load_dqs_for_write_group(write_group);
 669 }
 670
 671 /**
 672  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
 673  * @write_group:        Write group
 674  * @delay:              Delay value
 675  *
 676  * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
 677  */
 678 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
 679                                                   const u32 delay)
 680 {
 681         u32 i, new_delay;
 682
 683         /* DQ shift */
 684         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
 685                 scc_mgr_load_dq(i);
 686
 687         /* DM shift */
 688         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 689                 scc_mgr_load_dm(i);
 690
 691         /* DQS shift */
 692         new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
 693         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 694                 debug_cond(DLEVEL == 1,
 695                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 696                            __func__, __LINE__, write_group, delay, new_delay,
 697                            IO_IO_OUT2_DELAY_MAX,
 698                            new_delay - IO_IO_OUT2_DELAY_MAX);
 699                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 700                 scc_mgr_set_dqs_out1_delay(new_delay);
 701         }
 702
 703         scc_mgr_load_dqs_io();
 704
 705         /* OCT shift */
 706         new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
 707         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 708                 debug_cond(DLEVEL == 1,
 709                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 710                            __func__, __LINE__, write_group, delay,
 711                            new_delay, IO_IO_OUT2_DELAY_MAX,
 712                            new_delay - IO_IO_OUT2_DELAY_MAX);
 713                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 714                 scc_mgr_set_oct_out1_delay(write_group, new_delay);
 715         }
 716
 717         scc_mgr_load_dqs_for_write_group(write_group);
 718 }
 719
 720 /**
 721  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
 722  * @write_group:        Write group
 723  * @delay:              Delay value
 724  *
 725  * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
 726  */
 727 static void
 728 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
 729                                                 const u32 delay)
 730 {
 731         int r;
 732
 733         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 734              r += NUM_RANKS_PER_SHADOW_REG) {
 735                 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
 736                 writel(0, &sdr_scc_mgr->update);
 737         }
 738 }
 739
 740 /**
 741  * set_jump_as_return() - Return instruction optimization
 742  *
 743  * Optimization used to recover some slots in ddr3 inst_rom could be
 744  * applied to other protocols if we wanted to
 745  */
 746 static void set_jump_as_return(void)
 747 {
 748         /*
 749          * To save space, we replace return with jump to special shared
 750          * RETURN instruction so we set the counter to large value so that
 751          * we always jump.
 752          */
 753         writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
 754         writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 755 }
 756
 757 /*
 758  * should always use constants as argument to ensure all computations are
 759  * performed at compile time
 760  */
 761 static void delay_for_n_mem_clocks(const uint32_t clocks)
 762 {
 763         uint32_t afi_clocks;
 764         uint8_t inner = 0;
 765         uint8_t outer = 0;
 766         uint16_t c_loop = 0;
 767
 768         debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
 769
 770
 771         afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
 772         /* scale (rounding up) to get afi clocks */
 773
 774         /*
 775          * Note, we don't bother accounting for being off a little bit
 776          * because of a few extra instructions in outer loops
 777          * Note, the loops have a test at the end, and do the test before
 778          * the decrement, and so always perform the loop
 779          * 1 time more than the counter value
 780          */
 781         if (afi_clocks == 0) {
 782                 ;
 783         } else if (afi_clocks <= 0x100) {
 784                 inner = afi_clocks-1;
 785                 outer = 0;
 786                 c_loop = 0;
 787         } else if (afi_clocks <= 0x10000) {
 788                 inner = 0xff;
 789                 outer = (afi_clocks-1) >> 8;
 790                 c_loop = 0;
 791         } else {
 792                 inner = 0xff;
 793                 outer = 0xff;
 794                 c_loop = (afi_clocks-1) >> 16;
 795         }
 796
 797         /*
 798          * rom instructions are structured as follows:
 799          *
 800          *    IDLE_LOOP2: jnz cntr0, TARGET_A
 801          *    IDLE_LOOP1: jnz cntr1, TARGET_B
 802          *                return
 803          *
 804          * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
 805          * TARGET_B is set to IDLE_LOOP2 as well
 806          *
 807          * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
 808          * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
 809          *
 810          * a little confusing, but it helps save precious space in the inst_rom
 811          * and sequencer rom and keeps the delays more accurate and reduces
 812          * overhead
 813          */
 814         if (afi_clocks <= 0x100) {
 815                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 816                         &sdr_rw_load_mgr_regs->load_cntr1);
 817
 818                 writel(RW_MGR_IDLE_LOOP1,
 819                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 820
 821                 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 822                                           RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 823         } else {
 824                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 825                         &sdr_rw_load_mgr_regs->load_cntr0);
 826
 827                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
 828                         &sdr_rw_load_mgr_regs->load_cntr1);
 829
 830                 writel(RW_MGR_IDLE_LOOP2,
 831                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 832
 833                 writel(RW_MGR_IDLE_LOOP2,
 834                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 835
 836                 /* hack to get around compiler not being smart enough */
 837                 if (afi_clocks <= 0x10000) {
 838                         /* only need to run once */
 839                         writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 840                                                   RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 841                 } else {
 842                         do {
 843                                 writel(RW_MGR_IDLE_LOOP2,
 844                                         SDR_PHYGRP_RWMGRGRP_ADDRESS |
 845                                         RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 846                         } while (c_loop-- != 0);
 847                 }
 848         }
 849         debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
 850 }
 851
 852 /**
 853  * rw_mgr_mem_init_load_regs() - Load instruction registers
 854  * @cntr0:      Counter 0 value
 855  * @cntr1:      Counter 1 value
 856  * @cntr2:      Counter 2 value
 857  * @jump:       Jump instruction value
 858  *
 859  * Load instruction registers.
 860  */
 861 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
 862 {
 863         uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 864                            RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 865
 866         /* Load counters */
 867         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
 868                &sdr_rw_load_mgr_regs->load_cntr0);
 869         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
 870                &sdr_rw_load_mgr_regs->load_cntr1);
 871         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
 872                &sdr_rw_load_mgr_regs->load_cntr2);
 873
 874         /* Load jump address */
 875         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 876         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 877         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
 878
 879         /* Execute count instruction */
 880         writel(jump, grpaddr);
 881 }
 882
 883 /**
 884  * rw_mgr_mem_load_user() - Load user calibration values
 885  * @fin1:       Final instruction 1
 886  * @fin2:       Final instruction 2
 887  * @precharge:  If 1, precharge the banks at the end
 888  *
 889  * Load user calibration values and optionally precharge the banks.
 890  */
 891 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
 892                                  const int precharge)
 893 {
 894         u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 895                       RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 896         u32 r;
 897
 898         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
 899                 if (param->skip_ranks[r]) {
 900                         /* request to skip the rank */
 901                         continue;
 902                 }
 903
 904                 /* set rank */
 905                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
 906
 907                 /* precharge all banks ... */
 908                 if (precharge)
 909                         writel(RW_MGR_PRECHARGE_ALL, grpaddr);
 910
 911                 /*
 912                  * USER Use Mirror-ed commands for odd ranks if address
 913                  * mirrorring is on
 914                  */
 915                 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
 916                         set_jump_as_return();
 917                         writel(RW_MGR_MRS2_MIRR, grpaddr);
 918                         delay_for_n_mem_clocks(4);
 919                         set_jump_as_return();
 920                         writel(RW_MGR_MRS3_MIRR, grpaddr);
 921                         delay_for_n_mem_clocks(4);
 922                         set_jump_as_return();
 923                         writel(RW_MGR_MRS1_MIRR, grpaddr);
 924                         delay_for_n_mem_clocks(4);
 925                         set_jump_as_return();
 926                         writel(fin1, grpaddr);
 927                 } else {
 928                         set_jump_as_return();
 929                         writel(RW_MGR_MRS2, grpaddr);
 930                         delay_for_n_mem_clocks(4);
 931                         set_jump_as_return();
 932                         writel(RW_MGR_MRS3, grpaddr);
 933                         delay_for_n_mem_clocks(4);
 934                         set_jump_as_return();
 935                         writel(RW_MGR_MRS1, grpaddr);
 936                         set_jump_as_return();
 937                         writel(fin2, grpaddr);
 938                 }
 939
 940                 if (precharge)
 941                         continue;
 942
 943                 set_jump_as_return();
 944                 writel(RW_MGR_ZQCL, grpaddr);
 945
 946                 /* tZQinit = tDLLK = 512 ck cycles */
 947                 delay_for_n_mem_clocks(512);
 948         }
 949 }
 950
 951 static void rw_mgr_mem_initialize(void)
 952 {
 953         debug("%s:%d\n", __func__, __LINE__);
 954
 955         /* The reset / cke part of initialization is broadcasted to all ranks */
 956         writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 957                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 958
 959         /*
 960          * Here's how you load register for a loop
 961          * Counters are located @ 0x800
 962          * Jump address are located @ 0xC00
 963          * For both, registers 0 to 3 are selected using bits 3 and 2, like
 964          * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
 965          * I know this ain't pretty, but Avalon bus throws away the 2 least
 966          * significant bits
 967          */
 968
 969         /* start with memory RESET activated */
 970
 971         /* tINIT = 200us */
 972
 973         /*
 974          * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
 975          * If a and b are the number of iteration in 2 nested loops
 976          * it takes the following number of cycles to complete the operation:
 977          * number_of_cycles = ((2 + n) * a + 2) * b
 978          * where n is the number of instruction in the inner loop
 979          * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
 980          * b = 6A
 981          */
 982         rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
 983                                   SEQ_TINIT_CNTR2_VAL,
 984                                   RW_MGR_INIT_RESET_0_CKE_0);
 985
 986         /* indicate that memory is stable */
 987         writel(1, &phy_mgr_cfg->reset_mem_stbl);
 988
 989         /*
 990          * transition the RESET to high
 991          * Wait for 500us
 992          */
 993
 994         /*
 995          * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
 996          * If a and b are the number of iteration in 2 nested loops
 997          * it takes the following number of cycles to complete the operation
 998          * number_of_cycles = ((2 + n) * a + 2) * b
 999          * where n is the number of instruction in the inner loop
1000          * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1001          * b = FF
1002          */
1003         rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1004                                   SEQ_TRESET_CNTR2_VAL,
1005                                   RW_MGR_INIT_RESET_1_CKE_0);
1006
1007         /* bring up clock enable */
1008
1009         /* tXRP < 250 ck cycles */
1010         delay_for_n_mem_clocks(250);
1011
1012         rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1013                              0);
1014 }
1015
1016 /*
1017  * At the end of calibration we have to program the user settings in, and
1018  * USER  hand off the memory to the user.
1019  */
1020 static void rw_mgr_mem_handoff(void)
1021 {
1022         rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1023         /*
1024          * USER  need to wait tMOD (12CK or 15ns) time before issuing
1025          * other commands, but we will have plenty of NIOS cycles before
1026          * actual handoff so its okay.
1027          */
1028 }
1029
1030 /*
1031  * performs a guaranteed read on the patterns we are going to use during a
1032  * read test to ensure memory works
1033  */
1034 static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
1035         uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
1036         uint32_t all_ranks)
1037 {
1038         uint32_t r, vg;
1039         uint32_t correct_mask_vg;
1040         uint32_t tmp_bit_chk;
1041         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1042                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1043         uint32_t addr;
1044         uint32_t base_rw_mgr;
1045
1046         *bit_chk = param->read_correct_mask;
1047         correct_mask_vg = param->read_correct_mask_vg;
1048
1049         for (r = rank_bgn; r < rank_end; r++) {
1050                 if (param->skip_ranks[r])
1051                         /* request to skip the rank */
1052                         continue;
1053
1054                 /* set rank */
1055                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1056
1057                 /* Load up a constant bursts of read commands */
1058                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1059                 writel(RW_MGR_GUARANTEED_READ,
1060                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1061
1062                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1063                 writel(RW_MGR_GUARANTEED_READ_CONT,
1064                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1065
1066                 tmp_bit_chk = 0;
1067                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1068                         /* reset the fifos to get pointers to known state */
1069
1070                         writel(0, &phy_mgr_cmd->fifo_reset);
1071                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1072                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1073
1074                         tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1075                                 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1076
1077                         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1078                         writel(RW_MGR_GUARANTEED_READ, addr +
1079                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1080                                 vg) << 2));
1081
1082                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1083                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
1084
1085                         if (vg == 0)
1086                                 break;
1087                 }
1088                 *bit_chk &= tmp_bit_chk;
1089         }
1090
1091         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1092         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1093
1094         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1095         debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
1096                    %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
1097                    (long unsigned int)(*bit_chk == param->read_correct_mask));
1098         return *bit_chk == param->read_correct_mask;
1099 }
1100
1101 static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
1102         (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
1103 {
1104         return rw_mgr_mem_calibrate_read_test_patterns(0, group,
1105                 num_tries, bit_chk, 1);
1106 }
1107
1108 /* load up the patterns we are going to use during a read test */
1109 static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
1110         uint32_t all_ranks)
1111 {
1112         uint32_t r;
1113         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1114                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1115
1116         debug("%s:%d\n", __func__, __LINE__);
1117         for (r = rank_bgn; r < rank_end; r++) {
1118                 if (param->skip_ranks[r])
1119                         /* request to skip the rank */
1120                         continue;
1121
1122                 /* set rank */
1123                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1124
1125                 /* Load up a constant bursts */
1126                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1127
1128                 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1129                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1130
1131                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1132
1133                 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1134                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1135
1136                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1137
1138                 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1139                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1140
1141                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1142
1143                 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1144                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1145
1146                 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1147                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1148         }
1149
1150         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1151 }
1152
1153 /*
1154  * try a read and see if it returns correct data back. has dummy reads
1155  * inserted into the mix used to align dqs enable. has more thorough checks
1156  * than the regular read test.
1157  */
1158 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1159         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1160         uint32_t all_groups, uint32_t all_ranks)
1161 {
1162         uint32_t r, vg;
1163         uint32_t correct_mask_vg;
1164         uint32_t tmp_bit_chk;
1165         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1166                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1167         uint32_t addr;
1168         uint32_t base_rw_mgr;
1169
1170         *bit_chk = param->read_correct_mask;
1171         correct_mask_vg = param->read_correct_mask_vg;
1172
1173         uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1174                 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1175
1176         for (r = rank_bgn; r < rank_end; r++) {
1177                 if (param->skip_ranks[r])
1178                         /* request to skip the rank */
1179                         continue;
1180
1181                 /* set rank */
1182                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1183
1184                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1185
1186                 writel(RW_MGR_READ_B2B_WAIT1,
1187                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1188
1189                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1190                 writel(RW_MGR_READ_B2B_WAIT2,
1191                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1192
1193                 if (quick_read_mode)
1194                         writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1195                         /* need at least two (1+1) reads to capture failures */
1196                 else if (all_groups)
1197                         writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1198                 else
1199                         writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1200
1201                 writel(RW_MGR_READ_B2B,
1202                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1203                 if (all_groups)
1204                         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1205                                RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1206                                &sdr_rw_load_mgr_regs->load_cntr3);
1207                 else
1208                         writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1209
1210                 writel(RW_MGR_READ_B2B,
1211                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1212
1213                 tmp_bit_chk = 0;
1214                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1215                         /* reset the fifos to get pointers to known state */
1216                         writel(0, &phy_mgr_cmd->fifo_reset);
1217                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1218                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1219
1220                         tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1221                                 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1222
1223                         if (all_groups)
1224                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1225                         else
1226                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1227
1228                         writel(RW_MGR_READ_B2B, addr +
1229                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1230                                vg) << 2));
1231
1232                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1233                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1234
1235                         if (vg == 0)
1236                                 break;
1237                 }
1238                 *bit_chk &= tmp_bit_chk;
1239         }
1240
1241         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1242         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1243
1244         if (all_correct) {
1245                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1246                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1247                            (%u == %u) => %lu", __func__, __LINE__, group,
1248                            all_groups, *bit_chk, param->read_correct_mask,
1249                            (long unsigned int)(*bit_chk ==
1250                            param->read_correct_mask));
1251                 return *bit_chk == param->read_correct_mask;
1252         } else  {
1253                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1254                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1255                            (%u != %lu) => %lu\n", __func__, __LINE__,
1256                            group, all_groups, *bit_chk, (long unsigned int)0,
1257                            (long unsigned int)(*bit_chk != 0x00));
1258                 return *bit_chk != 0x00;
1259         }
1260 }
1261
1262 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1263         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1264         uint32_t all_groups)
1265 {
1266         return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1267                                               bit_chk, all_groups, 1);
1268 }
1269
1270 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1271 {
1272         writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1273         (*v)++;
1274 }
1275
1276 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1277 {
1278         uint32_t i;
1279
1280         for (i = 0; i < VFIFO_SIZE-1; i++)
1281                 rw_mgr_incr_vfifo(grp, v);
1282 }
1283
1284 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1285 {
1286         uint32_t  v;
1287         uint32_t fail_cnt = 0;
1288         uint32_t test_status;
1289
1290         for (v = 0; v < VFIFO_SIZE; ) {
1291                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1292                            __func__, __LINE__, v);
1293                 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1294                         (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1295                 if (!test_status) {
1296                         fail_cnt++;
1297
1298                         if (fail_cnt == 2)
1299                                 break;
1300                 }
1301
1302                 /* fiddle with FIFO */
1303                 rw_mgr_incr_vfifo(grp, &v);
1304         }
1305
1306         if (v >= VFIFO_SIZE) {
1307                 /* no failing read found!! Something must have gone wrong */
1308                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1309                            __func__, __LINE__);
1310                 return 0;
1311         } else {
1312                 return v;
1313         }
1314 }
1315
1316 static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
1317                               uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1318                               uint32_t *v, uint32_t *d, uint32_t *p,
1319                               uint32_t *i, uint32_t *max_working_cnt)
1320 {
1321         uint32_t found_begin = 0;
1322         uint32_t tmp_delay = 0;
1323         uint32_t test_status;
1324
1325         for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1326                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1327                 *work_bgn = tmp_delay;
1328                 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1329
1330                 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1331                         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1332                                 IO_DELAY_PER_OPA_TAP) {
1333                                 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1334
1335                                 test_status =
1336                                 rw_mgr_mem_calibrate_read_test_all_ranks
1337                                 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1338
1339                                 if (test_status) {
1340                                         *max_working_cnt = 1;
1341                                         found_begin = 1;
1342                                         break;
1343                                 }
1344                         }
1345
1346                         if (found_begin)
1347                                 break;
1348
1349                         if (*p > IO_DQS_EN_PHASE_MAX)
1350                                 /* fiddle with FIFO */
1351                                 rw_mgr_incr_vfifo(*grp, v);
1352                 }
1353
1354                 if (found_begin)
1355                         break;
1356         }
1357
1358         if (*i >= VFIFO_SIZE) {
1359                 /* cannot find working solution */
1360                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1361                            ptap/dtap\n", __func__, __LINE__);
1362                 return 0;
1363         } else {
1364                 return 1;
1365         }
1366 }
1367
1368 static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1369                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1370                              uint32_t *p, uint32_t *max_working_cnt)
1371 {
1372         uint32_t found_begin = 0;
1373         uint32_t tmp_delay;
1374
1375         /* Special case code for backing up a phase */
1376         if (*p == 0) {
1377                 *p = IO_DQS_EN_PHASE_MAX;
1378                 rw_mgr_decr_vfifo(*grp, v);
1379         } else {
1380                 (*p)--;
1381         }
1382         tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1383         scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1384
1385         for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1386                 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1387                 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1388
1389                 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1390                                                              PASS_ONE_BIT,
1391                                                              bit_chk, 0)) {
1392                         found_begin = 1;
1393                         *work_bgn = tmp_delay;
1394                         break;
1395                 }
1396         }
1397
1398         /* We have found a working dtap before the ptap found above */
1399         if (found_begin == 1)
1400                 (*max_working_cnt)++;
1401
1402         /*
1403          * Restore VFIFO to old state before we decremented it
1404          * (if needed).
1405          */
1406         (*p)++;
1407         if (*p > IO_DQS_EN_PHASE_MAX) {
1408                 *p = 0;
1409                 rw_mgr_incr_vfifo(*grp, v);
1410         }
1411
1412         scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1413 }
1414
1415 static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1416                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1417                              uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1418                              uint32_t *work_end)
1419 {
1420         uint32_t found_end = 0;
1421
1422         (*p)++;
1423         *work_end += IO_DELAY_PER_OPA_TAP;
1424         if (*p > IO_DQS_EN_PHASE_MAX) {
1425                 /* fiddle with FIFO */
1426                 *p = 0;
1427                 rw_mgr_incr_vfifo(*grp, v);
1428         }
1429
1430         for (; *i < VFIFO_SIZE + 1; (*i)++) {
1431                 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1432                         += IO_DELAY_PER_OPA_TAP) {
1433                         scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1434
1435                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1436                                 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1437                                 found_end = 1;
1438                                 break;
1439                         } else {
1440                                 (*max_working_cnt)++;
1441                         }
1442                 }
1443
1444                 if (found_end)
1445                         break;
1446
1447                 if (*p > IO_DQS_EN_PHASE_MAX) {
1448                         /* fiddle with FIFO */
1449                         rw_mgr_incr_vfifo(*grp, v);
1450                         *p = 0;
1451                 }
1452         }
1453
1454         if (*i >= VFIFO_SIZE + 1) {
1455                 /* cannot see edge of failing read */
1456                 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1457                            failed\n", __func__, __LINE__);
1458                 return 0;
1459         } else {
1460                 return 1;
1461         }
1462 }
1463
1464 static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
1465                                   uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1466                                   uint32_t *p, uint32_t *work_mid,
1467                                   uint32_t *work_end)
1468 {
1469         int i;
1470         int tmp_delay = 0;
1471
1472         *work_mid = (*work_bgn + *work_end) / 2;
1473
1474         debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1475                    *work_bgn, *work_end, *work_mid);
1476         /* Get the middle delay to be less than a VFIFO delay */
1477         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
1478                 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1479                 ;
1480         debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1481         while (*work_mid > tmp_delay)
1482                 *work_mid -= tmp_delay;
1483         debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
1484
1485         tmp_delay = 0;
1486         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
1487                 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1488                 ;
1489         tmp_delay -= IO_DELAY_PER_OPA_TAP;
1490         debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
1491         for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
1492                 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
1493                 ;
1494         debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
1495
1496         scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
1497         scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1498
1499         /*
1500          * push vfifo until we can successfully calibrate. We can do this
1501          * because the largest possible margin in 1 VFIFO cycle.
1502          */
1503         for (i = 0; i < VFIFO_SIZE; i++) {
1504                 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1505                            *v);
1506                 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1507                                                              PASS_ONE_BIT,
1508                                                              bit_chk, 0)) {
1509                         break;
1510                 }
1511
1512                 /* fiddle with FIFO */
1513                 rw_mgr_incr_vfifo(*grp, v);
1514         }
1515
1516         if (i >= VFIFO_SIZE) {
1517                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
1518                            failed\n", __func__, __LINE__);
1519                 return 0;
1520         } else {
1521                 return 1;
1522         }
1523 }
1524
1525 /* find a good dqs enable to use */
1526 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1527 {
1528         uint32_t v, d, p, i;
1529         uint32_t max_working_cnt;
1530         uint32_t bit_chk;
1531         uint32_t dtaps_per_ptap;
1532         uint32_t work_bgn, work_mid, work_end;
1533         uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1534
1535         debug("%s:%d %u\n", __func__, __LINE__, grp);
1536
1537         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1538
1539         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1540         scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1541
1542         /* ************************************************************** */
1543         /* * Step 0 : Determine number of delay taps for each phase tap * */
1544         dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1545
1546         /* ********************************************************* */
1547         /* * Step 1 : First push vfifo until we get a failing read * */
1548         v = find_vfifo_read(grp, &bit_chk);
1549
1550         max_working_cnt = 0;
1551
1552         /* ******************************************************** */
1553         /* * step 2: find first working phase, increment in ptaps * */
1554         work_bgn = 0;
1555         if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1556                                 &p, &i, &max_working_cnt) == 0)
1557                 return 0;
1558
1559         work_end = work_bgn;
1560
1561         /*
1562          * If d is 0 then the working window covers a phase tap and
1563          * we can follow the old procedure otherwise, we've found the beginning,
1564          * and we need to increment the dtaps until we find the end.
1565          */
1566         if (d == 0) {
1567                 /* ********************************************************* */
1568                 /* * step 3a: if we have room, back off by one and
1569                 increment in dtaps * */
1570
1571                 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1572                                  &max_working_cnt);
1573
1574                 /* ********************************************************* */
1575                 /* * step 4a: go forward from working phase to non working
1576                 phase, increment in ptaps * */
1577                 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1578                                          &i, &max_working_cnt, &work_end) == 0)
1579                         return 0;
1580
1581                 /* ********************************************************* */
1582                 /* * step 5a:  back off one from last, increment in dtaps  * */
1583
1584                 /* Special case code for backing up a phase */
1585                 if (p == 0) {
1586                         p = IO_DQS_EN_PHASE_MAX;
1587                         rw_mgr_decr_vfifo(grp, &v);
1588                 } else {
1589                         p = p - 1;
1590                 }
1591
1592                 work_end -= IO_DELAY_PER_OPA_TAP;
1593                 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1594
1595                 /* * The actual increment of dtaps is done outside of
1596                 the if/else loop to share code */
1597                 d = 0;
1598
1599                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1600                            vfifo=%u ptap=%u\n", __func__, __LINE__,
1601                            v, p);
1602         } else {
1603                 /* ******************************************************* */
1604                 /* * step 3-5b:  Find the right edge of the window using
1605                 delay taps   * */
1606                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1607                            ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1608                            v, p, d, work_bgn);
1609
1610                 work_end = work_bgn;
1611
1612                 /* * The actual increment of dtaps is done outside of the
1613                 if/else loop to share code */
1614
1615                 /* Only here to counterbalance a subtract later on which is
1616                 not needed if this branch of the algorithm is taken */
1617                 max_working_cnt++;
1618         }
1619
1620         /* The dtap increment to find the failing edge is done here */
1621         for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1622                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1623                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1624                                    end-2: dtap=%u\n", __func__, __LINE__, d);
1625                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1626
1627                         if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1628                                                                       PASS_ONE_BIT,
1629                                                                       &bit_chk, 0)) {
1630                                 break;
1631                         }
1632         }
1633
1634         /* Go back to working dtap */
1635         if (d != 0)
1636                 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1637
1638         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1639                    ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1640                    v, p, d-1, work_end);
1641
1642         if (work_end < work_bgn) {
1643                 /* nil range */
1644                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1645                            failed\n", __func__, __LINE__);
1646                 return 0;
1647         }
1648
1649         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1650                    __func__, __LINE__, work_bgn, work_end);
1651
1652         /* *************************************************************** */
1653         /*
1654          * * We need to calculate the number of dtaps that equal a ptap
1655          * * To do that we'll back up a ptap and re-find the edge of the
1656          * * window using dtaps
1657          */
1658
1659         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1660                    for tracking\n", __func__, __LINE__);
1661
1662         /* Special case code for backing up a phase */
1663         if (p == 0) {
1664                 p = IO_DQS_EN_PHASE_MAX;
1665                 rw_mgr_decr_vfifo(grp, &v);
1666                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1667                            cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1668                            v, p);
1669         } else {
1670                 p = p - 1;
1671                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1672                            phase only: v=%u p=%u", __func__, __LINE__,
1673                            v, p);
1674         }
1675
1676         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1677
1678         /*
1679          * Increase dtap until we first see a passing read (in case the
1680          * window is smaller than a ptap),
1681          * and then a failing read to mark the edge of the window again
1682          */
1683
1684         /* Find a passing read */
1685         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1686                    __func__, __LINE__);
1687         found_passing_read = 0;
1688         found_failing_read = 0;
1689         initial_failing_dtap = d;
1690         for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1691                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1692                            read d=%u\n", __func__, __LINE__, d);
1693                 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1694
1695                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1696                                                              PASS_ONE_BIT,
1697                                                              &bit_chk, 0)) {
1698                         found_passing_read = 1;
1699                         break;
1700                 }
1701         }
1702
1703         if (found_passing_read) {
1704                 /* Find a failing read */
1705                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1706                            read\n", __func__, __LINE__);
1707                 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1708                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1709                                    testing read d=%u\n", __func__, __LINE__, d);
1710                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1711
1712                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1713                                 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1714                                 found_failing_read = 1;
1715                                 break;
1716                         }
1717                 }
1718         } else {
1719                 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1720                            calculate dtaps", __func__, __LINE__);
1721                 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1722         }
1723
1724         /*
1725          * The dynamically calculated dtaps_per_ptap is only valid if we
1726          * found a passing/failing read. If we didn't, it means d hit the max
1727          * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1728          * statically calculated value.
1729          */
1730         if (found_passing_read && found_failing_read)
1731                 dtaps_per_ptap = d - initial_failing_dtap;
1732
1733         writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1734         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1735                    - %u = %u",  __func__, __LINE__, d,
1736                    initial_failing_dtap, dtaps_per_ptap);
1737
1738         /* ******************************************** */
1739         /* * step 6:  Find the centre of the window   * */
1740         if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1741                                    &work_mid, &work_end) == 0)
1742                 return 0;
1743
1744         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
1745                    vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
1746                    v, p-1, d);
1747         return 1;
1748 }
1749
1750 /*
1751  * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1752  * dq_in_delay values
1753  */
1754 static uint32_t
1755 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1756 (uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
1757 {
1758         uint32_t found;
1759         uint32_t i;
1760         uint32_t p;
1761         uint32_t d;
1762         uint32_t r;
1763
1764         const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
1765                 (RW_MGR_MEM_DQ_PER_READ_DQS-1);
1766                 /* we start at zero, so have one less dq to devide among */
1767
1768         debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
1769               test_bgn);
1770
1771         /* try different dq_in_delays since the dq path is shorter than dqs */
1772
1773         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1774              r += NUM_RANKS_PER_SHADOW_REG) {
1775                 for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++, d += delay_step) {
1776                         debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
1777                                    vfifo_find_dqs_", __func__, __LINE__);
1778                         debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
1779                                write_group, read_group);
1780                         debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
1781                         scc_mgr_set_dq_in_delay(p, d);
1782                         scc_mgr_load_dq(p);
1783                 }
1784                 writel(0, &sdr_scc_mgr->update);
1785         }
1786
1787         found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
1788
1789         debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
1790                    en_phase_sweep_dq", __func__, __LINE__);
1791         debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
1792                    chain to zero\n", write_group, read_group, found);
1793
1794         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1795              r += NUM_RANKS_PER_SHADOW_REG) {
1796                 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1797                         i++, p++) {
1798                         scc_mgr_set_dq_in_delay(p, 0);
1799                         scc_mgr_load_dq(p);
1800                 }
1801                 writel(0, &sdr_scc_mgr->update);
1802         }
1803
1804         return found;
1805 }
1806
1807 /* per-bit deskew DQ and center */
1808 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1809         uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1810         uint32_t use_read_test, uint32_t update_fom)
1811 {
1812         uint32_t i, p, d, min_index;
1813         /*
1814          * Store these as signed since there are comparisons with
1815          * signed numbers.
1816          */
1817         uint32_t bit_chk;
1818         uint32_t sticky_bit_chk;
1819         int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1820         int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1821         int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1822         int32_t mid;
1823         int32_t orig_mid_min, mid_min;
1824         int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1825                 final_dqs_en;
1826         int32_t dq_margin, dqs_margin;
1827         uint32_t stop;
1828         uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1829         uint32_t addr;
1830
1831         debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1832
1833         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1834         start_dqs = readl(addr + (read_group << 2));
1835         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1836                 start_dqs_en = readl(addr + ((read_group << 2)
1837                                      - IO_DQS_EN_DELAY_OFFSET));
1838
1839         /* set the left and right edge of each bit to an illegal value */
1840         /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1841         sticky_bit_chk = 0;
1842         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1843                 left_edge[i]  = IO_IO_IN_DELAY_MAX + 1;
1844                 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1845         }
1846
1847         /* Search for the left edge of the window for each bit */
1848         for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1849                 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1850
1851                 writel(0, &sdr_scc_mgr->update);
1852
1853                 /*
1854                  * Stop searching when the read test doesn't pass AND when
1855                  * we've seen a passing read on every bit.
1856                  */
1857                 if (use_read_test) {
1858                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1859                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1860                                 &bit_chk, 0, 0);
1861                 } else {
1862                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1863                                                         0, PASS_ONE_BIT,
1864                                                         &bit_chk, 0);
1865                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1866                                 (read_group - (write_group *
1867                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1868                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1869                         stop = (bit_chk == 0);
1870                 }
1871                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1872                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1873                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1874                            && %u", __func__, __LINE__, d,
1875                            sticky_bit_chk,
1876                         param->read_correct_mask, stop);
1877
1878                 if (stop == 1) {
1879                         break;
1880                 } else {
1881                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1882                                 if (bit_chk & 1) {
1883                                         /* Remember a passing test as the
1884                                         left_edge */
1885                                         left_edge[i] = d;
1886                                 } else {
1887                                         /* If a left edge has not been seen yet,
1888                                         then a future passing test will mark
1889                                         this edge as the right edge */
1890                                         if (left_edge[i] ==
1891                                                 IO_IO_IN_DELAY_MAX + 1) {
1892                                                 right_edge[i] = -(d + 1);
1893                                         }
1894                                 }
1895                                 bit_chk = bit_chk >> 1;
1896                         }
1897                 }
1898         }
1899
1900         /* Reset DQ delay chains to 0 */
1901         scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1902         sticky_bit_chk = 0;
1903         for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1904                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1905                            %d right_edge[%u]: %d\n", __func__, __LINE__,
1906                            i, left_edge[i], i, right_edge[i]);
1907
1908                 /*
1909                  * Check for cases where we haven't found the left edge,
1910                  * which makes our assignment of the the right edge invalid.
1911                  * Reset it to the illegal value.
1912                  */
1913                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1914                         right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1915                         right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1916                         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1917                                    right_edge[%u]: %d\n", __func__, __LINE__,
1918                                    i, right_edge[i]);
1919                 }
1920
1921                 /*
1922                  * Reset sticky bit (except for bits where we have seen
1923                  * both the left and right edge).
1924                  */
1925                 sticky_bit_chk = sticky_bit_chk << 1;
1926                 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1927                     (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1928                         sticky_bit_chk = sticky_bit_chk | 1;
1929                 }
1930
1931                 if (i == 0)
1932                         break;
1933         }
1934
1935         /* Search for the right edge of the window for each bit */
1936         for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1937                 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1938                 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1939                         uint32_t delay = d + start_dqs_en;
1940                         if (delay > IO_DQS_EN_DELAY_MAX)
1941                                 delay = IO_DQS_EN_DELAY_MAX;
1942                         scc_mgr_set_dqs_en_delay(read_group, delay);
1943                 }
1944                 scc_mgr_load_dqs(read_group);
1945
1946                 writel(0, &sdr_scc_mgr->update);
1947
1948                 /*
1949                  * Stop searching when the read test doesn't pass AND when
1950                  * we've seen a passing read on every bit.
1951                  */
1952                 if (use_read_test) {
1953                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1954                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1955                                 &bit_chk, 0, 0);
1956                 } else {
1957                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1958                                                         0, PASS_ONE_BIT,
1959                                                         &bit_chk, 0);
1960                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1961                                 (read_group - (write_group *
1962                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1963                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1964                         stop = (bit_chk == 0);
1965                 }
1966                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1967                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1968
1969                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1970                            %u && %u", __func__, __LINE__, d,
1971                            sticky_bit_chk, param->read_correct_mask, stop);
1972
1973                 if (stop == 1) {
1974                         break;
1975                 } else {
1976                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1977                                 if (bit_chk & 1) {
1978                                         /* Remember a passing test as
1979                                         the right_edge */
1980                                         right_edge[i] = d;
1981                                 } else {
1982                                         if (d != 0) {
1983                                                 /* If a right edge has not been
1984                                                 seen yet, then a future passing
1985                                                 test will mark this edge as the
1986                                                 left edge */
1987                                                 if (right_edge[i] ==
1988                                                 IO_IO_IN_DELAY_MAX + 1) {
1989                                                         left_edge[i] = -(d + 1);
1990                                                 }
1991                                         } else {
1992                                                 /* d = 0 failed, but it passed
1993                                                 when testing the left edge,
1994                                                 so it must be marginal,
1995                                                 set it to -1 */
1996                                                 if (right_edge[i] ==
1997                                                         IO_IO_IN_DELAY_MAX + 1 &&
1998                                                         left_edge[i] !=
1999                                                         IO_IO_IN_DELAY_MAX
2000                                                         + 1) {
2001                                                         right_edge[i] = -1;
2002                                                 }
2003                                                 /* If a right edge has not been
2004                                                 seen yet, then a future passing
2005                                                 test will mark this edge as the
2006                                                 left edge */
2007                                                 else if (right_edge[i] ==
2008                                                         IO_IO_IN_DELAY_MAX +
2009                                                         1) {
2010                                                         left_edge[i] = -(d + 1);
2011                                                 }
2012                                         }
2013                                 }
2014
2015                                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
2016                                            d=%u]: ", __func__, __LINE__, d);
2017                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
2018                                            (int)(bit_chk & 1), i, left_edge[i]);
2019                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2020                                            right_edge[i]);
2021                                 bit_chk = bit_chk >> 1;
2022                         }
2023                 }
2024         }
2025
2026         /* Check that all bits have a window */
2027         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2028                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2029                            %d right_edge[%u]: %d", __func__, __LINE__,
2030                            i, left_edge[i], i, right_edge[i]);
2031                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2032                         == IO_IO_IN_DELAY_MAX + 1)) {
2033                         /*
2034                          * Restore delay chain settings before letting the loop
2035                          * in rw_mgr_mem_calibrate_vfifo to retry different
2036                          * dqs/ck relationships.
2037                          */
2038                         scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2039                         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2040                                 scc_mgr_set_dqs_en_delay(read_group,
2041                                                          start_dqs_en);
2042                         }
2043                         scc_mgr_load_dqs(read_group);
2044                         writel(0, &sdr_scc_mgr->update);
2045
2046                         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2047                                    find edge [%u]: %d %d", __func__, __LINE__,
2048                                    i, left_edge[i], right_edge[i]);
2049                         if (use_read_test) {
2050                                 set_failing_group_stage(read_group *
2051                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2052                                         CAL_STAGE_VFIFO,
2053                                         CAL_SUBSTAGE_VFIFO_CENTER);
2054                         } else {
2055                                 set_failing_group_stage(read_group *
2056                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2057                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2058                                         CAL_SUBSTAGE_VFIFO_CENTER);
2059                         }
2060                         return 0;
2061                 }
2062         }
2063
2064         /* Find middle of window for each DQ bit */
2065         mid_min = left_edge[0] - right_edge[0];
2066         min_index = 0;
2067         for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2068                 mid = left_edge[i] - right_edge[i];
2069                 if (mid < mid_min) {
2070                         mid_min = mid;
2071                         min_index = i;
2072                 }
2073         }
2074
2075         /*
2076          * -mid_min/2 represents the amount that we need to move DQS.
2077          * If mid_min is odd and positive we'll need to add one to
2078          * make sure the rounding in further calculations is correct
2079          * (always bias to the right), so just add 1 for all positive values.
2080          */
2081         if (mid_min > 0)
2082                 mid_min++;
2083
2084         mid_min = mid_min / 2;
2085
2086         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2087                    __func__, __LINE__, mid_min, min_index);
2088
2089         /* Determine the amount we can change DQS (which is -mid_min) */
2090         orig_mid_min = mid_min;
2091         new_dqs = start_dqs - mid_min;
2092         if (new_dqs > IO_DQS_IN_DELAY_MAX)
2093                 new_dqs = IO_DQS_IN_DELAY_MAX;
2094         else if (new_dqs < 0)
2095                 new_dqs = 0;
2096
2097         mid_min = start_dqs - new_dqs;
2098         debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2099                    mid_min, new_dqs);
2100
2101         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2102                 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2103                         mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2104                 else if (start_dqs_en - mid_min < 0)
2105                         mid_min += start_dqs_en - mid_min;
2106         }
2107         new_dqs = start_dqs - mid_min;
2108
2109         debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2110                    new_dqs=%d mid_min=%d\n", start_dqs,
2111                    IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2112                    new_dqs, mid_min);
2113
2114         /* Initialize data for export structures */
2115         dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2116         dq_margin  = IO_IO_IN_DELAY_MAX + 1;
2117
2118         /* add delay to bring centre of all DQ windows to the same "level" */
2119         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2120                 /* Use values before divide by 2 to reduce round off error */
2121                 shift_dq = (left_edge[i] - right_edge[i] -
2122                         (left_edge[min_index] - right_edge[min_index]))/2  +
2123                         (orig_mid_min - mid_min);
2124
2125                 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2126                            shift_dq[%u]=%d\n", i, shift_dq);
2127
2128                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2129                 temp_dq_in_delay1 = readl(addr + (p << 2));
2130                 temp_dq_in_delay2 = readl(addr + (i << 2));
2131
2132                 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2133                         (int32_t)IO_IO_IN_DELAY_MAX) {
2134                         shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2135                 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2136                         shift_dq = -(int32_t)temp_dq_in_delay1;
2137                 }
2138                 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2139                            shift_dq[%u]=%d\n", i, shift_dq);
2140                 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2141                 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2142                 scc_mgr_load_dq(p);
2143
2144                 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2145                            left_edge[i] - shift_dq + (-mid_min),
2146                            right_edge[i] + shift_dq - (-mid_min));
2147                 /* To determine values for export structures */
2148                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2149                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2150
2151                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2152                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2153         }
2154
2155         final_dqs = new_dqs;
2156         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2157                 final_dqs_en = start_dqs_en - mid_min;
2158
2159         /* Move DQS-en */
2160         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2161                 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2162                 scc_mgr_load_dqs(read_group);
2163         }
2164
2165         /* Move DQS */
2166         scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2167         scc_mgr_load_dqs(read_group);
2168         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2169                    dqs_margin=%d", __func__, __LINE__,
2170                    dq_margin, dqs_margin);
2171
2172         /*
2173          * Do not remove this line as it makes sure all of our decisions
2174          * have been applied. Apply the update bit.
2175          */
2176         writel(0, &sdr_scc_mgr->update);
2177
2178         return (dq_margin >= 0) && (dqs_margin >= 0);
2179 }
2180
2181 /*
2182  * calibrate the read valid prediction FIFO.
2183  *
2184  *  - read valid prediction will consist of finding a good DQS enable phase,
2185  * DQS enable delay, DQS input phase, and DQS input delay.
2186  *  - we also do a per-bit deskew on the DQ lines.
2187  */
2188 static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
2189                                            uint32_t test_bgn)
2190 {
2191         uint32_t p, d, rank_bgn, sr;
2192         uint32_t dtaps_per_ptap;
2193         uint32_t bit_chk;
2194         uint32_t grp_calibrated;
2195         uint32_t write_group, write_test_bgn;
2196         uint32_t failed_substage;
2197
2198         debug("%s:%d: %u %u\n", __func__, __LINE__, read_group, test_bgn);
2199
2200         /* update info for sims */
2201         reg_file_set_stage(CAL_STAGE_VFIFO);
2202
2203         write_group = read_group;
2204         write_test_bgn = test_bgn;
2205
2206         /* USER Determine number of delay taps for each phase tap */
2207         dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2208                                       IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2209
2210         /* update info for sims */
2211         reg_file_set_group(read_group);
2212
2213         grp_calibrated = 0;
2214
2215         reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2216         failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2217
2218         for (d = 0; d <= dtaps_per_ptap && grp_calibrated == 0; d += 2) {
2219                 /*
2220                  * In RLDRAMX we may be messing the delay of pins in
2221                  * the same write group but outside of the current read
2222                  * the group, but that's ok because we haven't
2223                  * calibrated output side yet.
2224                  */
2225                 if (d > 0) {
2226                         scc_mgr_apply_group_all_out_delay_add_all_ranks(
2227                                                                 write_group, d);
2228                 }
2229
2230                 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
2231                         p++) {
2232                         /* set a particular dqdqs phase */
2233                         scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
2234
2235                         debug_cond(DLEVEL == 1, "%s:%d calibrate_vfifo: g=%u \
2236                                    p=%u d=%u\n", __func__, __LINE__,
2237                                    read_group, p, d);
2238
2239                         /*
2240                          * Load up the patterns used by read calibration
2241                          * using current DQDQS phase.
2242                          */
2243                         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2244                         if (!(gbl->phy_debug_mode_flags &
2245                                 PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
2246                                 if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
2247                                     (read_group, 1, &bit_chk)) {
2248                                         debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:",
2249                                                    __func__, __LINE__);
2250                                         debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
2251                                                    read_group, p, d);
2252                                         break;
2253                                 }
2254                         }
2255
2256 /* case:56390 */
2257                         grp_calibrated = 1;
2258                 if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
2259                     (write_group, read_group, test_bgn)) {
2260                                 /*
2261                                  * USER Read per-bit deskew can be done on a
2262                                  * per shadow register basis.
2263                                  */
2264                                 for (rank_bgn = 0, sr = 0;
2265                                         rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2266                                         rank_bgn += NUM_RANKS_PER_SHADOW_REG,
2267                                         ++sr) {
2268                                         /*
2269                                          * Determine if this set of ranks
2270                                          * should be skipped entirely.
2271                                          */
2272                                         if (!param->skip_shadow_regs[sr]) {
2273                                                 /*
2274                                                  * If doing read after write
2275                                                  * calibration, do not update
2276                                                  * FOM, now - do it then.
2277                                                  */
2278                                         if (!rw_mgr_mem_calibrate_vfifo_center
2279                                                 (rank_bgn, write_group,
2280                                                 read_group, test_bgn, 1, 0)) {
2281                                                         grp_calibrated = 0;
2282                                                         failed_substage =
2283                                                 CAL_SUBSTAGE_VFIFO_CENTER;
2284                                                 }
2285                                         }
2286                                 }
2287                         } else {
2288                                 grp_calibrated = 0;
2289                                 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2290                         }
2291                 }
2292         }
2293
2294         if (grp_calibrated == 0) {
2295                 set_failing_group_stage(write_group, CAL_STAGE_VFIFO,
2296                                         failed_substage);
2297                 return 0;
2298         }
2299
2300         /*
2301          * Reset the delay chains back to zero if they have moved > 1
2302          * (check for > 1 because loop will increase d even when pass in
2303          * first case).
2304          */
2305         if (d > 2)
2306                 scc_mgr_zero_group(write_group, 1);
2307
2308         return 1;
2309 }
2310
2311 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2312 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2313                                                uint32_t test_bgn)
2314 {
2315         uint32_t rank_bgn, sr;
2316         uint32_t grp_calibrated;
2317         uint32_t write_group;
2318
2319         debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2320
2321         /* update info for sims */
2322
2323         reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2324         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2325
2326         write_group = read_group;
2327
2328         /* update info for sims */
2329         reg_file_set_group(read_group);
2330
2331         grp_calibrated = 1;
2332         /* Read per-bit deskew can be done on a per shadow register basis */
2333         for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2334                 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2335                 /* Determine if this set of ranks should be skipped entirely */
2336                 if (!param->skip_shadow_regs[sr]) {
2337                 /* This is the last calibration round, update FOM here */
2338                         if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2339                                                                 write_group,
2340                                                                 read_group,
2341                                                                 test_bgn, 0,
2342                                                                 1)) {
2343                                 grp_calibrated = 0;
2344                         }
2345                 }
2346         }
2347
2348
2349         if (grp_calibrated == 0) {
2350                 set_failing_group_stage(write_group,
2351                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2352                                         CAL_SUBSTAGE_VFIFO_CENTER);
2353                 return 0;
2354         }
2355
2356         return 1;
2357 }
2358
2359 /* Calibrate LFIFO to find smallest read latency */
2360 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2361 {
2362         uint32_t found_one;
2363         uint32_t bit_chk;
2364
2365         debug("%s:%d\n", __func__, __LINE__);
2366
2367         /* update info for sims */
2368         reg_file_set_stage(CAL_STAGE_LFIFO);
2369         reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2370
2371         /* Load up the patterns used by read calibration for all ranks */
2372         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2373         found_one = 0;
2374
2375         do {
2376                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2377                 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2378                            __func__, __LINE__, gbl->curr_read_lat);
2379
2380                 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2381                                                               NUM_READ_TESTS,
2382                                                               PASS_ALL_BITS,
2383                                                               &bit_chk, 1)) {
2384                         break;
2385                 }
2386
2387                 found_one = 1;
2388                 /* reduce read latency and see if things are working */
2389                 /* correctly */
2390                 gbl->curr_read_lat--;
2391         } while (gbl->curr_read_lat > 0);
2392
2393         /* reset the fifos to get pointers to known state */
2394
2395         writel(0, &phy_mgr_cmd->fifo_reset);
2396
2397         if (found_one) {
2398                 /* add a fudge factor to the read latency that was determined */
2399                 gbl->curr_read_lat += 2;
2400                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2401                 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2402                            read_lat=%u\n", __func__, __LINE__,
2403                            gbl->curr_read_lat);
2404                 return 1;
2405         } else {
2406                 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2407                                         CAL_SUBSTAGE_READ_LATENCY);
2408
2409                 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2410                            read_lat=%u\n", __func__, __LINE__,
2411                            gbl->curr_read_lat);
2412                 return 0;
2413         }
2414 }
2415
2416 /*
2417  * issue write test command.
2418  * two variants are provided. one that just tests a write pattern and
2419  * another that tests datamask functionality.
2420  */
2421 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2422                                                   uint32_t test_dm)
2423 {
2424         uint32_t mcc_instruction;
2425         uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2426                 ENABLE_SUPER_QUICK_CALIBRATION);
2427         uint32_t rw_wl_nop_cycles;
2428         uint32_t addr;
2429
2430         /*
2431          * Set counter and jump addresses for the right
2432          * number of NOP cycles.
2433          * The number of supported NOP cycles can range from -1 to infinity
2434          * Three different cases are handled:
2435          *
2436          * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2437          *    mechanism will be used to insert the right number of NOPs
2438          *
2439          * 2. For a number of NOP cycles equals to 0, the micro-instruction
2440          *    issuing the write command will jump straight to the
2441          *    micro-instruction that turns on DQS (for DDRx), or outputs write
2442          *    data (for RLD), skipping
2443          *    the NOP micro-instruction all together
2444          *
2445          * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2446          *    turned on in the same micro-instruction that issues the write
2447          *    command. Then we need
2448          *    to directly jump to the micro-instruction that sends out the data
2449          *
2450          * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2451          *       (2 and 3). One jump-counter (0) is used to perform multiple
2452          *       write-read operations.
2453          *       one counter left to issue this command in "multiple-group" mode
2454          */
2455
2456         rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2457
2458         if (rw_wl_nop_cycles == -1) {
2459                 /*
2460                  * CNTR 2 - We want to execute the special write operation that
2461                  * turns on DQS right away and then skip directly to the
2462                  * instruction that sends out the data. We set the counter to a
2463                  * large number so that the jump is always taken.
2464                  */
2465                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2466
2467                 /* CNTR 3 - Not used */
2468                 if (test_dm) {
2469                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2470                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2471                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2472                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2473                                &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2474                 } else {
2475                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2476                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2477                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2478                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2479                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2480                 }
2481         } else if (rw_wl_nop_cycles == 0) {
2482                 /*
2483                  * CNTR 2 - We want to skip the NOP operation and go straight
2484                  * to the DQS enable instruction. We set the counter to a large
2485                  * number so that the jump is always taken.
2486                  */
2487                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2488
2489                 /* CNTR 3 - Not used */
2490                 if (test_dm) {
2491                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2492                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2493                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2494                 } else {
2495                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2496                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2497                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2498                 }
2499         } else {
2500                 /*
2501                  * CNTR 2 - In this case we want to execute the next instruction
2502                  * and NOT take the jump. So we set the counter to 0. The jump
2503                  * address doesn't count.
2504                  */
2505                 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2506                 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2507
2508                 /*
2509                  * CNTR 3 - Set the nop counter to the number of cycles we
2510                  * need to loop for, minus 1.
2511                  */
2512                 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2513                 if (test_dm) {
2514                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2515                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2516                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2517                 } else {
2518                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2519                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2520                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2521                 }
2522         }
2523
2524         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2525                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
2526
2527         if (quick_write_mode)
2528                 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2529         else
2530                 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2531
2532         writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2533
2534         /*
2535          * CNTR 1 - This is used to ensure enough time elapses
2536          * for read data to come back.
2537          */
2538         writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2539
2540         if (test_dm) {
2541                 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2542                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2543         } else {
2544                 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2545                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2546         }
2547
2548         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2549         writel(mcc_instruction, addr + (group << 2));
2550 }
2551
2552 /* Test writes, can check for a single bit pass or multiple bit pass */
2553 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2554         uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2555         uint32_t *bit_chk, uint32_t all_ranks)
2556 {
2557         uint32_t r;
2558         uint32_t correct_mask_vg;
2559         uint32_t tmp_bit_chk;
2560         uint32_t vg;
2561         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2562                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2563         uint32_t addr_rw_mgr;
2564         uint32_t base_rw_mgr;
2565
2566         *bit_chk = param->write_correct_mask;
2567         correct_mask_vg = param->write_correct_mask_vg;
2568
2569         for (r = rank_bgn; r < rank_end; r++) {
2570                 if (param->skip_ranks[r]) {
2571                         /* request to skip the rank */
2572                         continue;
2573                 }
2574
2575                 /* set rank */
2576                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2577
2578                 tmp_bit_chk = 0;
2579                 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2580                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2581                         /* reset the fifos to get pointers to known state */
2582                         writel(0, &phy_mgr_cmd->fifo_reset);
2583
2584                         tmp_bit_chk = tmp_bit_chk <<
2585                                 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2586                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2587                         rw_mgr_mem_calibrate_write_test_issue(write_group *
2588                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2589                                 use_dm);
2590
2591                         base_rw_mgr = readl(addr_rw_mgr);
2592                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2593                         if (vg == 0)
2594                                 break;
2595                 }
2596                 *bit_chk &= tmp_bit_chk;
2597         }
2598
2599         if (all_correct) {
2600                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2601                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2602                            %u => %lu", write_group, use_dm,
2603                            *bit_chk, param->write_correct_mask,
2604                            (long unsigned int)(*bit_chk ==
2605                            param->write_correct_mask));
2606                 return *bit_chk == param->write_correct_mask;
2607         } else {
2608                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2609                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2610                        write_group, use_dm, *bit_chk);
2611                 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2612                         (long unsigned int)(*bit_chk != 0));
2613                 return *bit_chk != 0x00;
2614         }
2615 }
2616
2617 /*
2618  * center all windows. do per-bit-deskew to possibly increase size of
2619  * certain windows.
2620  */
2621 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2622         uint32_t write_group, uint32_t test_bgn)
2623 {
2624         uint32_t i, p, min_index;
2625         int32_t d;
2626         /*
2627          * Store these as signed since there are comparisons with
2628          * signed numbers.
2629          */
2630         uint32_t bit_chk;
2631         uint32_t sticky_bit_chk;
2632         int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2633         int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2634         int32_t mid;
2635         int32_t mid_min, orig_mid_min;
2636         int32_t new_dqs, start_dqs, shift_dq;
2637         int32_t dq_margin, dqs_margin, dm_margin;
2638         uint32_t stop;
2639         uint32_t temp_dq_out1_delay;
2640         uint32_t addr;
2641
2642         debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2643
2644         dm_margin = 0;
2645
2646         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2647         start_dqs = readl(addr +
2648                           (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2649
2650         /* per-bit deskew */
2651
2652         /*
2653          * set the left and right edge of each bit to an illegal value
2654          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2655          */
2656         sticky_bit_chk = 0;
2657         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2658                 left_edge[i]  = IO_IO_OUT1_DELAY_MAX + 1;
2659                 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2660         }
2661
2662         /* Search for the left edge of the window for each bit */
2663         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2664                 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2665
2666                 writel(0, &sdr_scc_mgr->update);
2667
2668                 /*
2669                  * Stop searching when the read test doesn't pass AND when
2670                  * we've seen a passing read on every bit.
2671                  */
2672                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2673                         0, PASS_ONE_BIT, &bit_chk, 0);
2674                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2675                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2676                 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2677                            == %u && %u [bit_chk= %u ]\n",
2678                         d, sticky_bit_chk, param->write_correct_mask,
2679                         stop, bit_chk);
2680
2681                 if (stop == 1) {
2682                         break;
2683                 } else {
2684                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2685                                 if (bit_chk & 1) {
2686                                         /*
2687                                          * Remember a passing test as the
2688                                          * left_edge.
2689                                          */
2690                                         left_edge[i] = d;
2691                                 } else {
2692                                         /*
2693                                          * If a left edge has not been seen
2694                                          * yet, then a future passing test will
2695                                          * mark this edge as the right edge.
2696                                          */
2697                                         if (left_edge[i] ==
2698                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2699                                                 right_edge[i] = -(d + 1);
2700                                         }
2701                                 }
2702                                 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2703                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2704                                            (int)(bit_chk & 1), i, left_edge[i]);
2705                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2706                                        right_edge[i]);
2707                                 bit_chk = bit_chk >> 1;
2708                         }
2709                 }
2710         }
2711
2712         /* Reset DQ delay chains to 0 */
2713         scc_mgr_apply_group_dq_out1_delay(0);
2714         sticky_bit_chk = 0;
2715         for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2716                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2717                            %d right_edge[%u]: %d\n", __func__, __LINE__,
2718                            i, left_edge[i], i, right_edge[i]);
2719
2720                 /*
2721                  * Check for cases where we haven't found the left edge,
2722                  * which makes our assignment of the the right edge invalid.
2723                  * Reset it to the illegal value.
2724                  */
2725                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2726                     (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2727                         right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2728                         debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2729                                    right_edge[%u]: %d\n", __func__, __LINE__,
2730                                    i, right_edge[i]);
2731                 }
2732
2733                 /*
2734                  * Reset sticky bit (except for bits where we have
2735                  * seen the left edge).
2736                  */
2737                 sticky_bit_chk = sticky_bit_chk << 1;
2738                 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2739                         sticky_bit_chk = sticky_bit_chk | 1;
2740
2741                 if (i == 0)
2742                         break;
2743         }
2744
2745         /* Search for the right edge of the window for each bit */
2746         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2747                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2748                                                         d + start_dqs);
2749
2750                 writel(0, &sdr_scc_mgr->update);
2751
2752                 /*
2753                  * Stop searching when the read test doesn't pass AND when
2754                  * we've seen a passing read on every bit.
2755                  */
2756                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2757                         0, PASS_ONE_BIT, &bit_chk, 0);
2758
2759                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2760                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2761
2762                 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2763                            %u && %u\n", d, sticky_bit_chk,
2764                            param->write_correct_mask, stop);
2765
2766                 if (stop == 1) {
2767                         if (d == 0) {
2768                                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2769                                         i++) {
2770                                         /* d = 0 failed, but it passed when
2771                                         testing the left edge, so it must be
2772                                         marginal, set it to -1 */
2773                                         if (right_edge[i] ==
2774                                                 IO_IO_OUT1_DELAY_MAX + 1 &&
2775                                                 left_edge[i] !=
2776                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2777                                                 right_edge[i] = -1;
2778                                         }
2779                                 }
2780                         }
2781                         break;
2782                 } else {
2783                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2784                                 if (bit_chk & 1) {
2785                                         /*
2786                                          * Remember a passing test as
2787                                          * the right_edge.
2788                                          */
2789                                         right_edge[i] = d;
2790                                 } else {
2791                                         if (d != 0) {
2792                                                 /*
2793                                                  * If a right edge has not
2794                                                  * been seen yet, then a future
2795                                                  * passing test will mark this
2796                                                  * edge as the left edge.
2797                                                  */
2798                                                 if (right_edge[i] ==
2799                                                     IO_IO_OUT1_DELAY_MAX + 1)
2800                                                         left_edge[i] = -(d + 1);
2801                                         } else {
2802                                                 /*
2803                                                  * d = 0 failed, but it passed
2804                                                  * when testing the left edge,
2805                                                  * so it must be marginal, set
2806                                                  * it to -1.
2807                                                  */
2808                                                 if (right_edge[i] ==
2809                                                     IO_IO_OUT1_DELAY_MAX + 1 &&
2810                                                     left_edge[i] !=
2811                                                     IO_IO_OUT1_DELAY_MAX + 1)
2812                                                         right_edge[i] = -1;
2813                                                 /*
2814                                                  * If a right edge has not been
2815                                                  * seen yet, then a future
2816                                                  * passing test will mark this
2817                                                  * edge as the left edge.
2818                                                  */
2819                                                 else if (right_edge[i] ==
2820                                                         IO_IO_OUT1_DELAY_MAX +
2821                                                         1)
2822                                                         left_edge[i] = -(d + 1);
2823                                         }
2824                                 }
2825                                 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2826                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2827                                            (int)(bit_chk & 1), i, left_edge[i]);
2828                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2829                                            right_edge[i]);
2830                                 bit_chk = bit_chk >> 1;
2831                         }
2832                 }
2833         }
2834
2835         /* Check that all bits have a window */
2836         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2837                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2838                            %d right_edge[%u]: %d", __func__, __LINE__,
2839                            i, left_edge[i], i, right_edge[i]);
2840                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2841                     (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2842                         set_failing_group_stage(test_bgn + i,
2843                                                 CAL_STAGE_WRITES,
2844                                                 CAL_SUBSTAGE_WRITES_CENTER);
2845                         return 0;
2846                 }
2847         }
2848
2849         /* Find middle of window for each DQ bit */
2850         mid_min = left_edge[0] - right_edge[0];
2851         min_index = 0;
2852         for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2853                 mid = left_edge[i] - right_edge[i];
2854                 if (mid < mid_min) {
2855                         mid_min = mid;
2856                         min_index = i;
2857                 }
2858         }
2859
2860         /*
2861          * -mid_min/2 represents the amount that we need to move DQS.
2862          * If mid_min is odd and positive we'll need to add one to
2863          * make sure the rounding in further calculations is correct
2864          * (always bias to the right), so just add 1 for all positive values.
2865          */
2866         if (mid_min > 0)
2867                 mid_min++;
2868         mid_min = mid_min / 2;
2869         debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2870                    __LINE__, mid_min);
2871
2872         /* Determine the amount we can change DQS (which is -mid_min) */
2873         orig_mid_min = mid_min;
2874         new_dqs = start_dqs;
2875         mid_min = 0;
2876         debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2877                    mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2878         /* Initialize data for export structures */
2879         dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2880         dq_margin  = IO_IO_OUT1_DELAY_MAX + 1;
2881
2882         /* add delay to bring centre of all DQ windows to the same "level" */
2883         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2884                 /* Use values before divide by 2 to reduce round off error */
2885                 shift_dq = (left_edge[i] - right_edge[i] -
2886                         (left_edge[min_index] - right_edge[min_index]))/2  +
2887                 (orig_mid_min - mid_min);
2888
2889                 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2890                            [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2891
2892                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2893                 temp_dq_out1_delay = readl(addr + (i << 2));
2894                 if (shift_dq + (int32_t)temp_dq_out1_delay >
2895                         (int32_t)IO_IO_OUT1_DELAY_MAX) {
2896                         shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2897                 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2898                         shift_dq = -(int32_t)temp_dq_out1_delay;
2899                 }
2900                 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2901                            i, shift_dq);
2902                 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2903                 scc_mgr_load_dq(i);
2904
2905                 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2906                            left_edge[i] - shift_dq + (-mid_min),
2907                            right_edge[i] + shift_dq - (-mid_min));
2908                 /* To determine values for export structures */
2909                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2910                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2911
2912                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2913                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2914         }
2915
2916         /* Move DQS */
2917         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2918         writel(0, &sdr_scc_mgr->update);
2919
2920         /* Centre DM */
2921         debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2922
2923         /*
2924          * set the left and right edge of each bit to an illegal value,
2925          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2926          */
2927         left_edge[0]  = IO_IO_OUT1_DELAY_MAX + 1;
2928         right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2929         int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2930         int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2931         int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2932         int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2933         int32_t win_best = 0;
2934
2935         /* Search for the/part of the window with DM shift */
2936         for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
2937                 scc_mgr_apply_group_dm_out1_delay(d);
2938                 writel(0, &sdr_scc_mgr->update);
2939
2940                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2941                                                     PASS_ALL_BITS, &bit_chk,
2942                                                     0)) {
2943                         /* USE Set current end of the window */
2944                         end_curr = -d;
2945                         /*
2946                          * If a starting edge of our window has not been seen
2947                          * this is our current start of the DM window.
2948                          */
2949                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
2950                                 bgn_curr = -d;
2951
2952                         /*
2953                          * If current window is bigger than best seen.
2954                          * Set best seen to be current window.
2955                          */
2956                         if ((end_curr-bgn_curr+1) > win_best) {
2957                                 win_best = end_curr-bgn_curr+1;
2958                                 bgn_best = bgn_curr;
2959                                 end_best = end_curr;
2960                         }
2961                 } else {
2962                         /* We just saw a failing test. Reset temp edge */
2963                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2964                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2965                         }
2966                 }
2967
2968
2969         /* Reset DM delay chains to 0 */
2970         scc_mgr_apply_group_dm_out1_delay(0);
2971
2972         /*
2973          * Check to see if the current window nudges up aganist 0 delay.
2974          * If so we need to continue the search by shifting DQS otherwise DQS
2975          * search begins as a new search. */
2976         if (end_curr != 0) {
2977                 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2978                 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2979         }
2980
2981         /* Search for the/part of the window with DQS shifts */
2982         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
2983                 /*
2984                  * Note: This only shifts DQS, so are we limiting ourselve to
2985                  * width of DQ unnecessarily.
2986                  */
2987                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2988                                                         d + new_dqs);
2989
2990                 writel(0, &sdr_scc_mgr->update);
2991                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2992                                                     PASS_ALL_BITS, &bit_chk,
2993                                                     0)) {
2994                         /* USE Set current end of the window */
2995                         end_curr = d;
2996                         /*
2997                          * If a beginning edge of our window has not been seen
2998                          * this is our current begin of the DM window.
2999                          */
3000                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3001                                 bgn_curr = d;
3002
3003                         /*
3004                          * If current window is bigger than best seen. Set best
3005                          * seen to be current window.
3006                          */
3007                         if ((end_curr-bgn_curr+1) > win_best) {
3008                                 win_best = end_curr-bgn_curr+1;
3009                                 bgn_best = bgn_curr;
3010                                 end_best = end_curr;
3011                         }
3012                 } else {
3013                         /* We just saw a failing test. Reset temp edge */
3014                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3015                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3016
3017                         /* Early exit optimization: if ther remaining delay
3018                         chain space is less than already seen largest window
3019                         we can exit */
3020                         if ((win_best-1) >
3021                                 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3022                                         break;
3023                                 }
3024                         }
3025                 }
3026
3027         /* assign left and right edge for cal and reporting; */
3028         left_edge[0] = -1*bgn_best;
3029         right_edge[0] = end_best;
3030
3031         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3032                    __LINE__, left_edge[0], right_edge[0]);
3033
3034         /* Move DQS (back to orig) */
3035         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3036
3037         /* Move DM */
3038
3039         /* Find middle of window for the DM bit */
3040         mid = (left_edge[0] - right_edge[0]) / 2;
3041
3042         /* only move right, since we are not moving DQS/DQ */
3043         if (mid < 0)
3044                 mid = 0;
3045
3046         /* dm_marign should fail if we never find a window */
3047         if (win_best == 0)
3048                 dm_margin = -1;
3049         else
3050                 dm_margin = left_edge[0] - mid;
3051
3052         scc_mgr_apply_group_dm_out1_delay(mid);
3053         writel(0, &sdr_scc_mgr->update);
3054
3055         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3056                    dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3057                    right_edge[0], mid, dm_margin);
3058         /* Export values */
3059         gbl->fom_out += dq_margin + dqs_margin;
3060
3061         debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3062                    dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3063                    dq_margin, dqs_margin, dm_margin);
3064
3065         /*
3066          * Do not remove this line as it makes sure all of our
3067          * decisions have been applied.
3068          */
3069         writel(0, &sdr_scc_mgr->update);
3070         return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3071 }
3072
3073 /* calibrate the write operations */
3074 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3075         uint32_t test_bgn)
3076 {
3077         /* update info for sims */
3078         debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3079
3080         reg_file_set_stage(CAL_STAGE_WRITES);
3081         reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3082
3083         reg_file_set_group(g);
3084
3085         if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3086                 set_failing_group_stage(g, CAL_STAGE_WRITES,
3087                                         CAL_SUBSTAGE_WRITES_CENTER);
3088                 return 0;
3089         }
3090
3091         return 1;
3092 }
3093
3094 /* precharge all banks and activate row 0 in bank "000..." and bank "111..." */
3095 static void mem_precharge_and_activate(void)
3096 {
3097         uint32_t r;
3098
3099         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3100                 if (param->skip_ranks[r]) {
3101                         /* request to skip the rank */
3102                         continue;
3103                 }
3104
3105                 /* set rank */
3106                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3107
3108                 /* precharge all banks ... */
3109                 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3110                                              RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3111
3112                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3113                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3114                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3115
3116                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3117                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3118                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3119
3120                 /* activate rows */
3121                 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3122                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3123         }
3124 }
3125
3126 /**
3127  * mem_init_latency() - Configure memory RLAT and WLAT settings
3128  *
3129  * Configure memory RLAT and WLAT parameters.
3130  */
3131 static void mem_init_latency(void)
3132 {
3133         /*
3134          * For AV/CV, LFIFO is hardened and always runs at full rate
3135          * so max latency in AFI clocks, used here, is correspondingly
3136          * smaller.
3137          */
3138         const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3139         u32 rlat, wlat;
3140
3141         debug("%s:%d\n", __func__, __LINE__);
3142
3143         /*
3144          * Read in write latency.
3145          * WL for Hard PHY does not include additive latency.
3146          */
3147         wlat = readl(&data_mgr->t_wl_add);
3148         wlat += readl(&data_mgr->mem_t_add);
3149
3150         gbl->rw_wl_nop_cycles = wlat - 1;
3151
3152         /* Read in readl latency. */
3153         rlat = readl(&data_mgr->t_rl_add);
3154
3155         /* Set a pretty high read latency initially. */
3156         gbl->curr_read_lat = rlat + 16;
3157         if (gbl->curr_read_lat > max_latency)
3158                 gbl->curr_read_lat = max_latency;
3159
3160         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3161
3162         /* Advertise write latency. */
3163         writel(wlat, &phy_mgr_cfg->afi_wlat);
3164 }
3165
3166 /* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */
3167 static void mem_skip_calibrate(void)
3168 {
3169         uint32_t vfifo_offset;
3170         uint32_t i, j, r;
3171
3172         debug("%s:%d\n", __func__, __LINE__);
3173         /* Need to update every shadow register set used by the interface */
3174         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3175                 r += NUM_RANKS_PER_SHADOW_REG) {
3176                 /*
3177                  * Set output phase alignment settings appropriate for
3178                  * skip calibration.
3179                  */
3180                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3181                         scc_mgr_set_dqs_en_phase(i, 0);
3182 #if IO_DLL_CHAIN_LENGTH == 6
3183                         scc_mgr_set_dqdqs_output_phase(i, 6);
3184 #else
3185                         scc_mgr_set_dqdqs_output_phase(i, 7);
3186 #endif
3187                         /*
3188                          * Case:33398
3189                          *
3190                          * Write data arrives to the I/O two cycles before write
3191                          * latency is reached (720 deg).
3192                          *   -> due to bit-slip in a/c bus
3193                          *   -> to allow board skew where dqs is longer than ck
3194                          *      -> how often can this happen!?
3195                          *      -> can claim back some ptaps for high freq
3196                          *       support if we can relax this, but i digress...
3197                          *
3198                          * The write_clk leads mem_ck by 90 deg
3199                          * The minimum ptap of the OPA is 180 deg
3200                          * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3201                          * The write_clk is always delayed by 2 ptaps
3202                          *
3203                          * Hence, to make DQS aligned to CK, we need to delay
3204                          * DQS by:
3205                          *    (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3206                          *
3207                          * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3208                          * gives us the number of ptaps, which simplies to:
3209                          *
3210                          *    (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3211                          */
3212                         scc_mgr_set_dqdqs_output_phase(i, (1.25 *
3213                                 IO_DLL_CHAIN_LENGTH - 2));
3214                 }
3215                 writel(0xff, &sdr_scc_mgr->dqs_ena);
3216                 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3217
3218                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3219                         writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3220                                   SCC_MGR_GROUP_COUNTER_OFFSET);
3221                 }
3222                 writel(0xff, &sdr_scc_mgr->dq_ena);
3223                 writel(0xff, &sdr_scc_mgr->dm_ena);
3224                 writel(0, &sdr_scc_mgr->update);
3225         }
3226
3227         /* Compensate for simulation model behaviour */
3228         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3229                 scc_mgr_set_dqs_bus_in_delay(i, 10);
3230                 scc_mgr_load_dqs(i);
3231         }
3232         writel(0, &sdr_scc_mgr->update);
3233
3234         /*
3235          * ArriaV has hard FIFOs that can only be initialized by incrementing
3236          * in sequencer.
3237          */
3238         vfifo_offset = CALIB_VFIFO_OFFSET;
3239         for (j = 0; j < vfifo_offset; j++) {
3240                 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3241         }
3242         writel(0, &phy_mgr_cmd->fifo_reset);
3243
3244         /*
3245          * For ACV with hard lfifo, we get the skip-cal setting from
3246          * generation-time constant.
3247          */
3248         gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3249         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3250 }
3251
3252 /* Memory calibration entry point */
3253 static uint32_t mem_calibrate(void)
3254 {
3255         uint32_t i;
3256         uint32_t rank_bgn, sr;
3257         uint32_t write_group, write_test_bgn;
3258         uint32_t read_group, read_test_bgn;
3259         uint32_t run_groups, current_run;
3260         uint32_t failing_groups = 0;
3261         uint32_t group_failed = 0;
3262         uint32_t sr_failed = 0;
3263
3264         debug("%s:%d\n", __func__, __LINE__);
3265
3266         /* Initialize the data settings */
3267         gbl->error_substage = CAL_SUBSTAGE_NIL;
3268         gbl->error_stage = CAL_STAGE_NIL;
3269         gbl->error_group = 0xff;
3270         gbl->fom_in = 0;
3271         gbl->fom_out = 0;
3272
3273         /* Initialize WLAT and RLAT. */
3274         mem_init_latency();
3275
3276         /* Initialize bit slips. */
3277         mem_precharge_and_activate();
3278
3279         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3280                 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3281                           SCC_MGR_GROUP_COUNTER_OFFSET);
3282                 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3283                 if (i == 0)
3284                         scc_mgr_set_hhp_extras();
3285
3286                 scc_set_bypass_mode(i);
3287         }
3288
3289         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3290                 /*
3291                  * Set VFIFO and LFIFO to instant-on settings in skip
3292                  * calibration mode.
3293                  */
3294                 mem_skip_calibrate();
3295         } else {
3296                 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3297                         /*
3298                          * Zero all delay chain/phase settings for all
3299                          * groups and all shadow register sets.
3300                          */
3301                         scc_mgr_zero_all();
3302
3303                         run_groups = ~param->skip_groups;
3304
3305                         for (write_group = 0, write_test_bgn = 0; write_group
3306                                 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3307                                 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3308                                 /* Initialized the group failure */
3309                                 group_failed = 0;
3310
3311                                 current_run = run_groups & ((1 <<
3312                                         RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3313                                 run_groups = run_groups >>
3314                                         RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3315
3316                                 if (current_run == 0)
3317                                         continue;
3318
3319                                 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3320                                                     SCC_MGR_GROUP_COUNTER_OFFSET);
3321                                 scc_mgr_zero_group(write_group, 0);
3322
3323                                 for (read_group = write_group *
3324                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
3325                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3326                                         read_test_bgn = 0;
3327                                         read_group < (write_group + 1) *
3328                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
3329                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3330                                         group_failed == 0;
3331                                         read_group++, read_test_bgn +=
3332                                         RW_MGR_MEM_DQ_PER_READ_DQS) {
3333                                         /* Calibrate the VFIFO */
3334                                         if (!((STATIC_CALIB_STEPS) &
3335                                                 CALIB_SKIP_VFIFO)) {
3336                                                 if (!rw_mgr_mem_calibrate_vfifo
3337                                                         (read_group,
3338                                                         read_test_bgn)) {
3339                                                         group_failed = 1;
3340
3341                                                         if (!(gbl->
3342                                                         phy_debug_mode_flags &
3343                                                 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3344                                                                 return 0;
3345                                                         }
3346                                                 }
3347                                         }
3348                                 }
3349
3350                                 /* Calibrate the output side */
3351                                 if (group_failed == 0)  {
3352                                         for (rank_bgn = 0, sr = 0; rank_bgn
3353                                                 < RW_MGR_MEM_NUMBER_OF_RANKS;
3354                                                 rank_bgn +=
3355                                                 NUM_RANKS_PER_SHADOW_REG,
3356                                                 ++sr) {
3357                                                 sr_failed = 0;
3358                                                 if (!((STATIC_CALIB_STEPS) &
3359                                                 CALIB_SKIP_WRITES)) {
3360                                                         if ((STATIC_CALIB_STEPS)
3361                                                 & CALIB_SKIP_DELAY_SWEEPS) {
3362                                                 /* not needed in quick mode! */
3363                                                         } else {
3364                                                 /*
3365                                                  * Determine if this set of
3366                                                  * ranks should be skipped
3367                                                  * entirely.
3368                                                  */
3369                                         if (!param->skip_shadow_regs[sr]) {
3370                                                 if (!rw_mgr_mem_calibrate_writes
3371                                                 (rank_bgn, write_group,
3372                                                 write_test_bgn)) {
3373                                                         sr_failed = 1;
3374                                                         if (!(gbl->
3375                                                         phy_debug_mode_flags &
3376                                                 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3377                                                                 return 0;
3378                                                                         }
3379                                                                         }
3380                                                                 }
3381                                                         }
3382                                                 }
3383                                                 if (sr_failed != 0)
3384                                                         group_failed = 1;
3385                                         }
3386                                 }
3387
3388                                 if (group_failed == 0) {
3389                                         for (read_group = write_group *
3390                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
3391                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3392                                         read_test_bgn = 0;
3393                                                 read_group < (write_group + 1)
3394                                                 * RW_MGR_MEM_IF_READ_DQS_WIDTH
3395                                                 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3396                                                 group_failed == 0;
3397                                                 read_group++, read_test_bgn +=
3398                                                 RW_MGR_MEM_DQ_PER_READ_DQS) {
3399                                                 if (!((STATIC_CALIB_STEPS) &
3400                                                         CALIB_SKIP_WRITES)) {
3401                                         if (!rw_mgr_mem_calibrate_vfifo_end
3402                                                 (read_group, read_test_bgn)) {
3403                                                         group_failed = 1;
3404
3405                                                 if (!(gbl->phy_debug_mode_flags
3406                                                 & PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3407                                                                 return 0;
3408                                                                 }
3409                                                         }
3410                                                 }
3411                                         }
3412                                 }
3413
3414                                 if (group_failed != 0)
3415                                         failing_groups++;
3416                         }
3417
3418                         /*
3419                          * USER If there are any failing groups then report
3420                          * the failure.
3421                          */
3422                         if (failing_groups != 0)
3423                                 return 0;
3424
3425                         /* Calibrate the LFIFO */
3426                         if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) {
3427                                 /*
3428                                  * If we're skipping groups as part of debug,
3429                                  * don't calibrate LFIFO.
3430                                  */
3431                                 if (param->skip_groups == 0) {
3432                                         if (!rw_mgr_mem_calibrate_lfifo())
3433                                                 return 0;
3434                                 }
3435                         }
3436                 }
3437         }
3438
3439         /*
3440          * Do not remove this line as it makes sure all of our decisions
3441          * have been applied.
3442          */
3443         writel(0, &sdr_scc_mgr->update);
3444         return 1;
3445 }
3446
3447 /**
3448  * run_mem_calibrate() - Perform memory calibration
3449  *
3450  * This function triggers the entire memory calibration procedure.
3451  */
3452 static int run_mem_calibrate(void)
3453 {
3454         int pass;
3455
3456         debug("%s:%d\n", __func__, __LINE__);
3457
3458         /* Reset pass/fail status shown on afi_cal_success/fail */
3459         writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3460
3461         /* Stop tracking manager. */
3462         clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3463
3464         phy_mgr_initialize();
3465         rw_mgr_mem_initialize();
3466
3467         /* Perform the actual memory calibration. */
3468         pass = mem_calibrate();
3469
3470         mem_precharge_and_activate();
3471         writel(0, &phy_mgr_cmd->fifo_reset);
3472
3473         /* Handoff. */
3474         rw_mgr_mem_handoff();
3475         /*
3476          * In Hard PHY this is a 2-bit control:
3477          * 0: AFI Mux Select
3478          * 1: DDIO Mux Select
3479          */
3480         writel(0x2, &phy_mgr_cfg->mux_sel);
3481
3482         /* Start tracking manager. */
3483         setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3484
3485         return pass;
3486 }
3487
3488 /**
3489  * debug_mem_calibrate() - Report result of memory calibration
3490  * @pass:       Value indicating whether calibration passed or failed
3491  *
3492  * This function reports the results of the memory calibration
3493  * and writes debug information into the register file.
3494  */
3495 static void debug_mem_calibrate(int pass)
3496 {
3497         uint32_t debug_info;
3498
3499         if (pass) {
3500                 printf("%s: CALIBRATION PASSED\n", __FILE__);
3501
3502                 gbl->fom_in /= 2;
3503                 gbl->fom_out /= 2;
3504
3505                 if (gbl->fom_in > 0xff)
3506                         gbl->fom_in = 0xff;
3507
3508                 if (gbl->fom_out > 0xff)
3509                         gbl->fom_out = 0xff;
3510
3511                 /* Update the FOM in the register file */
3512                 debug_info = gbl->fom_in;
3513                 debug_info |= gbl->fom_out << 8;
3514                 writel(debug_info, &sdr_reg_file->fom);
3515
3516                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3517                 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3518         } else {
3519                 printf("%s: CALIBRATION FAILED\n", __FILE__);
3520
3521                 debug_info = gbl->error_stage;
3522                 debug_info |= gbl->error_substage << 8;
3523                 debug_info |= gbl->error_group << 16;
3524
3525                 writel(debug_info, &sdr_reg_file->failing_stage);
3526                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3527                 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3528
3529                 /* Update the failing group/stage in the register file */
3530                 debug_info = gbl->error_stage;
3531                 debug_info |= gbl->error_substage << 8;
3532                 debug_info |= gbl->error_group << 16;
3533                 writel(debug_info, &sdr_reg_file->failing_stage);
3534         }
3535
3536         printf("%s: Calibration complete\n", __FILE__);
3537 }
3538
3539 /**
3540  * hc_initialize_rom_data() - Initialize ROM data
3541  *
3542  * Initialize ROM data.
3543  */
3544 static void hc_initialize_rom_data(void)
3545 {
3546         u32 i, addr;
3547
3548         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3549         for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3550                 writel(inst_rom_init[i], addr + (i << 2));
3551
3552         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3553         for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3554                 writel(ac_rom_init[i], addr + (i << 2));
3555 }
3556
3557 /**
3558  * initialize_reg_file() - Initialize SDR register file
3559  *
3560  * Initialize SDR register file.
3561  */
3562 static void initialize_reg_file(void)
3563 {
3564         /* Initialize the register file with the correct data */
3565         writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3566         writel(0, &sdr_reg_file->debug_data_addr);
3567         writel(0, &sdr_reg_file->cur_stage);
3568         writel(0, &sdr_reg_file->fom);
3569         writel(0, &sdr_reg_file->failing_stage);
3570         writel(0, &sdr_reg_file->debug1);
3571         writel(0, &sdr_reg_file->debug2);
3572 }
3573
3574 /**
3575  * initialize_hps_phy() - Initialize HPS PHY
3576  *
3577  * Initialize HPS PHY.
3578  */
3579 static void initialize_hps_phy(void)
3580 {
3581         uint32_t reg;
3582         /*
3583          * Tracking also gets configured here because it's in the
3584          * same register.
3585          */
3586         uint32_t trk_sample_count = 7500;
3587         uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3588         /*
3589          * Format is number of outer loops in the 16 MSB, sample
3590          * count in 16 LSB.
3591          */
3592
3593         reg = 0;
3594         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3595         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3596         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3597         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3598         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3599         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3600         /*
3601          * This field selects the intrinsic latency to RDATA_EN/FULL path.
3602          * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3603          */
3604         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3605         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3606                 trk_sample_count);
3607         writel(reg, &sdr_ctrl->phy_ctrl0);
3608
3609         reg = 0;
3610         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3611                 trk_sample_count >>
3612                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3613         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3614                 trk_long_idle_sample_count);
3615         writel(reg, &sdr_ctrl->phy_ctrl1);
3616
3617         reg = 0;
3618         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3619                 trk_long_idle_sample_count >>
3620                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3621         writel(reg, &sdr_ctrl->phy_ctrl2);
3622 }
3623
3624 /**
3625  * initialize_tracking() - Initialize tracking
3626  *
3627  * Initialize the register file with usable initial data.
3628  */
3629 static void initialize_tracking(void)
3630 {
3631         /*
3632          * Initialize the register file with the correct data.
3633          * Compute usable version of value in case we skip full
3634          * computation later.
3635          */
3636         writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3637                &sdr_reg_file->dtaps_per_ptap);
3638
3639         /* trk_sample_count */
3640         writel(7500, &sdr_reg_file->trk_sample_count);
3641
3642         /* longidle outer loop [15:0] */
3643         writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3644
3645         /*
3646          * longidle sample count [31:24]
3647          * trfc, worst case of 933Mhz 4Gb [23:16]
3648          * trcd, worst case [15:8]
3649          * vfifo wait [7:0]
3650          */
3651         writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3652                &sdr_reg_file->delays);
3653
3654         /* mux delay */
3655         writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3656                (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3657                &sdr_reg_file->trk_rw_mgr_addr);
3658
3659         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3660                &sdr_reg_file->trk_read_dqs_width);
3661
3662         /* trefi [7:0] */
3663         writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3664                &sdr_reg_file->trk_rfsh);
3665 }
3666
3667 int sdram_calibration_full(void)
3668 {
3669         struct param_type my_param;
3670         struct gbl_type my_gbl;
3671         uint32_t pass;
3672
3673         memset(&my_param, 0, sizeof(my_param));
3674         memset(&my_gbl, 0, sizeof(my_gbl));
3675
3676         param = &my_param;
3677         gbl = &my_gbl;
3678
3679         /* Set the calibration enabled by default */
3680         gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3681         /*
3682          * Only sweep all groups (regardless of fail state) by default
3683          * Set enabled read test by default.
3684          */
3685 #if DISABLE_GUARANTEED_READ
3686         gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3687 #endif
3688         /* Initialize the register file */
3689         initialize_reg_file();
3690
3691         /* Initialize any PHY CSR */
3692         initialize_hps_phy();
3693
3694         scc_mgr_initialize();
3695
3696         initialize_tracking();
3697
3698         printf("%s: Preparing to start memory calibration\n", __FILE__);
3699
3700         debug("%s:%d\n", __func__, __LINE__);
3701         debug_cond(DLEVEL == 1,
3702                    "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3703                    RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3704                    RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3705                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3706                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3707         debug_cond(DLEVEL == 1,
3708                    "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3709                    RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3710                    RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3711                    IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3712         debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3713                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3714         debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3715                    IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3716                    IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3717         debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3718                    IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3719                    IO_IO_OUT2_DELAY_MAX);
3720         debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3721                    IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3722
3723         hc_initialize_rom_data();
3724
3725         /* update info for sims */
3726         reg_file_set_stage(CAL_STAGE_NIL);
3727         reg_file_set_group(0);
3728
3729         /*
3730          * Load global needed for those actions that require
3731          * some dynamic calibration support.
3732          */
3733         dyn_calib_steps = STATIC_CALIB_STEPS;
3734         /*
3735          * Load global to allow dynamic selection of delay loop settings
3736          * based on calibration mode.
3737          */
3738         if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3739                 skip_delay_mask = 0xff;
3740         else
3741                 skip_delay_mask = 0x0;
3742
3743         pass = run_mem_calibrate();
3744         debug_mem_calibrate(pass);
3745         return pass;
3746 }