2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
11 #include "sequencer.h"
12 #include "sequencer_auto.h"
13 #include "sequencer_auto_ac_init.h"
14 #include "sequencer_auto_inst_init.h"
15 #include "sequencer_defines.h"
17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
18 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
21 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
23 static struct socfpga_sdr_reg_file *sdr_reg_file =
24 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
27 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
30 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
33 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
35 static struct socfpga_data_mgr *data_mgr =
36 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
38 static struct socfpga_sdr_ctrl *sdr_ctrl =
39 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
44 * In order to reduce ROM size, most of the selectable calibration steps are
45 * decided at compile time based on the user's calibration mode selection,
46 * as captured by the STATIC_CALIB_STEPS selection below.
48 * However, to support simulation-time selection of fast simulation mode, where
49 * we skip everything except the bare minimum, we need a few of the steps to
50 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
51 * check, which is based on the rtl-supplied value, or we dynamically compute
52 * the value to use based on the dynamically-chosen calibration mode
56 #define STATIC_IN_RTL_SIM 0
57 #define STATIC_SKIP_DELAY_LOOPS 0
59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
60 STATIC_SKIP_DELAY_LOOPS)
62 /* calibration steps requested by the rtl */
63 uint16_t dyn_calib_steps;
66 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
67 * instead of static, we use boolean logic to select between
68 * non-skip and skip values
70 * The mask is set to include all bits when not-skipping, but is
74 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
77 ((non_skip_value) & skip_delay_mask)
80 struct param_type *param;
81 uint32_t curr_shadow_reg;
83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
84 uint32_t write_group, uint32_t use_dm,
85 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
91 * Only set the global stage if there was not been any other
94 if (gbl->error_stage == CAL_STAGE_NIL) {
95 gbl->error_substage = substage;
96 gbl->error_stage = stage;
97 gbl->error_group = group;
101 static void reg_file_set_group(u16 set_group)
103 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
106 static void reg_file_set_stage(u8 set_stage)
108 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
111 static void reg_file_set_sub_stage(u8 set_sub_stage)
113 set_sub_stage &= 0xff;
114 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
118 * phy_mgr_initialize() - Initialize PHY Manager
120 * Initialize PHY Manager.
122 static void phy_mgr_initialize(void)
126 debug("%s:%d\n", __func__, __LINE__);
127 /* Calibration has control over path to memory */
129 * In Hard PHY this is a 2-bit control:
133 writel(0x3, &phy_mgr_cfg->mux_sel);
135 /* USER memory clock is not stable we begin initialization */
136 writel(0, &phy_mgr_cfg->reset_mem_stbl);
138 /* USER calibration status all set to zero */
139 writel(0, &phy_mgr_cfg->cal_status);
141 writel(0, &phy_mgr_cfg->cal_debug_info);
143 /* Init params only if we do NOT skip calibration. */
144 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
147 ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
148 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
149 param->read_correct_mask_vg = (1 << ratio) - 1;
150 param->write_correct_mask_vg = (1 << ratio) - 1;
151 param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
152 param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
153 ratio = RW_MGR_MEM_DATA_WIDTH /
154 RW_MGR_MEM_DATA_MASK_WIDTH;
155 param->dm_correct_mask = (1 << ratio) - 1;
159 * set_rank_and_odt_mask() - Set Rank and ODT mask
161 * @odt_mode: ODT mode, OFF or READ_WRITE
163 * Set Rank and ODT mask (On-Die Termination).
165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
171 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
174 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
175 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
177 /* Read: ODT = 0 ; Write: ODT = 1 */
181 case 2: /* 2 Ranks */
182 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
184 * - Dual-Slot , Single-Rank (1 CS per DIMM)
186 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
188 * Since MEM_NUMBER_OF_RANKS is 2, they
189 * are both single rank with 2 CS each
190 * (special for RDIMM).
192 * Read: Turn on ODT on the opposite rank
193 * Write: Turn on ODT on all ranks
195 odt_mask_0 = 0x3 & ~(1 << rank);
199 * - Single-Slot , Dual-Rank (2 CS per DIMM)
201 * Read: Turn on ODT off on all ranks
202 * Write: Turn on ODT on active rank
205 odt_mask_1 = 0x3 & (1 << rank);
208 case 4: /* 4 Ranks */
210 * ----------+-----------------------+
212 * Read From +-----------------------+
213 * Rank | 3 | 2 | 1 | 0 |
214 * ----------+-----+-----+-----+-----+
215 * 0 | 0 | 1 | 0 | 0 |
216 * 1 | 1 | 0 | 0 | 0 |
217 * 2 | 0 | 0 | 0 | 1 |
218 * 3 | 0 | 0 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
222 * ----------+-----------------------+
224 * Write To +-----------------------+
225 * Rank | 3 | 2 | 1 | 0 |
226 * ----------+-----+-----+-----+-----+
227 * 0 | 0 | 1 | 0 | 1 |
228 * 1 | 1 | 0 | 1 | 0 |
229 * 2 | 0 | 1 | 0 | 1 |
230 * 3 | 1 | 0 | 1 | 0 |
231 * ----------+-----+-----+-----+-----+
255 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
256 ((0xFF & odt_mask_0) << 8) |
257 ((0xFF & odt_mask_1) << 16);
258 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
259 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
263 * scc_mgr_set() - Set SCC Manager register
264 * @off: Base offset in SCC Manager space
265 * @grp: Read/Write group
266 * @val: Value to be set
268 * This function sets the SCC Manager (Scan Chain Control Manager) register.
270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
272 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
276 * scc_mgr_initialize() - Initialize SCC Manager registers
278 * Initialize SCC Manager registers.
280 static void scc_mgr_initialize(void)
283 * Clear register file for HPS. 16 (2^4) is the size of the
284 * full register file in the scc mgr:
285 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
286 * MEM_IF_READ_DQS_WIDTH - 1);
290 for (i = 0; i < 16; i++) {
291 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
292 __func__, __LINE__, i);
293 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
299 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
304 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
309 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
314 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
319 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
325 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
330 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
335 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
341 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
342 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
346 /* load up dqs config settings */
347 static void scc_mgr_load_dqs(uint32_t dqs)
349 writel(dqs, &sdr_scc_mgr->dqs_ena);
352 /* load up dqs io config settings */
353 static void scc_mgr_load_dqs_io(void)
355 writel(0, &sdr_scc_mgr->dqs_io_ena);
358 /* load up dq config settings */
359 static void scc_mgr_load_dq(uint32_t dq_in_group)
361 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
364 /* load up dm config settings */
365 static void scc_mgr_load_dm(uint32_t dm)
367 writel(dm, &sdr_scc_mgr->dm_ena);
371 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
372 * @off: Base offset in SCC Manager space
373 * @grp: Read/Write group
374 * @val: Value to be set
375 * @update: If non-zero, trigger SCC Manager update for all ranks
377 * This function sets the SCC Manager (Scan Chain Control Manager) register
378 * and optionally triggers the SCC update for all ranks.
380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
385 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
386 r += NUM_RANKS_PER_SHADOW_REG) {
387 scc_mgr_set(off, grp, val);
389 if (update || (r == 0)) {
390 writel(grp, &sdr_scc_mgr->dqs_ena);
391 writel(0, &sdr_scc_mgr->update);
396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
399 * USER although the h/w doesn't support different phases per
400 * shadow register, for simplicity our scc manager modeling
401 * keeps different phase settings per shadow reg, and it's
402 * important for us to keep them in sync to match h/w.
403 * for efficiency, the scan chain update should occur only
406 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
407 read_group, phase, 0);
410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
414 * USER although the h/w doesn't support different phases per
415 * shadow register, for simplicity our scc manager modeling
416 * keeps different phase settings per shadow reg, and it's
417 * important for us to keep them in sync to match h/w.
418 * for efficiency, the scan chain update should occur only
421 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
422 write_group, phase, 0);
425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
429 * In shadow register mode, the T11 settings are stored in
430 * registers in the core, which are updated by the DQS_ENA
431 * signals. Not issuing the SCC_MGR_UPD command allows us to
432 * save lots of rank switching overhead, by calling
433 * select_shadow_regs_for_update with update_scan_chains
436 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
437 read_group, delay, 1);
438 writel(0, &sdr_scc_mgr->update);
442 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
443 * @write_group: Write group
444 * @delay: Delay value
446 * This function sets the OCT output delay in SCC manager.
448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
450 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
451 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
452 const int base = write_group * ratio;
455 * Load the setting in the SCC manager
456 * Although OCT affects only write data, the OCT delay is controlled
457 * by the DQS logic block which is instantiated once per read group.
458 * For protocols where a write group consists of multiple read groups,
459 * the setting must be set multiple times.
461 for (i = 0; i < ratio; i++)
462 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
466 * scc_mgr_set_hhp_extras() - Set HHP extras.
468 * Load the fixed setting in the SCC manager HHP extras.
470 static void scc_mgr_set_hhp_extras(void)
473 * Load the fixed setting in the SCC manager
474 * bits: 0:0 = 1'b1 - DQS bypass
475 * bits: 1:1 = 1'b1 - DQ bypass
476 * bits: 4:2 = 3'b001 - rfifo_mode
477 * bits: 6:5 = 2'b01 - rfifo clock_select
478 * bits: 7:7 = 1'b0 - separate gating from ungating setting
479 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
481 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
482 (1 << 2) | (1 << 1) | (1 << 0);
483 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
484 SCC_MGR_HHP_GLOBALS_OFFSET |
485 SCC_MGR_HHP_EXTRAS_OFFSET;
487 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
490 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
495 * scc_mgr_zero_all() - Zero all DQS config
497 * Zero all DQS config.
499 static void scc_mgr_zero_all(void)
504 * USER Zero all DQS config settings, across all groups and all
507 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
508 r += NUM_RANKS_PER_SHADOW_REG) {
509 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
511 * The phases actually don't exist on a per-rank basis,
512 * but there's no harm updating them several times, so
513 * let's keep the code simple.
515 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
516 scc_mgr_set_dqs_en_phase(i, 0);
517 scc_mgr_set_dqs_en_delay(i, 0);
520 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
521 scc_mgr_set_dqdqs_output_phase(i, 0);
522 /* Arria V/Cyclone V don't have out2. */
523 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
527 /* Multicast to all DQS group enables. */
528 writel(0xff, &sdr_scc_mgr->dqs_ena);
529 writel(0, &sdr_scc_mgr->update);
533 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
534 * @write_group: Write group
536 * Set bypass mode and trigger SCC update.
538 static void scc_set_bypass_mode(const u32 write_group)
540 /* Multicast to all DQ enables. */
541 writel(0xff, &sdr_scc_mgr->dq_ena);
542 writel(0xff, &sdr_scc_mgr->dm_ena);
544 /* Update current DQS IO enable. */
545 writel(0, &sdr_scc_mgr->dqs_io_ena);
547 /* Update the DQS logic. */
548 writel(write_group, &sdr_scc_mgr->dqs_ena);
551 writel(0, &sdr_scc_mgr->update);
555 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
556 * @write_group: Write group
558 * Load DQS settings for Write Group, do not trigger SCC update.
560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
562 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
563 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
564 const int base = write_group * ratio;
567 * Load the setting in the SCC manager
568 * Although OCT affects only write data, the OCT delay is controlled
569 * by the DQS logic block which is instantiated once per read group.
570 * For protocols where a write group consists of multiple read groups,
571 * the setting must be set multiple times.
573 for (i = 0; i < ratio; i++)
574 writel(base + i, &sdr_scc_mgr->dqs_ena);
578 * scc_mgr_zero_group() - Zero all configs for a group
580 * Zero DQ, DM, DQS and OCT configs for a group.
582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
586 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
587 r += NUM_RANKS_PER_SHADOW_REG) {
588 /* Zero all DQ config settings. */
589 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
590 scc_mgr_set_dq_out1_delay(i, 0);
592 scc_mgr_set_dq_in_delay(i, 0);
595 /* Multicast to all DQ enables. */
596 writel(0xff, &sdr_scc_mgr->dq_ena);
598 /* Zero all DM config settings. */
599 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
600 scc_mgr_set_dm_out1_delay(i, 0);
602 /* Multicast to all DM enables. */
603 writel(0xff, &sdr_scc_mgr->dm_ena);
605 /* Zero all DQS IO settings. */
607 scc_mgr_set_dqs_io_in_delay(0);
609 /* Arria V/Cyclone V don't have out2. */
610 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
611 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
612 scc_mgr_load_dqs_for_write_group(write_group);
614 /* Multicast to all DQS IO enables (only 1 in total). */
615 writel(0, &sdr_scc_mgr->dqs_io_ena);
617 /* Hit update to zero everything. */
618 writel(0, &sdr_scc_mgr->update);
623 * apply and load a particular input delay for the DQ pins in a group
624 * group_bgn is the index of the first dq pin (in the write group)
626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
630 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
631 scc_mgr_set_dq_in_delay(p, delay);
637 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
638 * @delay: Delay value
640 * Apply and load a particular output delay for the DQ pins in a group.
642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
646 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
647 scc_mgr_set_dq_out1_delay(i, delay);
652 /* apply and load a particular output delay for the DM pins in a group */
653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
657 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
658 scc_mgr_set_dm_out1_delay(i, delay1);
664 /* apply and load delay on both DQS and OCT out1 */
665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
668 scc_mgr_set_dqs_out1_delay(delay);
669 scc_mgr_load_dqs_io();
671 scc_mgr_set_oct_out1_delay(write_group, delay);
672 scc_mgr_load_dqs_for_write_group(write_group);
676 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
677 * @write_group: Write group
678 * @delay: Delay value
680 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
688 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
692 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
696 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
697 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
698 debug_cond(DLEVEL == 1,
699 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
700 __func__, __LINE__, write_group, delay, new_delay,
701 IO_IO_OUT2_DELAY_MAX,
702 new_delay - IO_IO_OUT2_DELAY_MAX);
703 new_delay -= IO_IO_OUT2_DELAY_MAX;
704 scc_mgr_set_dqs_out1_delay(new_delay);
707 scc_mgr_load_dqs_io();
710 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
711 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
712 debug_cond(DLEVEL == 1,
713 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
714 __func__, __LINE__, write_group, delay,
715 new_delay, IO_IO_OUT2_DELAY_MAX,
716 new_delay - IO_IO_OUT2_DELAY_MAX);
717 new_delay -= IO_IO_OUT2_DELAY_MAX;
718 scc_mgr_set_oct_out1_delay(write_group, new_delay);
721 scc_mgr_load_dqs_for_write_group(write_group);
725 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
726 * @write_group: Write group
727 * @delay: Delay value
729 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
737 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
738 r += NUM_RANKS_PER_SHADOW_REG) {
739 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
740 writel(0, &sdr_scc_mgr->update);
745 * set_jump_as_return() - Return instruction optimization
747 * Optimization used to recover some slots in ddr3 inst_rom could be
748 * applied to other protocols if we wanted to
750 static void set_jump_as_return(void)
753 * To save space, we replace return with jump to special shared
754 * RETURN instruction so we set the counter to large value so that
757 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
758 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
762 * should always use constants as argument to ensure all computations are
763 * performed at compile time
765 static void delay_for_n_mem_clocks(const uint32_t clocks)
772 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
775 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
776 /* scale (rounding up) to get afi clocks */
779 * Note, we don't bother accounting for being off a little bit
780 * because of a few extra instructions in outer loops
781 * Note, the loops have a test at the end, and do the test before
782 * the decrement, and so always perform the loop
783 * 1 time more than the counter value
785 if (afi_clocks == 0) {
787 } else if (afi_clocks <= 0x100) {
788 inner = afi_clocks-1;
791 } else if (afi_clocks <= 0x10000) {
793 outer = (afi_clocks-1) >> 8;
798 c_loop = (afi_clocks-1) >> 16;
802 * rom instructions are structured as follows:
804 * IDLE_LOOP2: jnz cntr0, TARGET_A
805 * IDLE_LOOP1: jnz cntr1, TARGET_B
808 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
809 * TARGET_B is set to IDLE_LOOP2 as well
811 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
812 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
814 * a little confusing, but it helps save precious space in the inst_rom
815 * and sequencer rom and keeps the delays more accurate and reduces
818 if (afi_clocks <= 0x100) {
819 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
820 &sdr_rw_load_mgr_regs->load_cntr1);
822 writel(RW_MGR_IDLE_LOOP1,
823 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
825 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
826 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
828 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
829 &sdr_rw_load_mgr_regs->load_cntr0);
831 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
832 &sdr_rw_load_mgr_regs->load_cntr1);
834 writel(RW_MGR_IDLE_LOOP2,
835 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
837 writel(RW_MGR_IDLE_LOOP2,
838 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
840 /* hack to get around compiler not being smart enough */
841 if (afi_clocks <= 0x10000) {
842 /* only need to run once */
843 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
844 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
847 writel(RW_MGR_IDLE_LOOP2,
848 SDR_PHYGRP_RWMGRGRP_ADDRESS |
849 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
850 } while (c_loop-- != 0);
853 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
857 * rw_mgr_mem_init_load_regs() - Load instruction registers
858 * @cntr0: Counter 0 value
859 * @cntr1: Counter 1 value
860 * @cntr2: Counter 2 value
861 * @jump: Jump instruction value
863 * Load instruction registers.
865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
867 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
868 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
871 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
872 &sdr_rw_load_mgr_regs->load_cntr0);
873 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
874 &sdr_rw_load_mgr_regs->load_cntr1);
875 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
876 &sdr_rw_load_mgr_regs->load_cntr2);
878 /* Load jump address */
879 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
880 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
881 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
883 /* Execute count instruction */
884 writel(jump, grpaddr);
888 * rw_mgr_mem_load_user() - Load user calibration values
889 * @fin1: Final instruction 1
890 * @fin2: Final instruction 2
891 * @precharge: If 1, precharge the banks at the end
893 * Load user calibration values and optionally precharge the banks.
895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
898 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
899 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
902 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
903 if (param->skip_ranks[r]) {
904 /* request to skip the rank */
909 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
911 /* precharge all banks ... */
913 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
916 * USER Use Mirror-ed commands for odd ranks if address
919 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
920 set_jump_as_return();
921 writel(RW_MGR_MRS2_MIRR, grpaddr);
922 delay_for_n_mem_clocks(4);
923 set_jump_as_return();
924 writel(RW_MGR_MRS3_MIRR, grpaddr);
925 delay_for_n_mem_clocks(4);
926 set_jump_as_return();
927 writel(RW_MGR_MRS1_MIRR, grpaddr);
928 delay_for_n_mem_clocks(4);
929 set_jump_as_return();
930 writel(fin1, grpaddr);
932 set_jump_as_return();
933 writel(RW_MGR_MRS2, grpaddr);
934 delay_for_n_mem_clocks(4);
935 set_jump_as_return();
936 writel(RW_MGR_MRS3, grpaddr);
937 delay_for_n_mem_clocks(4);
938 set_jump_as_return();
939 writel(RW_MGR_MRS1, grpaddr);
940 set_jump_as_return();
941 writel(fin2, grpaddr);
947 set_jump_as_return();
948 writel(RW_MGR_ZQCL, grpaddr);
950 /* tZQinit = tDLLK = 512 ck cycles */
951 delay_for_n_mem_clocks(512);
956 * rw_mgr_mem_initialize() - Initialize RW Manager
958 * Initialize RW Manager.
960 static void rw_mgr_mem_initialize(void)
962 debug("%s:%d\n", __func__, __LINE__);
964 /* The reset / cke part of initialization is broadcasted to all ranks */
965 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
966 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
969 * Here's how you load register for a loop
970 * Counters are located @ 0x800
971 * Jump address are located @ 0xC00
972 * For both, registers 0 to 3 are selected using bits 3 and 2, like
973 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
974 * I know this ain't pretty, but Avalon bus throws away the 2 least
978 /* Start with memory RESET activated */
983 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
984 * If a and b are the number of iteration in 2 nested loops
985 * it takes the following number of cycles to complete the operation:
986 * number_of_cycles = ((2 + n) * a + 2) * b
987 * where n is the number of instruction in the inner loop
988 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
991 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
993 RW_MGR_INIT_RESET_0_CKE_0);
995 /* Indicate that memory is stable. */
996 writel(1, &phy_mgr_cfg->reset_mem_stbl);
999 * transition the RESET to high
1004 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005 * If a and b are the number of iteration in 2 nested loops
1006 * it takes the following number of cycles to complete the operation
1007 * number_of_cycles = ((2 + n) * a + 2) * b
1008 * where n is the number of instruction in the inner loop
1009 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1012 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013 SEQ_TRESET_CNTR2_VAL,
1014 RW_MGR_INIT_RESET_1_CKE_0);
1016 /* Bring up clock enable. */
1018 /* tXRP < 250 ck cycles */
1019 delay_for_n_mem_clocks(250);
1021 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1026 * At the end of calibration we have to program the user settings in, and
1027 * USER hand off the memory to the user.
1029 static void rw_mgr_mem_handoff(void)
1031 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1033 * USER need to wait tMOD (12CK or 15ns) time before issuing
1034 * other commands, but we will have plenty of NIOS cycles before
1035 * actual handoff so its okay.
1040 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041 * @rank_bgn: Rank number
1042 * @group: Read/Write Group
1043 * @all_ranks: Test all ranks
1045 * Performs a guaranteed read on the patterns we are going to use during a
1046 * read test to ensure memory works.
1049 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050 const u32 all_ranks)
1052 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054 const u32 addr_offset =
1055 (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056 const u32 rank_end = all_ranks ?
1057 RW_MGR_MEM_NUMBER_OF_RANKS :
1058 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059 const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061 const u32 correct_mask_vg = param->read_correct_mask_vg;
1063 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1067 bit_chk = param->read_correct_mask;
1069 for (r = rank_bgn; r < rank_end; r++) {
1070 /* Request to skip the rank */
1071 if (param->skip_ranks[r])
1075 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1077 /* Load up a constant bursts of read commands */
1078 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079 writel(RW_MGR_GUARANTEED_READ,
1080 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1082 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083 writel(RW_MGR_GUARANTEED_READ_CONT,
1084 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1087 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1089 /* Reset the FIFOs to get pointers to known state. */
1090 writel(0, &phy_mgr_cmd->fifo_reset);
1091 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1093 writel(RW_MGR_GUARANTEED_READ,
1094 addr + addr_offset + (vg << 2));
1096 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1097 tmp_bit_chk <<= shift_ratio;
1098 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1101 bit_chk &= tmp_bit_chk;
1104 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1106 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1108 if (bit_chk != param->read_correct_mask)
1111 debug_cond(DLEVEL == 1,
1112 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113 __func__, __LINE__, group, bit_chk,
1114 param->read_correct_mask, ret);
1120 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121 * @rank_bgn: Rank number
1122 * @all_ranks: Test all ranks
1124 * Load up the patterns we are going to use during a read test.
1126 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127 const int all_ranks)
1129 const u32 rank_end = all_ranks ?
1130 RW_MGR_MEM_NUMBER_OF_RANKS :
1131 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1134 debug("%s:%d\n", __func__, __LINE__);
1136 for (r = rank_bgn; r < rank_end; r++) {
1137 if (param->skip_ranks[r])
1138 /* request to skip the rank */
1142 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1144 /* Load up a constant bursts */
1145 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1147 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1150 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1152 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1155 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1157 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1160 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1162 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1165 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1169 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1173 * try a read and see if it returns correct data back. has dummy reads
1174 * inserted into the mix used to align dqs enable. has more thorough checks
1175 * than the regular read test.
1177 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1178 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1179 uint32_t all_groups, uint32_t all_ranks)
1182 uint32_t correct_mask_vg;
1183 uint32_t tmp_bit_chk;
1184 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1185 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1187 uint32_t base_rw_mgr;
1189 *bit_chk = param->read_correct_mask;
1190 correct_mask_vg = param->read_correct_mask_vg;
1192 uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1193 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1195 for (r = rank_bgn; r < rank_end; r++) {
1196 if (param->skip_ranks[r])
1197 /* request to skip the rank */
1201 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1203 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1205 writel(RW_MGR_READ_B2B_WAIT1,
1206 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1208 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1209 writel(RW_MGR_READ_B2B_WAIT2,
1210 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1212 if (quick_read_mode)
1213 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1214 /* need at least two (1+1) reads to capture failures */
1215 else if (all_groups)
1216 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1218 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1220 writel(RW_MGR_READ_B2B,
1221 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1223 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1224 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1225 &sdr_rw_load_mgr_regs->load_cntr3);
1227 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1229 writel(RW_MGR_READ_B2B,
1230 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1233 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1234 /* reset the fifos to get pointers to known state */
1235 writel(0, &phy_mgr_cmd->fifo_reset);
1236 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1237 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1239 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1240 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1243 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1245 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1247 writel(RW_MGR_READ_B2B, addr +
1248 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1251 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1252 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1257 *bit_chk &= tmp_bit_chk;
1260 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1261 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1264 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1265 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1266 (%u == %u) => %lu", __func__, __LINE__, group,
1267 all_groups, *bit_chk, param->read_correct_mask,
1268 (long unsigned int)(*bit_chk ==
1269 param->read_correct_mask));
1270 return *bit_chk == param->read_correct_mask;
1272 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1273 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1274 (%u != %lu) => %lu\n", __func__, __LINE__,
1275 group, all_groups, *bit_chk, (long unsigned int)0,
1276 (long unsigned int)(*bit_chk != 0x00));
1277 return *bit_chk != 0x00;
1281 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1282 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1283 uint32_t all_groups)
1285 return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1286 bit_chk, all_groups, 1);
1290 * rw_mgr_incr_vfifo() - Increase VFIFO value
1291 * @grp: Read/Write group
1293 * Increase VFIFO value.
1295 static void rw_mgr_incr_vfifo(const u32 grp)
1297 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1301 * rw_mgr_decr_vfifo() - Decrease VFIFO value
1302 * @grp: Read/Write group
1304 * Decrease VFIFO value.
1306 static void rw_mgr_decr_vfifo(const u32 grp)
1310 for (i = 0; i < VFIFO_SIZE - 1; i++)
1311 rw_mgr_incr_vfifo(grp);
1315 * find_vfifo_failing_read() - Push VFIFO to get a failing read
1316 * @grp: Read/Write group
1318 * Push VFIFO until a failing read happens.
1320 static int find_vfifo_failing_read(const u32 grp)
1322 u32 v, ret, bit_chk, fail_cnt = 0;
1324 for (v = 0; v < VFIFO_SIZE; v++) {
1325 debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
1326 __func__, __LINE__, v);
1327 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1328 PASS_ONE_BIT, &bit_chk, 0);
1336 /* Fiddle with FIFO. */
1337 rw_mgr_incr_vfifo(grp);
1340 /* No failing read found! Something must have gone wrong. */
1341 debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
1346 * sdr_find_phase() - Find DQS enable phase
1347 * @working: If 1, look for working phase, if 0, look for non-working phase
1348 * @grp: Read/Write group
1349 * @work: Working window position
1351 * @p: DQS Phase Iterator
1353 * Find working or non-working DQS enable phase setting.
1355 static int sdr_find_phase(int working, const u32 grp, u32 *work,
1359 const u32 end = VFIFO_SIZE + (working ? 0 : 1);
1361 for (; *i < end; (*i)++) {
1365 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++) {
1366 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1368 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1369 PASS_ONE_BIT, &bit_chk, 0);
1376 *work += IO_DELAY_PER_OPA_TAP;
1379 if (*p > IO_DQS_EN_PHASE_MAX) {
1380 /* Fiddle with FIFO. */
1381 rw_mgr_incr_vfifo(grp);
1391 * sdr_working_phase() - Find working DQS enable phase
1392 * @grp: Read/Write group
1393 * @work_bgn: Working window start position
1394 * @d: dtaps output value
1395 * @p: DQS Phase Iterator
1398 * Find working DQS enable phase setting.
1400 static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
1403 const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
1404 IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1409 for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1411 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1412 ret = sdr_find_phase(1, grp, work_bgn, i, p);
1415 *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1418 /* Cannot find working solution */
1419 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1420 __func__, __LINE__);
1425 * sdr_backup_phase() - Find DQS enable backup phase
1426 * @grp: Read/Write group
1427 * @work_bgn: Working window start position
1428 * @p: DQS Phase Iterator
1430 * Find DQS enable backup phase setting.
1432 static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
1434 u32 tmp_delay, bit_chk, d;
1437 /* Special case code for backing up a phase */
1439 *p = IO_DQS_EN_PHASE_MAX;
1440 rw_mgr_decr_vfifo(grp);
1444 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1445 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1447 for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
1448 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1450 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1451 PASS_ONE_BIT, &bit_chk, 0);
1453 *work_bgn = tmp_delay;
1457 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1460 /* Restore VFIFO to old state before we decremented it (if needed). */
1462 if (*p > IO_DQS_EN_PHASE_MAX) {
1464 rw_mgr_incr_vfifo(grp);
1467 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1471 * sdr_nonworking_phase() - Find non-working DQS enable phase
1472 * @grp: Read/Write group
1473 * @work_end: Working window end position
1474 * @p: DQS Phase Iterator
1477 * Find non-working DQS enable phase setting.
1479 static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
1484 *work_end += IO_DELAY_PER_OPA_TAP;
1485 if (*p > IO_DQS_EN_PHASE_MAX) {
1486 /* Fiddle with FIFO. */
1488 rw_mgr_incr_vfifo(grp);
1491 ret = sdr_find_phase(0, grp, work_end, i, p);
1493 /* Cannot see edge of failing read. */
1494 debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
1495 __func__, __LINE__);
1502 * sdr_find_window_center() - Find center of the working DQS window.
1503 * @grp: Read/Write group
1504 * @work_bgn: First working settings
1505 * @work_end: Last working settings
1507 * Find center of the working DQS enable window.
1509 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1512 u32 bit_chk, work_mid;
1516 work_mid = (work_bgn + work_end) / 2;
1518 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1519 work_bgn, work_end, work_mid);
1520 /* Get the middle delay to be less than a VFIFO delay */
1521 tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
1523 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1524 work_mid %= tmp_delay;
1525 debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
1527 tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1528 if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1529 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1530 p = tmp_delay / IO_DELAY_PER_OPA_TAP;
1532 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1534 d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1535 if (d > IO_DQS_EN_DELAY_MAX)
1536 d = IO_DQS_EN_DELAY_MAX;
1537 tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1539 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1541 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1542 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1545 * push vfifo until we can successfully calibrate. We can do this
1546 * because the largest possible margin in 1 VFIFO cycle.
1548 for (i = 0; i < VFIFO_SIZE; i++) {
1549 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
1550 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1553 debug_cond(DLEVEL == 2,
1554 "%s:%d center: found: ptap=%u dtap=%u\n",
1555 __func__, __LINE__, p, d);
1559 /* Fiddle with FIFO. */
1560 rw_mgr_incr_vfifo(grp);
1563 debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1564 __func__, __LINE__);
1568 /* find a good dqs enable to use */
1569 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp)
1573 uint32_t dtaps_per_ptap;
1574 uint32_t work_bgn, work_end;
1575 uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1577 debug("%s:%d %u\n", __func__, __LINE__, grp);
1579 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1581 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1582 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1584 /* Step 0: Determine number of delay taps for each phase tap. */
1585 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP / IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1587 /* Step 1: First push vfifo until we get a failing read. */
1588 find_vfifo_failing_read(grp);
1590 /* Step 2: Find first working phase, increment in ptaps. */
1592 if (sdr_working_phase(grp, &work_bgn, &d, &p, &i))
1595 work_end = work_bgn;
1598 * If d is 0 then the working window covers a phase tap and we can
1599 * follow the old procedure. Otherwise, we've found the beginning
1600 * and we need to increment the dtaps until we find the end.
1604 * Step 3a: If we have room, back off by one and
1605 * increment in dtaps.
1607 sdr_backup_phase(grp, &work_bgn, &p);
1610 * Step 4a: go forward from working phase to non working
1611 * phase, increment in ptaps.
1613 if (sdr_nonworking_phase(grp, &work_end, &p, &i))
1616 /* Step 5a: Back off one from last, increment in dtaps. */
1618 /* Special case code for backing up a phase */
1620 p = IO_DQS_EN_PHASE_MAX;
1621 rw_mgr_decr_vfifo(grp);
1626 work_end -= IO_DELAY_PER_OPA_TAP;
1627 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1631 debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
1632 __func__, __LINE__, p);
1635 * Step 3-5b: Find the right edge of the window
1638 debug_cond(DLEVEL == 2,
1639 "%s:%d ptap=%u dtap=%u bgn=%u\n",
1640 __func__, __LINE__, p, d, work_bgn);
1642 work_end = work_bgn;
1645 /* The dtap increment to find the failing edge is done here. */
1646 for (; d <= IO_DQS_EN_DELAY_MAX;
1647 d++, work_end += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1648 debug_cond(DLEVEL == 2, "%s:%d end-2: dtap=%u\n",
1649 __func__, __LINE__, d);
1651 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1653 if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1660 /* Go back to working dtap */
1662 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1664 debug_cond(DLEVEL == 2,
1665 "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
1666 __func__, __LINE__, p, d - 1, work_end);
1668 if (work_end < work_bgn) {
1670 debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
1671 __func__, __LINE__);
1675 debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
1676 __func__, __LINE__, work_bgn, work_end);
1679 * We need to calculate the number of dtaps that equal a ptap.
1680 * To do that we'll back up a ptap and re-find the edge of the
1681 * window using dtaps
1683 debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
1684 __func__, __LINE__);
1686 /* Special case code for backing up a phase */
1688 p = IO_DQS_EN_PHASE_MAX;
1689 rw_mgr_decr_vfifo(grp);
1690 debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
1691 __func__, __LINE__, p);
1694 debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
1695 __func__, __LINE__, p);
1698 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1701 * Increase dtap until we first see a passing read (in case the
1702 * window is smaller than a ptap), and then a failing read to
1703 * mark the edge of the window again.
1706 /* Find a passing read. */
1707 debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
1708 __func__, __LINE__);
1709 found_passing_read = 0;
1710 found_failing_read = 0;
1711 initial_failing_dtap = d;
1712 for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1713 debug_cond(DLEVEL == 2, "%s:%d testing read d=%u\n",
1714 __func__, __LINE__, d);
1715 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1717 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1720 found_passing_read = 1;
1725 if (found_passing_read) {
1726 /* Find a failing read. */
1727 debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
1728 __func__, __LINE__);
1729 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1730 debug_cond(DLEVEL == 2, "%s:%d testing read d=%u\n",
1731 __func__, __LINE__, d);
1732 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1734 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1735 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1736 found_failing_read = 1;
1741 debug_cond(DLEVEL == 1,
1742 "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
1743 __func__, __LINE__);
1747 * The dynamically calculated dtaps_per_ptap is only valid if we
1748 * found a passing/failing read. If we didn't, it means d hit the max
1749 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1750 * statically calculated value.
1752 if (found_passing_read && found_failing_read)
1753 dtaps_per_ptap = d - initial_failing_dtap;
1755 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1756 debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
1757 __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
1759 /* Step 6: Find the centre of the window. */
1760 if (sdr_find_window_centre(grp, work_bgn, work_end))
1766 /* per-bit deskew DQ and center */
1767 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1768 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1769 uint32_t use_read_test, uint32_t update_fom)
1771 uint32_t i, p, d, min_index;
1773 * Store these as signed since there are comparisons with
1777 uint32_t sticky_bit_chk;
1778 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1779 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1780 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1782 int32_t orig_mid_min, mid_min;
1783 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1785 int32_t dq_margin, dqs_margin;
1787 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1790 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1792 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1793 start_dqs = readl(addr + (read_group << 2));
1794 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1795 start_dqs_en = readl(addr + ((read_group << 2)
1796 - IO_DQS_EN_DELAY_OFFSET));
1798 /* set the left and right edge of each bit to an illegal value */
1799 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1801 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1802 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1803 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1806 /* Search for the left edge of the window for each bit */
1807 for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1808 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1810 writel(0, &sdr_scc_mgr->update);
1813 * Stop searching when the read test doesn't pass AND when
1814 * we've seen a passing read on every bit.
1816 if (use_read_test) {
1817 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1818 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1821 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1824 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1825 (read_group - (write_group *
1826 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1827 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1828 stop = (bit_chk == 0);
1830 sticky_bit_chk = sticky_bit_chk | bit_chk;
1831 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1832 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1833 && %u", __func__, __LINE__, d,
1835 param->read_correct_mask, stop);
1840 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1842 /* Remember a passing test as the
1846 /* If a left edge has not been seen yet,
1847 then a future passing test will mark
1848 this edge as the right edge */
1850 IO_IO_IN_DELAY_MAX + 1) {
1851 right_edge[i] = -(d + 1);
1854 bit_chk = bit_chk >> 1;
1859 /* Reset DQ delay chains to 0 */
1860 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1862 for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1863 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1864 %d right_edge[%u]: %d\n", __func__, __LINE__,
1865 i, left_edge[i], i, right_edge[i]);
1868 * Check for cases where we haven't found the left edge,
1869 * which makes our assignment of the the right edge invalid.
1870 * Reset it to the illegal value.
1872 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1873 right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1874 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1875 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1876 right_edge[%u]: %d\n", __func__, __LINE__,
1881 * Reset sticky bit (except for bits where we have seen
1882 * both the left and right edge).
1884 sticky_bit_chk = sticky_bit_chk << 1;
1885 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1886 (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1887 sticky_bit_chk = sticky_bit_chk | 1;
1894 /* Search for the right edge of the window for each bit */
1895 for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1896 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1897 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1898 uint32_t delay = d + start_dqs_en;
1899 if (delay > IO_DQS_EN_DELAY_MAX)
1900 delay = IO_DQS_EN_DELAY_MAX;
1901 scc_mgr_set_dqs_en_delay(read_group, delay);
1903 scc_mgr_load_dqs(read_group);
1905 writel(0, &sdr_scc_mgr->update);
1908 * Stop searching when the read test doesn't pass AND when
1909 * we've seen a passing read on every bit.
1911 if (use_read_test) {
1912 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1913 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1916 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1919 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1920 (read_group - (write_group *
1921 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1922 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1923 stop = (bit_chk == 0);
1925 sticky_bit_chk = sticky_bit_chk | bit_chk;
1926 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1928 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1929 %u && %u", __func__, __LINE__, d,
1930 sticky_bit_chk, param->read_correct_mask, stop);
1935 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1937 /* Remember a passing test as
1942 /* If a right edge has not been
1943 seen yet, then a future passing
1944 test will mark this edge as the
1946 if (right_edge[i] ==
1947 IO_IO_IN_DELAY_MAX + 1) {
1948 left_edge[i] = -(d + 1);
1951 /* d = 0 failed, but it passed
1952 when testing the left edge,
1953 so it must be marginal,
1955 if (right_edge[i] ==
1956 IO_IO_IN_DELAY_MAX + 1 &&
1962 /* If a right edge has not been
1963 seen yet, then a future passing
1964 test will mark this edge as the
1966 else if (right_edge[i] ==
1967 IO_IO_IN_DELAY_MAX +
1969 left_edge[i] = -(d + 1);
1974 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
1975 d=%u]: ", __func__, __LINE__, d);
1976 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
1977 (int)(bit_chk & 1), i, left_edge[i]);
1978 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
1980 bit_chk = bit_chk >> 1;
1985 /* Check that all bits have a window */
1986 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1987 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1988 %d right_edge[%u]: %d", __func__, __LINE__,
1989 i, left_edge[i], i, right_edge[i]);
1990 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
1991 == IO_IO_IN_DELAY_MAX + 1)) {
1993 * Restore delay chain settings before letting the loop
1994 * in rw_mgr_mem_calibrate_vfifo to retry different
1995 * dqs/ck relationships.
1997 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
1998 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1999 scc_mgr_set_dqs_en_delay(read_group,
2002 scc_mgr_load_dqs(read_group);
2003 writel(0, &sdr_scc_mgr->update);
2005 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2006 find edge [%u]: %d %d", __func__, __LINE__,
2007 i, left_edge[i], right_edge[i]);
2008 if (use_read_test) {
2009 set_failing_group_stage(read_group *
2010 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2012 CAL_SUBSTAGE_VFIFO_CENTER);
2014 set_failing_group_stage(read_group *
2015 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2016 CAL_STAGE_VFIFO_AFTER_WRITES,
2017 CAL_SUBSTAGE_VFIFO_CENTER);
2023 /* Find middle of window for each DQ bit */
2024 mid_min = left_edge[0] - right_edge[0];
2026 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2027 mid = left_edge[i] - right_edge[i];
2028 if (mid < mid_min) {
2035 * -mid_min/2 represents the amount that we need to move DQS.
2036 * If mid_min is odd and positive we'll need to add one to
2037 * make sure the rounding in further calculations is correct
2038 * (always bias to the right), so just add 1 for all positive values.
2043 mid_min = mid_min / 2;
2045 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2046 __func__, __LINE__, mid_min, min_index);
2048 /* Determine the amount we can change DQS (which is -mid_min) */
2049 orig_mid_min = mid_min;
2050 new_dqs = start_dqs - mid_min;
2051 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2052 new_dqs = IO_DQS_IN_DELAY_MAX;
2053 else if (new_dqs < 0)
2056 mid_min = start_dqs - new_dqs;
2057 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2060 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2061 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2062 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2063 else if (start_dqs_en - mid_min < 0)
2064 mid_min += start_dqs_en - mid_min;
2066 new_dqs = start_dqs - mid_min;
2068 debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2069 new_dqs=%d mid_min=%d\n", start_dqs,
2070 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2073 /* Initialize data for export structures */
2074 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2075 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2077 /* add delay to bring centre of all DQ windows to the same "level" */
2078 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2079 /* Use values before divide by 2 to reduce round off error */
2080 shift_dq = (left_edge[i] - right_edge[i] -
2081 (left_edge[min_index] - right_edge[min_index]))/2 +
2082 (orig_mid_min - mid_min);
2084 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2085 shift_dq[%u]=%d\n", i, shift_dq);
2087 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2088 temp_dq_in_delay1 = readl(addr + (p << 2));
2089 temp_dq_in_delay2 = readl(addr + (i << 2));
2091 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2092 (int32_t)IO_IO_IN_DELAY_MAX) {
2093 shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2094 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2095 shift_dq = -(int32_t)temp_dq_in_delay1;
2097 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2098 shift_dq[%u]=%d\n", i, shift_dq);
2099 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2100 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2103 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2104 left_edge[i] - shift_dq + (-mid_min),
2105 right_edge[i] + shift_dq - (-mid_min));
2106 /* To determine values for export structures */
2107 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2108 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2110 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2111 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2114 final_dqs = new_dqs;
2115 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2116 final_dqs_en = start_dqs_en - mid_min;
2119 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2120 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2121 scc_mgr_load_dqs(read_group);
2125 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2126 scc_mgr_load_dqs(read_group);
2127 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2128 dqs_margin=%d", __func__, __LINE__,
2129 dq_margin, dqs_margin);
2132 * Do not remove this line as it makes sure all of our decisions
2133 * have been applied. Apply the update bit.
2135 writel(0, &sdr_scc_mgr->update);
2137 return (dq_margin >= 0) && (dqs_margin >= 0);
2141 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2142 * @rw_group: Read/Write Group
2143 * @phase: DQ/DQS phase
2145 * Because initially no communication ca be reliably performed with the memory
2146 * device, the sequencer uses a guaranteed write mechanism to write data into
2147 * the memory device.
2149 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2154 /* Set a particular DQ/DQS phase. */
2155 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2157 debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2158 __func__, __LINE__, rw_group, phase);
2161 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2162 * Load up the patterns used by read calibration using the
2163 * current DQDQS phase.
2165 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2167 if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2171 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2172 * Back-to-Back reads of the patterns used for calibration.
2174 ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2176 debug_cond(DLEVEL == 1,
2177 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2178 __func__, __LINE__, rw_group, phase);
2183 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2184 * @rw_group: Read/Write Group
2185 * @test_bgn: Rank at which the test begins
2187 * DQS enable calibration ensures reliable capture of the DQ signal without
2188 * glitches on the DQS line.
2190 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2194 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2195 * DQS and DQS Eanble Signal Relationships.
2198 /* We start at zero, so have one less dq to devide among */
2199 const u32 delay_step = IO_IO_IN_DELAY_MAX /
2200 (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
2204 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2206 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2207 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2208 r += NUM_RANKS_PER_SHADOW_REG) {
2209 for (i = 0, p = test_bgn, d = 0;
2210 i < RW_MGR_MEM_DQ_PER_READ_DQS;
2211 i++, p++, d += delay_step) {
2212 debug_cond(DLEVEL == 1,
2213 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2214 __func__, __LINE__, rw_group, r, i, p, d);
2216 scc_mgr_set_dq_in_delay(p, d);
2220 writel(0, &sdr_scc_mgr->update);
2224 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2225 * dq_in_delay values
2227 found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2229 debug_cond(DLEVEL == 1,
2230 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2231 __func__, __LINE__, rw_group, found);
2233 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2234 r += NUM_RANKS_PER_SHADOW_REG) {
2235 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2236 writel(0, &sdr_scc_mgr->update);
2247 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2248 * @rw_group: Read/Write Group
2249 * @test_bgn: Rank at which the test begins
2250 * @use_read_test: Perform a read test
2251 * @update_fom: Update FOM
2253 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2257 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2258 const int use_read_test,
2259 const int update_fom)
2262 int ret, grp_calibrated;
2266 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2267 * Read per-bit deskew can be done on a per shadow register basis.
2270 for (rank_bgn = 0, sr = 0;
2271 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2272 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2273 /* Check if this set of ranks should be skipped entirely. */
2274 if (param->skip_shadow_regs[sr])
2277 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2287 if (!grp_calibrated)
2294 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2295 * @rw_group: Read/Write Group
2296 * @test_bgn: Rank at which the test begins
2298 * Stage 1: Calibrate the read valid prediction FIFO.
2300 * This function implements UniPHY calibration Stage 1, as explained in
2301 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2303 * - read valid prediction will consist of finding:
2304 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2305 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2306 * - we also do a per-bit deskew on the DQ lines.
2308 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2311 uint32_t dtaps_per_ptap;
2312 uint32_t failed_substage;
2316 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2318 /* Update info for sims */
2319 reg_file_set_group(rw_group);
2320 reg_file_set_stage(CAL_STAGE_VFIFO);
2321 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2323 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2325 /* USER Determine number of delay taps for each phase tap. */
2326 dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2327 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2329 for (d = 0; d <= dtaps_per_ptap; d += 2) {
2331 * In RLDRAMX we may be messing the delay of pins in
2332 * the same write rw_group but outside of the current read
2333 * the rw_group, but that's ok because we haven't calibrated
2337 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2341 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2342 /* 1) Guaranteed Write */
2343 ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2347 /* 2) DQS Enable Calibration */
2348 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2351 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2355 /* 3) Centering DQ/DQS */
2357 * If doing read after write calibration, do not update
2358 * FOM now. Do it then.
2360 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2363 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2372 /* Calibration Stage 1 failed. */
2373 set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2376 /* Calibration Stage 1 completed OK. */
2379 * Reset the delay chains back to zero if they have moved > 1
2380 * (check for > 1 because loop will increase d even when pass in
2384 scc_mgr_zero_group(rw_group, 1);
2389 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2390 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2393 uint32_t rank_bgn, sr;
2394 uint32_t grp_calibrated;
2395 uint32_t write_group;
2397 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2399 /* update info for sims */
2401 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2402 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2404 write_group = read_group;
2406 /* update info for sims */
2407 reg_file_set_group(read_group);
2410 /* Read per-bit deskew can be done on a per shadow register basis */
2411 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2412 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2413 /* Determine if this set of ranks should be skipped entirely */
2414 if (!param->skip_shadow_regs[sr]) {
2415 /* This is the last calibration round, update FOM here */
2416 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2427 if (grp_calibrated == 0) {
2428 set_failing_group_stage(write_group,
2429 CAL_STAGE_VFIFO_AFTER_WRITES,
2430 CAL_SUBSTAGE_VFIFO_CENTER);
2437 /* Calibrate LFIFO to find smallest read latency */
2438 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2443 debug("%s:%d\n", __func__, __LINE__);
2445 /* update info for sims */
2446 reg_file_set_stage(CAL_STAGE_LFIFO);
2447 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2449 /* Load up the patterns used by read calibration for all ranks */
2450 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2454 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2455 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2456 __func__, __LINE__, gbl->curr_read_lat);
2458 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2466 /* reduce read latency and see if things are working */
2468 gbl->curr_read_lat--;
2469 } while (gbl->curr_read_lat > 0);
2471 /* reset the fifos to get pointers to known state */
2473 writel(0, &phy_mgr_cmd->fifo_reset);
2476 /* add a fudge factor to the read latency that was determined */
2477 gbl->curr_read_lat += 2;
2478 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2479 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2480 read_lat=%u\n", __func__, __LINE__,
2481 gbl->curr_read_lat);
2484 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2485 CAL_SUBSTAGE_READ_LATENCY);
2487 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2488 read_lat=%u\n", __func__, __LINE__,
2489 gbl->curr_read_lat);
2495 * issue write test command.
2496 * two variants are provided. one that just tests a write pattern and
2497 * another that tests datamask functionality.
2499 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2502 uint32_t mcc_instruction;
2503 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2504 ENABLE_SUPER_QUICK_CALIBRATION);
2505 uint32_t rw_wl_nop_cycles;
2509 * Set counter and jump addresses for the right
2510 * number of NOP cycles.
2511 * The number of supported NOP cycles can range from -1 to infinity
2512 * Three different cases are handled:
2514 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2515 * mechanism will be used to insert the right number of NOPs
2517 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2518 * issuing the write command will jump straight to the
2519 * micro-instruction that turns on DQS (for DDRx), or outputs write
2520 * data (for RLD), skipping
2521 * the NOP micro-instruction all together
2523 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2524 * turned on in the same micro-instruction that issues the write
2525 * command. Then we need
2526 * to directly jump to the micro-instruction that sends out the data
2528 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2529 * (2 and 3). One jump-counter (0) is used to perform multiple
2530 * write-read operations.
2531 * one counter left to issue this command in "multiple-group" mode
2534 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2536 if (rw_wl_nop_cycles == -1) {
2538 * CNTR 2 - We want to execute the special write operation that
2539 * turns on DQS right away and then skip directly to the
2540 * instruction that sends out the data. We set the counter to a
2541 * large number so that the jump is always taken.
2543 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2545 /* CNTR 3 - Not used */
2547 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2548 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2549 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2550 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2551 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2553 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2554 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2555 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2556 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2557 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2559 } else if (rw_wl_nop_cycles == 0) {
2561 * CNTR 2 - We want to skip the NOP operation and go straight
2562 * to the DQS enable instruction. We set the counter to a large
2563 * number so that the jump is always taken.
2565 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2567 /* CNTR 3 - Not used */
2569 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2570 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2571 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2573 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2574 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2575 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2579 * CNTR 2 - In this case we want to execute the next instruction
2580 * and NOT take the jump. So we set the counter to 0. The jump
2581 * address doesn't count.
2583 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2584 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2587 * CNTR 3 - Set the nop counter to the number of cycles we
2588 * need to loop for, minus 1.
2590 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2592 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2593 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2594 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2596 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2597 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2598 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2602 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2603 RW_MGR_RESET_READ_DATAPATH_OFFSET);
2605 if (quick_write_mode)
2606 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2608 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2610 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2613 * CNTR 1 - This is used to ensure enough time elapses
2614 * for read data to come back.
2616 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2619 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2620 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2622 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2623 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2626 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2627 writel(mcc_instruction, addr + (group << 2));
2630 /* Test writes, can check for a single bit pass or multiple bit pass */
2631 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2632 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2633 uint32_t *bit_chk, uint32_t all_ranks)
2636 uint32_t correct_mask_vg;
2637 uint32_t tmp_bit_chk;
2639 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2640 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2641 uint32_t addr_rw_mgr;
2642 uint32_t base_rw_mgr;
2644 *bit_chk = param->write_correct_mask;
2645 correct_mask_vg = param->write_correct_mask_vg;
2647 for (r = rank_bgn; r < rank_end; r++) {
2648 if (param->skip_ranks[r]) {
2649 /* request to skip the rank */
2654 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2657 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2658 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2659 /* reset the fifos to get pointers to known state */
2660 writel(0, &phy_mgr_cmd->fifo_reset);
2662 tmp_bit_chk = tmp_bit_chk <<
2663 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2664 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2665 rw_mgr_mem_calibrate_write_test_issue(write_group *
2666 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2669 base_rw_mgr = readl(addr_rw_mgr);
2670 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2674 *bit_chk &= tmp_bit_chk;
2678 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2679 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2680 %u => %lu", write_group, use_dm,
2681 *bit_chk, param->write_correct_mask,
2682 (long unsigned int)(*bit_chk ==
2683 param->write_correct_mask));
2684 return *bit_chk == param->write_correct_mask;
2686 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2687 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2688 write_group, use_dm, *bit_chk);
2689 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2690 (long unsigned int)(*bit_chk != 0));
2691 return *bit_chk != 0x00;
2696 * center all windows. do per-bit-deskew to possibly increase size of
2699 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2700 uint32_t write_group, uint32_t test_bgn)
2702 uint32_t i, p, min_index;
2705 * Store these as signed since there are comparisons with
2709 uint32_t sticky_bit_chk;
2710 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2711 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2713 int32_t mid_min, orig_mid_min;
2714 int32_t new_dqs, start_dqs, shift_dq;
2715 int32_t dq_margin, dqs_margin, dm_margin;
2717 uint32_t temp_dq_out1_delay;
2720 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2724 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2725 start_dqs = readl(addr +
2726 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2728 /* per-bit deskew */
2731 * set the left and right edge of each bit to an illegal value
2732 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2735 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2736 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2737 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2740 /* Search for the left edge of the window for each bit */
2741 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2742 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2744 writel(0, &sdr_scc_mgr->update);
2747 * Stop searching when the read test doesn't pass AND when
2748 * we've seen a passing read on every bit.
2750 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2751 0, PASS_ONE_BIT, &bit_chk, 0);
2752 sticky_bit_chk = sticky_bit_chk | bit_chk;
2753 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2754 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2755 == %u && %u [bit_chk= %u ]\n",
2756 d, sticky_bit_chk, param->write_correct_mask,
2762 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2765 * Remember a passing test as the
2771 * If a left edge has not been seen
2772 * yet, then a future passing test will
2773 * mark this edge as the right edge.
2776 IO_IO_OUT1_DELAY_MAX + 1) {
2777 right_edge[i] = -(d + 1);
2780 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2781 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2782 (int)(bit_chk & 1), i, left_edge[i]);
2783 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2785 bit_chk = bit_chk >> 1;
2790 /* Reset DQ delay chains to 0 */
2791 scc_mgr_apply_group_dq_out1_delay(0);
2793 for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2794 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2795 %d right_edge[%u]: %d\n", __func__, __LINE__,
2796 i, left_edge[i], i, right_edge[i]);
2799 * Check for cases where we haven't found the left edge,
2800 * which makes our assignment of the the right edge invalid.
2801 * Reset it to the illegal value.
2803 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2804 (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2805 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2806 debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2807 right_edge[%u]: %d\n", __func__, __LINE__,
2812 * Reset sticky bit (except for bits where we have
2813 * seen the left edge).
2815 sticky_bit_chk = sticky_bit_chk << 1;
2816 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2817 sticky_bit_chk = sticky_bit_chk | 1;
2823 /* Search for the right edge of the window for each bit */
2824 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2825 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2828 writel(0, &sdr_scc_mgr->update);
2831 * Stop searching when the read test doesn't pass AND when
2832 * we've seen a passing read on every bit.
2834 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2835 0, PASS_ONE_BIT, &bit_chk, 0);
2837 sticky_bit_chk = sticky_bit_chk | bit_chk;
2838 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2840 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2841 %u && %u\n", d, sticky_bit_chk,
2842 param->write_correct_mask, stop);
2846 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2848 /* d = 0 failed, but it passed when
2849 testing the left edge, so it must be
2850 marginal, set it to -1 */
2851 if (right_edge[i] ==
2852 IO_IO_OUT1_DELAY_MAX + 1 &&
2854 IO_IO_OUT1_DELAY_MAX + 1) {
2861 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2864 * Remember a passing test as
2871 * If a right edge has not
2872 * been seen yet, then a future
2873 * passing test will mark this
2874 * edge as the left edge.
2876 if (right_edge[i] ==
2877 IO_IO_OUT1_DELAY_MAX + 1)
2878 left_edge[i] = -(d + 1);
2881 * d = 0 failed, but it passed
2882 * when testing the left edge,
2883 * so it must be marginal, set
2886 if (right_edge[i] ==
2887 IO_IO_OUT1_DELAY_MAX + 1 &&
2889 IO_IO_OUT1_DELAY_MAX + 1)
2892 * If a right edge has not been
2893 * seen yet, then a future
2894 * passing test will mark this
2895 * edge as the left edge.
2897 else if (right_edge[i] ==
2898 IO_IO_OUT1_DELAY_MAX +
2900 left_edge[i] = -(d + 1);
2903 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2904 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2905 (int)(bit_chk & 1), i, left_edge[i]);
2906 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2908 bit_chk = bit_chk >> 1;
2913 /* Check that all bits have a window */
2914 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2915 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2916 %d right_edge[%u]: %d", __func__, __LINE__,
2917 i, left_edge[i], i, right_edge[i]);
2918 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2919 (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2920 set_failing_group_stage(test_bgn + i,
2922 CAL_SUBSTAGE_WRITES_CENTER);
2927 /* Find middle of window for each DQ bit */
2928 mid_min = left_edge[0] - right_edge[0];
2930 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2931 mid = left_edge[i] - right_edge[i];
2932 if (mid < mid_min) {
2939 * -mid_min/2 represents the amount that we need to move DQS.
2940 * If mid_min is odd and positive we'll need to add one to
2941 * make sure the rounding in further calculations is correct
2942 * (always bias to the right), so just add 1 for all positive values.
2946 mid_min = mid_min / 2;
2947 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2950 /* Determine the amount we can change DQS (which is -mid_min) */
2951 orig_mid_min = mid_min;
2952 new_dqs = start_dqs;
2954 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2955 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2956 /* Initialize data for export structures */
2957 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2958 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2960 /* add delay to bring centre of all DQ windows to the same "level" */
2961 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2962 /* Use values before divide by 2 to reduce round off error */
2963 shift_dq = (left_edge[i] - right_edge[i] -
2964 (left_edge[min_index] - right_edge[min_index]))/2 +
2965 (orig_mid_min - mid_min);
2967 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2968 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2970 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2971 temp_dq_out1_delay = readl(addr + (i << 2));
2972 if (shift_dq + (int32_t)temp_dq_out1_delay >
2973 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2974 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2975 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2976 shift_dq = -(int32_t)temp_dq_out1_delay;
2978 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2980 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2983 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2984 left_edge[i] - shift_dq + (-mid_min),
2985 right_edge[i] + shift_dq - (-mid_min));
2986 /* To determine values for export structures */
2987 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2988 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2990 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2991 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2995 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2996 writel(0, &sdr_scc_mgr->update);
2999 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3002 * set the left and right edge of each bit to an illegal value,
3003 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
3005 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3006 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3007 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3008 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3009 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
3010 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
3011 int32_t win_best = 0;
3013 /* Search for the/part of the window with DM shift */
3014 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
3015 scc_mgr_apply_group_dm_out1_delay(d);
3016 writel(0, &sdr_scc_mgr->update);
3018 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3019 PASS_ALL_BITS, &bit_chk,
3021 /* USE Set current end of the window */
3024 * If a starting edge of our window has not been seen
3025 * this is our current start of the DM window.
3027 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3031 * If current window is bigger than best seen.
3032 * Set best seen to be current window.
3034 if ((end_curr-bgn_curr+1) > win_best) {
3035 win_best = end_curr-bgn_curr+1;
3036 bgn_best = bgn_curr;
3037 end_best = end_curr;
3040 /* We just saw a failing test. Reset temp edge */
3041 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3042 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3047 /* Reset DM delay chains to 0 */
3048 scc_mgr_apply_group_dm_out1_delay(0);
3051 * Check to see if the current window nudges up aganist 0 delay.
3052 * If so we need to continue the search by shifting DQS otherwise DQS
3053 * search begins as a new search. */
3054 if (end_curr != 0) {
3055 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3056 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3059 /* Search for the/part of the window with DQS shifts */
3060 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3062 * Note: This only shifts DQS, so are we limiting ourselve to
3063 * width of DQ unnecessarily.
3065 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3068 writel(0, &sdr_scc_mgr->update);
3069 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3070 PASS_ALL_BITS, &bit_chk,
3072 /* USE Set current end of the window */
3075 * If a beginning edge of our window has not been seen
3076 * this is our current begin of the DM window.
3078 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3082 * If current window is bigger than best seen. Set best
3083 * seen to be current window.
3085 if ((end_curr-bgn_curr+1) > win_best) {
3086 win_best = end_curr-bgn_curr+1;
3087 bgn_best = bgn_curr;
3088 end_best = end_curr;
3091 /* We just saw a failing test. Reset temp edge */
3092 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3093 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3095 /* Early exit optimization: if ther remaining delay
3096 chain space is less than already seen largest window
3099 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3105 /* assign left and right edge for cal and reporting; */
3106 left_edge[0] = -1*bgn_best;
3107 right_edge[0] = end_best;
3109 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3110 __LINE__, left_edge[0], right_edge[0]);
3112 /* Move DQS (back to orig) */
3113 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3117 /* Find middle of window for the DM bit */
3118 mid = (left_edge[0] - right_edge[0]) / 2;
3120 /* only move right, since we are not moving DQS/DQ */
3124 /* dm_marign should fail if we never find a window */
3128 dm_margin = left_edge[0] - mid;
3130 scc_mgr_apply_group_dm_out1_delay(mid);
3131 writel(0, &sdr_scc_mgr->update);
3133 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3134 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3135 right_edge[0], mid, dm_margin);
3137 gbl->fom_out += dq_margin + dqs_margin;
3139 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3140 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3141 dq_margin, dqs_margin, dm_margin);
3144 * Do not remove this line as it makes sure all of our
3145 * decisions have been applied.
3147 writel(0, &sdr_scc_mgr->update);
3148 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3151 /* calibrate the write operations */
3152 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3155 /* update info for sims */
3156 debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3158 reg_file_set_stage(CAL_STAGE_WRITES);
3159 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3161 reg_file_set_group(g);
3163 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3164 set_failing_group_stage(g, CAL_STAGE_WRITES,
3165 CAL_SUBSTAGE_WRITES_CENTER);
3173 * mem_precharge_and_activate() - Precharge all banks and activate
3175 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3177 static void mem_precharge_and_activate(void)
3181 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3182 /* Test if the rank should be skipped. */
3183 if (param->skip_ranks[r])
3187 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3189 /* Precharge all banks. */
3190 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3191 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3193 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3194 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3195 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3197 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3198 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3199 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3201 /* Activate rows. */
3202 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3203 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3208 * mem_init_latency() - Configure memory RLAT and WLAT settings
3210 * Configure memory RLAT and WLAT parameters.
3212 static void mem_init_latency(void)
3215 * For AV/CV, LFIFO is hardened and always runs at full rate
3216 * so max latency in AFI clocks, used here, is correspondingly
3219 const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3222 debug("%s:%d\n", __func__, __LINE__);
3225 * Read in write latency.
3226 * WL for Hard PHY does not include additive latency.
3228 wlat = readl(&data_mgr->t_wl_add);
3229 wlat += readl(&data_mgr->mem_t_add);
3231 gbl->rw_wl_nop_cycles = wlat - 1;
3233 /* Read in readl latency. */
3234 rlat = readl(&data_mgr->t_rl_add);
3236 /* Set a pretty high read latency initially. */
3237 gbl->curr_read_lat = rlat + 16;
3238 if (gbl->curr_read_lat > max_latency)
3239 gbl->curr_read_lat = max_latency;
3241 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3243 /* Advertise write latency. */
3244 writel(wlat, &phy_mgr_cfg->afi_wlat);
3248 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3250 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3252 static void mem_skip_calibrate(void)
3254 uint32_t vfifo_offset;
3257 debug("%s:%d\n", __func__, __LINE__);
3258 /* Need to update every shadow register set used by the interface */
3259 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3260 r += NUM_RANKS_PER_SHADOW_REG) {
3262 * Set output phase alignment settings appropriate for
3265 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3266 scc_mgr_set_dqs_en_phase(i, 0);
3267 #if IO_DLL_CHAIN_LENGTH == 6
3268 scc_mgr_set_dqdqs_output_phase(i, 6);
3270 scc_mgr_set_dqdqs_output_phase(i, 7);
3275 * Write data arrives to the I/O two cycles before write
3276 * latency is reached (720 deg).
3277 * -> due to bit-slip in a/c bus
3278 * -> to allow board skew where dqs is longer than ck
3279 * -> how often can this happen!?
3280 * -> can claim back some ptaps for high freq
3281 * support if we can relax this, but i digress...
3283 * The write_clk leads mem_ck by 90 deg
3284 * The minimum ptap of the OPA is 180 deg
3285 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3286 * The write_clk is always delayed by 2 ptaps
3288 * Hence, to make DQS aligned to CK, we need to delay
3290 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3292 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3293 * gives us the number of ptaps, which simplies to:
3295 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3297 scc_mgr_set_dqdqs_output_phase(i,
3298 1.25 * IO_DLL_CHAIN_LENGTH - 2);
3300 writel(0xff, &sdr_scc_mgr->dqs_ena);
3301 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3303 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3304 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3305 SCC_MGR_GROUP_COUNTER_OFFSET);
3307 writel(0xff, &sdr_scc_mgr->dq_ena);
3308 writel(0xff, &sdr_scc_mgr->dm_ena);
3309 writel(0, &sdr_scc_mgr->update);
3312 /* Compensate for simulation model behaviour */
3313 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3314 scc_mgr_set_dqs_bus_in_delay(i, 10);
3315 scc_mgr_load_dqs(i);
3317 writel(0, &sdr_scc_mgr->update);
3320 * ArriaV has hard FIFOs that can only be initialized by incrementing
3323 vfifo_offset = CALIB_VFIFO_OFFSET;
3324 for (j = 0; j < vfifo_offset; j++)
3325 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3326 writel(0, &phy_mgr_cmd->fifo_reset);
3329 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3330 * setting from generation-time constant.
3332 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3333 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3337 * mem_calibrate() - Memory calibration entry point.
3339 * Perform memory calibration.
3341 static uint32_t mem_calibrate(void)
3344 uint32_t rank_bgn, sr;
3345 uint32_t write_group, write_test_bgn;
3346 uint32_t read_group, read_test_bgn;
3347 uint32_t run_groups, current_run;
3348 uint32_t failing_groups = 0;
3349 uint32_t group_failed = 0;
3351 const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3352 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3354 debug("%s:%d\n", __func__, __LINE__);
3356 /* Initialize the data settings */
3357 gbl->error_substage = CAL_SUBSTAGE_NIL;
3358 gbl->error_stage = CAL_STAGE_NIL;
3359 gbl->error_group = 0xff;
3363 /* Initialize WLAT and RLAT. */
3366 /* Initialize bit slips. */
3367 mem_precharge_and_activate();
3369 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3370 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3371 SCC_MGR_GROUP_COUNTER_OFFSET);
3372 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3374 scc_mgr_set_hhp_extras();
3376 scc_set_bypass_mode(i);
3379 /* Calibration is skipped. */
3380 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3382 * Set VFIFO and LFIFO to instant-on settings in skip
3385 mem_skip_calibrate();
3388 * Do not remove this line as it makes sure all of our
3389 * decisions have been applied.
3391 writel(0, &sdr_scc_mgr->update);
3395 /* Calibration is not skipped. */
3396 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3398 * Zero all delay chain/phase settings for all
3399 * groups and all shadow register sets.
3403 run_groups = ~param->skip_groups;
3405 for (write_group = 0, write_test_bgn = 0; write_group
3406 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3407 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3409 /* Initialize the group failure */
3412 current_run = run_groups & ((1 <<
3413 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3414 run_groups = run_groups >>
3415 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3417 if (current_run == 0)
3420 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3421 SCC_MGR_GROUP_COUNTER_OFFSET);
3422 scc_mgr_zero_group(write_group, 0);
3424 for (read_group = write_group * rwdqs_ratio,
3426 read_group < (write_group + 1) * rwdqs_ratio;
3428 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3429 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3432 /* Calibrate the VFIFO */
3433 if (rw_mgr_mem_calibrate_vfifo(read_group,
3437 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3440 /* The group failed, we're done. */
3444 /* Calibrate the output side */
3445 for (rank_bgn = 0, sr = 0;
3446 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3447 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3448 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3451 /* Not needed in quick mode! */
3452 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3456 * Determine if this set of ranks
3457 * should be skipped entirely.
3459 if (param->skip_shadow_regs[sr])
3462 /* Calibrate WRITEs */
3463 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3464 write_group, write_test_bgn))
3468 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3472 /* Some group failed, we're done. */
3476 for (read_group = write_group * rwdqs_ratio,
3478 read_group < (write_group + 1) * rwdqs_ratio;
3480 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3481 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3484 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3488 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3491 /* The group failed, we're done. */
3495 /* No group failed, continue as usual. */
3498 grp_failed: /* A group failed, increment the counter. */
3503 * USER If there are any failing groups then report
3506 if (failing_groups != 0)
3509 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3513 * If we're skipping groups as part of debug,
3514 * don't calibrate LFIFO.
3516 if (param->skip_groups != 0)
3519 /* Calibrate the LFIFO */
3520 if (!rw_mgr_mem_calibrate_lfifo())
3525 * Do not remove this line as it makes sure all of our decisions
3526 * have been applied.
3528 writel(0, &sdr_scc_mgr->update);
3533 * run_mem_calibrate() - Perform memory calibration
3535 * This function triggers the entire memory calibration procedure.
3537 static int run_mem_calibrate(void)
3541 debug("%s:%d\n", __func__, __LINE__);
3543 /* Reset pass/fail status shown on afi_cal_success/fail */
3544 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3546 /* Stop tracking manager. */
3547 clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3549 phy_mgr_initialize();
3550 rw_mgr_mem_initialize();
3552 /* Perform the actual memory calibration. */
3553 pass = mem_calibrate();
3555 mem_precharge_and_activate();
3556 writel(0, &phy_mgr_cmd->fifo_reset);
3559 rw_mgr_mem_handoff();
3561 * In Hard PHY this is a 2-bit control:
3563 * 1: DDIO Mux Select
3565 writel(0x2, &phy_mgr_cfg->mux_sel);
3567 /* Start tracking manager. */
3568 setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3574 * debug_mem_calibrate() - Report result of memory calibration
3575 * @pass: Value indicating whether calibration passed or failed
3577 * This function reports the results of the memory calibration
3578 * and writes debug information into the register file.
3580 static void debug_mem_calibrate(int pass)
3582 uint32_t debug_info;
3585 printf("%s: CALIBRATION PASSED\n", __FILE__);
3590 if (gbl->fom_in > 0xff)
3593 if (gbl->fom_out > 0xff)
3594 gbl->fom_out = 0xff;
3596 /* Update the FOM in the register file */
3597 debug_info = gbl->fom_in;
3598 debug_info |= gbl->fom_out << 8;
3599 writel(debug_info, &sdr_reg_file->fom);
3601 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3602 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3604 printf("%s: CALIBRATION FAILED\n", __FILE__);
3606 debug_info = gbl->error_stage;
3607 debug_info |= gbl->error_substage << 8;
3608 debug_info |= gbl->error_group << 16;
3610 writel(debug_info, &sdr_reg_file->failing_stage);
3611 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3612 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3614 /* Update the failing group/stage in the register file */
3615 debug_info = gbl->error_stage;
3616 debug_info |= gbl->error_substage << 8;
3617 debug_info |= gbl->error_group << 16;
3618 writel(debug_info, &sdr_reg_file->failing_stage);
3621 printf("%s: Calibration complete\n", __FILE__);
3625 * hc_initialize_rom_data() - Initialize ROM data
3627 * Initialize ROM data.
3629 static void hc_initialize_rom_data(void)
3633 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3634 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3635 writel(inst_rom_init[i], addr + (i << 2));
3637 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3638 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3639 writel(ac_rom_init[i], addr + (i << 2));
3643 * initialize_reg_file() - Initialize SDR register file
3645 * Initialize SDR register file.
3647 static void initialize_reg_file(void)
3649 /* Initialize the register file with the correct data */
3650 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3651 writel(0, &sdr_reg_file->debug_data_addr);
3652 writel(0, &sdr_reg_file->cur_stage);
3653 writel(0, &sdr_reg_file->fom);
3654 writel(0, &sdr_reg_file->failing_stage);
3655 writel(0, &sdr_reg_file->debug1);
3656 writel(0, &sdr_reg_file->debug2);
3660 * initialize_hps_phy() - Initialize HPS PHY
3662 * Initialize HPS PHY.
3664 static void initialize_hps_phy(void)
3668 * Tracking also gets configured here because it's in the
3671 uint32_t trk_sample_count = 7500;
3672 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3674 * Format is number of outer loops in the 16 MSB, sample
3679 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3680 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3681 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3682 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3683 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3684 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3686 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3687 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3689 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3690 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3692 writel(reg, &sdr_ctrl->phy_ctrl0);
3695 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3697 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3698 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3699 trk_long_idle_sample_count);
3700 writel(reg, &sdr_ctrl->phy_ctrl1);
3703 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3704 trk_long_idle_sample_count >>
3705 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3706 writel(reg, &sdr_ctrl->phy_ctrl2);
3710 * initialize_tracking() - Initialize tracking
3712 * Initialize the register file with usable initial data.
3714 static void initialize_tracking(void)
3717 * Initialize the register file with the correct data.
3718 * Compute usable version of value in case we skip full
3719 * computation later.
3721 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3722 &sdr_reg_file->dtaps_per_ptap);
3724 /* trk_sample_count */
3725 writel(7500, &sdr_reg_file->trk_sample_count);
3727 /* longidle outer loop [15:0] */
3728 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3731 * longidle sample count [31:24]
3732 * trfc, worst case of 933Mhz 4Gb [23:16]
3733 * trcd, worst case [15:8]
3736 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3737 &sdr_reg_file->delays);
3740 writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3741 (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3742 &sdr_reg_file->trk_rw_mgr_addr);
3744 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3745 &sdr_reg_file->trk_read_dqs_width);
3748 writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3749 &sdr_reg_file->trk_rfsh);
3752 int sdram_calibration_full(void)
3754 struct param_type my_param;
3755 struct gbl_type my_gbl;
3758 memset(&my_param, 0, sizeof(my_param));
3759 memset(&my_gbl, 0, sizeof(my_gbl));
3764 /* Set the calibration enabled by default */
3765 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3767 * Only sweep all groups (regardless of fail state) by default
3768 * Set enabled read test by default.
3770 #if DISABLE_GUARANTEED_READ
3771 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3773 /* Initialize the register file */
3774 initialize_reg_file();
3776 /* Initialize any PHY CSR */
3777 initialize_hps_phy();
3779 scc_mgr_initialize();
3781 initialize_tracking();
3783 printf("%s: Preparing to start memory calibration\n", __FILE__);
3785 debug("%s:%d\n", __func__, __LINE__);
3786 debug_cond(DLEVEL == 1,
3787 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3788 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3789 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3790 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3791 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3792 debug_cond(DLEVEL == 1,
3793 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3794 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3795 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3796 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3797 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3798 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3799 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3800 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3801 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3802 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3803 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3804 IO_IO_OUT2_DELAY_MAX);
3805 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3806 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3808 hc_initialize_rom_data();
3810 /* update info for sims */
3811 reg_file_set_stage(CAL_STAGE_NIL);
3812 reg_file_set_group(0);
3815 * Load global needed for those actions that require
3816 * some dynamic calibration support.
3818 dyn_calib_steps = STATIC_CALIB_STEPS;
3820 * Load global to allow dynamic selection of delay loop settings
3821 * based on calibration mode.
3823 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3824 skip_delay_mask = 0xff;
3826 skip_delay_mask = 0x0;
3828 pass = run_mem_calibrate();
3829 debug_mem_calibrate(pass);