git.sur5r.net Git - u-boot/blob - drivers/ddr/altera/sequencer.c

   1 /*
   2  * Copyright Altera Corporation (C) 2012-2015
   3  *
   4  * SPDX-License-Identifier:    BSD-3-Clause
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/sdram.h>
  10 #include "sequencer.h"
  11 #include "sequencer_auto.h"
  12 #include "sequencer_auto_ac_init.h"
  13 #include "sequencer_auto_inst_init.h"
  14 #include "sequencer_defines.h"
  15
  16 static void scc_mgr_load_dqs_for_write_group(uint32_t write_group);
  17
  18 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
  19         (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
  20
  21 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
  22         (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
  23
  24 static struct socfpga_sdr_reg_file *sdr_reg_file =
  25         (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
  26
  27 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
  28         (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
  29
  30 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
  31         (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
  32
  33 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
  34         (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
  35
  36 static struct socfpga_data_mgr *data_mgr =
  37         (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
  38
  39 static struct socfpga_sdr_ctrl *sdr_ctrl =
  40         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  41
  42 #define DELTA_D         1
  43
  44 /*
  45  * In order to reduce ROM size, most of the selectable calibration steps are
  46  * decided at compile time based on the user's calibration mode selection,
  47  * as captured by the STATIC_CALIB_STEPS selection below.
  48  *
  49  * However, to support simulation-time selection of fast simulation mode, where
  50  * we skip everything except the bare minimum, we need a few of the steps to
  51  * be dynamic.  In those cases, we either use the DYNAMIC_CALIB_STEPS for the
  52  * check, which is based on the rtl-supplied value, or we dynamically compute
  53  * the value to use based on the dynamically-chosen calibration mode
  54  */
  55
  56 #define DLEVEL 0
  57 #define STATIC_IN_RTL_SIM 0
  58 #define STATIC_SKIP_DELAY_LOOPS 0
  59
  60 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
  61         STATIC_SKIP_DELAY_LOOPS)
  62
  63 /* calibration steps requested by the rtl */
  64 uint16_t dyn_calib_steps;
  65
  66 /*
  67  * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
  68  * instead of static, we use boolean logic to select between
  69  * non-skip and skip values
  70  *
  71  * The mask is set to include all bits when not-skipping, but is
  72  * zero when skipping
  73  */
  74
  75 uint16_t skip_delay_mask;       /* mask off bits when skipping/not-skipping */
  76
  77 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
  78         ((non_skip_value) & skip_delay_mask)
  79
  80 struct gbl_type *gbl;
  81 struct param_type *param;
  82 uint32_t curr_shadow_reg;
  83
  84 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
  85         uint32_t write_group, uint32_t use_dm,
  86         uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
  87
  88 static void set_failing_group_stage(uint32_t group, uint32_t stage,
  89         uint32_t substage)
  90 {
  91         /*
  92          * Only set the global stage if there was not been any other
  93          * failing group
  94          */
  95         if (gbl->error_stage == CAL_STAGE_NIL)  {
  96                 gbl->error_substage = substage;
  97                 gbl->error_stage = stage;
  98                 gbl->error_group = group;
  99         }
 100 }
 101
 102 static void reg_file_set_group(u16 set_group)
 103 {
 104         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
 105 }
 106
 107 static void reg_file_set_stage(u8 set_stage)
 108 {
 109         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
 110 }
 111
 112 static void reg_file_set_sub_stage(u8 set_sub_stage)
 113 {
 114         set_sub_stage &= 0xff;
 115         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
 116 }
 117
 118 static void initialize(void)
 119 {
 120         debug("%s:%d\n", __func__, __LINE__);
 121         /* USER calibration has control over path to memory */
 122         /*
 123          * In Hard PHY this is a 2-bit control:
 124          * 0: AFI Mux Select
 125          * 1: DDIO Mux Select
 126          */
 127         writel(0x3, &phy_mgr_cfg->mux_sel);
 128
 129         /* USER memory clock is not stable we begin initialization  */
 130         writel(0, &phy_mgr_cfg->reset_mem_stbl);
 131
 132         /* USER calibration status all set to zero */
 133         writel(0, &phy_mgr_cfg->cal_status);
 134
 135         writel(0, &phy_mgr_cfg->cal_debug_info);
 136
 137         if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
 138                 param->read_correct_mask_vg  = ((uint32_t)1 <<
 139                         (RW_MGR_MEM_DQ_PER_READ_DQS /
 140                         RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
 141                 param->write_correct_mask_vg = ((uint32_t)1 <<
 142                         (RW_MGR_MEM_DQ_PER_READ_DQS /
 143                         RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
 144                 param->read_correct_mask     = ((uint32_t)1 <<
 145                         RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
 146                 param->write_correct_mask    = ((uint32_t)1 <<
 147                         RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
 148                 param->dm_correct_mask       = ((uint32_t)1 <<
 149                         (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH))
 150                         - 1;
 151         }
 152 }
 153
 154 static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
 155 {
 156         uint32_t odt_mask_0 = 0;
 157         uint32_t odt_mask_1 = 0;
 158         uint32_t cs_and_odt_mask;
 159
 160         if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
 161                 if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
 162                         /*
 163                          * 1 Rank
 164                          * Read: ODT = 0
 165                          * Write: ODT = 1
 166                          */
 167                         odt_mask_0 = 0x0;
 168                         odt_mask_1 = 0x1;
 169                 } else if (RW_MGR_MEM_NUMBER_OF_RANKS == 2) {
 170                         /* 2 Ranks */
 171                         if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
 172                                 /* - Dual-Slot , Single-Rank
 173                                  * (1 chip-select per DIMM)
 174                                  * OR
 175                                  * - RDIMM, 4 total CS (2 CS per DIMM)
 176                                  * means 2 DIMM
 177                                  * Since MEM_NUMBER_OF_RANKS is 2 they are
 178                                  * both single rank
 179                                  * with 2 CS each (special for RDIMM)
 180                                  * Read: Turn on ODT on the opposite rank
 181                                  * Write: Turn on ODT on all ranks
 182                                  */
 183                                 odt_mask_0 = 0x3 & ~(1 << rank);
 184                                 odt_mask_1 = 0x3;
 185                         } else {
 186                                 /*
 187                                  * USER - Single-Slot , Dual-rank DIMMs
 188                                  * (2 chip-selects per DIMM)
 189                                  * USER Read: Turn on ODT off on all ranks
 190                                  * USER Write: Turn on ODT on active rank
 191                                  */
 192                                 odt_mask_0 = 0x0;
 193                                 odt_mask_1 = 0x3 & (1 << rank);
 194                         }
 195                 } else {
 196                         /* 4 Ranks
 197                          * Read:
 198                          * ----------+-----------------------+
 199                          *           |                       |
 200                          *           |         ODT           |
 201                          * Read From +-----------------------+
 202                          *   Rank    |  3  |  2  |  1  |  0  |
 203                          * ----------+-----+-----+-----+-----+
 204                          *     0     |  0  |  1  |  0  |  0  |
 205                          *     1     |  1  |  0  |  0  |  0  |
 206                          *     2     |  0  |  0  |  0  |  1  |
 207                          *     3     |  0  |  0  |  1  |  0  |
 208                          * ----------+-----+-----+-----+-----+
 209                          *
 210                          * Write:
 211                          * ----------+-----------------------+
 212                          *           |                       |
 213                          *           |         ODT           |
 214                          * Write To  +-----------------------+
 215                          *   Rank    |  3  |  2  |  1  |  0  |
 216                          * ----------+-----+-----+-----+-----+
 217                          *     0     |  0  |  1  |  0  |  1  |
 218                          *     1     |  1  |  0  |  1  |  0  |
 219                          *     2     |  0  |  1  |  0  |  1  |
 220                          *     3     |  1  |  0  |  1  |  0  |
 221                          * ----------+-----+-----+-----+-----+
 222                          */
 223                         switch (rank) {
 224                         case 0:
 225                                 odt_mask_0 = 0x4;
 226                                 odt_mask_1 = 0x5;
 227                                 break;
 228                         case 1:
 229                                 odt_mask_0 = 0x8;
 230                                 odt_mask_1 = 0xA;
 231                                 break;
 232                         case 2:
 233                                 odt_mask_0 = 0x1;
 234                                 odt_mask_1 = 0x5;
 235                                 break;
 236                         case 3:
 237                                 odt_mask_0 = 0x2;
 238                                 odt_mask_1 = 0xA;
 239                                 break;
 240                         }
 241                 }
 242         } else {
 243                 odt_mask_0 = 0x0;
 244                 odt_mask_1 = 0x0;
 245         }
 246
 247         cs_and_odt_mask =
 248                 (0xFF & ~(1 << rank)) |
 249                 ((0xFF & odt_mask_0) << 8) |
 250                 ((0xFF & odt_mask_1) << 16);
 251         writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 252                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 253 }
 254
 255 static void scc_mgr_initialize(void)
 256 {
 257         u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_RFILE_OFFSET;
 258
 259         /*
 260          * Clear register file for HPS
 261          * 16 (2^4) is the size of the full register file in the scc mgr:
 262          *      RFILE_DEPTH = log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
 263          * MEM_IF_READ_DQS_WIDTH - 1) + 1;
 264          */
 265         uint32_t i;
 266         for (i = 0; i < 16; i++) {
 267                 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
 268                            __func__, __LINE__, i);
 269                 writel(0, addr + (i << 2));
 270         }
 271 }
 272
 273 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
 274 {
 275         u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQDQS_OUT_PHASE_OFFSET;
 276
 277         /* Load the setting in the SCC manager */
 278         writel(phase, addr + (write_group << 2));
 279 }
 280
 281 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
 282 {
 283         u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
 284
 285         /* Load the setting in the SCC manager */
 286         writel(delay, addr + (read_group << 2));
 287 }
 288
 289 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
 290 {
 291         u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_PHASE_OFFSET;
 292
 293         /* Load the setting in the SCC manager */
 294         writel(phase, addr + (read_group << 2));
 295 }
 296
 297 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
 298 {
 299         uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_DELAY_OFFSET;
 300
 301         /* Load the setting in the SCC manager */
 302         writel(delay + IO_DQS_EN_DELAY_OFFSET, addr + (read_group << 2));
 303 }
 304
 305 static void scc_mgr_set_dqs_io_in_delay(uint32_t write_group, uint32_t delay)
 306 {
 307         u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
 308
 309         writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
 310 }
 311
 312 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
 313 {
 314         uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
 315
 316         /* Load the setting in the SCC manager */
 317         writel(delay, addr + (dq_in_group << 2));
 318 }
 319
 320 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
 321 {
 322         uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
 323
 324         /* Load the setting in the SCC manager */
 325         writel(delay, addr + (dq_in_group << 2));
 326 }
 327
 328 static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
 329                                               uint32_t delay)
 330 {
 331         uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
 332
 333         /* Load the setting in the SCC manager */
 334         writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
 335 }
 336
 337 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
 338 {
 339         uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
 340
 341         /* Load the setting in the SCC manager */
 342         writel(delay, addr + ((RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm) << 2));
 343 }
 344
 345 /* load up dqs config settings */
 346 static void scc_mgr_load_dqs(uint32_t dqs)
 347 {
 348         writel(dqs, &sdr_scc_mgr->dqs_ena);
 349 }
 350
 351 /* load up dqs io config settings */
 352 static void scc_mgr_load_dqs_io(void)
 353 {
 354         writel(0, &sdr_scc_mgr->dqs_io_ena);
 355 }
 356
 357 /* load up dq config settings */
 358 static void scc_mgr_load_dq(uint32_t dq_in_group)
 359 {
 360         writel(dq_in_group, &sdr_scc_mgr->dq_ena);
 361 }
 362
 363 /* load up dm config settings */
 364 static void scc_mgr_load_dm(uint32_t dm)
 365 {
 366         writel(dm, &sdr_scc_mgr->dm_ena);
 367 }
 368
 369 static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
 370                                                uint32_t phase)
 371 {
 372         uint32_t r;
 373         uint32_t update_scan_chains;
 374
 375         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 376              r += NUM_RANKS_PER_SHADOW_REG) {
 377                 /*
 378                  * USER although the h/w doesn't support different phases per
 379                  * shadow register, for simplicity our scc manager modeling
 380                  * keeps different phase settings per shadow reg, and it's
 381                  * important for us to keep them in sync to match h/w.
 382                  * for efficiency, the scan chain update should occur only
 383                  * once to sr0.
 384                  */
 385                 update_scan_chains = (r == 0) ? 1 : 0;
 386
 387                 scc_mgr_set_dqs_en_phase(read_group, phase);
 388
 389                 if (update_scan_chains) {
 390                         writel(read_group, &sdr_scc_mgr->dqs_ena);
 391                         writel(0, &sdr_scc_mgr->update);
 392                 }
 393         }
 394 }
 395
 396 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
 397                                                      uint32_t phase)
 398 {
 399         uint32_t r;
 400         uint32_t update_scan_chains;
 401
 402         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 403              r += NUM_RANKS_PER_SHADOW_REG) {
 404                 /*
 405                  * USER although the h/w doesn't support different phases per
 406                  * shadow register, for simplicity our scc manager modeling
 407                  * keeps different phase settings per shadow reg, and it's
 408                  * important for us to keep them in sync to match h/w.
 409                  * for efficiency, the scan chain update should occur only
 410                  * once to sr0.
 411                  */
 412                 update_scan_chains = (r == 0) ? 1 : 0;
 413
 414                 scc_mgr_set_dqdqs_output_phase(write_group, phase);
 415
 416                 if (update_scan_chains) {
 417                         writel(write_group, &sdr_scc_mgr->dqs_ena);
 418                         writel(0, &sdr_scc_mgr->update);
 419                 }
 420         }
 421 }
 422
 423 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
 424                                                uint32_t delay)
 425 {
 426         uint32_t r;
 427
 428         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 429                 r += NUM_RANKS_PER_SHADOW_REG) {
 430                 scc_mgr_set_dqs_en_delay(read_group, delay);
 431
 432                 writel(read_group, &sdr_scc_mgr->dqs_ena);
 433                 /*
 434                  * In shadow register mode, the T11 settings are stored in
 435                  * registers in the core, which are updated by the DQS_ENA
 436                  * signals. Not issuing the SCC_MGR_UPD command allows us to
 437                  * save lots of rank switching overhead, by calling
 438                  * select_shadow_regs_for_update with update_scan_chains
 439                  * set to 0.
 440                  */
 441                 writel(0, &sdr_scc_mgr->update);
 442         }
 443         /*
 444          * In shadow register mode, the T11 settings are stored in
 445          * registers in the core, which are updated by the DQS_ENA
 446          * signals. Not issuing the SCC_MGR_UPD command allows us to
 447          * save lots of rank switching overhead, by calling
 448          * select_shadow_regs_for_update with update_scan_chains
 449          * set to 0.
 450          */
 451         writel(0, &sdr_scc_mgr->update);
 452 }
 453
 454 static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
 455 {
 456         uint32_t read_group;
 457         uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_OCT_OUT1_DELAY_OFFSET;
 458
 459         /*
 460          * Load the setting in the SCC manager
 461          * Although OCT affects only write data, the OCT delay is controlled
 462          * by the DQS logic block which is instantiated once per read group.
 463          * For protocols where a write group consists of multiple read groups,
 464          * the setting must be set multiple times.
 465          */
 466         for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
 467              RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 468              read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
 469              RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
 470                 writel(delay, addr + (read_group << 2));
 471 }
 472
 473 static void scc_mgr_set_hhp_extras(void)
 474 {
 475         /*
 476          * Load the fixed setting in the SCC manager
 477          * bits: 0:0 = 1'b1   - dqs bypass
 478          * bits: 1:1 = 1'b1   - dq bypass
 479          * bits: 4:2 = 3'b001   - rfifo_mode
 480          * bits: 6:5 = 2'b01  - rfifo clock_select
 481          * bits: 7:7 = 1'b0  - separate gating from ungating setting
 482          * bits: 8:8 = 1'b0  - separate OE from Output delay setting
 483          */
 484         uint32_t value = (0<<8) | (0<<7) | (1<<5) | (1<<2) | (1<<1) | (1<<0);
 485         uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_GLOBALS_OFFSET;
 486
 487         writel(value, addr + SCC_MGR_HHP_EXTRAS_OFFSET);
 488 }
 489
 490 /*
 491  * USER Zero all DQS config
 492  * TODO: maybe rename to scc_mgr_zero_dqs_config (or something)
 493  */
 494 static void scc_mgr_zero_all(void)
 495 {
 496         uint32_t i, r;
 497
 498         /*
 499          * USER Zero all DQS config settings, across all groups and all
 500          * shadow registers
 501          */
 502         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
 503              NUM_RANKS_PER_SHADOW_REG) {
 504                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
 505                         /*
 506                          * The phases actually don't exist on a per-rank basis,
 507                          * but there's no harm updating them several times, so
 508                          * let's keep the code simple.
 509                          */
 510                         scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
 511                         scc_mgr_set_dqs_en_phase(i, 0);
 512                         scc_mgr_set_dqs_en_delay(i, 0);
 513                 }
 514
 515                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
 516                         scc_mgr_set_dqdqs_output_phase(i, 0);
 517                         /* av/cv don't have out2 */
 518                         scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
 519                 }
 520         }
 521
 522         /* multicast to all DQS group enables */
 523         writel(0xff, &sdr_scc_mgr->dqs_ena);
 524         writel(0, &sdr_scc_mgr->update);
 525 }
 526
 527 static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
 528 {
 529         /* mode = 0 : Do NOT bypass - Half Rate Mode */
 530         /* mode = 1 : Bypass - Full Rate Mode */
 531
 532         /* only need to set once for all groups, pins, dq, dqs, dm */
 533         if (write_group == 0) {
 534                 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n", __func__,
 535                            __LINE__);
 536                 scc_mgr_set_hhp_extras();
 537                 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
 538                           __func__, __LINE__);
 539         }
 540         /* multicast to all DQ enables */
 541         writel(0xff, &sdr_scc_mgr->dq_ena);
 542         writel(0xff, &sdr_scc_mgr->dm_ena);
 543
 544         /* update current DQS IO enable */
 545         writel(0, &sdr_scc_mgr->dqs_io_ena);
 546
 547         /* update the DQS logic */
 548         writel(write_group, &sdr_scc_mgr->dqs_ena);
 549
 550         /* hit update */
 551         writel(0, &sdr_scc_mgr->update);
 552 }
 553
 554 static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
 555 {
 556         uint32_t read_group;
 557         uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
 558         /*
 559          * Although OCT affects only write data, the OCT delay is controlled
 560          * by the DQS logic block which is instantiated once per read group.
 561          * For protocols where a write group consists of multiple read groups,
 562          * the setting must be scanned multiple times.
 563          */
 564         for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
 565              RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 566              read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
 567              RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
 568                 writel(read_group, addr);
 569 }
 570
 571 static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
 572                                int32_t out_only)
 573 {
 574         uint32_t i, r;
 575
 576         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
 577                 NUM_RANKS_PER_SHADOW_REG) {
 578                 /* Zero all DQ config settings */
 579                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 580                         scc_mgr_set_dq_out1_delay(i, 0);
 581                         if (!out_only)
 582                                 scc_mgr_set_dq_in_delay(i, 0);
 583                 }
 584
 585                 /* multicast to all DQ enables */
 586                 writel(0xff, &sdr_scc_mgr->dq_ena);
 587
 588                 /* Zero all DM config settings */
 589                 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
 590                         scc_mgr_set_dm_out1_delay(i, 0);
 591                 }
 592
 593                 /* multicast to all DM enables */
 594                 writel(0xff, &sdr_scc_mgr->dm_ena);
 595
 596                 /* zero all DQS io settings */
 597                 if (!out_only)
 598                         scc_mgr_set_dqs_io_in_delay(write_group, 0);
 599                 /* av/cv don't have out2 */
 600                 scc_mgr_set_dqs_out1_delay(write_group, IO_DQS_OUT_RESERVE);
 601                 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
 602                 scc_mgr_load_dqs_for_write_group(write_group);
 603
 604                 /* multicast to all DQS IO enables (only 1) */
 605                 writel(0, &sdr_scc_mgr->dqs_io_ena);
 606
 607                 /* hit update to zero everything */
 608                 writel(0, &sdr_scc_mgr->update);
 609         }
 610 }
 611
 612 /*
 613  * apply and load a particular input delay for the DQ pins in a group
 614  * group_bgn is the index of the first dq pin (in the write group)
 615  */
 616 static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group,
 617                                             uint32_t group_bgn, uint32_t delay)
 618 {
 619         uint32_t i, p;
 620
 621         for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
 622                 scc_mgr_set_dq_in_delay(p, delay);
 623                 scc_mgr_load_dq(p);
 624         }
 625 }
 626
 627 /* apply and load a particular output delay for the DQ pins in a group */
 628 static void scc_mgr_apply_group_dq_out1_delay(uint32_t write_group,
 629                                               uint32_t group_bgn,
 630                                               uint32_t delay1)
 631 {
 632         uint32_t i, p;
 633
 634         for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
 635                 scc_mgr_set_dq_out1_delay(i, delay1);
 636                 scc_mgr_load_dq(i);
 637         }
 638 }
 639
 640 /* apply and load a particular output delay for the DM pins in a group */
 641 static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group,
 642                                               uint32_t delay1)
 643 {
 644         uint32_t i;
 645
 646         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
 647                 scc_mgr_set_dm_out1_delay(i, delay1);
 648                 scc_mgr_load_dm(i);
 649         }
 650 }
 651
 652
 653 /* apply and load delay on both DQS and OCT out1 */
 654 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
 655                                                     uint32_t delay)
 656 {
 657         scc_mgr_set_dqs_out1_delay(write_group, delay);
 658         scc_mgr_load_dqs_io();
 659
 660         scc_mgr_set_oct_out1_delay(write_group, delay);
 661         scc_mgr_load_dqs_for_write_group(write_group);
 662 }
 663
 664 /* apply a delay to the entire output side: DQ, DM, DQS, OCT */
 665 static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group,
 666                                                   uint32_t group_bgn,
 667                                                   uint32_t delay)
 668 {
 669         uint32_t i, p, new_delay;
 670
 671         /* dq shift */
 672         for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
 673                 new_delay = READ_SCC_DQ_OUT2_DELAY;
 674                 new_delay += delay;
 675
 676                 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 677                         debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQ[%u,%u]:\
 678                                    %u > %lu => %lu", __func__, __LINE__,
 679                                    write_group, group_bgn, delay, i, p, new_delay,
 680                                    (long unsigned int)IO_IO_OUT2_DELAY_MAX,
 681                                    (long unsigned int)IO_IO_OUT2_DELAY_MAX);
 682                         new_delay = IO_IO_OUT2_DELAY_MAX;
 683                 }
 684
 685                 scc_mgr_load_dq(i);
 686         }
 687
 688         /* dm shift */
 689         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
 690                 new_delay = READ_SCC_DM_IO_OUT2_DELAY;
 691                 new_delay += delay;
 692
 693                 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 694                         debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DM[%u]:\
 695                                    %u > %lu => %lu\n",  __func__, __LINE__,
 696                                    write_group, group_bgn, delay, i, new_delay,
 697                                    (long unsigned int)IO_IO_OUT2_DELAY_MAX,
 698                                    (long unsigned int)IO_IO_OUT2_DELAY_MAX);
 699                         new_delay = IO_IO_OUT2_DELAY_MAX;
 700                 }
 701
 702                 scc_mgr_load_dm(i);
 703         }
 704
 705         /* dqs shift */
 706         new_delay = READ_SCC_DQS_IO_OUT2_DELAY;
 707         new_delay += delay;
 708
 709         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 710                 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
 711                            " adding %u to OUT1\n", __func__, __LINE__,
 712                            write_group, group_bgn, delay, new_delay,
 713                            IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
 714                            new_delay - IO_IO_OUT2_DELAY_MAX);
 715                 scc_mgr_set_dqs_out1_delay(write_group, new_delay -
 716                                            IO_IO_OUT2_DELAY_MAX);
 717                 new_delay = IO_IO_OUT2_DELAY_MAX;
 718         }
 719
 720         scc_mgr_load_dqs_io();
 721
 722         /* oct shift */
 723         new_delay = READ_SCC_OCT_OUT2_DELAY;
 724         new_delay += delay;
 725
 726         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 727                 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
 728                            " adding %u to OUT1\n", __func__, __LINE__,
 729                            write_group, group_bgn, delay, new_delay,
 730                            IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
 731                            new_delay - IO_IO_OUT2_DELAY_MAX);
 732                 scc_mgr_set_oct_out1_delay(write_group, new_delay -
 733                                            IO_IO_OUT2_DELAY_MAX);
 734                 new_delay = IO_IO_OUT2_DELAY_MAX;
 735         }
 736
 737         scc_mgr_load_dqs_for_write_group(write_group);
 738 }
 739
 740 /*
 741  * USER apply a delay to the entire output side (DQ, DM, DQS, OCT)
 742  * and to all ranks
 743  */
 744 static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
 745         uint32_t write_group, uint32_t group_bgn, uint32_t delay)
 746 {
 747         uint32_t r;
 748
 749         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 750                 r += NUM_RANKS_PER_SHADOW_REG) {
 751                 scc_mgr_apply_group_all_out_delay_add(write_group,
 752                                                       group_bgn, delay);
 753                 writel(0, &sdr_scc_mgr->update);
 754         }
 755 }
 756
 757 /* optimization used to recover some slots in ddr3 inst_rom */
 758 /* could be applied to other protocols if we wanted to */
 759 static void set_jump_as_return(void)
 760 {
 761         /*
 762          * to save space, we replace return with jump to special shared
 763          * RETURN instruction so we set the counter to large value so that
 764          * we always jump
 765          */
 766         writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
 767         writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 768 }
 769
 770 /*
 771  * should always use constants as argument to ensure all computations are
 772  * performed at compile time
 773  */
 774 static void delay_for_n_mem_clocks(const uint32_t clocks)
 775 {
 776         uint32_t afi_clocks;
 777         uint8_t inner = 0;
 778         uint8_t outer = 0;
 779         uint16_t c_loop = 0;
 780
 781         debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
 782
 783
 784         afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
 785         /* scale (rounding up) to get afi clocks */
 786
 787         /*
 788          * Note, we don't bother accounting for being off a little bit
 789          * because of a few extra instructions in outer loops
 790          * Note, the loops have a test at the end, and do the test before
 791          * the decrement, and so always perform the loop
 792          * 1 time more than the counter value
 793          */
 794         if (afi_clocks == 0) {
 795                 ;
 796         } else if (afi_clocks <= 0x100) {
 797                 inner = afi_clocks-1;
 798                 outer = 0;
 799                 c_loop = 0;
 800         } else if (afi_clocks <= 0x10000) {
 801                 inner = 0xff;
 802                 outer = (afi_clocks-1) >> 8;
 803                 c_loop = 0;
 804         } else {
 805                 inner = 0xff;
 806                 outer = 0xff;
 807                 c_loop = (afi_clocks-1) >> 16;
 808         }
 809
 810         /*
 811          * rom instructions are structured as follows:
 812          *
 813          *    IDLE_LOOP2: jnz cntr0, TARGET_A
 814          *    IDLE_LOOP1: jnz cntr1, TARGET_B
 815          *                return
 816          *
 817          * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
 818          * TARGET_B is set to IDLE_LOOP2 as well
 819          *
 820          * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
 821          * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
 822          *
 823          * a little confusing, but it helps save precious space in the inst_rom
 824          * and sequencer rom and keeps the delays more accurate and reduces
 825          * overhead
 826          */
 827         if (afi_clocks <= 0x100) {
 828                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 829                         &sdr_rw_load_mgr_regs->load_cntr1);
 830
 831                 writel(RW_MGR_IDLE_LOOP1,
 832                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 833
 834                 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 835                                           RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 836         } else {
 837                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 838                         &sdr_rw_load_mgr_regs->load_cntr0);
 839
 840                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
 841                         &sdr_rw_load_mgr_regs->load_cntr1);
 842
 843                 writel(RW_MGR_IDLE_LOOP2,
 844                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 845
 846                 writel(RW_MGR_IDLE_LOOP2,
 847                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 848
 849                 /* hack to get around compiler not being smart enough */
 850                 if (afi_clocks <= 0x10000) {
 851                         /* only need to run once */
 852                         writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 853                                                   RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 854                 } else {
 855                         do {
 856                                 writel(RW_MGR_IDLE_LOOP2,
 857                                         SDR_PHYGRP_RWMGRGRP_ADDRESS |
 858                                         RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 859                         } while (c_loop-- != 0);
 860                 }
 861         }
 862         debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
 863 }
 864
 865 static void rw_mgr_mem_initialize(void)
 866 {
 867         uint32_t r;
 868         uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 869                            RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 870
 871         debug("%s:%d\n", __func__, __LINE__);
 872
 873         /* The reset / cke part of initialization is broadcasted to all ranks */
 874         writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 875                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 876
 877         /*
 878          * Here's how you load register for a loop
 879          * Counters are located @ 0x800
 880          * Jump address are located @ 0xC00
 881          * For both, registers 0 to 3 are selected using bits 3 and 2, like
 882          * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
 883          * I know this ain't pretty, but Avalon bus throws away the 2 least
 884          * significant bits
 885          */
 886
 887         /* start with memory RESET activated */
 888
 889         /* tINIT = 200us */
 890
 891         /*
 892          * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
 893          * If a and b are the number of iteration in 2 nested loops
 894          * it takes the following number of cycles to complete the operation:
 895          * number_of_cycles = ((2 + n) * a + 2) * b
 896          * where n is the number of instruction in the inner loop
 897          * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
 898          * b = 6A
 899          */
 900
 901         /* Load counters */
 902         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL),
 903                &sdr_rw_load_mgr_regs->load_cntr0);
 904         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL),
 905                &sdr_rw_load_mgr_regs->load_cntr1);
 906         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL),
 907                &sdr_rw_load_mgr_regs->load_cntr2);
 908
 909         /* Load jump address */
 910         writel(RW_MGR_INIT_RESET_0_CKE_0,
 911                 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 912         writel(RW_MGR_INIT_RESET_0_CKE_0,
 913                 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 914         writel(RW_MGR_INIT_RESET_0_CKE_0,
 915                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
 916
 917         /* Execute count instruction */
 918         writel(RW_MGR_INIT_RESET_0_CKE_0, grpaddr);
 919
 920         /* indicate that memory is stable */
 921         writel(1, &phy_mgr_cfg->reset_mem_stbl);
 922
 923         /*
 924          * transition the RESET to high
 925          * Wait for 500us
 926          */
 927
 928         /*
 929          * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
 930          * If a and b are the number of iteration in 2 nested loops
 931          * it takes the following number of cycles to complete the operation
 932          * number_of_cycles = ((2 + n) * a + 2) * b
 933          * where n is the number of instruction in the inner loop
 934          * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
 935          * b = FF
 936          */
 937
 938         /* Load counters */
 939         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL),
 940                &sdr_rw_load_mgr_regs->load_cntr0);
 941         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL),
 942                &sdr_rw_load_mgr_regs->load_cntr1);
 943         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL),
 944                &sdr_rw_load_mgr_regs->load_cntr2);
 945
 946         /* Load jump address */
 947         writel(RW_MGR_INIT_RESET_1_CKE_0,
 948                 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 949         writel(RW_MGR_INIT_RESET_1_CKE_0,
 950                 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 951         writel(RW_MGR_INIT_RESET_1_CKE_0,
 952                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
 953
 954         writel(RW_MGR_INIT_RESET_1_CKE_0, grpaddr);
 955
 956         /* bring up clock enable */
 957
 958         /* tXRP < 250 ck cycles */
 959         delay_for_n_mem_clocks(250);
 960
 961         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
 962                 if (param->skip_ranks[r]) {
 963                         /* request to skip the rank */
 964                         continue;
 965                 }
 966
 967                 /* set rank */
 968                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
 969
 970                 /*
 971                  * USER Use Mirror-ed commands for odd ranks if address
 972                  * mirrorring is on
 973                  */
 974                 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
 975                         set_jump_as_return();
 976                         writel(RW_MGR_MRS2_MIRR, grpaddr);
 977                         delay_for_n_mem_clocks(4);
 978                         set_jump_as_return();
 979                         writel(RW_MGR_MRS3_MIRR, grpaddr);
 980                         delay_for_n_mem_clocks(4);
 981                         set_jump_as_return();
 982                         writel(RW_MGR_MRS1_MIRR, grpaddr);
 983                         delay_for_n_mem_clocks(4);
 984                         set_jump_as_return();
 985                         writel(RW_MGR_MRS0_DLL_RESET_MIRR, grpaddr);
 986                 } else {
 987                         set_jump_as_return();
 988                         writel(RW_MGR_MRS2, grpaddr);
 989                         delay_for_n_mem_clocks(4);
 990                         set_jump_as_return();
 991                         writel(RW_MGR_MRS3, grpaddr);
 992                         delay_for_n_mem_clocks(4);
 993                         set_jump_as_return();
 994                         writel(RW_MGR_MRS1, grpaddr);
 995                         set_jump_as_return();
 996                         writel(RW_MGR_MRS0_DLL_RESET, grpaddr);
 997                 }
 998                 set_jump_as_return();
 999                 writel(RW_MGR_ZQCL, grpaddr);
1000
1001                 /* tZQinit = tDLLK = 512 ck cycles */
1002                 delay_for_n_mem_clocks(512);
1003         }
1004 }
1005
1006 /*
1007  * At the end of calibration we have to program the user settings in, and
1008  * USER  hand off the memory to the user.
1009  */
1010 static void rw_mgr_mem_handoff(void)
1011 {
1012         uint32_t r;
1013         uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1014                            RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1015
1016         debug("%s:%d\n", __func__, __LINE__);
1017         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
1018                 if (param->skip_ranks[r])
1019                         /* request to skip the rank */
1020                         continue;
1021                 /* set rank */
1022                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
1023
1024                 /* precharge all banks ... */
1025                 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
1026
1027                 /* load up MR settings specified by user */
1028
1029                 /*
1030                  * Use Mirror-ed commands for odd ranks if address
1031                  * mirrorring is on
1032                  */
1033                 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
1034                         set_jump_as_return();
1035                         writel(RW_MGR_MRS2_MIRR, grpaddr);
1036                         delay_for_n_mem_clocks(4);
1037                         set_jump_as_return();
1038                         writel(RW_MGR_MRS3_MIRR, grpaddr);
1039                         delay_for_n_mem_clocks(4);
1040                         set_jump_as_return();
1041                         writel(RW_MGR_MRS1_MIRR, grpaddr);
1042                         delay_for_n_mem_clocks(4);
1043                         set_jump_as_return();
1044                         writel(RW_MGR_MRS0_USER_MIRR, grpaddr);
1045                 } else {
1046                         set_jump_as_return();
1047                         writel(RW_MGR_MRS2, grpaddr);
1048                         delay_for_n_mem_clocks(4);
1049                         set_jump_as_return();
1050                         writel(RW_MGR_MRS3, grpaddr);
1051                         delay_for_n_mem_clocks(4);
1052                         set_jump_as_return();
1053                         writel(RW_MGR_MRS1, grpaddr);
1054                         delay_for_n_mem_clocks(4);
1055                         set_jump_as_return();
1056                         writel(RW_MGR_MRS0_USER, grpaddr);
1057                 }
1058                 /*
1059                  * USER  need to wait tMOD (12CK or 15ns) time before issuing
1060                  * other commands, but we will have plenty of NIOS cycles before
1061                  * actual handoff so its okay.
1062                  */
1063         }
1064 }
1065
1066 /*
1067  * performs a guaranteed read on the patterns we are going to use during a
1068  * read test to ensure memory works
1069  */
1070 static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
1071         uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
1072         uint32_t all_ranks)
1073 {
1074         uint32_t r, vg;
1075         uint32_t correct_mask_vg;
1076         uint32_t tmp_bit_chk;
1077         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1078                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1079         uint32_t addr;
1080         uint32_t base_rw_mgr;
1081
1082         *bit_chk = param->read_correct_mask;
1083         correct_mask_vg = param->read_correct_mask_vg;
1084
1085         for (r = rank_bgn; r < rank_end; r++) {
1086                 if (param->skip_ranks[r])
1087                         /* request to skip the rank */
1088                         continue;
1089
1090                 /* set rank */
1091                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1092
1093                 /* Load up a constant bursts of read commands */
1094                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1095                 writel(RW_MGR_GUARANTEED_READ,
1096                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1097
1098                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1099                 writel(RW_MGR_GUARANTEED_READ_CONT,
1100                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1101
1102                 tmp_bit_chk = 0;
1103                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1104                         /* reset the fifos to get pointers to known state */
1105
1106                         writel(0, &phy_mgr_cmd->fifo_reset);
1107                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1108                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1109
1110                         tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1111                                 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1112
1113                         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1114                         writel(RW_MGR_GUARANTEED_READ, addr +
1115                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1116                                 vg) << 2));
1117
1118                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1119                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
1120
1121                         if (vg == 0)
1122                                 break;
1123                 }
1124                 *bit_chk &= tmp_bit_chk;
1125         }
1126
1127         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1128         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1129
1130         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1131         debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
1132                    %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
1133                    (long unsigned int)(*bit_chk == param->read_correct_mask));
1134         return *bit_chk == param->read_correct_mask;
1135 }
1136
1137 static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
1138         (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
1139 {
1140         return rw_mgr_mem_calibrate_read_test_patterns(0, group,
1141                 num_tries, bit_chk, 1);
1142 }
1143
1144 /* load up the patterns we are going to use during a read test */
1145 static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
1146         uint32_t all_ranks)
1147 {
1148         uint32_t r;
1149         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1150                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1151
1152         debug("%s:%d\n", __func__, __LINE__);
1153         for (r = rank_bgn; r < rank_end; r++) {
1154                 if (param->skip_ranks[r])
1155                         /* request to skip the rank */
1156                         continue;
1157
1158                 /* set rank */
1159                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1160
1161                 /* Load up a constant bursts */
1162                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1163
1164                 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1165                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1166
1167                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1168
1169                 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1170                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1171
1172                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1173
1174                 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1175                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1176
1177                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1178
1179                 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1180                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1181
1182                 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1183                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1184         }
1185
1186         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1187 }
1188
1189 /*
1190  * try a read and see if it returns correct data back. has dummy reads
1191  * inserted into the mix used to align dqs enable. has more thorough checks
1192  * than the regular read test.
1193  */
1194 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1195         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1196         uint32_t all_groups, uint32_t all_ranks)
1197 {
1198         uint32_t r, vg;
1199         uint32_t correct_mask_vg;
1200         uint32_t tmp_bit_chk;
1201         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1202                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1203         uint32_t addr;
1204         uint32_t base_rw_mgr;
1205
1206         *bit_chk = param->read_correct_mask;
1207         correct_mask_vg = param->read_correct_mask_vg;
1208
1209         uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1210                 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1211
1212         for (r = rank_bgn; r < rank_end; r++) {
1213                 if (param->skip_ranks[r])
1214                         /* request to skip the rank */
1215                         continue;
1216
1217                 /* set rank */
1218                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1219
1220                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1221
1222                 writel(RW_MGR_READ_B2B_WAIT1,
1223                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1224
1225                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1226                 writel(RW_MGR_READ_B2B_WAIT2,
1227                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1228
1229                 if (quick_read_mode)
1230                         writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1231                         /* need at least two (1+1) reads to capture failures */
1232                 else if (all_groups)
1233                         writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1234                 else
1235                         writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1236
1237                 writel(RW_MGR_READ_B2B,
1238                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1239                 if (all_groups)
1240                         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1241                                RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1242                                &sdr_rw_load_mgr_regs->load_cntr3);
1243                 else
1244                         writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1245
1246                 writel(RW_MGR_READ_B2B,
1247                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1248
1249                 tmp_bit_chk = 0;
1250                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1251                         /* reset the fifos to get pointers to known state */
1252                         writel(0, &phy_mgr_cmd->fifo_reset);
1253                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1254                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1255
1256                         tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1257                                 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1258
1259                         if (all_groups)
1260                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1261                         else
1262                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1263
1264                         writel(RW_MGR_READ_B2B, addr +
1265                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1266                                vg) << 2));
1267
1268                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1269                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1270
1271                         if (vg == 0)
1272                                 break;
1273                 }
1274                 *bit_chk &= tmp_bit_chk;
1275         }
1276
1277         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1278         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1279
1280         if (all_correct) {
1281                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1282                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1283                            (%u == %u) => %lu", __func__, __LINE__, group,
1284                            all_groups, *bit_chk, param->read_correct_mask,
1285                            (long unsigned int)(*bit_chk ==
1286                            param->read_correct_mask));
1287                 return *bit_chk == param->read_correct_mask;
1288         } else  {
1289                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1290                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1291                            (%u != %lu) => %lu\n", __func__, __LINE__,
1292                            group, all_groups, *bit_chk, (long unsigned int)0,
1293                            (long unsigned int)(*bit_chk != 0x00));
1294                 return *bit_chk != 0x00;
1295         }
1296 }
1297
1298 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1299         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1300         uint32_t all_groups)
1301 {
1302         return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1303                                               bit_chk, all_groups, 1);
1304 }
1305
1306 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1307 {
1308         writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1309         (*v)++;
1310 }
1311
1312 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1313 {
1314         uint32_t i;
1315
1316         for (i = 0; i < VFIFO_SIZE-1; i++)
1317                 rw_mgr_incr_vfifo(grp, v);
1318 }
1319
1320 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1321 {
1322         uint32_t  v;
1323         uint32_t fail_cnt = 0;
1324         uint32_t test_status;
1325
1326         for (v = 0; v < VFIFO_SIZE; ) {
1327                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1328                            __func__, __LINE__, v);
1329                 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1330                         (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1331                 if (!test_status) {
1332                         fail_cnt++;
1333
1334                         if (fail_cnt == 2)
1335                                 break;
1336                 }
1337
1338                 /* fiddle with FIFO */
1339                 rw_mgr_incr_vfifo(grp, &v);
1340         }
1341
1342         if (v >= VFIFO_SIZE) {
1343                 /* no failing read found!! Something must have gone wrong */
1344                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1345                            __func__, __LINE__);
1346                 return 0;
1347         } else {
1348                 return v;
1349         }
1350 }
1351
1352 static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
1353                               uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1354                               uint32_t *v, uint32_t *d, uint32_t *p,
1355                               uint32_t *i, uint32_t *max_working_cnt)
1356 {
1357         uint32_t found_begin = 0;
1358         uint32_t tmp_delay = 0;
1359         uint32_t test_status;
1360
1361         for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1362                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1363                 *work_bgn = tmp_delay;
1364                 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1365
1366                 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1367                         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1368                                 IO_DELAY_PER_OPA_TAP) {
1369                                 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1370
1371                                 test_status =
1372                                 rw_mgr_mem_calibrate_read_test_all_ranks
1373                                 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1374
1375                                 if (test_status) {
1376                                         *max_working_cnt = 1;
1377                                         found_begin = 1;
1378                                         break;
1379                                 }
1380                         }
1381
1382                         if (found_begin)
1383                                 break;
1384
1385                         if (*p > IO_DQS_EN_PHASE_MAX)
1386                                 /* fiddle with FIFO */
1387                                 rw_mgr_incr_vfifo(*grp, v);
1388                 }
1389
1390                 if (found_begin)
1391                         break;
1392         }
1393
1394         if (*i >= VFIFO_SIZE) {
1395                 /* cannot find working solution */
1396                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1397                            ptap/dtap\n", __func__, __LINE__);
1398                 return 0;
1399         } else {
1400                 return 1;
1401         }
1402 }
1403
1404 static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1405                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1406                              uint32_t *p, uint32_t *max_working_cnt)
1407 {
1408         uint32_t found_begin = 0;
1409         uint32_t tmp_delay;
1410
1411         /* Special case code for backing up a phase */
1412         if (*p == 0) {
1413                 *p = IO_DQS_EN_PHASE_MAX;
1414                 rw_mgr_decr_vfifo(*grp, v);
1415         } else {
1416                 (*p)--;
1417         }
1418         tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1419         scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1420
1421         for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1422                 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1423                 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1424
1425                 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1426                                                              PASS_ONE_BIT,
1427                                                              bit_chk, 0)) {
1428                         found_begin = 1;
1429                         *work_bgn = tmp_delay;
1430                         break;
1431                 }
1432         }
1433
1434         /* We have found a working dtap before the ptap found above */
1435         if (found_begin == 1)
1436                 (*max_working_cnt)++;
1437
1438         /*
1439          * Restore VFIFO to old state before we decremented it
1440          * (if needed).
1441          */
1442         (*p)++;
1443         if (*p > IO_DQS_EN_PHASE_MAX) {
1444                 *p = 0;
1445                 rw_mgr_incr_vfifo(*grp, v);
1446         }
1447
1448         scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1449 }
1450
1451 static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1452                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1453                              uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1454                              uint32_t *work_end)
1455 {
1456         uint32_t found_end = 0;
1457
1458         (*p)++;
1459         *work_end += IO_DELAY_PER_OPA_TAP;
1460         if (*p > IO_DQS_EN_PHASE_MAX) {
1461                 /* fiddle with FIFO */
1462                 *p = 0;
1463                 rw_mgr_incr_vfifo(*grp, v);
1464         }
1465
1466         for (; *i < VFIFO_SIZE + 1; (*i)++) {
1467                 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1468                         += IO_DELAY_PER_OPA_TAP) {
1469                         scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1470
1471                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1472                                 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1473                                 found_end = 1;
1474                                 break;
1475                         } else {
1476                                 (*max_working_cnt)++;
1477                         }
1478                 }
1479
1480                 if (found_end)
1481                         break;
1482
1483                 if (*p > IO_DQS_EN_PHASE_MAX) {
1484                         /* fiddle with FIFO */
1485                         rw_mgr_incr_vfifo(*grp, v);
1486                         *p = 0;
1487                 }
1488         }
1489
1490         if (*i >= VFIFO_SIZE + 1) {
1491                 /* cannot see edge of failing read */
1492                 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1493                            failed\n", __func__, __LINE__);
1494                 return 0;
1495         } else {
1496                 return 1;
1497         }
1498 }
1499
1500 static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
1501                                   uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1502                                   uint32_t *p, uint32_t *work_mid,
1503                                   uint32_t *work_end)
1504 {
1505         int i;
1506         int tmp_delay = 0;
1507
1508         *work_mid = (*work_bgn + *work_end) / 2;
1509
1510         debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1511                    *work_bgn, *work_end, *work_mid);
1512         /* Get the middle delay to be less than a VFIFO delay */
1513         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
1514                 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1515                 ;
1516         debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1517         while (*work_mid > tmp_delay)
1518                 *work_mid -= tmp_delay;
1519         debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
1520
1521         tmp_delay = 0;
1522         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
1523                 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1524                 ;
1525         tmp_delay -= IO_DELAY_PER_OPA_TAP;
1526         debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
1527         for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
1528                 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
1529                 ;
1530         debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
1531
1532         scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
1533         scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1534
1535         /*
1536          * push vfifo until we can successfully calibrate. We can do this
1537          * because the largest possible margin in 1 VFIFO cycle.
1538          */
1539         for (i = 0; i < VFIFO_SIZE; i++) {
1540                 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1541                            *v);
1542                 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1543                                                              PASS_ONE_BIT,
1544                                                              bit_chk, 0)) {
1545                         break;
1546                 }
1547
1548                 /* fiddle with FIFO */
1549                 rw_mgr_incr_vfifo(*grp, v);
1550         }
1551
1552         if (i >= VFIFO_SIZE) {
1553                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
1554                            failed\n", __func__, __LINE__);
1555                 return 0;
1556         } else {
1557                 return 1;
1558         }
1559 }
1560
1561 /* find a good dqs enable to use */
1562 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1563 {
1564         uint32_t v, d, p, i;
1565         uint32_t max_working_cnt;
1566         uint32_t bit_chk;
1567         uint32_t dtaps_per_ptap;
1568         uint32_t work_bgn, work_mid, work_end;
1569         uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1570
1571         debug("%s:%d %u\n", __func__, __LINE__, grp);
1572
1573         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1574
1575         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1576         scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1577
1578         /* ************************************************************** */
1579         /* * Step 0 : Determine number of delay taps for each phase tap * */
1580         dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1581
1582         /* ********************************************************* */
1583         /* * Step 1 : First push vfifo until we get a failing read * */
1584         v = find_vfifo_read(grp, &bit_chk);
1585
1586         max_working_cnt = 0;
1587
1588         /* ******************************************************** */
1589         /* * step 2: find first working phase, increment in ptaps * */
1590         work_bgn = 0;
1591         if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1592                                 &p, &i, &max_working_cnt) == 0)
1593                 return 0;
1594
1595         work_end = work_bgn;
1596
1597         /*
1598          * If d is 0 then the working window covers a phase tap and
1599          * we can follow the old procedure otherwise, we've found the beginning,
1600          * and we need to increment the dtaps until we find the end.
1601          */
1602         if (d == 0) {
1603                 /* ********************************************************* */
1604                 /* * step 3a: if we have room, back off by one and
1605                 increment in dtaps * */
1606
1607                 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1608                                  &max_working_cnt);
1609
1610                 /* ********************************************************* */
1611                 /* * step 4a: go forward from working phase to non working
1612                 phase, increment in ptaps * */
1613                 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1614                                          &i, &max_working_cnt, &work_end) == 0)
1615                         return 0;
1616
1617                 /* ********************************************************* */
1618                 /* * step 5a:  back off one from last, increment in dtaps  * */
1619
1620                 /* Special case code for backing up a phase */
1621                 if (p == 0) {
1622                         p = IO_DQS_EN_PHASE_MAX;
1623                         rw_mgr_decr_vfifo(grp, &v);
1624                 } else {
1625                         p = p - 1;
1626                 }
1627
1628                 work_end -= IO_DELAY_PER_OPA_TAP;
1629                 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1630
1631                 /* * The actual increment of dtaps is done outside of
1632                 the if/else loop to share code */
1633                 d = 0;
1634
1635                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1636                            vfifo=%u ptap=%u\n", __func__, __LINE__,
1637                            v, p);
1638         } else {
1639                 /* ******************************************************* */
1640                 /* * step 3-5b:  Find the right edge of the window using
1641                 delay taps   * */
1642                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1643                            ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1644                            v, p, d, work_bgn);
1645
1646                 work_end = work_bgn;
1647
1648                 /* * The actual increment of dtaps is done outside of the
1649                 if/else loop to share code */
1650
1651                 /* Only here to counterbalance a subtract later on which is
1652                 not needed if this branch of the algorithm is taken */
1653                 max_working_cnt++;
1654         }
1655
1656         /* The dtap increment to find the failing edge is done here */
1657         for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1658                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1659                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1660                                    end-2: dtap=%u\n", __func__, __LINE__, d);
1661                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1662
1663                         if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1664                                                                       PASS_ONE_BIT,
1665                                                                       &bit_chk, 0)) {
1666                                 break;
1667                         }
1668         }
1669
1670         /* Go back to working dtap */
1671         if (d != 0)
1672                 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1673
1674         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1675                    ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1676                    v, p, d-1, work_end);
1677
1678         if (work_end < work_bgn) {
1679                 /* nil range */
1680                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1681                            failed\n", __func__, __LINE__);
1682                 return 0;
1683         }
1684
1685         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1686                    __func__, __LINE__, work_bgn, work_end);
1687
1688         /* *************************************************************** */
1689         /*
1690          * * We need to calculate the number of dtaps that equal a ptap
1691          * * To do that we'll back up a ptap and re-find the edge of the
1692          * * window using dtaps
1693          */
1694
1695         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1696                    for tracking\n", __func__, __LINE__);
1697
1698         /* Special case code for backing up a phase */
1699         if (p == 0) {
1700                 p = IO_DQS_EN_PHASE_MAX;
1701                 rw_mgr_decr_vfifo(grp, &v);
1702                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1703                            cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1704                            v, p);
1705         } else {
1706                 p = p - 1;
1707                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1708                            phase only: v=%u p=%u", __func__, __LINE__,
1709                            v, p);
1710         }
1711
1712         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1713
1714         /*
1715          * Increase dtap until we first see a passing read (in case the
1716          * window is smaller than a ptap),
1717          * and then a failing read to mark the edge of the window again
1718          */
1719
1720         /* Find a passing read */
1721         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1722                    __func__, __LINE__);
1723         found_passing_read = 0;
1724         found_failing_read = 0;
1725         initial_failing_dtap = d;
1726         for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1727                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1728                            read d=%u\n", __func__, __LINE__, d);
1729                 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1730
1731                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1732                                                              PASS_ONE_BIT,
1733                                                              &bit_chk, 0)) {
1734                         found_passing_read = 1;
1735                         break;
1736                 }
1737         }
1738
1739         if (found_passing_read) {
1740                 /* Find a failing read */
1741                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1742                            read\n", __func__, __LINE__);
1743                 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1744                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1745                                    testing read d=%u\n", __func__, __LINE__, d);
1746                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1747
1748                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1749                                 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1750                                 found_failing_read = 1;
1751                                 break;
1752                         }
1753                 }
1754         } else {
1755                 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1756                            calculate dtaps", __func__, __LINE__);
1757                 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1758         }
1759
1760         /*
1761          * The dynamically calculated dtaps_per_ptap is only valid if we
1762          * found a passing/failing read. If we didn't, it means d hit the max
1763          * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1764          * statically calculated value.
1765          */
1766         if (found_passing_read && found_failing_read)
1767                 dtaps_per_ptap = d - initial_failing_dtap;
1768
1769         writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1770         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1771                    - %u = %u",  __func__, __LINE__, d,
1772                    initial_failing_dtap, dtaps_per_ptap);
1773
1774         /* ******************************************** */
1775         /* * step 6:  Find the centre of the window   * */
1776         if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1777                                    &work_mid, &work_end) == 0)
1778                 return 0;
1779
1780         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
1781                    vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
1782                    v, p-1, d);
1783         return 1;
1784 }
1785
1786 /*
1787  * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1788  * dq_in_delay values
1789  */
1790 static uint32_t
1791 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1792 (uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
1793 {
1794         uint32_t found;
1795         uint32_t i;
1796         uint32_t p;
1797         uint32_t d;
1798         uint32_t r;
1799
1800         const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
1801                 (RW_MGR_MEM_DQ_PER_READ_DQS-1);
1802                 /* we start at zero, so have one less dq to devide among */
1803
1804         debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
1805               test_bgn);
1806
1807         /* try different dq_in_delays since the dq path is shorter than dqs */
1808
1809         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1810              r += NUM_RANKS_PER_SHADOW_REG) {
1811                 for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1812                         i++, p++, d += delay_step) {
1813                         debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
1814                                    vfifo_find_dqs_", __func__, __LINE__);
1815                         debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
1816                                write_group, read_group);
1817                         debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
1818                         scc_mgr_set_dq_in_delay(p, d);
1819                         scc_mgr_load_dq(p);
1820                 }
1821                 writel(0, &sdr_scc_mgr->update);
1822         }
1823
1824         found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
1825
1826         debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
1827                    en_phase_sweep_dq", __func__, __LINE__);
1828         debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
1829                    chain to zero\n", write_group, read_group, found);
1830
1831         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1832              r += NUM_RANKS_PER_SHADOW_REG) {
1833                 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1834                         i++, p++) {
1835                         scc_mgr_set_dq_in_delay(p, 0);
1836                         scc_mgr_load_dq(p);
1837                 }
1838                 writel(0, &sdr_scc_mgr->update);
1839         }
1840
1841         return found;
1842 }
1843
1844 /* per-bit deskew DQ and center */
1845 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1846         uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1847         uint32_t use_read_test, uint32_t update_fom)
1848 {
1849         uint32_t i, p, d, min_index;
1850         /*
1851          * Store these as signed since there are comparisons with
1852          * signed numbers.
1853          */
1854         uint32_t bit_chk;
1855         uint32_t sticky_bit_chk;
1856         int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1857         int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1858         int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1859         int32_t mid;
1860         int32_t orig_mid_min, mid_min;
1861         int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1862                 final_dqs_en;
1863         int32_t dq_margin, dqs_margin;
1864         uint32_t stop;
1865         uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1866         uint32_t addr;
1867
1868         debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1869
1870         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1871         start_dqs = readl(addr + (read_group << 2));
1872         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1873                 start_dqs_en = readl(addr + ((read_group << 2)
1874                                      - IO_DQS_EN_DELAY_OFFSET));
1875
1876         /* set the left and right edge of each bit to an illegal value */
1877         /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1878         sticky_bit_chk = 0;
1879         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1880                 left_edge[i]  = IO_IO_IN_DELAY_MAX + 1;
1881                 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1882         }
1883
1884         /* Search for the left edge of the window for each bit */
1885         for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1886                 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1887
1888                 writel(0, &sdr_scc_mgr->update);
1889
1890                 /*
1891                  * Stop searching when the read test doesn't pass AND when
1892                  * we've seen a passing read on every bit.
1893                  */
1894                 if (use_read_test) {
1895                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1896                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1897                                 &bit_chk, 0, 0);
1898                 } else {
1899                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1900                                                         0, PASS_ONE_BIT,
1901                                                         &bit_chk, 0);
1902                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1903                                 (read_group - (write_group *
1904                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1905                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1906                         stop = (bit_chk == 0);
1907                 }
1908                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1909                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1910                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1911                            && %u", __func__, __LINE__, d,
1912                            sticky_bit_chk,
1913                         param->read_correct_mask, stop);
1914
1915                 if (stop == 1) {
1916                         break;
1917                 } else {
1918                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1919                                 if (bit_chk & 1) {
1920                                         /* Remember a passing test as the
1921                                         left_edge */
1922                                         left_edge[i] = d;
1923                                 } else {
1924                                         /* If a left edge has not been seen yet,
1925                                         then a future passing test will mark
1926                                         this edge as the right edge */
1927                                         if (left_edge[i] ==
1928                                                 IO_IO_IN_DELAY_MAX + 1) {
1929                                                 right_edge[i] = -(d + 1);
1930                                         }
1931                                 }
1932                                 bit_chk = bit_chk >> 1;
1933                         }
1934                 }
1935         }
1936
1937         /* Reset DQ delay chains to 0 */
1938         scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, 0);
1939         sticky_bit_chk = 0;
1940         for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1941                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1942                            %d right_edge[%u]: %d\n", __func__, __LINE__,
1943                            i, left_edge[i], i, right_edge[i]);
1944
1945                 /*
1946                  * Check for cases where we haven't found the left edge,
1947                  * which makes our assignment of the the right edge invalid.
1948                  * Reset it to the illegal value.
1949                  */
1950                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1951                         right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1952                         right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1953                         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1954                                    right_edge[%u]: %d\n", __func__, __LINE__,
1955                                    i, right_edge[i]);
1956                 }
1957
1958                 /*
1959                  * Reset sticky bit (except for bits where we have seen
1960                  * both the left and right edge).
1961                  */
1962                 sticky_bit_chk = sticky_bit_chk << 1;
1963                 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1964                     (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1965                         sticky_bit_chk = sticky_bit_chk | 1;
1966                 }
1967
1968                 if (i == 0)
1969                         break;
1970         }
1971
1972         /* Search for the right edge of the window for each bit */
1973         for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1974                 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1975                 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1976                         uint32_t delay = d + start_dqs_en;
1977                         if (delay > IO_DQS_EN_DELAY_MAX)
1978                                 delay = IO_DQS_EN_DELAY_MAX;
1979                         scc_mgr_set_dqs_en_delay(read_group, delay);
1980                 }
1981                 scc_mgr_load_dqs(read_group);
1982
1983                 writel(0, &sdr_scc_mgr->update);
1984
1985                 /*
1986                  * Stop searching when the read test doesn't pass AND when
1987                  * we've seen a passing read on every bit.
1988                  */
1989                 if (use_read_test) {
1990                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1991                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1992                                 &bit_chk, 0, 0);
1993                 } else {
1994                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1995                                                         0, PASS_ONE_BIT,
1996                                                         &bit_chk, 0);
1997                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1998                                 (read_group - (write_group *
1999                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
2000                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
2001                         stop = (bit_chk == 0);
2002                 }
2003                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2004                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
2005
2006                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
2007                            %u && %u", __func__, __LINE__, d,
2008                            sticky_bit_chk, param->read_correct_mask, stop);
2009
2010                 if (stop == 1) {
2011                         break;
2012                 } else {
2013                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2014                                 if (bit_chk & 1) {
2015                                         /* Remember a passing test as
2016                                         the right_edge */
2017                                         right_edge[i] = d;
2018                                 } else {
2019                                         if (d != 0) {
2020                                                 /* If a right edge has not been
2021                                                 seen yet, then a future passing
2022                                                 test will mark this edge as the
2023                                                 left edge */
2024                                                 if (right_edge[i] ==
2025                                                 IO_IO_IN_DELAY_MAX + 1) {
2026                                                         left_edge[i] = -(d + 1);
2027                                                 }
2028                                         } else {
2029                                                 /* d = 0 failed, but it passed
2030                                                 when testing the left edge,
2031                                                 so it must be marginal,
2032                                                 set it to -1 */
2033                                                 if (right_edge[i] ==
2034                                                         IO_IO_IN_DELAY_MAX + 1 &&
2035                                                         left_edge[i] !=
2036                                                         IO_IO_IN_DELAY_MAX
2037                                                         + 1) {
2038                                                         right_edge[i] = -1;
2039                                                 }
2040                                                 /* If a right edge has not been
2041                                                 seen yet, then a future passing
2042                                                 test will mark this edge as the
2043                                                 left edge */
2044                                                 else if (right_edge[i] ==
2045                                                         IO_IO_IN_DELAY_MAX +
2046                                                         1) {
2047                                                         left_edge[i] = -(d + 1);
2048                                                 }
2049                                         }
2050                                 }
2051
2052                                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
2053                                            d=%u]: ", __func__, __LINE__, d);
2054                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
2055                                            (int)(bit_chk & 1), i, left_edge[i]);
2056                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2057                                            right_edge[i]);
2058                                 bit_chk = bit_chk >> 1;
2059                         }
2060                 }
2061         }
2062
2063         /* Check that all bits have a window */
2064         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2065                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2066                            %d right_edge[%u]: %d", __func__, __LINE__,
2067                            i, left_edge[i], i, right_edge[i]);
2068                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2069                         == IO_IO_IN_DELAY_MAX + 1)) {
2070                         /*
2071                          * Restore delay chain settings before letting the loop
2072                          * in rw_mgr_mem_calibrate_vfifo to retry different
2073                          * dqs/ck relationships.
2074                          */
2075                         scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2076                         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2077                                 scc_mgr_set_dqs_en_delay(read_group,
2078                                                          start_dqs_en);
2079                         }
2080                         scc_mgr_load_dqs(read_group);
2081                         writel(0, &sdr_scc_mgr->update);
2082
2083                         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2084                                    find edge [%u]: %d %d", __func__, __LINE__,
2085                                    i, left_edge[i], right_edge[i]);
2086                         if (use_read_test) {
2087                                 set_failing_group_stage(read_group *
2088                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2089                                         CAL_STAGE_VFIFO,
2090                                         CAL_SUBSTAGE_VFIFO_CENTER);
2091                         } else {
2092                                 set_failing_group_stage(read_group *
2093                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2094                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2095                                         CAL_SUBSTAGE_VFIFO_CENTER);
2096                         }
2097                         return 0;
2098                 }
2099         }
2100
2101         /* Find middle of window for each DQ bit */
2102         mid_min = left_edge[0] - right_edge[0];
2103         min_index = 0;
2104         for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2105                 mid = left_edge[i] - right_edge[i];
2106                 if (mid < mid_min) {
2107                         mid_min = mid;
2108                         min_index = i;
2109                 }
2110         }
2111
2112         /*
2113          * -mid_min/2 represents the amount that we need to move DQS.
2114          * If mid_min is odd and positive we'll need to add one to
2115          * make sure the rounding in further calculations is correct
2116          * (always bias to the right), so just add 1 for all positive values.
2117          */
2118         if (mid_min > 0)
2119                 mid_min++;
2120
2121         mid_min = mid_min / 2;
2122
2123         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2124                    __func__, __LINE__, mid_min, min_index);
2125
2126         /* Determine the amount we can change DQS (which is -mid_min) */
2127         orig_mid_min = mid_min;
2128         new_dqs = start_dqs - mid_min;
2129         if (new_dqs > IO_DQS_IN_DELAY_MAX)
2130                 new_dqs = IO_DQS_IN_DELAY_MAX;
2131         else if (new_dqs < 0)
2132                 new_dqs = 0;
2133
2134         mid_min = start_dqs - new_dqs;
2135         debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2136                    mid_min, new_dqs);
2137
2138         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2139                 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2140                         mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2141                 else if (start_dqs_en - mid_min < 0)
2142                         mid_min += start_dqs_en - mid_min;
2143         }
2144         new_dqs = start_dqs - mid_min;
2145
2146         debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2147                    new_dqs=%d mid_min=%d\n", start_dqs,
2148                    IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2149                    new_dqs, mid_min);
2150
2151         /* Initialize data for export structures */
2152         dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2153         dq_margin  = IO_IO_IN_DELAY_MAX + 1;
2154
2155         /* add delay to bring centre of all DQ windows to the same "level" */
2156         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2157                 /* Use values before divide by 2 to reduce round off error */
2158                 shift_dq = (left_edge[i] - right_edge[i] -
2159                         (left_edge[min_index] - right_edge[min_index]))/2  +
2160                         (orig_mid_min - mid_min);
2161
2162                 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2163                            shift_dq[%u]=%d\n", i, shift_dq);
2164
2165                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2166                 temp_dq_in_delay1 = readl(addr + (p << 2));
2167                 temp_dq_in_delay2 = readl(addr + (i << 2));
2168
2169                 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2170                         (int32_t)IO_IO_IN_DELAY_MAX) {
2171                         shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2172                 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2173                         shift_dq = -(int32_t)temp_dq_in_delay1;
2174                 }
2175                 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2176                            shift_dq[%u]=%d\n", i, shift_dq);
2177                 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2178                 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2179                 scc_mgr_load_dq(p);
2180
2181                 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2182                            left_edge[i] - shift_dq + (-mid_min),
2183                            right_edge[i] + shift_dq - (-mid_min));
2184                 /* To determine values for export structures */
2185                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2186                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2187
2188                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2189                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2190         }
2191
2192         final_dqs = new_dqs;
2193         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2194                 final_dqs_en = start_dqs_en - mid_min;
2195
2196         /* Move DQS-en */
2197         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2198                 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2199                 scc_mgr_load_dqs(read_group);
2200         }
2201
2202         /* Move DQS */
2203         scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2204         scc_mgr_load_dqs(read_group);
2205         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2206                    dqs_margin=%d", __func__, __LINE__,
2207                    dq_margin, dqs_margin);
2208
2209         /*
2210          * Do not remove this line as it makes sure all of our decisions
2211          * have been applied. Apply the update bit.
2212          */
2213         writel(0, &sdr_scc_mgr->update);
2214
2215         return (dq_margin >= 0) && (dqs_margin >= 0);
2216 }
2217
2218 /*
2219  * calibrate the read valid prediction FIFO.
2220  *
2221  *  - read valid prediction will consist of finding a good DQS enable phase,
2222  * DQS enable delay, DQS input phase, and DQS input delay.
2223  *  - we also do a per-bit deskew on the DQ lines.
2224  */
2225 static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
2226                                            uint32_t test_bgn)
2227 {
2228         uint32_t p, d, rank_bgn, sr;
2229         uint32_t dtaps_per_ptap;
2230         uint32_t tmp_delay;
2231         uint32_t bit_chk;
2232         uint32_t grp_calibrated;
2233         uint32_t write_group, write_test_bgn;
2234         uint32_t failed_substage;
2235
2236         debug("%s:%d: %u %u\n", __func__, __LINE__, read_group, test_bgn);
2237
2238         /* update info for sims */
2239         reg_file_set_stage(CAL_STAGE_VFIFO);
2240
2241         write_group = read_group;
2242         write_test_bgn = test_bgn;
2243
2244         /* USER Determine number of delay taps for each phase tap */
2245         dtaps_per_ptap = 0;
2246         tmp_delay = 0;
2247         while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
2248                 dtaps_per_ptap++;
2249                 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
2250         }
2251         dtaps_per_ptap--;
2252         tmp_delay = 0;
2253
2254         /* update info for sims */
2255         reg_file_set_group(read_group);
2256
2257         grp_calibrated = 0;
2258
2259         reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2260         failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2261
2262         for (d = 0; d <= dtaps_per_ptap && grp_calibrated == 0; d += 2) {
2263                 /*
2264                  * In RLDRAMX we may be messing the delay of pins in
2265                  * the same write group but outside of the current read
2266                  * the group, but that's ok because we haven't
2267                  * calibrated output side yet.
2268                  */
2269                 if (d > 0) {
2270                         scc_mgr_apply_group_all_out_delay_add_all_ranks
2271                         (write_group, write_test_bgn, d);
2272                 }
2273
2274                 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
2275                         p++) {
2276                         /* set a particular dqdqs phase */
2277                         scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
2278
2279                         debug_cond(DLEVEL == 1, "%s:%d calibrate_vfifo: g=%u \
2280                                    p=%u d=%u\n", __func__, __LINE__,
2281                                    read_group, p, d);
2282
2283                         /*
2284                          * Load up the patterns used by read calibration
2285                          * using current DQDQS phase.
2286                          */
2287                         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2288                         if (!(gbl->phy_debug_mode_flags &
2289                                 PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
2290                                 if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
2291                                     (read_group, 1, &bit_chk)) {
2292                                         debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:",
2293                                                    __func__, __LINE__);
2294                                         debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
2295                                                    read_group, p, d);
2296                                         break;
2297                                 }
2298                         }
2299
2300 /* case:56390 */
2301                         grp_calibrated = 1;
2302                 if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
2303                     (write_group, read_group, test_bgn)) {
2304                                 /*
2305                                  * USER Read per-bit deskew can be done on a
2306                                  * per shadow register basis.
2307                                  */
2308                                 for (rank_bgn = 0, sr = 0;
2309                                         rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2310                                         rank_bgn += NUM_RANKS_PER_SHADOW_REG,
2311                                         ++sr) {
2312                                         /*
2313                                          * Determine if this set of ranks
2314                                          * should be skipped entirely.
2315                                          */
2316                                         if (!param->skip_shadow_regs[sr]) {
2317                                                 /*
2318                                                  * If doing read after write
2319                                                  * calibration, do not update
2320                                                  * FOM, now - do it then.
2321                                                  */
2322                                         if (!rw_mgr_mem_calibrate_vfifo_center
2323                                                 (rank_bgn, write_group,
2324                                                 read_group, test_bgn, 1, 0)) {
2325                                                         grp_calibrated = 0;
2326                                                         failed_substage =
2327                                                 CAL_SUBSTAGE_VFIFO_CENTER;
2328                                                 }
2329                                         }
2330                                 }
2331                         } else {
2332                                 grp_calibrated = 0;
2333                                 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2334                         }
2335                 }
2336         }
2337
2338         if (grp_calibrated == 0) {
2339                 set_failing_group_stage(write_group, CAL_STAGE_VFIFO,
2340                                         failed_substage);
2341                 return 0;
2342         }
2343
2344         /*
2345          * Reset the delay chains back to zero if they have moved > 1
2346          * (check for > 1 because loop will increase d even when pass in
2347          * first case).
2348          */
2349         if (d > 2)
2350                 scc_mgr_zero_group(write_group, write_test_bgn, 1);
2351
2352         return 1;
2353 }
2354
2355 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2356 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2357                                                uint32_t test_bgn)
2358 {
2359         uint32_t rank_bgn, sr;
2360         uint32_t grp_calibrated;
2361         uint32_t write_group;
2362
2363         debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2364
2365         /* update info for sims */
2366
2367         reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2368         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2369
2370         write_group = read_group;
2371
2372         /* update info for sims */
2373         reg_file_set_group(read_group);
2374
2375         grp_calibrated = 1;
2376         /* Read per-bit deskew can be done on a per shadow register basis */
2377         for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2378                 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2379                 /* Determine if this set of ranks should be skipped entirely */
2380                 if (!param->skip_shadow_regs[sr]) {
2381                 /* This is the last calibration round, update FOM here */
2382                         if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2383                                                                 write_group,
2384                                                                 read_group,
2385                                                                 test_bgn, 0,
2386                                                                 1)) {
2387                                 grp_calibrated = 0;
2388                         }
2389                 }
2390         }
2391
2392
2393         if (grp_calibrated == 0) {
2394                 set_failing_group_stage(write_group,
2395                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2396                                         CAL_SUBSTAGE_VFIFO_CENTER);
2397                 return 0;
2398         }
2399
2400         return 1;
2401 }
2402
2403 /* Calibrate LFIFO to find smallest read latency */
2404 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2405 {
2406         uint32_t found_one;
2407         uint32_t bit_chk;
2408
2409         debug("%s:%d\n", __func__, __LINE__);
2410
2411         /* update info for sims */
2412         reg_file_set_stage(CAL_STAGE_LFIFO);
2413         reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2414
2415         /* Load up the patterns used by read calibration for all ranks */
2416         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2417         found_one = 0;
2418
2419         do {
2420                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2421                 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2422                            __func__, __LINE__, gbl->curr_read_lat);
2423
2424                 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2425                                                               NUM_READ_TESTS,
2426                                                               PASS_ALL_BITS,
2427                                                               &bit_chk, 1)) {
2428                         break;
2429                 }
2430
2431                 found_one = 1;
2432                 /* reduce read latency and see if things are working */
2433                 /* correctly */
2434                 gbl->curr_read_lat--;
2435         } while (gbl->curr_read_lat > 0);
2436
2437         /* reset the fifos to get pointers to known state */
2438
2439         writel(0, &phy_mgr_cmd->fifo_reset);
2440
2441         if (found_one) {
2442                 /* add a fudge factor to the read latency that was determined */
2443                 gbl->curr_read_lat += 2;
2444                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2445                 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2446                            read_lat=%u\n", __func__, __LINE__,
2447                            gbl->curr_read_lat);
2448                 return 1;
2449         } else {
2450                 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2451                                         CAL_SUBSTAGE_READ_LATENCY);
2452
2453                 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2454                            read_lat=%u\n", __func__, __LINE__,
2455                            gbl->curr_read_lat);
2456                 return 0;
2457         }
2458 }
2459
2460 /*
2461  * issue write test command.
2462  * two variants are provided. one that just tests a write pattern and
2463  * another that tests datamask functionality.
2464  */
2465 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2466                                                   uint32_t test_dm)
2467 {
2468         uint32_t mcc_instruction;
2469         uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2470                 ENABLE_SUPER_QUICK_CALIBRATION);
2471         uint32_t rw_wl_nop_cycles;
2472         uint32_t addr;
2473
2474         /*
2475          * Set counter and jump addresses for the right
2476          * number of NOP cycles.
2477          * The number of supported NOP cycles can range from -1 to infinity
2478          * Three different cases are handled:
2479          *
2480          * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2481          *    mechanism will be used to insert the right number of NOPs
2482          *
2483          * 2. For a number of NOP cycles equals to 0, the micro-instruction
2484          *    issuing the write command will jump straight to the
2485          *    micro-instruction that turns on DQS (for DDRx), or outputs write
2486          *    data (for RLD), skipping
2487          *    the NOP micro-instruction all together
2488          *
2489          * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2490          *    turned on in the same micro-instruction that issues the write
2491          *    command. Then we need
2492          *    to directly jump to the micro-instruction that sends out the data
2493          *
2494          * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2495          *       (2 and 3). One jump-counter (0) is used to perform multiple
2496          *       write-read operations.
2497          *       one counter left to issue this command in "multiple-group" mode
2498          */
2499
2500         rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2501
2502         if (rw_wl_nop_cycles == -1) {
2503                 /*
2504                  * CNTR 2 - We want to execute the special write operation that
2505                  * turns on DQS right away and then skip directly to the
2506                  * instruction that sends out the data. We set the counter to a
2507                  * large number so that the jump is always taken.
2508                  */
2509                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2510
2511                 /* CNTR 3 - Not used */
2512                 if (test_dm) {
2513                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2514                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2515                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2516                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2517                                &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2518                 } else {
2519                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2520                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2521                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2522                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2523                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2524                 }
2525         } else if (rw_wl_nop_cycles == 0) {
2526                 /*
2527                  * CNTR 2 - We want to skip the NOP operation and go straight
2528                  * to the DQS enable instruction. We set the counter to a large
2529                  * number so that the jump is always taken.
2530                  */
2531                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2532
2533                 /* CNTR 3 - Not used */
2534                 if (test_dm) {
2535                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2536                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2537                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2538                 } else {
2539                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2540                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2541                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2542                 }
2543         } else {
2544                 /*
2545                  * CNTR 2 - In this case we want to execute the next instruction
2546                  * and NOT take the jump. So we set the counter to 0. The jump
2547                  * address doesn't count.
2548                  */
2549                 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2550                 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2551
2552                 /*
2553                  * CNTR 3 - Set the nop counter to the number of cycles we
2554                  * need to loop for, minus 1.
2555                  */
2556                 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2557                 if (test_dm) {
2558                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2559                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2560                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2561                 } else {
2562                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2563                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2564                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2565                 }
2566         }
2567
2568         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2569                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
2570
2571         if (quick_write_mode)
2572                 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2573         else
2574                 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2575
2576         writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2577
2578         /*
2579          * CNTR 1 - This is used to ensure enough time elapses
2580          * for read data to come back.
2581          */
2582         writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2583
2584         if (test_dm) {
2585                 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2586                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2587         } else {
2588                 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2589                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2590         }
2591
2592         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2593         writel(mcc_instruction, addr + (group << 2));
2594 }
2595
2596 /* Test writes, can check for a single bit pass or multiple bit pass */
2597 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2598         uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2599         uint32_t *bit_chk, uint32_t all_ranks)
2600 {
2601         uint32_t r;
2602         uint32_t correct_mask_vg;
2603         uint32_t tmp_bit_chk;
2604         uint32_t vg;
2605         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2606                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2607         uint32_t addr_rw_mgr;
2608         uint32_t base_rw_mgr;
2609
2610         *bit_chk = param->write_correct_mask;
2611         correct_mask_vg = param->write_correct_mask_vg;
2612
2613         for (r = rank_bgn; r < rank_end; r++) {
2614                 if (param->skip_ranks[r]) {
2615                         /* request to skip the rank */
2616                         continue;
2617                 }
2618
2619                 /* set rank */
2620                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2621
2622                 tmp_bit_chk = 0;
2623                 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2624                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2625                         /* reset the fifos to get pointers to known state */
2626                         writel(0, &phy_mgr_cmd->fifo_reset);
2627
2628                         tmp_bit_chk = tmp_bit_chk <<
2629                                 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2630                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2631                         rw_mgr_mem_calibrate_write_test_issue(write_group *
2632                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2633                                 use_dm);
2634
2635                         base_rw_mgr = readl(addr_rw_mgr);
2636                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2637                         if (vg == 0)
2638                                 break;
2639                 }
2640                 *bit_chk &= tmp_bit_chk;
2641         }
2642
2643         if (all_correct) {
2644                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2645                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2646                            %u => %lu", write_group, use_dm,
2647                            *bit_chk, param->write_correct_mask,
2648                            (long unsigned int)(*bit_chk ==
2649                            param->write_correct_mask));
2650                 return *bit_chk == param->write_correct_mask;
2651         } else {
2652                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2653                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2654                        write_group, use_dm, *bit_chk);
2655                 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2656                         (long unsigned int)(*bit_chk != 0));
2657                 return *bit_chk != 0x00;
2658         }
2659 }
2660
2661 /*
2662  * center all windows. do per-bit-deskew to possibly increase size of
2663  * certain windows.
2664  */
2665 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2666         uint32_t write_group, uint32_t test_bgn)
2667 {
2668         uint32_t i, p, min_index;
2669         int32_t d;
2670         /*
2671          * Store these as signed since there are comparisons with
2672          * signed numbers.
2673          */
2674         uint32_t bit_chk;
2675         uint32_t sticky_bit_chk;
2676         int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2677         int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2678         int32_t mid;
2679         int32_t mid_min, orig_mid_min;
2680         int32_t new_dqs, start_dqs, shift_dq;
2681         int32_t dq_margin, dqs_margin, dm_margin;
2682         uint32_t stop;
2683         uint32_t temp_dq_out1_delay;
2684         uint32_t addr;
2685
2686         debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2687
2688         dm_margin = 0;
2689
2690         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2691         start_dqs = readl(addr +
2692                           (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2693
2694         /* per-bit deskew */
2695
2696         /*
2697          * set the left and right edge of each bit to an illegal value
2698          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2699          */
2700         sticky_bit_chk = 0;
2701         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2702                 left_edge[i]  = IO_IO_OUT1_DELAY_MAX + 1;
2703                 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2704         }
2705
2706         /* Search for the left edge of the window for each bit */
2707         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2708                 scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, d);
2709
2710                 writel(0, &sdr_scc_mgr->update);
2711
2712                 /*
2713                  * Stop searching when the read test doesn't pass AND when
2714                  * we've seen a passing read on every bit.
2715                  */
2716                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2717                         0, PASS_ONE_BIT, &bit_chk, 0);
2718                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2719                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2720                 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2721                            == %u && %u [bit_chk= %u ]\n",
2722                         d, sticky_bit_chk, param->write_correct_mask,
2723                         stop, bit_chk);
2724
2725                 if (stop == 1) {
2726                         break;
2727                 } else {
2728                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2729                                 if (bit_chk & 1) {
2730                                         /*
2731                                          * Remember a passing test as the
2732                                          * left_edge.
2733                                          */
2734                                         left_edge[i] = d;
2735                                 } else {
2736                                         /*
2737                                          * If a left edge has not been seen
2738                                          * yet, then a future passing test will
2739                                          * mark this edge as the right edge.
2740                                          */
2741                                         if (left_edge[i] ==
2742                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2743                                                 right_edge[i] = -(d + 1);
2744                                         }
2745                                 }
2746                                 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2747                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2748                                            (int)(bit_chk & 1), i, left_edge[i]);
2749                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2750                                        right_edge[i]);
2751                                 bit_chk = bit_chk >> 1;
2752                         }
2753                 }
2754         }
2755
2756         /* Reset DQ delay chains to 0 */
2757         scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, 0);
2758         sticky_bit_chk = 0;
2759         for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2760                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2761                            %d right_edge[%u]: %d\n", __func__, __LINE__,
2762                            i, left_edge[i], i, right_edge[i]);
2763
2764                 /*
2765                  * Check for cases where we haven't found the left edge,
2766                  * which makes our assignment of the the right edge invalid.
2767                  * Reset it to the illegal value.
2768                  */
2769                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2770                     (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2771                         right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2772                         debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2773                                    right_edge[%u]: %d\n", __func__, __LINE__,
2774                                    i, right_edge[i]);
2775                 }
2776
2777                 /*
2778                  * Reset sticky bit (except for bits where we have
2779                  * seen the left edge).
2780                  */
2781                 sticky_bit_chk = sticky_bit_chk << 1;
2782                 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2783                         sticky_bit_chk = sticky_bit_chk | 1;
2784
2785                 if (i == 0)
2786                         break;
2787         }
2788
2789         /* Search for the right edge of the window for each bit */
2790         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2791                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2792                                                         d + start_dqs);
2793
2794                 writel(0, &sdr_scc_mgr->update);
2795
2796                 /*
2797                  * Stop searching when the read test doesn't pass AND when
2798                  * we've seen a passing read on every bit.
2799                  */
2800                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2801                         0, PASS_ONE_BIT, &bit_chk, 0);
2802
2803                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2804                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2805
2806                 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2807                            %u && %u\n", d, sticky_bit_chk,
2808                            param->write_correct_mask, stop);
2809
2810                 if (stop == 1) {
2811                         if (d == 0) {
2812                                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2813                                         i++) {
2814                                         /* d = 0 failed, but it passed when
2815                                         testing the left edge, so it must be
2816                                         marginal, set it to -1 */
2817                                         if (right_edge[i] ==
2818                                                 IO_IO_OUT1_DELAY_MAX + 1 &&
2819                                                 left_edge[i] !=
2820                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2821                                                 right_edge[i] = -1;
2822                                         }
2823                                 }
2824                         }
2825                         break;
2826                 } else {
2827                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2828                                 if (bit_chk & 1) {
2829                                         /*
2830                                          * Remember a passing test as
2831                                          * the right_edge.
2832                                          */
2833                                         right_edge[i] = d;
2834                                 } else {
2835                                         if (d != 0) {
2836                                                 /*
2837                                                  * If a right edge has not
2838                                                  * been seen yet, then a future
2839                                                  * passing test will mark this
2840                                                  * edge as the left edge.
2841                                                  */
2842                                                 if (right_edge[i] ==
2843                                                     IO_IO_OUT1_DELAY_MAX + 1)
2844                                                         left_edge[i] = -(d + 1);
2845                                         } else {
2846                                                 /*
2847                                                  * d = 0 failed, but it passed
2848                                                  * when testing the left edge,
2849                                                  * so it must be marginal, set
2850                                                  * it to -1.
2851                                                  */
2852                                                 if (right_edge[i] ==
2853                                                     IO_IO_OUT1_DELAY_MAX + 1 &&
2854                                                     left_edge[i] !=
2855                                                     IO_IO_OUT1_DELAY_MAX + 1)
2856                                                         right_edge[i] = -1;
2857                                                 /*
2858                                                  * If a right edge has not been
2859                                                  * seen yet, then a future
2860                                                  * passing test will mark this
2861                                                  * edge as the left edge.
2862                                                  */
2863                                                 else if (right_edge[i] ==
2864                                                         IO_IO_OUT1_DELAY_MAX +
2865                                                         1)
2866                                                         left_edge[i] = -(d + 1);
2867                                         }
2868                                 }
2869                                 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2870                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2871                                            (int)(bit_chk & 1), i, left_edge[i]);
2872                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2873                                            right_edge[i]);
2874                                 bit_chk = bit_chk >> 1;
2875                         }
2876                 }
2877         }
2878
2879         /* Check that all bits have a window */
2880         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2881                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2882                            %d right_edge[%u]: %d", __func__, __LINE__,
2883                            i, left_edge[i], i, right_edge[i]);
2884                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2885                     (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2886                         set_failing_group_stage(test_bgn + i,
2887                                                 CAL_STAGE_WRITES,
2888                                                 CAL_SUBSTAGE_WRITES_CENTER);
2889                         return 0;
2890                 }
2891         }
2892
2893         /* Find middle of window for each DQ bit */
2894         mid_min = left_edge[0] - right_edge[0];
2895         min_index = 0;
2896         for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2897                 mid = left_edge[i] - right_edge[i];
2898                 if (mid < mid_min) {
2899                         mid_min = mid;
2900                         min_index = i;
2901                 }
2902         }
2903
2904         /*
2905          * -mid_min/2 represents the amount that we need to move DQS.
2906          * If mid_min is odd and positive we'll need to add one to
2907          * make sure the rounding in further calculations is correct
2908          * (always bias to the right), so just add 1 for all positive values.
2909          */
2910         if (mid_min > 0)
2911                 mid_min++;
2912         mid_min = mid_min / 2;
2913         debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2914                    __LINE__, mid_min);
2915
2916         /* Determine the amount we can change DQS (which is -mid_min) */
2917         orig_mid_min = mid_min;
2918         new_dqs = start_dqs;
2919         mid_min = 0;
2920         debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2921                    mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2922         /* Initialize data for export structures */
2923         dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2924         dq_margin  = IO_IO_OUT1_DELAY_MAX + 1;
2925
2926         /* add delay to bring centre of all DQ windows to the same "level" */
2927         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2928                 /* Use values before divide by 2 to reduce round off error */
2929                 shift_dq = (left_edge[i] - right_edge[i] -
2930                         (left_edge[min_index] - right_edge[min_index]))/2  +
2931                 (orig_mid_min - mid_min);
2932
2933                 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2934                            [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2935
2936                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2937                 temp_dq_out1_delay = readl(addr + (i << 2));
2938                 if (shift_dq + (int32_t)temp_dq_out1_delay >
2939                         (int32_t)IO_IO_OUT1_DELAY_MAX) {
2940                         shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2941                 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2942                         shift_dq = -(int32_t)temp_dq_out1_delay;
2943                 }
2944                 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2945                            i, shift_dq);
2946                 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2947                 scc_mgr_load_dq(i);
2948
2949                 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2950                            left_edge[i] - shift_dq + (-mid_min),
2951                            right_edge[i] + shift_dq - (-mid_min));
2952                 /* To determine values for export structures */
2953                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2954                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2955
2956                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2957                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2958         }
2959
2960         /* Move DQS */
2961         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2962         writel(0, &sdr_scc_mgr->update);
2963
2964         /* Centre DM */
2965         debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2966
2967         /*
2968          * set the left and right edge of each bit to an illegal value,
2969          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2970          */
2971         left_edge[0]  = IO_IO_OUT1_DELAY_MAX + 1;
2972         right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2973         int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2974         int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2975         int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2976         int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2977         int32_t win_best = 0;
2978
2979         /* Search for the/part of the window with DM shift */
2980         for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
2981                 scc_mgr_apply_group_dm_out1_delay(write_group, d);
2982                 writel(0, &sdr_scc_mgr->update);
2983
2984                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2985                                                     PASS_ALL_BITS, &bit_chk,
2986                                                     0)) {
2987                         /* USE Set current end of the window */
2988                         end_curr = -d;
2989                         /*
2990                          * If a starting edge of our window has not been seen
2991                          * this is our current start of the DM window.
2992                          */
2993                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
2994                                 bgn_curr = -d;
2995
2996                         /*
2997                          * If current window is bigger than best seen.
2998                          * Set best seen to be current window.
2999                          */
3000                         if ((end_curr-bgn_curr+1) > win_best) {
3001                                 win_best = end_curr-bgn_curr+1;
3002                                 bgn_best = bgn_curr;
3003                                 end_best = end_curr;
3004                         }
3005                 } else {
3006                         /* We just saw a failing test. Reset temp edge */
3007                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3008                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3009                         }
3010                 }
3011
3012
3013         /* Reset DM delay chains to 0 */
3014         scc_mgr_apply_group_dm_out1_delay(write_group, 0);
3015
3016         /*
3017          * Check to see if the current window nudges up aganist 0 delay.
3018          * If so we need to continue the search by shifting DQS otherwise DQS
3019          * search begins as a new search. */
3020         if (end_curr != 0) {
3021                 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3022                 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3023         }
3024
3025         /* Search for the/part of the window with DQS shifts */
3026         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3027                 /*
3028                  * Note: This only shifts DQS, so are we limiting ourselve to
3029                  * width of DQ unnecessarily.
3030                  */
3031                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3032                                                         d + new_dqs);
3033
3034                 writel(0, &sdr_scc_mgr->update);
3035                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3036                                                     PASS_ALL_BITS, &bit_chk,
3037                                                     0)) {
3038                         /* USE Set current end of the window */
3039                         end_curr = d;
3040                         /*
3041                          * If a beginning edge of our window has not been seen
3042                          * this is our current begin of the DM window.
3043                          */
3044                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3045                                 bgn_curr = d;
3046
3047                         /*
3048                          * If current window is bigger than best seen. Set best
3049                          * seen to be current window.
3050                          */
3051                         if ((end_curr-bgn_curr+1) > win_best) {
3052                                 win_best = end_curr-bgn_curr+1;
3053                                 bgn_best = bgn_curr;
3054                                 end_best = end_curr;
3055                         }
3056                 } else {
3057                         /* We just saw a failing test. Reset temp edge */
3058                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3059                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3060
3061                         /* Early exit optimization: if ther remaining delay
3062                         chain space is less than already seen largest window
3063                         we can exit */
3064                         if ((win_best-1) >
3065                                 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3066                                         break;
3067                                 }
3068                         }
3069                 }
3070
3071         /* assign left and right edge for cal and reporting; */
3072         left_edge[0] = -1*bgn_best;
3073         right_edge[0] = end_best;
3074
3075         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3076                    __LINE__, left_edge[0], right_edge[0]);
3077
3078         /* Move DQS (back to orig) */
3079         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3080
3081         /* Move DM */
3082
3083         /* Find middle of window for the DM bit */
3084         mid = (left_edge[0] - right_edge[0]) / 2;
3085
3086         /* only move right, since we are not moving DQS/DQ */
3087         if (mid < 0)
3088                 mid = 0;
3089
3090         /* dm_marign should fail if we never find a window */
3091         if (win_best == 0)
3092                 dm_margin = -1;
3093         else
3094                 dm_margin = left_edge[0] - mid;
3095
3096         scc_mgr_apply_group_dm_out1_delay(write_group, mid);
3097         writel(0, &sdr_scc_mgr->update);
3098
3099         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3100                    dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3101                    right_edge[0], mid, dm_margin);
3102         /* Export values */
3103         gbl->fom_out += dq_margin + dqs_margin;
3104
3105         debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3106                    dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3107                    dq_margin, dqs_margin, dm_margin);
3108
3109         /*
3110          * Do not remove this line as it makes sure all of our
3111          * decisions have been applied.
3112          */
3113         writel(0, &sdr_scc_mgr->update);
3114         return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3115 }
3116
3117 /* calibrate the write operations */
3118 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3119         uint32_t test_bgn)
3120 {
3121         /* update info for sims */
3122         debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3123
3124         reg_file_set_stage(CAL_STAGE_WRITES);
3125         reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3126
3127         reg_file_set_group(g);
3128
3129         if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3130                 set_failing_group_stage(g, CAL_STAGE_WRITES,
3131                                         CAL_SUBSTAGE_WRITES_CENTER);
3132                 return 0;
3133         }
3134
3135         return 1;
3136 }
3137
3138 /* precharge all banks and activate row 0 in bank "000..." and bank "111..." */
3139 static void mem_precharge_and_activate(void)
3140 {
3141         uint32_t r;
3142
3143         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3144                 if (param->skip_ranks[r]) {
3145                         /* request to skip the rank */
3146                         continue;
3147                 }
3148
3149                 /* set rank */
3150                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3151
3152                 /* precharge all banks ... */
3153                 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3154                                              RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3155
3156                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3157                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3158                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3159
3160                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3161                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3162                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3163
3164                 /* activate rows */
3165                 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3166                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3167         }
3168 }
3169
3170 /* Configure various memory related parameters. */
3171 static void mem_config(void)
3172 {
3173         uint32_t rlat, wlat;
3174         uint32_t rw_wl_nop_cycles;
3175         uint32_t max_latency;
3176
3177         debug("%s:%d\n", __func__, __LINE__);
3178         /* read in write and read latency */
3179         wlat = readl(&data_mgr->t_wl_add);
3180         wlat += readl(&data_mgr->mem_t_add);
3181
3182         /* WL for hard phy does not include additive latency */
3183
3184         /*
3185          * add addtional write latency to offset the address/command extra
3186          * clock cycle. We change the AC mux setting causing AC to be delayed
3187          * by one mem clock cycle. Only do this for DDR3
3188          */
3189         wlat = wlat + 1;
3190
3191         rlat = readl(&data_mgr->t_rl_add);
3192
3193         rw_wl_nop_cycles = wlat - 2;
3194         gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
3195
3196         /*
3197          * For AV/CV, lfifo is hardened and always runs at full rate so
3198          * max latency in AFI clocks, used here, is correspondingly smaller.
3199          */
3200         max_latency = (1<<MAX_LATENCY_COUNT_WIDTH)/1 - 1;
3201         /* configure for a burst length of 8 */
3202
3203         /* write latency */
3204         /* Adjust Write Latency for Hard PHY */
3205         wlat = wlat + 1;
3206
3207         /* set a pretty high read latency initially */
3208         gbl->curr_read_lat = rlat + 16;
3209
3210         if (gbl->curr_read_lat > max_latency)
3211                 gbl->curr_read_lat = max_latency;
3212
3213         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3214
3215         /* advertise write latency */
3216         gbl->curr_write_lat = wlat;
3217         writel(wlat - 2, &phy_mgr_cfg->afi_wlat);
3218
3219         /* initialize bit slips */
3220         mem_precharge_and_activate();
3221 }
3222
3223 /* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */
3224 static void mem_skip_calibrate(void)
3225 {
3226         uint32_t vfifo_offset;
3227         uint32_t i, j, r;
3228
3229         debug("%s:%d\n", __func__, __LINE__);
3230         /* Need to update every shadow register set used by the interface */
3231         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3232                 r += NUM_RANKS_PER_SHADOW_REG) {
3233                 /*
3234                  * Set output phase alignment settings appropriate for
3235                  * skip calibration.
3236                  */
3237                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3238                         scc_mgr_set_dqs_en_phase(i, 0);
3239 #if IO_DLL_CHAIN_LENGTH == 6
3240                         scc_mgr_set_dqdqs_output_phase(i, 6);
3241 #else
3242                         scc_mgr_set_dqdqs_output_phase(i, 7);
3243 #endif
3244                         /*
3245                          * Case:33398
3246                          *
3247                          * Write data arrives to the I/O two cycles before write
3248                          * latency is reached (720 deg).
3249                          *   -> due to bit-slip in a/c bus
3250                          *   -> to allow board skew where dqs is longer than ck
3251                          *      -> how often can this happen!?
3252                          *      -> can claim back some ptaps for high freq
3253                          *       support if we can relax this, but i digress...
3254                          *
3255                          * The write_clk leads mem_ck by 90 deg
3256                          * The minimum ptap of the OPA is 180 deg
3257                          * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3258                          * The write_clk is always delayed by 2 ptaps
3259                          *
3260                          * Hence, to make DQS aligned to CK, we need to delay
3261                          * DQS by:
3262                          *    (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3263                          *
3264                          * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3265                          * gives us the number of ptaps, which simplies to:
3266                          *
3267                          *    (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3268                          */
3269                         scc_mgr_set_dqdqs_output_phase(i, (1.25 *
3270                                 IO_DLL_CHAIN_LENGTH - 2));
3271                 }
3272                 writel(0xff, &sdr_scc_mgr->dqs_ena);
3273                 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3274
3275                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3276                         writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3277                                   SCC_MGR_GROUP_COUNTER_OFFSET);
3278                 }
3279                 writel(0xff, &sdr_scc_mgr->dq_ena);
3280                 writel(0xff, &sdr_scc_mgr->dm_ena);
3281                 writel(0, &sdr_scc_mgr->update);
3282         }
3283
3284         /* Compensate for simulation model behaviour */
3285         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3286                 scc_mgr_set_dqs_bus_in_delay(i, 10);
3287                 scc_mgr_load_dqs(i);
3288         }
3289         writel(0, &sdr_scc_mgr->update);
3290
3291         /*
3292          * ArriaV has hard FIFOs that can only be initialized by incrementing
3293          * in sequencer.
3294          */
3295         vfifo_offset = CALIB_VFIFO_OFFSET;
3296         for (j = 0; j < vfifo_offset; j++) {
3297                 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3298         }
3299         writel(0, &phy_mgr_cmd->fifo_reset);
3300
3301         /*
3302          * For ACV with hard lfifo, we get the skip-cal setting from
3303          * generation-time constant.
3304          */
3305         gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3306         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3307 }
3308
3309 /* Memory calibration entry point */
3310 static uint32_t mem_calibrate(void)
3311 {
3312         uint32_t i;
3313         uint32_t rank_bgn, sr;
3314         uint32_t write_group, write_test_bgn;
3315         uint32_t read_group, read_test_bgn;
3316         uint32_t run_groups, current_run;
3317         uint32_t failing_groups = 0;
3318         uint32_t group_failed = 0;
3319         uint32_t sr_failed = 0;
3320
3321         debug("%s:%d\n", __func__, __LINE__);
3322         /* Initialize the data settings */
3323
3324         gbl->error_substage = CAL_SUBSTAGE_NIL;
3325         gbl->error_stage = CAL_STAGE_NIL;
3326         gbl->error_group = 0xff;
3327         gbl->fom_in = 0;
3328         gbl->fom_out = 0;
3329
3330         mem_config();
3331
3332         uint32_t bypass_mode = 0x1;
3333         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3334                 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3335                           SCC_MGR_GROUP_COUNTER_OFFSET);
3336                 scc_set_bypass_mode(i, bypass_mode);
3337         }
3338
3339         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3340                 /*
3341                  * Set VFIFO and LFIFO to instant-on settings in skip
3342                  * calibration mode.
3343                  */
3344                 mem_skip_calibrate();
3345         } else {
3346                 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3347                         /*
3348                          * Zero all delay chain/phase settings for all
3349                          * groups and all shadow register sets.
3350                          */
3351                         scc_mgr_zero_all();
3352
3353                         run_groups = ~param->skip_groups;
3354
3355                         for (write_group = 0, write_test_bgn = 0; write_group
3356                                 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3357                                 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3358                                 /* Initialized the group failure */
3359                                 group_failed = 0;
3360
3361                                 current_run = run_groups & ((1 <<
3362                                         RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3363                                 run_groups = run_groups >>
3364                                         RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3365
3366                                 if (current_run == 0)
3367                                         continue;
3368
3369                                 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3370                                                     SCC_MGR_GROUP_COUNTER_OFFSET);
3371                                 scc_mgr_zero_group(write_group, write_test_bgn,
3372                                                    0);
3373
3374                                 for (read_group = write_group *
3375                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
3376                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3377                                         read_test_bgn = 0;
3378                                         read_group < (write_group + 1) *
3379                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
3380                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3381                                         group_failed == 0;
3382                                         read_group++, read_test_bgn +=
3383                                         RW_MGR_MEM_DQ_PER_READ_DQS) {
3384                                         /* Calibrate the VFIFO */
3385                                         if (!((STATIC_CALIB_STEPS) &
3386                                                 CALIB_SKIP_VFIFO)) {
3387                                                 if (!rw_mgr_mem_calibrate_vfifo
3388                                                         (read_group,
3389                                                         read_test_bgn)) {
3390                                                         group_failed = 1;
3391
3392                                                         if (!(gbl->
3393                                                         phy_debug_mode_flags &
3394                                                 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3395                                                                 return 0;
3396                                                         }
3397                                                 }
3398                                         }
3399                                 }
3400
3401                                 /* Calibrate the output side */
3402                                 if (group_failed == 0)  {
3403                                         for (rank_bgn = 0, sr = 0; rank_bgn
3404                                                 < RW_MGR_MEM_NUMBER_OF_RANKS;
3405                                                 rank_bgn +=
3406                                                 NUM_RANKS_PER_SHADOW_REG,
3407                                                 ++sr) {
3408                                                 sr_failed = 0;
3409                                                 if (!((STATIC_CALIB_STEPS) &
3410                                                 CALIB_SKIP_WRITES)) {
3411                                                         if ((STATIC_CALIB_STEPS)
3412                                                 & CALIB_SKIP_DELAY_SWEEPS) {
3413                                                 /* not needed in quick mode! */
3414                                                         } else {
3415                                                 /*
3416                                                  * Determine if this set of
3417                                                  * ranks should be skipped
3418                                                  * entirely.
3419                                                  */
3420                                         if (!param->skip_shadow_regs[sr]) {
3421                                                 if (!rw_mgr_mem_calibrate_writes
3422                                                 (rank_bgn, write_group,
3423                                                 write_test_bgn)) {
3424                                                         sr_failed = 1;
3425                                                         if (!(gbl->
3426                                                         phy_debug_mode_flags &
3427                                                 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3428                                                                 return 0;
3429                                                                         }
3430                                                                         }
3431                                                                 }
3432                                                         }
3433                                                 }
3434                                                 if (sr_failed != 0)
3435                                                         group_failed = 1;
3436                                         }
3437                                 }
3438
3439                                 if (group_failed == 0) {
3440                                         for (read_group = write_group *
3441                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
3442                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3443                                         read_test_bgn = 0;
3444                                                 read_group < (write_group + 1)
3445                                                 * RW_MGR_MEM_IF_READ_DQS_WIDTH
3446                                                 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3447                                                 group_failed == 0;
3448                                                 read_group++, read_test_bgn +=
3449                                                 RW_MGR_MEM_DQ_PER_READ_DQS) {
3450                                                 if (!((STATIC_CALIB_STEPS) &
3451                                                         CALIB_SKIP_WRITES)) {
3452                                         if (!rw_mgr_mem_calibrate_vfifo_end
3453                                                 (read_group, read_test_bgn)) {
3454                                                         group_failed = 1;
3455
3456                                                 if (!(gbl->phy_debug_mode_flags
3457                                                 & PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3458                                                                 return 0;
3459                                                                 }
3460                                                         }
3461                                                 }
3462                                         }
3463                                 }
3464
3465                                 if (group_failed != 0)
3466                                         failing_groups++;
3467                         }
3468
3469                         /*
3470                          * USER If there are any failing groups then report
3471                          * the failure.
3472                          */
3473                         if (failing_groups != 0)
3474                                 return 0;
3475
3476                         /* Calibrate the LFIFO */
3477                         if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) {
3478                                 /*
3479                                  * If we're skipping groups as part of debug,
3480                                  * don't calibrate LFIFO.
3481                                  */
3482                                 if (param->skip_groups == 0) {
3483                                         if (!rw_mgr_mem_calibrate_lfifo())
3484                                                 return 0;
3485                                 }
3486                         }
3487                 }
3488         }
3489
3490         /*
3491          * Do not remove this line as it makes sure all of our decisions
3492          * have been applied.
3493          */
3494         writel(0, &sdr_scc_mgr->update);
3495         return 1;
3496 }
3497
3498 static uint32_t run_mem_calibrate(void)
3499 {
3500         uint32_t pass;
3501         uint32_t debug_info;
3502
3503         debug("%s:%d\n", __func__, __LINE__);
3504
3505         /* Reset pass/fail status shown on afi_cal_success/fail */
3506         writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3507
3508         /* stop tracking manger */
3509         uint32_t ctrlcfg = readl(&sdr_ctrl->ctrl_cfg);
3510
3511         writel(ctrlcfg & 0xFFBFFFFF, &sdr_ctrl->ctrl_cfg);
3512
3513         initialize();
3514         rw_mgr_mem_initialize();
3515
3516         pass = mem_calibrate();
3517
3518         mem_precharge_and_activate();
3519         writel(0, &phy_mgr_cmd->fifo_reset);
3520
3521         /*
3522          * Handoff:
3523          * Don't return control of the PHY back to AFI when in debug mode.
3524          */
3525         if ((gbl->phy_debug_mode_flags & PHY_DEBUG_IN_DEBUG_MODE) == 0) {
3526                 rw_mgr_mem_handoff();
3527                 /*
3528                  * In Hard PHY this is a 2-bit control:
3529                  * 0: AFI Mux Select
3530                  * 1: DDIO Mux Select
3531                  */
3532                 writel(0x2, &phy_mgr_cfg->mux_sel);
3533         }
3534
3535         writel(ctrlcfg, &sdr_ctrl->ctrl_cfg);
3536
3537         if (pass) {
3538                 printf("%s: CALIBRATION PASSED\n", __FILE__);
3539
3540                 gbl->fom_in /= 2;
3541                 gbl->fom_out /= 2;
3542
3543                 if (gbl->fom_in > 0xff)
3544                         gbl->fom_in = 0xff;
3545
3546                 if (gbl->fom_out > 0xff)
3547                         gbl->fom_out = 0xff;
3548
3549                 /* Update the FOM in the register file */
3550                 debug_info = gbl->fom_in;
3551                 debug_info |= gbl->fom_out << 8;
3552                 writel(debug_info, &sdr_reg_file->fom);
3553
3554                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3555                 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3556         } else {
3557                 printf("%s: CALIBRATION FAILED\n", __FILE__);
3558
3559                 debug_info = gbl->error_stage;
3560                 debug_info |= gbl->error_substage << 8;
3561                 debug_info |= gbl->error_group << 16;
3562
3563                 writel(debug_info, &sdr_reg_file->failing_stage);
3564                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3565                 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3566
3567                 /* Update the failing group/stage in the register file */
3568                 debug_info = gbl->error_stage;
3569                 debug_info |= gbl->error_substage << 8;
3570                 debug_info |= gbl->error_group << 16;
3571                 writel(debug_info, &sdr_reg_file->failing_stage);
3572         }
3573
3574         return pass;
3575 }
3576
3577 /**
3578  * hc_initialize_rom_data() - Initialize ROM data
3579  *
3580  * Initialize ROM data.
3581  */
3582 static void hc_initialize_rom_data(void)
3583 {
3584         u32 i, addr;
3585
3586         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3587         for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3588                 writel(inst_rom_init[i], addr + (i << 2));
3589
3590         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3591         for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3592                 writel(ac_rom_init[i], addr + (i << 2));
3593 }
3594
3595 /**
3596  * initialize_reg_file() - Initialize SDR register file
3597  *
3598  * Initialize SDR register file.
3599  */
3600 static void initialize_reg_file(void)
3601 {
3602         /* Initialize the register file with the correct data */
3603         writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3604         writel(0, &sdr_reg_file->debug_data_addr);
3605         writel(0, &sdr_reg_file->cur_stage);
3606         writel(0, &sdr_reg_file->fom);
3607         writel(0, &sdr_reg_file->failing_stage);
3608         writel(0, &sdr_reg_file->debug1);
3609         writel(0, &sdr_reg_file->debug2);
3610 }
3611
3612 /**
3613  * initialize_hps_phy() - Initialize HPS PHY
3614  *
3615  * Initialize HPS PHY.
3616  */
3617 static void initialize_hps_phy(void)
3618 {
3619         uint32_t reg;
3620         /*
3621          * Tracking also gets configured here because it's in the
3622          * same register.
3623          */
3624         uint32_t trk_sample_count = 7500;
3625         uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3626         /*
3627          * Format is number of outer loops in the 16 MSB, sample
3628          * count in 16 LSB.
3629          */
3630
3631         reg = 0;
3632         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3633         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3634         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3635         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3636         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3637         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3638         /*
3639          * This field selects the intrinsic latency to RDATA_EN/FULL path.
3640          * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3641          */
3642         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3643         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3644                 trk_sample_count);
3645         writel(reg, &sdr_ctrl->phy_ctrl0);
3646
3647         reg = 0;
3648         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3649                 trk_sample_count >>
3650                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3651         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3652                 trk_long_idle_sample_count);
3653         writel(reg, &sdr_ctrl->phy_ctrl1);
3654
3655         reg = 0;
3656         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3657                 trk_long_idle_sample_count >>
3658                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3659         writel(reg, &sdr_ctrl->phy_ctrl2);
3660 }
3661
3662 static void initialize_tracking(void)
3663 {
3664         uint32_t concatenated_longidle = 0x0;
3665         uint32_t concatenated_delays = 0x0;
3666         uint32_t concatenated_rw_addr = 0x0;
3667         uint32_t concatenated_refresh = 0x0;
3668         uint32_t trk_sample_count = 7500;
3669         uint32_t dtaps_per_ptap;
3670         uint32_t tmp_delay;
3671
3672         /*
3673          * compute usable version of value in case we skip full
3674          * computation later
3675          */
3676         dtaps_per_ptap = 0;
3677         tmp_delay = 0;
3678         while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
3679                 dtaps_per_ptap++;
3680                 tmp_delay += IO_DELAY_PER_DCHAIN_TAP;
3681         }
3682         dtaps_per_ptap--;
3683
3684         concatenated_longidle = concatenated_longidle ^ 10;
3685                 /*longidle outer loop */
3686         concatenated_longidle = concatenated_longidle << 16;
3687         concatenated_longidle = concatenated_longidle ^ 100;
3688                 /*longidle sample count */
3689         concatenated_delays = concatenated_delays ^ 243;
3690                 /* trfc, worst case of 933Mhz 4Gb */
3691         concatenated_delays = concatenated_delays << 8;
3692         concatenated_delays = concatenated_delays ^ 14;
3693                 /* trcd, worst case */
3694         concatenated_delays = concatenated_delays << 8;
3695         concatenated_delays = concatenated_delays ^ 10;
3696                 /* vfifo wait */
3697         concatenated_delays = concatenated_delays << 8;
3698         concatenated_delays = concatenated_delays ^ 4;
3699                 /* mux delay */
3700
3701         concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_IDLE;
3702         concatenated_rw_addr = concatenated_rw_addr << 8;
3703         concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_ACTIVATE_1;
3704         concatenated_rw_addr = concatenated_rw_addr << 8;
3705         concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_SGLE_READ;
3706         concatenated_rw_addr = concatenated_rw_addr << 8;
3707         concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_PRECHARGE_ALL;
3708
3709         concatenated_refresh = concatenated_refresh ^ RW_MGR_REFRESH_ALL;
3710         concatenated_refresh = concatenated_refresh << 24;
3711         concatenated_refresh = concatenated_refresh ^ 1000; /* trefi */
3712
3713         /* Initialize the register file with the correct data */
3714         writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
3715         writel(trk_sample_count, &sdr_reg_file->trk_sample_count);
3716         writel(concatenated_longidle, &sdr_reg_file->trk_longidle);
3717         writel(concatenated_delays, &sdr_reg_file->delays);
3718         writel(concatenated_rw_addr, &sdr_reg_file->trk_rw_mgr_addr);
3719         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, &sdr_reg_file->trk_read_dqs_width);
3720         writel(concatenated_refresh, &sdr_reg_file->trk_rfsh);
3721 }
3722
3723 int sdram_calibration_full(void)
3724 {
3725         struct param_type my_param;
3726         struct gbl_type my_gbl;
3727         uint32_t pass;
3728         uint32_t i;
3729
3730         param = &my_param;
3731         gbl = &my_gbl;
3732
3733         /* Initialize the debug mode flags */
3734         gbl->phy_debug_mode_flags = 0;
3735         /* Set the calibration enabled by default */
3736         gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3737         /*
3738          * Only sweep all groups (regardless of fail state) by default
3739          * Set enabled read test by default.
3740          */
3741 #if DISABLE_GUARANTEED_READ
3742         gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3743 #endif
3744         /* Initialize the register file */
3745         initialize_reg_file();
3746
3747         /* Initialize any PHY CSR */
3748         initialize_hps_phy();
3749
3750         scc_mgr_initialize();
3751
3752         initialize_tracking();
3753
3754         /* USER Enable all ranks, groups */
3755         for (i = 0; i < RW_MGR_MEM_NUMBER_OF_RANKS; i++)
3756                 param->skip_ranks[i] = 0;
3757         for (i = 0; i < NUM_SHADOW_REGS; ++i)
3758                 param->skip_shadow_regs[i] = 0;
3759         param->skip_groups = 0;
3760
3761         printf("%s: Preparing to start memory calibration\n", __FILE__);
3762
3763         debug("%s:%d\n", __func__, __LINE__);
3764         debug_cond(DLEVEL == 1,
3765                    "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3766                    RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3767                    RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3768                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3769                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3770         debug_cond(DLEVEL == 1,
3771                    "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3772                    RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3773                    RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3774                    IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3775         debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3776                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3777         debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3778                    IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3779                    IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3780         debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3781                    IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3782                    IO_IO_OUT2_DELAY_MAX);
3783         debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3784                    IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3785
3786         hc_initialize_rom_data();
3787
3788         /* update info for sims */
3789         reg_file_set_stage(CAL_STAGE_NIL);
3790         reg_file_set_group(0);
3791
3792         /*
3793          * Load global needed for those actions that require
3794          * some dynamic calibration support.
3795          */
3796         dyn_calib_steps = STATIC_CALIB_STEPS;
3797         /*
3798          * Load global to allow dynamic selection of delay loop settings
3799          * based on calibration mode.
3800          */
3801         if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3802                 skip_delay_mask = 0xff;
3803         else
3804                 skip_delay_mask = 0x0;
3805
3806         pass = run_mem_calibrate();
3807
3808         printf("%s: Calibration complete\n", __FILE__);
3809         return pass;
3810 }