2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
10 #define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \
11 / rwcfg->mem_if_write_dqs_width)
12 #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \
13 / rwcfg->mem_if_write_dqs_width)
15 #define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \
16 / rwcfg->mem_if_write_dqs_width)
17 #define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS)
19 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
20 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400
21 #define RW_MGR_RESET_READ_DATAPATH_OFFSET 0x1000
22 #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET 0x1400
23 #define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800
24 #define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00
26 #define NUM_SHADOW_REGS 1
28 #define RW_MGR_RANK_NONE 0xFF
29 #define RW_MGR_RANK_ALL 0x00
31 #define RW_MGR_ODT_MODE_OFF 0
32 #define RW_MGR_ODT_MODE_READ_WRITE 1
34 #define NUM_CALIB_REPEAT 1
36 #define NUM_READ_TESTS 7
37 #define NUM_READ_PB_TESTS 7
38 #define NUM_WRITE_TESTS 15
39 #define NUM_WRITE_PB_TESTS 31
41 #define PASS_ALL_BITS 1
42 #define PASS_ONE_BIT 0
44 /* calibration stages */
45 #define CAL_STAGE_NIL 0
46 #define CAL_STAGE_VFIFO 1
47 #define CAL_STAGE_WLEVEL 2
48 #define CAL_STAGE_LFIFO 3
49 #define CAL_STAGE_WRITES 4
50 #define CAL_STAGE_FULLTEST 5
51 #define CAL_STAGE_REFRESH 6
52 #define CAL_STAGE_CAL_SKIPPED 7
53 #define CAL_STAGE_CAL_ABORTED 8
54 #define CAL_STAGE_VFIFO_AFTER_WRITES 9
56 /* calibration substages */
57 #define CAL_SUBSTAGE_NIL 0
58 #define CAL_SUBSTAGE_GUARANTEED_READ 1
59 #define CAL_SUBSTAGE_DQS_EN_PHASE 2
60 #define CAL_SUBSTAGE_VFIFO_CENTER 3
61 #define CAL_SUBSTAGE_WORKING_DELAY 1
62 #define CAL_SUBSTAGE_LAST_WORKING_DELAY 2
63 #define CAL_SUBSTAGE_WLEVEL_COPY 3
64 #define CAL_SUBSTAGE_WRITES_CENTER 1
65 #define CAL_SUBSTAGE_READ_LATENCY 1
66 #define CAL_SUBSTAGE_REFRESH 1
68 #define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000
69 #define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100
70 #define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200
71 #define SCC_MGR_DQS_EN_DELAY_OFFSET 0x0300
72 #define SCC_MGR_DQDQS_OUT_PHASE_OFFSET 0x0400
73 #define SCC_MGR_OCT_OUT1_DELAY_OFFSET 0x0500
74 #define SCC_MGR_IO_OUT1_DELAY_OFFSET 0x0700
75 #define SCC_MGR_IO_IN_DELAY_OFFSET 0x0900
77 /* HHP-HPS-specific versions of some commands */
78 #define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET 0x0600
79 #define SCC_MGR_IO_OE_DELAY_OFFSET 0x0800
80 #define SCC_MGR_HHP_GLOBALS_OFFSET 0x0A00
81 #define SCC_MGR_HHP_RFILE_OFFSET 0x0B00
82 #define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00
84 #define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0)
85 #define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000)
86 #define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000)
87 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000)
88 #define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800)
90 #define PHY_MGR_CAL_RESET (0)
91 #define PHY_MGR_CAL_SUCCESS (1)
92 #define PHY_MGR_CAL_FAIL (2)
94 #define CALIB_SKIP_DELAY_LOOPS (1 << 0)
95 #define CALIB_SKIP_ALL_BITS_CHK (1 << 1)
96 #define CALIB_SKIP_DELAY_SWEEPS (1 << 2)
97 #define CALIB_SKIP_VFIFO (1 << 3)
98 #define CALIB_SKIP_LFIFO (1 << 4)
99 #define CALIB_SKIP_WLEVEL (1 << 5)
100 #define CALIB_SKIP_WRITES (1 << 6)
101 #define CALIB_SKIP_FULL_TEST (1 << 7)
102 #define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \
103 CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
104 CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
105 #define CALIB_IN_RTL_SIM (1 << 8)
107 /* Scan chain manager command addresses */
108 #define READ_SCC_OCT_OUT2_DELAY 0
109 #define READ_SCC_DQ_OUT2_DELAY 0
110 #define READ_SCC_DQS_IO_OUT2_DELAY 0
111 #define READ_SCC_DM_IO_OUT2_DELAY 0
113 /* HHP-HPS-specific values */
114 #define SCC_MGR_HHP_EXTRAS_OFFSET 0
115 #define SCC_MGR_HHP_DQSE_MAP_OFFSET 1
117 /* PHY Debug mode flag constants */
118 #define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
119 #define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
120 #define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
121 #define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
122 #define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
123 #define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
125 struct socfpga_sdr_rw_load_manager {
132 struct socfpga_sdr_rw_load_jump_manager {
139 struct socfpga_sdr_reg_file {
148 u32 trk_sample_count;
152 u32 trk_read_dqs_width;
156 /* parameter variable holder */
158 u32 read_correct_mask;
159 u32 read_correct_mask_vg;
160 u32 write_correct_mask;
161 u32 write_correct_mask_vg;
165 /* global variable holder */
167 uint32_t phy_debug_mode_flags;
169 /* current read latency */
171 uint32_t curr_read_lat;
175 uint32_t error_substage;
176 uint32_t error_stage;
177 uint32_t error_group;
179 /* figure-of-merit in, figure-of-merit out */
184 /*USER Number of RW Mgr NOP cycles between
185 write command and write data */
186 uint32_t rw_wl_nop_cycles;
189 struct socfpga_sdr_scc_mgr {
200 /* PHY manager configuration registers. */
201 struct socfpga_phy_mgr_cfg {
207 u32 vfifo_rd_en_ovrd;
212 /* PHY manager command addresses. */
213 struct socfpga_phy_mgr_cmd {
215 u32 inc_vfifo_hard_phy;
221 struct socfpga_data_mgr {
227 #endif /* _SEQUENCER_H_ */