git.sur5r.net Git - u-boot/blob - drivers/ddr/fsl/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  */
  12
  13 #include <common.h>
  14 #include <fsl_ddr_sdram.h>
  15 #include <fsl_errata.h>
  16 #include <fsl_ddr.h>
  17 #include <fsl_immap.h>
  18 #include <asm/io.h>
  19 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
  20         defined(CONFIG_ARM)
  21 #include <asm/arch/clock.h>
  22 #endif
  23
  24 /*
  25  * Determine Rtt value.
  26  *
  27  * This should likely be either board or controller specific.
  28  *
  29  * Rtt(nominal) - DDR2:
  30  *      0 = Rtt disabled
  31  *      1 = 75 ohm
  32  *      2 = 150 ohm
  33  *      3 = 50 ohm
  34  * Rtt(nominal) - DDR3:
  35  *      0 = Rtt disabled
  36  *      1 = 60 ohm
  37  *      2 = 120 ohm
  38  *      3 = 40 ohm
  39  *      4 = 20 ohm
  40  *      5 = 30 ohm
  41  *
  42  * FIXME: Apparently 8641 needs a value of 2
  43  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  44  *
  45  * FIXME: There was some effort down this line earlier:
  46  *
  47  *      unsigned int i;
  48  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  49  *              if (popts->dimmslot[i].num_valid_cs
  50  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  51  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  52  *                      rtt = 2;
  53  *                      break;
  54  *              }
  55  *      }
  56  */
  57 static inline int fsl_ddr_get_rtt(void)
  58 {
  59         int rtt;
  60
  61 #if defined(CONFIG_SYS_FSL_DDR1)
  62         rtt = 0;
  63 #elif defined(CONFIG_SYS_FSL_DDR2)
  64         rtt = 3;
  65 #else
  66         rtt = 0;
  67 #endif
  68
  69         return rtt;
  70 }
  71
  72 #ifdef CONFIG_SYS_FSL_DDR4
  73 /*
  74  * compute CAS write latency according to DDR4 spec
  75  * CWL = 9 for <= 1600MT/s
  76  *       10 for <= 1866MT/s
  77  *       11 for <= 2133MT/s
  78  *       12 for <= 2400MT/s
  79  *       14 for <= 2667MT/s
  80  *       16 for <= 2933MT/s
  81  *       18 for higher
  82  */
  83 static inline unsigned int compute_cas_write_latency(
  84                                 const unsigned int ctrl_num)
  85 {
  86         unsigned int cwl;
  87         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  88         if (mclk_ps >= 1250)
  89                 cwl = 9;
  90         else if (mclk_ps >= 1070)
  91                 cwl = 10;
  92         else if (mclk_ps >= 935)
  93                 cwl = 11;
  94         else if (mclk_ps >= 833)
  95                 cwl = 12;
  96         else if (mclk_ps >= 750)
  97                 cwl = 14;
  98         else if (mclk_ps >= 681)
  99                 cwl = 16;
 100         else
 101                 cwl = 18;
 102
 103         return cwl;
 104 }
 105 #else
 106 /*
 107  * compute the CAS write latency according to DDR3 spec
 108  * CWL = 5 if tCK >= 2.5ns
 109  *       6 if 2.5ns > tCK >= 1.875ns
 110  *       7 if 1.875ns > tCK >= 1.5ns
 111  *       8 if 1.5ns > tCK >= 1.25ns
 112  *       9 if 1.25ns > tCK >= 1.07ns
 113  *       10 if 1.07ns > tCK >= 0.935ns
 114  *       11 if 0.935ns > tCK >= 0.833ns
 115  *       12 if 0.833ns > tCK >= 0.75ns
 116  */
 117 static inline unsigned int compute_cas_write_latency(
 118                                 const unsigned int ctrl_num)
 119 {
 120         unsigned int cwl;
 121         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 122
 123         if (mclk_ps >= 2500)
 124                 cwl = 5;
 125         else if (mclk_ps >= 1875)
 126                 cwl = 6;
 127         else if (mclk_ps >= 1500)
 128                 cwl = 7;
 129         else if (mclk_ps >= 1250)
 130                 cwl = 8;
 131         else if (mclk_ps >= 1070)
 132                 cwl = 9;
 133         else if (mclk_ps >= 935)
 134                 cwl = 10;
 135         else if (mclk_ps >= 833)
 136                 cwl = 11;
 137         else if (mclk_ps >= 750)
 138                 cwl = 12;
 139         else {
 140                 cwl = 12;
 141                 printf("Warning: CWL is out of range\n");
 142         }
 143         return cwl;
 144 }
 145 #endif
 146
 147 /* Chip Select Configuration (CSn_CONFIG) */
 148 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 149                                const memctl_options_t *popts,
 150                                const dimm_params_t *dimm_params)
 151 {
 152         unsigned int cs_n_en = 0; /* Chip Select enable */
 153         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 154         unsigned int intlv_ctl = 0; /* Interleaving control */
 155         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 156         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 157         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 158         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 159         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 160         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 161         int go_config = 0;
 162 #ifdef CONFIG_SYS_FSL_DDR4
 163         unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
 164 #else
 165         unsigned int n_banks_per_sdram_device;
 166 #endif
 167
 168         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 169         switch (i) {
 170         case 0:
 171                 if (dimm_params[dimm_number].n_ranks > 0) {
 172                         go_config = 1;
 173                         /* These fields only available in CS0_CONFIG */
 174                         if (!popts->memctl_interleaving)
 175                                 break;
 176                         switch (popts->memctl_interleaving_mode) {
 177                         case FSL_DDR_256B_INTERLEAVING:
 178                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 179                         case FSL_DDR_PAGE_INTERLEAVING:
 180                         case FSL_DDR_BANK_INTERLEAVING:
 181                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 182                                 intlv_en = popts->memctl_interleaving;
 183                                 intlv_ctl = popts->memctl_interleaving_mode;
 184                                 break;
 185                         default:
 186                                 break;
 187                         }
 188                 }
 189                 break;
 190         case 1:
 191                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 192                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 193                         go_config = 1;
 194                 break;
 195         case 2:
 196                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 197                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 198                         go_config = 1;
 199                 break;
 200         case 3:
 201                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 202                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 203                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 204                         go_config = 1;
 205                 break;
 206         default:
 207                 break;
 208         }
 209         if (go_config) {
 210                 cs_n_en = 1;
 211                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 212                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 213                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 214 #ifdef CONFIG_SYS_FSL_DDR4
 215                 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
 216                 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
 217 #else
 218                 n_banks_per_sdram_device
 219                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 220                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 221 #endif
 222                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 223                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 224         }
 225         ddr->cs[i].config = (0
 226                 | ((cs_n_en & 0x1) << 31)
 227                 | ((intlv_en & 0x3) << 29)
 228                 | ((intlv_ctl & 0xf) << 24)
 229                 | ((ap_n_en & 0x1) << 23)
 230
 231                 /* XXX: some implementation only have 1 bit starting at left */
 232                 | ((odt_rd_cfg & 0x7) << 20)
 233
 234                 /* XXX: Some implementation only have 1 bit starting at left */
 235                 | ((odt_wr_cfg & 0x7) << 16)
 236
 237                 | ((ba_bits_cs_n & 0x3) << 14)
 238                 | ((row_bits_cs_n & 0x7) << 8)
 239 #ifdef CONFIG_SYS_FSL_DDR4
 240                 | ((bg_bits_cs_n & 0x3) << 4)
 241 #endif
 242                 | ((col_bits_cs_n & 0x7) << 0)
 243                 );
 244         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 245 }
 246
 247 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 248 /* FIXME: 8572 */
 249 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 250 {
 251         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 252
 253         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 254         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 255 }
 256
 257 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 258
 259 #if !defined(CONFIG_SYS_FSL_DDR1)
 260 /*
 261  * Check DIMM configuration, return 2 if quad-rank or two dual-rank
 262  * Return 1 if other two slots configuration. Return 0 if single slot.
 263  */
 264 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 265 {
 266 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 267         if (dimm_params[0].n_ranks == 4)
 268                 return 2;
 269 #endif
 270
 271 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 272         if ((dimm_params[0].n_ranks == 2) &&
 273                 (dimm_params[1].n_ranks == 2))
 274                 return 2;
 275
 276 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 277         if (dimm_params[0].n_ranks == 4)
 278                 return 2;
 279 #endif
 280
 281         if ((dimm_params[0].n_ranks != 0) &&
 282             (dimm_params[2].n_ranks != 0))
 283                 return 1;
 284 #endif
 285         return 0;
 286 }
 287
 288 /*
 289  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 290  *
 291  * Avoid writing for DDR I.  The new PQ38 DDR controller
 292  * dreams up non-zero default values to be backwards compatible.
 293  */
 294 static void set_timing_cfg_0(const unsigned int ctrl_num,
 295                                 fsl_ddr_cfg_regs_t *ddr,
 296                                 const memctl_options_t *popts,
 297                                 const dimm_params_t *dimm_params)
 298 {
 299         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 300         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 301         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 302         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 303         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 304
 305         /* Active powerdown exit timing (tXARD and tXARDS). */
 306         unsigned char act_pd_exit_mclk;
 307         /* Precharge powerdown exit timing (tXP). */
 308         unsigned char pre_pd_exit_mclk;
 309         /* ODT powerdown exit timing (tAXPD). */
 310         unsigned char taxpd_mclk = 0;
 311         /* Mode register set cycle time (tMRD). */
 312         unsigned char tmrd_mclk;
 313 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
 314         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 315 #endif
 316
 317 #ifdef CONFIG_SYS_FSL_DDR4
 318         /* tXP=max(4nCK, 6ns) */
 319         int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
 320         unsigned int data_rate = get_ddr_freq(ctrl_num);
 321
 322         /* for faster clock, need more time for data setup */
 323         trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
 324
 325         /*
 326          * for single quad-rank DIMM and two-slot DIMMs
 327          * to avoid ODT overlap
 328          */
 329         switch (avoid_odt_overlap(dimm_params)) {
 330         case 2:
 331                 twrt_mclk = 2;
 332                 twwt_mclk = 2;
 333                 trrt_mclk = 2;
 334                 break;
 335         default:
 336                 twrt_mclk = 1;
 337                 twwt_mclk = 1;
 338                 trrt_mclk = 0;
 339                 break;
 340         }
 341
 342         act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 343         pre_pd_exit_mclk = act_pd_exit_mclk;
 344         /*
 345          * MRS_CYC = max(tMRD, tMOD)
 346          * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
 347          */
 348         tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
 349 #elif defined(CONFIG_SYS_FSL_DDR3)
 350         unsigned int data_rate = get_ddr_freq(ctrl_num);
 351         int txp;
 352         unsigned int ip_rev;
 353         int odt_overlap;
 354         /*
 355          * (tXARD and tXARDS). Empirical?
 356          * The DDR3 spec has not tXARD,
 357          * we use the tXP instead of it.
 358          * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
 359          *     max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
 360          * spec has not the tAXPD, we use
 361          * tAXPD=1, need design to confirm.
 362          */
 363         txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
 364
 365         ip_rev = fsl_ddr_get_version(ctrl_num);
 366         if (ip_rev >= 0x40700) {
 367                 /*
 368                  * MRS_CYC = max(tMRD, tMOD)
 369                  * tMRD = 4nCK (8nCK for RDIMM)
 370                  * tMOD = max(12nCK, 15ns)
 371                  */
 372                 tmrd_mclk = max((unsigned int)12,
 373                                 picos_to_mclk(ctrl_num, 15000));
 374         } else {
 375                 /*
 376                  * MRS_CYC = tMRD
 377                  * tMRD = 4nCK (8nCK for RDIMM)
 378                  */
 379                 if (popts->registered_dimm_en)
 380                         tmrd_mclk = 8;
 381                 else
 382                         tmrd_mclk = 4;
 383         }
 384
 385         /* set the turnaround time */
 386
 387         /*
 388          * for single quad-rank DIMM and two-slot DIMMs
 389          * to avoid ODT overlap
 390          */
 391         odt_overlap = avoid_odt_overlap(dimm_params);
 392         switch (odt_overlap) {
 393         case 2:
 394                 twwt_mclk = 2;
 395                 trrt_mclk = 1;
 396                 break;
 397         case 1:
 398                 twwt_mclk = 1;
 399                 trrt_mclk = 0;
 400                 break;
 401         default:
 402                 break;
 403         }
 404
 405         /* for faster clock, need more time for data setup */
 406         trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 407
 408         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 409                 twrt_mclk = 1;
 410
 411         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 412                 act_pd_exit_mclk = 1;
 413                 pre_pd_exit_mclk = 1;
 414                 taxpd_mclk = 1;
 415         } else {
 416                 /* act_pd_exit_mclk = tXARD, see above */
 417                 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 418                 /* Mode register MR0[A12] is '1' - fast exit */
 419                 pre_pd_exit_mclk = act_pd_exit_mclk;
 420                 taxpd_mclk = 1;
 421         }
 422 #else /* CONFIG_SYS_FSL_DDR2 */
 423         /*
 424          * (tXARD and tXARDS). Empirical?
 425          * tXARD = 2 for DDR2
 426          * tXP=2
 427          * tAXPD=8
 428          */
 429         act_pd_exit_mclk = 2;
 430         pre_pd_exit_mclk = 2;
 431         taxpd_mclk = 8;
 432         tmrd_mclk = 2;
 433 #endif
 434
 435         if (popts->trwt_override)
 436                 trwt_mclk = popts->trwt;
 437
 438         ddr->timing_cfg_0 = (0
 439                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 440                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 441                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 442                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 443                 | ((act_pd_exit_mclk & 0xf) << 20)  /* ACT_PD_EXIT */
 444                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 445                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 446                 | ((tmrd_mclk & 0x1f) << 0)     /* MRS_CYC */
 447                 );
 448         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 449 }
 450 #endif  /* !defined(CONFIG_SYS_FSL_DDR1) */
 451
 452 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 453 static void set_timing_cfg_3(const unsigned int ctrl_num,
 454                              fsl_ddr_cfg_regs_t *ddr,
 455                              const memctl_options_t *popts,
 456                              const common_timing_params_t *common_dimm,
 457                              unsigned int cas_latency,
 458                              unsigned int additive_latency)
 459 {
 460         /* Extended precharge to activate interval (tRP) */
 461         unsigned int ext_pretoact = 0;
 462         /* Extended Activate to precharge interval (tRAS) */
 463         unsigned int ext_acttopre = 0;
 464         /* Extended activate to read/write interval (tRCD) */
 465         unsigned int ext_acttorw = 0;
 466         /* Extended refresh recovery time (tRFC) */
 467         unsigned int ext_refrec;
 468         /* Extended MCAS latency from READ cmd */
 469         unsigned int ext_caslat = 0;
 470         /* Extended additive latency */
 471         unsigned int ext_add_lat = 0;
 472         /* Extended last data to precharge interval (tWR) */
 473         unsigned int ext_wrrec = 0;
 474         /* Control Adjust */
 475         unsigned int cntl_adj = 0;
 476
 477         ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
 478         ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
 479         ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
 480         ext_caslat = (2 * cas_latency - 1) >> 4;
 481         ext_add_lat = additive_latency >> 4;
 482 #ifdef CONFIG_SYS_FSL_DDR4
 483         ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
 484 #else
 485         ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
 486         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 487 #endif
 488         ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
 489                 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 490
 491         ddr->timing_cfg_3 = (0
 492                 | ((ext_pretoact & 0x1) << 28)
 493                 | ((ext_acttopre & 0x3) << 24)
 494                 | ((ext_acttorw & 0x1) << 22)
 495                 | ((ext_refrec & 0x1F) << 16)
 496                 | ((ext_caslat & 0x3) << 12)
 497                 | ((ext_add_lat & 0x1) << 10)
 498                 | ((ext_wrrec & 0x1) << 8)
 499                 | ((cntl_adj & 0x7) << 0)
 500                 );
 501         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 502 }
 503
 504 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 505 static void set_timing_cfg_1(const unsigned int ctrl_num,
 506                              fsl_ddr_cfg_regs_t *ddr,
 507                              const memctl_options_t *popts,
 508                              const common_timing_params_t *common_dimm,
 509                              unsigned int cas_latency)
 510 {
 511         /* Precharge-to-activate interval (tRP) */
 512         unsigned char pretoact_mclk;
 513         /* Activate to precharge interval (tRAS) */
 514         unsigned char acttopre_mclk;
 515         /*  Activate to read/write interval (tRCD) */
 516         unsigned char acttorw_mclk;
 517         /* CASLAT */
 518         unsigned char caslat_ctrl;
 519         /*  Refresh recovery time (tRFC) ; trfc_low */
 520         unsigned char refrec_ctrl;
 521         /* Last data to precharge minimum interval (tWR) */
 522         unsigned char wrrec_mclk;
 523         /* Activate-to-activate interval (tRRD) */
 524         unsigned char acttoact_mclk;
 525         /* Last write data pair to read command issue interval (tWTR) */
 526         unsigned char wrtord_mclk;
 527 #ifdef CONFIG_SYS_FSL_DDR4
 528         /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
 529         static const u8 wrrec_table[] = {
 530                 10, 10, 10, 10, 10,
 531                 10, 10, 10, 10, 10,
 532                 12, 12, 14, 14, 16,
 533                 16, 18, 18, 20, 20,
 534                 24, 24, 24, 24};
 535 #else
 536         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 537         static const u8 wrrec_table[] = {
 538                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 539 #endif
 540
 541         pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
 542         acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
 543         acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
 544
 545         /*
 546          * Translate CAS Latency to a DDR controller field value:
 547          *
 548          *      CAS Lat DDR I   DDR II  Ctrl
 549          *      Clocks  SPD Bit SPD Bit Value
 550          *      ------- ------- ------- -----
 551          *      1.0     0               0001
 552          *      1.5     1               0010
 553          *      2.0     2       2       0011
 554          *      2.5     3               0100
 555          *      3.0     4       3       0101
 556          *      3.5     5               0110
 557          *      4.0             4       0111
 558          *      4.5                     1000
 559          *      5.0             5       1001
 560          */
 561 #if defined(CONFIG_SYS_FSL_DDR1)
 562         caslat_ctrl = (cas_latency + 1) & 0x07;
 563 #elif defined(CONFIG_SYS_FSL_DDR2)
 564         caslat_ctrl = 2 * cas_latency - 1;
 565 #else
 566         /*
 567          * if the CAS latency more than 8 cycle,
 568          * we need set extend bit for it at
 569          * TIMING_CFG_3[EXT_CASLAT]
 570          */
 571         if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
 572                 caslat_ctrl = 2 * cas_latency - 1;
 573         else
 574                 caslat_ctrl = (cas_latency - 1) << 1;
 575 #endif
 576
 577 #ifdef CONFIG_SYS_FSL_DDR4
 578         refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
 579         wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 580         acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
 581         wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
 582         if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
 583                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 584         else
 585                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 586 #else
 587         refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
 588         wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 589         acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
 590         wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
 591         if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
 592                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 593         else
 594                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 595 #endif
 596         if (popts->otf_burst_chop_en)
 597                 wrrec_mclk += 2;
 598
 599         /*
 600          * JEDEC has min requirement for tRRD
 601          */
 602 #if defined(CONFIG_SYS_FSL_DDR3)
 603         if (acttoact_mclk < 4)
 604                 acttoact_mclk = 4;
 605 #endif
 606         /*
 607          * JEDEC has some min requirements for tWTR
 608          */
 609 #if defined(CONFIG_SYS_FSL_DDR2)
 610         if (wrtord_mclk < 2)
 611                 wrtord_mclk = 2;
 612 #elif defined(CONFIG_SYS_FSL_DDR3)
 613         if (wrtord_mclk < 4)
 614                 wrtord_mclk = 4;
 615 #endif
 616         if (popts->otf_burst_chop_en)
 617                 wrtord_mclk += 2;
 618
 619         ddr->timing_cfg_1 = (0
 620                 | ((pretoact_mclk & 0x0F) << 28)
 621                 | ((acttopre_mclk & 0x0F) << 24)
 622                 | ((acttorw_mclk & 0xF) << 20)
 623                 | ((caslat_ctrl & 0xF) << 16)
 624                 | ((refrec_ctrl & 0xF) << 12)
 625                 | ((wrrec_mclk & 0x0F) << 8)
 626                 | ((acttoact_mclk & 0x0F) << 4)
 627                 | ((wrtord_mclk & 0x0F) << 0)
 628                 );
 629         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 630 }
 631
 632 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 633 static void set_timing_cfg_2(const unsigned int ctrl_num,
 634                              fsl_ddr_cfg_regs_t *ddr,
 635                              const memctl_options_t *popts,
 636                              const common_timing_params_t *common_dimm,
 637                              unsigned int cas_latency,
 638                              unsigned int additive_latency)
 639 {
 640         /* Additive latency */
 641         unsigned char add_lat_mclk;
 642         /* CAS-to-preamble override */
 643         unsigned short cpo;
 644         /* Write latency */
 645         unsigned char wr_lat;
 646         /*  Read to precharge (tRTP) */
 647         unsigned char rd_to_pre;
 648         /* Write command to write data strobe timing adjustment */
 649         unsigned char wr_data_delay;
 650         /* Minimum CKE pulse width (tCKE) */
 651         unsigned char cke_pls;
 652         /* Window for four activates (tFAW) */
 653         unsigned short four_act;
 654 #ifdef CONFIG_SYS_FSL_DDR3
 655         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 656 #endif
 657
 658         /* FIXME add check that this must be less than acttorw_mclk */
 659         add_lat_mclk = additive_latency;
 660         cpo = popts->cpo_override;
 661
 662 #if defined(CONFIG_SYS_FSL_DDR1)
 663         /*
 664          * This is a lie.  It should really be 1, but if it is
 665          * set to 1, bits overlap into the old controller's
 666          * otherwise unused ACSM field.  If we leave it 0, then
 667          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 668          */
 669         wr_lat = 0;
 670 #elif defined(CONFIG_SYS_FSL_DDR2)
 671         wr_lat = cas_latency - 1;
 672 #else
 673         wr_lat = compute_cas_write_latency(ctrl_num);
 674 #endif
 675
 676 #ifdef CONFIG_SYS_FSL_DDR4
 677         rd_to_pre = picos_to_mclk(ctrl_num, 7500);
 678 #else
 679         rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
 680 #endif
 681         /*
 682          * JEDEC has some min requirements for tRTP
 683          */
 684 #if defined(CONFIG_SYS_FSL_DDR2)
 685         if (rd_to_pre  < 2)
 686                 rd_to_pre  = 2;
 687 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 688         if (rd_to_pre < 4)
 689                 rd_to_pre = 4;
 690 #endif
 691         if (popts->otf_burst_chop_en)
 692                 rd_to_pre += 2; /* according to UM */
 693
 694         wr_data_delay = popts->write_data_delay;
 695 #ifdef CONFIG_SYS_FSL_DDR4
 696         cpo = 0;
 697         cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
 698 #elif defined(CONFIG_SYS_FSL_DDR3)
 699         /*
 700          * cke pulse = max(3nCK, 7.5ns) for DDR3-800
 701          *             max(3nCK, 5.625ns) for DDR3-1066, 1333
 702          *             max(3nCK, 5ns) for DDR3-1600, 1866, 2133
 703          */
 704         cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
 705                                         (mclk_ps > 1245 ? 5625 : 5000)));
 706 #else
 707         cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
 708 #endif
 709         four_act = picos_to_mclk(ctrl_num,
 710                                  popts->tfaw_window_four_activates_ps);
 711
 712         ddr->timing_cfg_2 = (0
 713                 | ((add_lat_mclk & 0xf) << 28)
 714                 | ((cpo & 0x1f) << 23)
 715                 | ((wr_lat & 0xf) << 19)
 716                 | (((wr_lat & 0x10) >> 4) << 18)
 717                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 718                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 719                 | ((cke_pls & 0x7) << 6)
 720                 | ((four_act & 0x3f) << 0)
 721                 );
 722         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 723 }
 724
 725 /* DDR SDRAM Register Control Word */
 726 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 727                                const memctl_options_t *popts,
 728                                const common_timing_params_t *common_dimm)
 729 {
 730         if (common_dimm->all_dimms_registered &&
 731             !common_dimm->all_dimms_unbuffered) {
 732                 if (popts->rcw_override) {
 733                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 734                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 735                         ddr->ddr_sdram_rcw_3 = popts->rcw_3;
 736                 } else {
 737                         ddr->ddr_sdram_rcw_1 =
 738                                 common_dimm->rcw[0] << 28 | \
 739                                 common_dimm->rcw[1] << 24 | \
 740                                 common_dimm->rcw[2] << 20 | \
 741                                 common_dimm->rcw[3] << 16 | \
 742                                 common_dimm->rcw[4] << 12 | \
 743                                 common_dimm->rcw[5] << 8 | \
 744                                 common_dimm->rcw[6] << 4 | \
 745                                 common_dimm->rcw[7];
 746                         ddr->ddr_sdram_rcw_2 =
 747                                 common_dimm->rcw[8] << 28 | \
 748                                 common_dimm->rcw[9] << 24 | \
 749                                 common_dimm->rcw[10] << 20 | \
 750                                 common_dimm->rcw[11] << 16 | \
 751                                 common_dimm->rcw[12] << 12 | \
 752                                 common_dimm->rcw[13] << 8 | \
 753                                 common_dimm->rcw[14] << 4 | \
 754                                 common_dimm->rcw[15];
 755                 }
 756                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n",
 757                       ddr->ddr_sdram_rcw_1);
 758                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n",
 759                       ddr->ddr_sdram_rcw_2);
 760                 debug("FSLDDR: ddr_sdram_rcw_3 = 0x%08x\n",
 761                       ddr->ddr_sdram_rcw_3);
 762         }
 763 }
 764
 765 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 766 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 767                                const memctl_options_t *popts,
 768                                const common_timing_params_t *common_dimm)
 769 {
 770         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 771         unsigned int sren;              /* Self refresh enable (during sleep) */
 772         unsigned int ecc_en;            /* ECC enable. */
 773         unsigned int rd_en;             /* Registered DIMM enable */
 774         unsigned int sdram_type;        /* Type of SDRAM */
 775         unsigned int dyn_pwr;           /* Dynamic power management mode */
 776         unsigned int dbw;               /* DRAM dta bus width */
 777         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 778         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 779         unsigned int threet_en;         /* Enable 3T timing */
 780         unsigned int twot_en;           /* Enable 2T timing */
 781         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 782         unsigned int x32_en = 0;        /* x32 enable */
 783         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 784         unsigned int hse;               /* Global half strength override */
 785         unsigned int acc_ecc_en = 0;    /* Accumulated ECC enable */
 786         unsigned int mem_halt = 0;      /* memory controller halt */
 787         unsigned int bi = 0;            /* Bypass initialization */
 788
 789         mem_en = 1;
 790         sren = popts->self_refresh_in_sleep;
 791         if (common_dimm->all_dimms_ecc_capable) {
 792                 /* Allow setting of ECC only if all DIMMs are ECC. */
 793                 ecc_en = popts->ecc_mode;
 794         } else {
 795                 ecc_en = 0;
 796         }
 797
 798         if (common_dimm->all_dimms_registered &&
 799             !common_dimm->all_dimms_unbuffered) {
 800                 rd_en = 1;
 801                 twot_en = 0;
 802         } else {
 803                 rd_en = 0;
 804                 twot_en = popts->twot_en;
 805         }
 806
 807         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 808
 809         dyn_pwr = popts->dynamic_power;
 810         dbw = popts->data_bus_width;
 811         /* 8-beat burst enable DDR-III case
 812          * we must clear it when use the on-the-fly mode,
 813          * must set it when use the 32-bits bus mode.
 814          */
 815         if ((sdram_type == SDRAM_TYPE_DDR3) ||
 816             (sdram_type == SDRAM_TYPE_DDR4)) {
 817                 if (popts->burst_length == DDR_BL8)
 818                         eight_be = 1;
 819                 if (popts->burst_length == DDR_OTF)
 820                         eight_be = 0;
 821                 if (dbw == 0x1)
 822                         eight_be = 1;
 823         }
 824
 825         threet_en = popts->threet_en;
 826         ba_intlv_ctl = popts->ba_intlv_ctl;
 827         hse = popts->half_strength_driver_enable;
 828
 829         /* set when ddr bus width < 64 */
 830         acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
 831
 832         ddr->ddr_sdram_cfg = (0
 833                         | ((mem_en & 0x1) << 31)
 834                         | ((sren & 0x1) << 30)
 835                         | ((ecc_en & 0x1) << 29)
 836                         | ((rd_en & 0x1) << 28)
 837                         | ((sdram_type & 0x7) << 24)
 838                         | ((dyn_pwr & 0x1) << 21)
 839                         | ((dbw & 0x3) << 19)
 840                         | ((eight_be & 0x1) << 18)
 841                         | ((ncap & 0x1) << 17)
 842                         | ((threet_en & 0x1) << 16)
 843                         | ((twot_en & 0x1) << 15)
 844                         | ((ba_intlv_ctl & 0x7F) << 8)
 845                         | ((x32_en & 0x1) << 5)
 846                         | ((pchb8 & 0x1) << 4)
 847                         | ((hse & 0x1) << 3)
 848                         | ((acc_ecc_en & 0x1) << 2)
 849                         | ((mem_halt & 0x1) << 1)
 850                         | ((bi & 0x1) << 0)
 851                         );
 852         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 853 }
 854
 855 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 856 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 857                                fsl_ddr_cfg_regs_t *ddr,
 858                                const memctl_options_t *popts,
 859                                const unsigned int unq_mrs_en)
 860 {
 861         unsigned int frc_sr = 0;        /* Force self refresh */
 862         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 863         unsigned int odt_cfg = 0;       /* ODT configuration */
 864         unsigned int num_pr;            /* Number of posted refreshes */
 865         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 866         unsigned int x4_en = 0;         /* x4 DRAM enable */
 867         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 868         unsigned int ap_en;             /* Address Parity Enable */
 869         unsigned int d_init;            /* DRAM data initialization */
 870         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 871         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 872         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 873         int i;
 874 #ifndef CONFIG_SYS_FSL_DDR4
 875         unsigned int dll_rst_dis = 1;   /* DLL reset disable */
 876         unsigned int dqs_cfg;           /* DQS configuration */
 877
 878         dqs_cfg = popts->dqs_config;
 879 #endif
 880         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 881                 if (popts->cs_local_opts[i].odt_rd_cfg
 882                         || popts->cs_local_opts[i].odt_wr_cfg) {
 883                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 884                         break;
 885                 }
 886         }
 887         sr_ie = popts->self_refresh_interrupt_en;
 888         num_pr = 1;     /* Make this configurable */
 889
 890         /*
 891          * 8572 manual says
 892          *     {TIMING_CFG_1[PRETOACT]
 893          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 894          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 895          *      << DDR_SDRAM_INTERVAL[REFINT]
 896          */
 897 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 898         obc_cfg = popts->otf_burst_chop_en;
 899 #else
 900         obc_cfg = 0;
 901 #endif
 902
 903 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 904         slow = get_ddr_freq(ctrl_num) < 1249000000;
 905 #endif
 906
 907         if (popts->registered_dimm_en)
 908                 rcw_en = 1;
 909
 910         /* DDR4 can have address parity for UDIMM and discrete */
 911         if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
 912             (!popts->registered_dimm_en)) {
 913                 ap_en = 0;
 914         } else {
 915                 ap_en = popts->ap_en;
 916         }
 917
 918         x4_en = popts->x4_en ? 1 : 0;
 919
 920 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 921         /* Use the DDR controller to auto initialize memory. */
 922         d_init = popts->ecc_init_using_memctl;
 923         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 924         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 925 #else
 926         /* Memory will be initialized via DMA, or not at all. */
 927         d_init = 0;
 928 #endif
 929
 930 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 931         md_en = popts->mirrored_dimm;
 932 #endif
 933         qd_en = popts->quad_rank_present ? 1 : 0;
 934         ddr->ddr_sdram_cfg_2 = (0
 935                 | ((frc_sr & 0x1) << 31)
 936                 | ((sr_ie & 0x1) << 30)
 937 #ifndef CONFIG_SYS_FSL_DDR4
 938                 | ((dll_rst_dis & 0x1) << 29)
 939                 | ((dqs_cfg & 0x3) << 26)
 940 #endif
 941                 | ((odt_cfg & 0x3) << 21)
 942                 | ((num_pr & 0xf) << 12)
 943                 | ((slow & 1) << 11)
 944                 | (x4_en << 10)
 945                 | (qd_en << 9)
 946                 | (unq_mrs_en << 8)
 947                 | ((obc_cfg & 0x1) << 6)
 948                 | ((ap_en & 0x1) << 5)
 949                 | ((d_init & 0x1) << 4)
 950                 | ((rcw_en & 0x1) << 2)
 951                 | ((md_en & 0x1) << 0)
 952                 );
 953         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 954 }
 955
 956 #ifdef CONFIG_SYS_FSL_DDR4
 957 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 958 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
 959                                 fsl_ddr_cfg_regs_t *ddr,
 960                                 const memctl_options_t *popts,
 961                                 const common_timing_params_t *common_dimm,
 962                                 const unsigned int unq_mrs_en)
 963 {
 964         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 965         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 966         int i;
 967         unsigned int wr_crc = 0;        /* Disable */
 968         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 969         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 970         unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
 971         unsigned int mpr = 0;   /* serial */
 972         unsigned int wc_lat;
 973         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 974
 975         if (popts->rtt_override)
 976                 rtt_wr = popts->rtt_wr_override_value;
 977         else
 978                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 979
 980         if (common_dimm->extended_op_srt)
 981                 srt = common_dimm->extended_op_srt;
 982
 983         esdmode2 = (0
 984                 | ((wr_crc & 0x1) << 12)
 985                 | ((rtt_wr & 0x3) << 9)
 986                 | ((srt & 0x3) << 6)
 987                 | ((cwl & 0x7) << 3));
 988
 989         if (mclk_ps >= 1250)
 990                 wc_lat = 0;
 991         else if (mclk_ps >= 833)
 992                 wc_lat = 1;
 993         else
 994                 wc_lat = 2;
 995
 996         esdmode3 = (0
 997                 | ((mpr & 0x3) << 11)
 998                 | ((wc_lat & 0x3) << 9));
 999
1000         ddr->ddr_sdram_mode_2 = (0
1001                                  | ((esdmode2 & 0xFFFF) << 16)
1002                                  | ((esdmode3 & 0xFFFF) << 0)
1003                                  );
1004         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1005
1006         if (unq_mrs_en) {       /* unique mode registers are supported */
1007                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1008                         if (popts->rtt_override)
1009                                 rtt_wr = popts->rtt_wr_override_value;
1010                         else
1011                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1012
1013                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
1014                         esdmode2 |= (rtt_wr & 0x3) << 9;
1015                         switch (i) {
1016                         case 1:
1017                                 ddr->ddr_sdram_mode_4 = (0
1018                                         | ((esdmode2 & 0xFFFF) << 16)
1019                                         | ((esdmode3 & 0xFFFF) << 0)
1020                                         );
1021                                 break;
1022                         case 2:
1023                                 ddr->ddr_sdram_mode_6 = (0
1024                                         | ((esdmode2 & 0xFFFF) << 16)
1025                                         | ((esdmode3 & 0xFFFF) << 0)
1026                                         );
1027                                 break;
1028                         case 3:
1029                                 ddr->ddr_sdram_mode_8 = (0
1030                                         | ((esdmode2 & 0xFFFF) << 16)
1031                                         | ((esdmode3 & 0xFFFF) << 0)
1032                                         );
1033                                 break;
1034                         }
1035                 }
1036                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1037                       ddr->ddr_sdram_mode_4);
1038                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1039                       ddr->ddr_sdram_mode_6);
1040                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1041                       ddr->ddr_sdram_mode_8);
1042         }
1043 }
1044 #elif defined(CONFIG_SYS_FSL_DDR3)
1045 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1046 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1047                                 fsl_ddr_cfg_regs_t *ddr,
1048                                 const memctl_options_t *popts,
1049                                 const common_timing_params_t *common_dimm,
1050                                 const unsigned int unq_mrs_en)
1051 {
1052         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1053         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1054         int i;
1055         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
1056         unsigned int srt = 0;   /* self-refresh temerature, normal range */
1057         unsigned int asr = 0;   /* auto self-refresh disable */
1058         unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
1059         unsigned int pasr = 0;  /* partial array self refresh disable */
1060
1061         if (popts->rtt_override)
1062                 rtt_wr = popts->rtt_wr_override_value;
1063         else
1064                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1065
1066         if (common_dimm->extended_op_srt)
1067                 srt = common_dimm->extended_op_srt;
1068
1069         esdmode2 = (0
1070                 | ((rtt_wr & 0x3) << 9)
1071                 | ((srt & 0x1) << 7)
1072                 | ((asr & 0x1) << 6)
1073                 | ((cwl & 0x7) << 3)
1074                 | ((pasr & 0x7) << 0));
1075         ddr->ddr_sdram_mode_2 = (0
1076                                  | ((esdmode2 & 0xFFFF) << 16)
1077                                  | ((esdmode3 & 0xFFFF) << 0)
1078                                  );
1079         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1080
1081         if (unq_mrs_en) {       /* unique mode registers are supported */
1082                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1083                         if (popts->rtt_override)
1084                                 rtt_wr = popts->rtt_wr_override_value;
1085                         else
1086                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1087
1088                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
1089                         esdmode2 |= (rtt_wr & 0x3) << 9;
1090                         switch (i) {
1091                         case 1:
1092                                 ddr->ddr_sdram_mode_4 = (0
1093                                         | ((esdmode2 & 0xFFFF) << 16)
1094                                         | ((esdmode3 & 0xFFFF) << 0)
1095                                         );
1096                                 break;
1097                         case 2:
1098                                 ddr->ddr_sdram_mode_6 = (0
1099                                         | ((esdmode2 & 0xFFFF) << 16)
1100                                         | ((esdmode3 & 0xFFFF) << 0)
1101                                         );
1102                                 break;
1103                         case 3:
1104                                 ddr->ddr_sdram_mode_8 = (0
1105                                         | ((esdmode2 & 0xFFFF) << 16)
1106                                         | ((esdmode3 & 0xFFFF) << 0)
1107                                         );
1108                                 break;
1109                         }
1110                 }
1111                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1112                         ddr->ddr_sdram_mode_4);
1113                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1114                         ddr->ddr_sdram_mode_6);
1115                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1116                         ddr->ddr_sdram_mode_8);
1117         }
1118 }
1119
1120 #else /* for DDR2 and DDR1 */
1121 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1122 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1123                                 fsl_ddr_cfg_regs_t *ddr,
1124                                 const memctl_options_t *popts,
1125                                 const common_timing_params_t *common_dimm,
1126                                 const unsigned int unq_mrs_en)
1127 {
1128         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1129         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1130
1131         ddr->ddr_sdram_mode_2 = (0
1132                                  | ((esdmode2 & 0xFFFF) << 16)
1133                                  | ((esdmode3 & 0xFFFF) << 0)
1134                                  );
1135         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1136 }
1137 #endif
1138
1139 #ifdef CONFIG_SYS_FSL_DDR4
1140 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1141 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1142                                 const memctl_options_t *popts,
1143                                 const common_timing_params_t *common_dimm,
1144                                 const unsigned int unq_mrs_en)
1145 {
1146         int i;
1147         unsigned short esdmode4 = 0;    /* Extended SDRAM mode 4 */
1148         unsigned short esdmode5;        /* Extended SDRAM mode 5 */
1149         int rtt_park = 0;
1150         bool four_cs = false;
1151         const unsigned int mclk_ps = get_memory_clk_period_ps(0);
1152
1153 #if CONFIG_CHIP_SELECTS_PER_CTRL == 4
1154         if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
1155             (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
1156             (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
1157             (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
1158                 four_cs = true;
1159 #endif
1160         if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
1161                 esdmode5 = 0x00000500;  /* Data mask enable, RTT_PARK CS0 */
1162                 rtt_park = four_cs ? 0 : 1;
1163         } else {
1164                 esdmode5 = 0x00000400;  /* Data mask enabled */
1165         }
1166
1167         /*
1168          * For DDR3, set C/A latency if address parity is enabled.
1169          * For DDR4, set C/A latency for UDIMM only. For RDIMM the delay is
1170          * handled by register chip and RCW settings.
1171          */
1172         if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
1173             ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
1174              !popts->registered_dimm_en)) {
1175                 if (mclk_ps >= 935) {
1176                         /* for DDR4-1600/1866/2133 */
1177                         esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1178                 } else if (mclk_ps >= 833) {
1179                         /* for DDR4-2400 */
1180                         esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1181                 } else {
1182                         printf("parity: mclk_ps = %d not supported\n", mclk_ps);
1183                 }
1184         }
1185
1186         ddr->ddr_sdram_mode_9 = (0
1187                                  | ((esdmode4 & 0xffff) << 16)
1188                                  | ((esdmode5 & 0xffff) << 0)
1189                                 );
1190
1191         /* Normally only the first enabled CS use 0x500, others use 0x400
1192          * But when four chip-selects are all enabled, all mode registers
1193          * need 0x500 to park.
1194          */
1195
1196         debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1197         if (unq_mrs_en) {       /* unique mode registers are supported */
1198                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1199                         if (!rtt_park &&
1200                             (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
1201                                 esdmode5 |= 0x00000500; /* RTT_PARK */
1202                                 rtt_park = four_cs ? 0 : 1;
1203                         } else {
1204                                 esdmode5 = 0x00000400;
1205                         }
1206
1207                         if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
1208                             ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
1209                              !popts->registered_dimm_en)) {
1210                                 if (mclk_ps >= 935) {
1211                                         /* for DDR4-1600/1866/2133 */
1212                                         esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1213                                 } else if (mclk_ps >= 833) {
1214                                         /* for DDR4-2400 */
1215                                         esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1216                                 } else {
1217                                         printf("parity: mclk_ps = %d not supported\n",
1218                                                mclk_ps);
1219                                 }
1220                         }
1221
1222                         switch (i) {
1223                         case 1:
1224                                 ddr->ddr_sdram_mode_11 = (0
1225                                         | ((esdmode4 & 0xFFFF) << 16)
1226                                         | ((esdmode5 & 0xFFFF) << 0)
1227                                         );
1228                                 break;
1229                         case 2:
1230                                 ddr->ddr_sdram_mode_13 = (0
1231                                         | ((esdmode4 & 0xFFFF) << 16)
1232                                         | ((esdmode5 & 0xFFFF) << 0)
1233                                         );
1234                                 break;
1235                         case 3:
1236                                 ddr->ddr_sdram_mode_15 = (0
1237                                         | ((esdmode4 & 0xFFFF) << 16)
1238                                         | ((esdmode5 & 0xFFFF) << 0)
1239                                         );
1240                                 break;
1241                         }
1242                 }
1243                 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1244                       ddr->ddr_sdram_mode_11);
1245                 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1246                       ddr->ddr_sdram_mode_13);
1247                 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1248                       ddr->ddr_sdram_mode_15);
1249         }
1250 }
1251
1252 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1253 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1254                                 fsl_ddr_cfg_regs_t *ddr,
1255                                 const memctl_options_t *popts,
1256                                 const common_timing_params_t *common_dimm,
1257                                 const unsigned int unq_mrs_en)
1258 {
1259         int i;
1260         unsigned short esdmode6 = 0;    /* Extended SDRAM mode 6 */
1261         unsigned short esdmode7 = 0;    /* Extended SDRAM mode 7 */
1262         unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1263
1264         esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1265
1266         if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
1267                 esdmode6 |= 1 << 6;     /* Range 2 */
1268
1269         ddr->ddr_sdram_mode_10 = (0
1270                                  | ((esdmode6 & 0xffff) << 16)
1271                                  | ((esdmode7 & 0xffff) << 0)
1272                                 );
1273         debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
1274         if (unq_mrs_en) {       /* unique mode registers are supported */
1275                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1276                         switch (i) {
1277                         case 1:
1278                                 ddr->ddr_sdram_mode_12 = (0
1279                                         | ((esdmode6 & 0xFFFF) << 16)
1280                                         | ((esdmode7 & 0xFFFF) << 0)
1281                                         );
1282                                 break;
1283                         case 2:
1284                                 ddr->ddr_sdram_mode_14 = (0
1285                                         | ((esdmode6 & 0xFFFF) << 16)
1286                                         | ((esdmode7 & 0xFFFF) << 0)
1287                                         );
1288                                 break;
1289                         case 3:
1290                                 ddr->ddr_sdram_mode_16 = (0
1291                                         | ((esdmode6 & 0xFFFF) << 16)
1292                                         | ((esdmode7 & 0xFFFF) << 0)
1293                                         );
1294                                 break;
1295                         }
1296                 }
1297                 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1298                       ddr->ddr_sdram_mode_12);
1299                 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1300                       ddr->ddr_sdram_mode_14);
1301                 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1302                       ddr->ddr_sdram_mode_16);
1303         }
1304 }
1305
1306 #endif
1307
1308 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1309 static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1310                                 fsl_ddr_cfg_regs_t *ddr,
1311                                 const memctl_options_t *popts,
1312                                 const common_timing_params_t *common_dimm)
1313 {
1314         unsigned int refint;    /* Refresh interval */
1315         unsigned int bstopre;   /* Precharge interval */
1316
1317         refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
1318
1319         bstopre = popts->bstopre;
1320
1321         /* refint field used 0x3FFF in earlier controllers */
1322         ddr->ddr_sdram_interval = (0
1323                                    | ((refint & 0xFFFF) << 16)
1324                                    | ((bstopre & 0x3FFF) << 0)
1325                                    );
1326         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1327 }
1328
1329 #ifdef CONFIG_SYS_FSL_DDR4
1330 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1331 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1332                                fsl_ddr_cfg_regs_t *ddr,
1333                                const memctl_options_t *popts,
1334                                const common_timing_params_t *common_dimm,
1335                                unsigned int cas_latency,
1336                                unsigned int additive_latency,
1337                                const unsigned int unq_mrs_en)
1338 {
1339         int i;
1340         unsigned short esdmode;         /* Extended SDRAM mode */
1341         unsigned short sdmode;          /* SDRAM mode */
1342
1343         /* Mode Register - MR1 */
1344         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1345         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1346         unsigned int rtt;
1347         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1348         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1349         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1350         unsigned int dll_en = 1;        /* DLL Enable  1=Enable (Normal),
1351                                                        0=Disable (Test/Debug) */
1352
1353         /* Mode Register - MR0 */
1354         unsigned int wr = 0;    /* Write Recovery */
1355         unsigned int dll_rst;   /* DLL Reset */
1356         unsigned int mode;      /* Normal=0 or Test=1 */
1357         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1358         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1359         unsigned int bt;
1360         unsigned int bl;        /* BL: Burst Length */
1361
1362         unsigned int wr_mclk;
1363         /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1364         static const u8 wr_table[] = {
1365                 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1366         /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1367         static const u8 cas_latency_table[] = {
1368                 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1369                 9, 9, 10, 10, 11, 11};
1370
1371         if (popts->rtt_override)
1372                 rtt = popts->rtt_override_value;
1373         else
1374                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1375
1376         if (additive_latency == (cas_latency - 1))
1377                 al = 1;
1378         if (additive_latency == (cas_latency - 2))
1379                 al = 2;
1380
1381         if (popts->quad_rank_present)
1382                 dic = 1;        /* output driver impedance 240/7 ohm */
1383
1384         /*
1385          * The esdmode value will also be used for writing
1386          * MR1 during write leveling for DDR3, although the
1387          * bits specifically related to the write leveling
1388          * scheme will be handled automatically by the DDR
1389          * controller. so we set the wrlvl_en = 0 here.
1390          */
1391         esdmode = (0
1392                 | ((qoff & 0x1) << 12)
1393                 | ((tdqs_en & 0x1) << 11)
1394                 | ((rtt & 0x7) << 8)
1395                 | ((wrlvl_en & 0x1) << 7)
1396                 | ((al & 0x3) << 3)
1397                 | ((dic & 0x3) << 1)   /* DIC field is split */
1398                 | ((dll_en & 0x1) << 0)
1399                 );
1400
1401         /*
1402          * DLL control for precharge PD
1403          * 0=slow exit DLL off (tXPDLL)
1404          * 1=fast exit DLL on (tXP)
1405          */
1406
1407         wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1408         if (wr_mclk <= 24) {
1409                 wr = wr_table[wr_mclk - 10];
1410         } else {
1411                 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1412                        wr_mclk);
1413         }
1414
1415         dll_rst = 0;    /* dll no reset */
1416         mode = 0;       /* normal mode */
1417
1418         /* look up table to get the cas latency bits */
1419         if (cas_latency >= 9 && cas_latency <= 24)
1420                 caslat = cas_latency_table[cas_latency - 9];
1421         else
1422                 printf("Error: unsupported cas latency for mode register\n");
1423
1424         bt = 0; /* Nibble sequential */
1425
1426         switch (popts->burst_length) {
1427         case DDR_BL8:
1428                 bl = 0;
1429                 break;
1430         case DDR_OTF:
1431                 bl = 1;
1432                 break;
1433         case DDR_BC4:
1434                 bl = 2;
1435                 break;
1436         default:
1437                 printf("Error: invalid burst length of %u specified. ",
1438                        popts->burst_length);
1439                 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1440                 bl = 1;
1441                 break;
1442         }
1443
1444         sdmode = (0
1445                   | ((wr & 0x7) << 9)
1446                   | ((dll_rst & 0x1) << 8)
1447                   | ((mode & 0x1) << 7)
1448                   | (((caslat >> 1) & 0x7) << 4)
1449                   | ((bt & 0x1) << 3)
1450                   | ((caslat & 1) << 2)
1451                   | ((bl & 0x3) << 0)
1452                   );
1453
1454         ddr->ddr_sdram_mode = (0
1455                                | ((esdmode & 0xFFFF) << 16)
1456                                | ((sdmode & 0xFFFF) << 0)
1457                                );
1458
1459         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1460
1461         if (unq_mrs_en) {       /* unique mode registers are supported */
1462                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1463                         if (popts->rtt_override)
1464                                 rtt = popts->rtt_override_value;
1465                         else
1466                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1467
1468                         esdmode &= 0xF8FF;      /* clear bit 10,9,8 for rtt */
1469                         esdmode |= (rtt & 0x7) << 8;
1470                         switch (i) {
1471                         case 1:
1472                                 ddr->ddr_sdram_mode_3 = (0
1473                                        | ((esdmode & 0xFFFF) << 16)
1474                                        | ((sdmode & 0xFFFF) << 0)
1475                                        );
1476                                 break;
1477                         case 2:
1478                                 ddr->ddr_sdram_mode_5 = (0
1479                                        | ((esdmode & 0xFFFF) << 16)
1480                                        | ((sdmode & 0xFFFF) << 0)
1481                                        );
1482                                 break;
1483                         case 3:
1484                                 ddr->ddr_sdram_mode_7 = (0
1485                                        | ((esdmode & 0xFFFF) << 16)
1486                                        | ((sdmode & 0xFFFF) << 0)
1487                                        );
1488                                 break;
1489                         }
1490                 }
1491                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1492                       ddr->ddr_sdram_mode_3);
1493                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1494                       ddr->ddr_sdram_mode_5);
1495                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1496                       ddr->ddr_sdram_mode_5);
1497         }
1498 }
1499
1500 #elif defined(CONFIG_SYS_FSL_DDR3)
1501 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1502 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1503                                fsl_ddr_cfg_regs_t *ddr,
1504                                const memctl_options_t *popts,
1505                                const common_timing_params_t *common_dimm,
1506                                unsigned int cas_latency,
1507                                unsigned int additive_latency,
1508                                const unsigned int unq_mrs_en)
1509 {
1510         int i;
1511         unsigned short esdmode;         /* Extended SDRAM mode */
1512         unsigned short sdmode;          /* SDRAM mode */
1513
1514         /* Mode Register - MR1 */
1515         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1516         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1517         unsigned int rtt;
1518         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1519         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1520         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1521         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1522                                                        1=Disable (Test/Debug) */
1523
1524         /* Mode Register - MR0 */
1525         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
1526         unsigned int wr = 0;    /* Write Recovery */
1527         unsigned int dll_rst;   /* DLL Reset */
1528         unsigned int mode;      /* Normal=0 or Test=1 */
1529         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1530         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1531         unsigned int bt;
1532         unsigned int bl;        /* BL: Burst Length */
1533
1534         unsigned int wr_mclk;
1535         /*
1536          * DDR_SDRAM_MODE doesn't support 9,11,13,15
1537          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1538          * for this table
1539          */
1540         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1541
1542         if (popts->rtt_override)
1543                 rtt = popts->rtt_override_value;
1544         else
1545                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1546
1547         if (additive_latency == (cas_latency - 1))
1548                 al = 1;
1549         if (additive_latency == (cas_latency - 2))
1550                 al = 2;
1551
1552         if (popts->quad_rank_present)
1553                 dic = 1;        /* output driver impedance 240/7 ohm */
1554
1555         /*
1556          * The esdmode value will also be used for writing
1557          * MR1 during write leveling for DDR3, although the
1558          * bits specifically related to the write leveling
1559          * scheme will be handled automatically by the DDR
1560          * controller. so we set the wrlvl_en = 0 here.
1561          */
1562         esdmode = (0
1563                 | ((qoff & 0x1) << 12)
1564                 | ((tdqs_en & 0x1) << 11)
1565                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1566                 | ((wrlvl_en & 0x1) << 7)
1567                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1568                 | ((dic & 0x2) << 4)   /* DIC field is split */
1569                 | ((al & 0x3) << 3)
1570                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1571                 | ((dic & 0x1) << 1)   /* DIC field is split */
1572                 | ((dll_en & 0x1) << 0)
1573                 );
1574
1575         /*
1576          * DLL control for precharge PD
1577          * 0=slow exit DLL off (tXPDLL)
1578          * 1=fast exit DLL on (tXP)
1579          */
1580         dll_on = 1;
1581
1582         wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1583         if (wr_mclk <= 16) {
1584                 wr = wr_table[wr_mclk - 5];
1585         } else {
1586                 printf("Error: unsupported write recovery for mode register "
1587                        "wr_mclk = %d\n", wr_mclk);
1588         }
1589
1590         dll_rst = 0;    /* dll no reset */
1591         mode = 0;       /* normal mode */
1592
1593         /* look up table to get the cas latency bits */
1594         if (cas_latency >= 5 && cas_latency <= 16) {
1595                 unsigned char cas_latency_table[] = {
1596                         0x2,    /* 5 clocks */
1597                         0x4,    /* 6 clocks */
1598                         0x6,    /* 7 clocks */
1599                         0x8,    /* 8 clocks */
1600                         0xa,    /* 9 clocks */
1601                         0xc,    /* 10 clocks */
1602                         0xe,    /* 11 clocks */
1603                         0x1,    /* 12 clocks */
1604                         0x3,    /* 13 clocks */
1605                         0x5,    /* 14 clocks */
1606                         0x7,    /* 15 clocks */
1607                         0x9,    /* 16 clocks */
1608                 };
1609                 caslat = cas_latency_table[cas_latency - 5];
1610         } else {
1611                 printf("Error: unsupported cas latency for mode register\n");
1612         }
1613
1614         bt = 0; /* Nibble sequential */
1615
1616         switch (popts->burst_length) {
1617         case DDR_BL8:
1618                 bl = 0;
1619                 break;
1620         case DDR_OTF:
1621                 bl = 1;
1622                 break;
1623         case DDR_BC4:
1624                 bl = 2;
1625                 break;
1626         default:
1627                 printf("Error: invalid burst length of %u specified. "
1628                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1629                         popts->burst_length);
1630                 bl = 1;
1631                 break;
1632         }
1633
1634         sdmode = (0
1635                   | ((dll_on & 0x1) << 12)
1636                   | ((wr & 0x7) << 9)
1637                   | ((dll_rst & 0x1) << 8)
1638                   | ((mode & 0x1) << 7)
1639                   | (((caslat >> 1) & 0x7) << 4)
1640                   | ((bt & 0x1) << 3)
1641                   | ((caslat & 1) << 2)
1642                   | ((bl & 0x3) << 0)
1643                   );
1644
1645         ddr->ddr_sdram_mode = (0
1646                                | ((esdmode & 0xFFFF) << 16)
1647                                | ((sdmode & 0xFFFF) << 0)
1648                                );
1649
1650         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1651
1652         if (unq_mrs_en) {       /* unique mode registers are supported */
1653                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1654                         if (popts->rtt_override)
1655                                 rtt = popts->rtt_override_value;
1656                         else
1657                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1658
1659                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1660                         esdmode |= (0
1661                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1662                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1663                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1664                                 );
1665                         switch (i) {
1666                         case 1:
1667                                 ddr->ddr_sdram_mode_3 = (0
1668                                        | ((esdmode & 0xFFFF) << 16)
1669                                        | ((sdmode & 0xFFFF) << 0)
1670                                        );
1671                                 break;
1672                         case 2:
1673                                 ddr->ddr_sdram_mode_5 = (0
1674                                        | ((esdmode & 0xFFFF) << 16)
1675                                        | ((sdmode & 0xFFFF) << 0)
1676                                        );
1677                                 break;
1678                         case 3:
1679                                 ddr->ddr_sdram_mode_7 = (0
1680                                        | ((esdmode & 0xFFFF) << 16)
1681                                        | ((sdmode & 0xFFFF) << 0)
1682                                        );
1683                                 break;
1684                         }
1685                 }
1686                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1687                         ddr->ddr_sdram_mode_3);
1688                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1689                         ddr->ddr_sdram_mode_5);
1690                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1691                         ddr->ddr_sdram_mode_5);
1692         }
1693 }
1694
1695 #else /* !CONFIG_SYS_FSL_DDR3 */
1696
1697 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1698 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1699                                fsl_ddr_cfg_regs_t *ddr,
1700                                const memctl_options_t *popts,
1701                                const common_timing_params_t *common_dimm,
1702                                unsigned int cas_latency,
1703                                unsigned int additive_latency,
1704                                const unsigned int unq_mrs_en)
1705 {
1706         unsigned short esdmode;         /* Extended SDRAM mode */
1707         unsigned short sdmode;          /* SDRAM mode */
1708
1709         /*
1710          * FIXME: This ought to be pre-calculated in a
1711          * technology-specific routine,
1712          * e.g. compute_DDR2_mode_register(), and then the
1713          * sdmode and esdmode passed in as part of common_dimm.
1714          */
1715
1716         /* Extended Mode Register */
1717         unsigned int mrs = 0;           /* Mode Register Set */
1718         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1719         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1720         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1721         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1722                                            0x7=OCD default state */
1723         unsigned int rtt;
1724         unsigned int al;                /* Posted CAS# additive latency (AL) */
1725         unsigned int ods = 0;           /* Output Drive Strength:
1726                                                 0 = Full strength (18ohm)
1727                                                 1 = Reduced strength (4ohm) */
1728         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1729                                                        1=Disable (Test/Debug) */
1730
1731         /* Mode Register (MR) */
1732         unsigned int mr;        /* Mode Register Definition */
1733         unsigned int pd;        /* Power-Down Mode */
1734         unsigned int wr;        /* Write Recovery */
1735         unsigned int dll_res;   /* DLL Reset */
1736         unsigned int mode;      /* Normal=0 or Test=1 */
1737         unsigned int caslat = 0;/* CAS# latency */
1738         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1739         unsigned int bt;
1740         unsigned int bl;        /* BL: Burst Length */
1741
1742         dqs_en = !popts->dqs_config;
1743         rtt = fsl_ddr_get_rtt();
1744
1745         al = additive_latency;
1746
1747         esdmode = (0
1748                 | ((mrs & 0x3) << 14)
1749                 | ((outputs & 0x1) << 12)
1750                 | ((rdqs_en & 0x1) << 11)
1751                 | ((dqs_en & 0x1) << 10)
1752                 | ((ocd & 0x7) << 7)
1753                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1754                 | ((al & 0x7) << 3)
1755                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1756                 | ((ods & 0x1) << 1)
1757                 | ((dll_en & 0x1) << 0)
1758                 );
1759
1760         mr = 0;          /* FIXME: CHECKME */
1761
1762         /*
1763          * 0 = Fast Exit (Normal)
1764          * 1 = Slow Exit (Low Power)
1765          */
1766         pd = 0;
1767
1768 #if defined(CONFIG_SYS_FSL_DDR1)
1769         wr = 0;       /* Historical */
1770 #elif defined(CONFIG_SYS_FSL_DDR2)
1771         wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1772 #endif
1773         dll_res = 0;
1774         mode = 0;
1775
1776 #if defined(CONFIG_SYS_FSL_DDR1)
1777         if (1 <= cas_latency && cas_latency <= 4) {
1778                 unsigned char mode_caslat_table[4] = {
1779                         0x5,    /* 1.5 clocks */
1780                         0x2,    /* 2.0 clocks */
1781                         0x6,    /* 2.5 clocks */
1782                         0x3     /* 3.0 clocks */
1783                 };
1784                 caslat = mode_caslat_table[cas_latency - 1];
1785         } else {
1786                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1787         }
1788 #elif defined(CONFIG_SYS_FSL_DDR2)
1789         caslat = cas_latency;
1790 #endif
1791         bt = 0;
1792
1793         switch (popts->burst_length) {
1794         case DDR_BL4:
1795                 bl = 2;
1796                 break;
1797         case DDR_BL8:
1798                 bl = 3;
1799                 break;
1800         default:
1801                 printf("Error: invalid burst length of %u specified. "
1802                         " Defaulting to 4 beats.\n",
1803                         popts->burst_length);
1804                 bl = 2;
1805                 break;
1806         }
1807
1808         sdmode = (0
1809                   | ((mr & 0x3) << 14)
1810                   | ((pd & 0x1) << 12)
1811                   | ((wr & 0x7) << 9)
1812                   | ((dll_res & 0x1) << 8)
1813                   | ((mode & 0x1) << 7)
1814                   | ((caslat & 0x7) << 4)
1815                   | ((bt & 0x1) << 3)
1816                   | ((bl & 0x7) << 0)
1817                   );
1818
1819         ddr->ddr_sdram_mode = (0
1820                                | ((esdmode & 0xFFFF) << 16)
1821                                | ((sdmode & 0xFFFF) << 0)
1822                                );
1823         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1824 }
1825 #endif
1826
1827 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1828 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1829 {
1830         unsigned int init_value;        /* Initialization value */
1831
1832 #ifdef CONFIG_MEM_INIT_VALUE
1833         init_value = CONFIG_MEM_INIT_VALUE;
1834 #else
1835         init_value = 0xDEADBEEF;
1836 #endif
1837         ddr->ddr_data_init = init_value;
1838 }
1839
1840 /*
1841  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1842  * The old controller on the 8540/60 doesn't have this register.
1843  * Hope it's OK to set it (to 0) anyway.
1844  */
1845 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1846                                          const memctl_options_t *popts)
1847 {
1848         unsigned int clk_adjust;        /* Clock adjust */
1849         unsigned int ss_en = 0;         /* Source synchronous enable */
1850
1851 #if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
1852         /* Per FSL Application Note: AN2805 */
1853         ss_en = 1;
1854 #endif
1855         if (fsl_ddr_get_version(0) >= 0x40701) {
1856                 /* clk_adjust in 5-bits on T-series and LS-series */
1857                 clk_adjust = (popts->clk_adjust & 0x1F) << 22;
1858         } else {
1859                 /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
1860                 clk_adjust = (popts->clk_adjust & 0xF) << 23;
1861         }
1862
1863         ddr->ddr_sdram_clk_cntl = (0
1864                                    | ((ss_en & 0x1) << 31)
1865                                    | clk_adjust
1866                                    );
1867         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1868 }
1869
1870 /* DDR Initialization Address (DDR_INIT_ADDR) */
1871 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1872 {
1873         unsigned int init_addr = 0;     /* Initialization address */
1874
1875         ddr->ddr_init_addr = init_addr;
1876 }
1877
1878 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1879 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1880 {
1881         unsigned int uia = 0;   /* Use initialization address */
1882         unsigned int init_ext_addr = 0; /* Initialization address */
1883
1884         ddr->ddr_init_ext_addr = (0
1885                                   | ((uia & 0x1) << 31)
1886                                   | (init_ext_addr & 0xF)
1887                                   );
1888 }
1889
1890 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1891 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1892                                 const memctl_options_t *popts)
1893 {
1894         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1895         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1896         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1897         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1898         unsigned int trwt_mclk = 0;     /* ext_rwt */
1899         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1900
1901 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1902         if (popts->burst_length == DDR_BL8) {
1903                 /* We set BL/2 for fixed BL8 */
1904                 rrt = 0;        /* BL/2 clocks */
1905                 wwt = 0;        /* BL/2 clocks */
1906         } else {
1907                 /* We need to set BL/2 + 2 to BC4 and OTF */
1908                 rrt = 2;        /* BL/2 + 2 clocks */
1909                 wwt = 2;        /* BL/2 + 2 clocks */
1910         }
1911 #endif
1912 #ifdef CONFIG_SYS_FSL_DDR4
1913         dll_lock = 2;   /* tDLLK = 1024 clocks */
1914 #elif defined(CONFIG_SYS_FSL_DDR3)
1915         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1916 #endif
1917
1918         if (popts->trwt_override)
1919                 trwt_mclk = popts->trwt;
1920
1921         ddr->timing_cfg_4 = (0
1922                              | ((rwt & 0xf) << 28)
1923                              | ((wrt & 0xf) << 24)
1924                              | ((rrt & 0xf) << 20)
1925                              | ((wwt & 0xf) << 16)
1926                              | ((trwt_mclk & 0xc) << 12)
1927                              | (dll_lock & 0x3)
1928                              );
1929         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1930 }
1931
1932 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1933 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1934 {
1935         unsigned int rodt_on = 0;       /* Read to ODT on */
1936         unsigned int rodt_off = 0;      /* Read to ODT off */
1937         unsigned int wodt_on = 0;       /* Write to ODT on */
1938         unsigned int wodt_off = 0;      /* Write to ODT off */
1939
1940 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1941         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1942                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1943         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1944         if (cas_latency >= wr_lat)
1945                 rodt_on = cas_latency - wr_lat + 1;
1946         rodt_off = 4;   /*  4 clocks */
1947         wodt_on = 1;    /*  1 clocks */
1948         wodt_off = 4;   /*  4 clocks */
1949 #endif
1950
1951         ddr->timing_cfg_5 = (0
1952                              | ((rodt_on & 0x1f) << 24)
1953                              | ((rodt_off & 0x7) << 20)
1954                              | ((wodt_on & 0x1f) << 12)
1955                              | ((wodt_off & 0x7) << 8)
1956                              );
1957         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1958 }
1959
1960 #ifdef CONFIG_SYS_FSL_DDR4
1961 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1962 {
1963         unsigned int hs_caslat = 0;
1964         unsigned int hs_wrlat = 0;
1965         unsigned int hs_wrrec = 0;
1966         unsigned int hs_clkadj = 0;
1967         unsigned int hs_wrlvl_start = 0;
1968
1969         ddr->timing_cfg_6 = (0
1970                              | ((hs_caslat & 0x1f) << 24)
1971                              | ((hs_wrlat & 0x1f) << 19)
1972                              | ((hs_wrrec & 0x1f) << 12)
1973                              | ((hs_clkadj & 0x1f) << 6)
1974                              | ((hs_wrlvl_start & 0x1f) << 0)
1975                             );
1976         debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1977 }
1978
1979 static void set_timing_cfg_7(const unsigned int ctrl_num,
1980                              fsl_ddr_cfg_regs_t *ddr,
1981                              const memctl_options_t *popts,
1982                              const common_timing_params_t *common_dimm)
1983 {
1984         unsigned int txpr, tcksre, tcksrx;
1985         unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd;
1986         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
1987
1988         txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
1989         tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
1990         tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
1991
1992         if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN &&
1993             CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) {
1994                 /* for DDR4 only */
1995                 par_lat = (popts->rcw_2 & 0xf) + 1;
1996                 debug("PAR_LAT = %u for mclk_ps = %d\n", par_lat, mclk_ps);
1997         }
1998
1999         cs_to_cmd = 0;
2000
2001         if (txpr <= 200)
2002                 cke_rst = 0;
2003         else if (txpr <= 256)
2004                 cke_rst = 1;
2005         else if (txpr <= 512)
2006                 cke_rst = 2;
2007         else
2008                 cke_rst = 3;
2009
2010         if (tcksre <= 19)
2011                 cksre = tcksre - 5;
2012         else
2013                 cksre = 15;
2014
2015         if (tcksrx <= 19)
2016                 cksrx = tcksrx - 5;
2017         else
2018                 cksrx = 15;
2019
2020         ddr->timing_cfg_7 = (0
2021                              | ((cke_rst & 0x3) << 28)
2022                              | ((cksre & 0xf) << 24)
2023                              | ((cksrx & 0xf) << 20)
2024                              | ((par_lat & 0xf) << 16)
2025                              | ((cs_to_cmd & 0xf) << 4)
2026                             );
2027         debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
2028 }
2029
2030 static void set_timing_cfg_8(const unsigned int ctrl_num,
2031                              fsl_ddr_cfg_regs_t *ddr,
2032                              const memctl_options_t *popts,
2033                              const common_timing_params_t *common_dimm,
2034                              unsigned int cas_latency)
2035 {
2036         int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
2037         unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
2038         int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
2039         int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
2040                       ((ddr->timing_cfg_2 & 0x00040000) >> 14);
2041
2042         rwt_bg = cas_latency + 2 + 4 - wr_lat;
2043         if (rwt_bg < tccdl)
2044                 rwt_bg = tccdl - rwt_bg;
2045         else
2046                 rwt_bg = 0;
2047
2048         wrt_bg = wr_lat + 4 + 1 - cas_latency;
2049         if (wrt_bg < tccdl)
2050                 wrt_bg = tccdl - wrt_bg;
2051         else
2052                 wrt_bg = 0;
2053
2054         if (popts->burst_length == DDR_BL8) {
2055                 rrt_bg = tccdl - 4;
2056                 wwt_bg = tccdl - 4;
2057         } else {
2058                 rrt_bg = tccdl - 2;
2059                 wwt_bg = tccdl - 2;
2060         }
2061
2062         acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
2063         wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
2064         if (popts->otf_burst_chop_en)
2065                 wrtord_bg += 2;
2066
2067         pre_all_rec = 0;
2068
2069         ddr->timing_cfg_8 = (0
2070                              | ((rwt_bg & 0xf) << 28)
2071                              | ((wrt_bg & 0xf) << 24)
2072                              | ((rrt_bg & 0xf) << 20)
2073                              | ((wwt_bg & 0xf) << 16)
2074                              | ((acttoact_bg & 0xf) << 12)
2075                              | ((wrtord_bg & 0xf) << 8)
2076                              | ((pre_all_rec & 0x1f) << 0)
2077                             );
2078
2079         debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
2080 }
2081
2082 static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
2083 {
2084         ddr->timing_cfg_9 = 0;
2085         debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
2086 }
2087
2088 /* This function needs to be called after set_ddr_sdram_cfg() is called */
2089 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
2090                                const dimm_params_t *dimm_params)
2091 {
2092         unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
2093         int i;
2094
2095         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
2096                 if (dimm_params[i].n_ranks)
2097                         break;
2098         }
2099         if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
2100                 puts("DDR error: no DIMM found!\n");
2101                 return;
2102         }
2103
2104         ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
2105                         ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
2106                         ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
2107                         ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
2108                         ((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
2109
2110         ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
2111                         ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
2112                         ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
2113                         ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
2114                         ((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
2115
2116         ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
2117                         ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
2118                         ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
2119                         ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
2120                         ((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
2121
2122         /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
2123         ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
2124                         ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
2125                         (acc_ecc_en ? 0 :
2126                          (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
2127                         dimm_params[i].dq_mapping_ors;
2128
2129         debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
2130         debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
2131         debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
2132         debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
2133 }
2134 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
2135                                const memctl_options_t *popts)
2136 {
2137         int rd_pre;
2138
2139         rd_pre = popts->quad_rank_present ? 1 : 0;
2140
2141         ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
2142         /* Disable MRS on parity error for RDIMMs */
2143         ddr->ddr_sdram_cfg_3 |= popts->registered_dimm_en ? 1 : 0;
2144
2145         debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2146 }
2147 #endif  /* CONFIG_SYS_FSL_DDR4 */
2148
2149 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
2150 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
2151 {
2152         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2153         /* Normal Operation Full Calibration Time (tZQoper) */
2154         unsigned int zqoper = 0;
2155         /* Normal Operation Short Calibration Time (tZQCS) */
2156         unsigned int zqcs = 0;
2157 #ifdef CONFIG_SYS_FSL_DDR4
2158         unsigned int zqcs_init;
2159 #endif
2160
2161         if (zq_en) {
2162 #ifdef CONFIG_SYS_FSL_DDR4
2163                 zqinit = 10;    /* 1024 clocks */
2164                 zqoper = 9;     /* 512 clocks */
2165                 zqcs = 7;       /* 128 clocks */
2166                 zqcs_init = 5;  /* 1024 refresh sequences */
2167 #else
2168                 zqinit = 9;     /* 512 clocks */
2169                 zqoper = 8;     /* 256 clocks */
2170                 zqcs = 6;       /* 64 clocks */
2171 #endif
2172         }
2173
2174         ddr->ddr_zq_cntl = (0
2175                             | ((zq_en & 0x1) << 31)
2176                             | ((zqinit & 0xF) << 24)
2177                             | ((zqoper & 0xF) << 16)
2178                             | ((zqcs & 0xF) << 8)
2179 #ifdef CONFIG_SYS_FSL_DDR4
2180                             | ((zqcs_init & 0xF) << 0)
2181 #endif
2182                             );
2183         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
2184 }
2185
2186 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
2187 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2188                                 const memctl_options_t *popts)
2189 {
2190         /*
2191          * First DQS pulse rising edge after margining mode
2192          * is programmed (tWL_MRD)
2193          */
2194         unsigned int wrlvl_mrd = 0;
2195         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2196         unsigned int wrlvl_odten = 0;
2197         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2198         unsigned int wrlvl_dqsen = 0;
2199         /* WRLVL_SMPL: Write leveling sample time */
2200         unsigned int wrlvl_smpl = 0;
2201         /* WRLVL_WLR: Write leveling repeition time */
2202         unsigned int wrlvl_wlr = 0;
2203         /* WRLVL_START: Write leveling start time */
2204         unsigned int wrlvl_start = 0;
2205
2206         /* suggest enable write leveling for DDR3 due to fly-by topology */
2207         if (wrlvl_en) {
2208                 /* tWL_MRD min = 40 nCK, we set it 64 */
2209                 wrlvl_mrd = 0x6;
2210                 /* tWL_ODTEN 128 */
2211                 wrlvl_odten = 0x7;
2212                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2213                 wrlvl_dqsen = 0x5;
2214                 /*
2215                  * Write leveling sample time at least need 6 clocks
2216                  * higher than tWLO to allow enough time for progagation
2217                  * delay and sampling the prime data bits.
2218                  */
2219                 wrlvl_smpl = 0xf;
2220                 /*
2221                  * Write leveling repetition time
2222                  * at least tWLO + 6 clocks clocks
2223                  * we set it 64
2224                  */
2225                 wrlvl_wlr = 0x6;
2226                 /*
2227                  * Write leveling start time
2228                  * The value use for the DQS_ADJUST for the first sample
2229                  * when write leveling is enabled. It probably needs to be
2230                  * overridden per platform.
2231                  */
2232                 wrlvl_start = 0x8;
2233                 /*
2234                  * Override the write leveling sample and start time
2235                  * according to specific board
2236                  */
2237                 if (popts->wrlvl_override) {
2238                         wrlvl_smpl = popts->wrlvl_sample;
2239                         wrlvl_start = popts->wrlvl_start;
2240                 }
2241         }
2242
2243         ddr->ddr_wrlvl_cntl = (0
2244                                | ((wrlvl_en & 0x1) << 31)
2245                                | ((wrlvl_mrd & 0x7) << 24)
2246                                | ((wrlvl_odten & 0x7) << 20)
2247                                | ((wrlvl_dqsen & 0x7) << 16)
2248                                | ((wrlvl_smpl & 0xf) << 12)
2249                                | ((wrlvl_wlr & 0x7) << 8)
2250                                | ((wrlvl_start & 0x1F) << 0)
2251                                );
2252         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2253         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2254         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2255         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2256         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2257
2258 }
2259
2260 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
2261 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2262 {
2263         /* Self Refresh Idle Threshold */
2264         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2265 }
2266
2267 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2268 {
2269         if (popts->addr_hash) {
2270                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
2271                 puts("Address hashing enabled.\n");
2272         }
2273 }
2274
2275 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2276 {
2277         ddr->ddr_cdr1 = popts->ddr_cdr1;
2278         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2279 }
2280
2281 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2282 {
2283         ddr->ddr_cdr2 = popts->ddr_cdr2;
2284         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2285 }
2286
2287 unsigned int
2288 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2289 {
2290         unsigned int res = 0;
2291
2292         /*
2293          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2294          * not set at the same time.
2295          */
2296         if (ddr->ddr_sdram_cfg & 0x10000000
2297             && ddr->ddr_sdram_cfg & 0x00008000) {
2298                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2299                                 " should not be set at the same time.\n");
2300                 res++;
2301         }
2302
2303         return res;
2304 }
2305
2306 unsigned int
2307 compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2308                                const memctl_options_t *popts,
2309                                fsl_ddr_cfg_regs_t *ddr,
2310                                const common_timing_params_t *common_dimm,
2311                                const dimm_params_t *dimm_params,
2312                                unsigned int dbw_cap_adj,
2313                                unsigned int size_only)
2314 {
2315         unsigned int i;
2316         unsigned int cas_latency;
2317         unsigned int additive_latency;
2318         unsigned int sr_it;
2319         unsigned int zq_en;
2320         unsigned int wrlvl_en;
2321         unsigned int ip_rev = 0;
2322         unsigned int unq_mrs_en = 0;
2323         int cs_en = 1;
2324 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2325         unsigned int ddr_freq;
2326 #endif
2327 #if (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
2328         defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
2329         defined(CONFIG_SYS_FSL_ERRATUM_A009942)
2330         struct ccsr_ddr __iomem *ddrc;
2331
2332         switch (ctrl_num) {
2333         case 0:
2334                 ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
2335                 break;
2336 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
2337         case 1:
2338                 ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
2339                 break;
2340 #endif
2341 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
2342         case 2:
2343                 ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
2344                 break;
2345 #endif
2346 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
2347         case 3:
2348                 ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
2349                 break;
2350 #endif
2351         default:
2352                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
2353                 return 1;
2354         }
2355 #endif
2356
2357         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2358
2359         if (common_dimm == NULL) {
2360                 printf("Error: subset DIMM params struct null pointer\n");
2361                 return 1;
2362         }
2363
2364         /*
2365          * Process overrides first.
2366          *
2367          * FIXME: somehow add dereated caslat to this
2368          */
2369         cas_latency = (popts->cas_latency_override)
2370                 ? popts->cas_latency_override_value
2371                 : common_dimm->lowest_common_spd_caslat;
2372
2373         additive_latency = (popts->additive_latency_override)
2374                 ? popts->additive_latency_override_value
2375                 : common_dimm->additive_latency;
2376
2377         sr_it = (popts->auto_self_refresh_en)
2378                 ? popts->sr_it
2379                 : 0;
2380         /* ZQ calibration */
2381         zq_en = (popts->zq_en) ? 1 : 0;
2382         /* write leveling */
2383         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2384
2385         /* Chip Select Memory Bounds (CSn_BNDS) */
2386         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2387                 unsigned long long ea, sa;
2388                 unsigned int cs_per_dimm
2389                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2390                 unsigned int dimm_number
2391                         = i / cs_per_dimm;
2392                 unsigned long long rank_density
2393                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2394
2395                 if (dimm_params[dimm_number].n_ranks == 0) {
2396                         debug("Skipping setup of CS%u "
2397                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2398                         continue;
2399                 }
2400                 if (popts->memctl_interleaving) {
2401                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2402                         case FSL_DDR_CS0_CS1_CS2_CS3:
2403                                 break;
2404                         case FSL_DDR_CS0_CS1:
2405                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2406                                 if (i > 1)
2407                                         cs_en = 0;
2408                                 break;
2409                         case FSL_DDR_CS2_CS3:
2410                         default:
2411                                 if (i > 0)
2412                                         cs_en = 0;
2413                                 break;
2414                         }
2415                         sa = common_dimm->base_address;
2416                         ea = sa + common_dimm->total_mem - 1;
2417                 } else if (!popts->memctl_interleaving) {
2418                         /*
2419                          * If memory interleaving between controllers is NOT
2420                          * enabled, the starting address for each memory
2421                          * controller is distinct.  However, because rank
2422                          * interleaving is enabled, the starting and ending
2423                          * addresses of the total memory on that memory
2424                          * controller needs to be programmed into its
2425                          * respective CS0_BNDS.
2426                          */
2427                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2428                         case FSL_DDR_CS0_CS1_CS2_CS3:
2429                                 sa = common_dimm->base_address;
2430                                 ea = sa + common_dimm->total_mem - 1;
2431                                 break;
2432                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2433                                 if ((i >= 2) && (dimm_number == 0)) {
2434                                         sa = dimm_params[dimm_number].base_address +
2435                                               2 * rank_density;
2436                                         ea = sa + 2 * rank_density - 1;
2437                                 } else {
2438                                         sa = dimm_params[dimm_number].base_address;
2439                                         ea = sa + 2 * rank_density - 1;
2440                                 }
2441                                 break;
2442                         case FSL_DDR_CS0_CS1:
2443                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2444                                         sa = dimm_params[dimm_number].base_address;
2445                                         ea = sa + rank_density - 1;
2446                                         if (i != 1)
2447                                                 sa += (i % cs_per_dimm) * rank_density;
2448                                         ea += (i % cs_per_dimm) * rank_density;
2449                                 } else {
2450                                         sa = 0;
2451                                         ea = 0;
2452                                 }
2453                                 if (i == 0)
2454                                         ea += rank_density;
2455                                 break;
2456                         case FSL_DDR_CS2_CS3:
2457                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2458                                         sa = dimm_params[dimm_number].base_address;
2459                                         ea = sa + rank_density - 1;
2460                                         if (i != 3)
2461                                                 sa += (i % cs_per_dimm) * rank_density;
2462                                         ea += (i % cs_per_dimm) * rank_density;
2463                                 } else {
2464                                         sa = 0;
2465                                         ea = 0;
2466                                 }
2467                                 if (i == 2)
2468                                         ea += (rank_density >> dbw_cap_adj);
2469                                 break;
2470                         default:  /* No bank(chip-select) interleaving */
2471                                 sa = dimm_params[dimm_number].base_address;
2472                                 ea = sa + rank_density - 1;
2473                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2474                                         sa += (i % cs_per_dimm) * rank_density;
2475                                         ea += (i % cs_per_dimm) * rank_density;
2476                                 } else {
2477                                         sa = 0;
2478                                         ea = 0;
2479                                 }
2480                                 break;
2481                         }
2482                 }
2483
2484                 sa >>= 24;
2485                 ea >>= 24;
2486
2487                 if (cs_en) {
2488                         ddr->cs[i].bnds = (0
2489                                 | ((sa & 0xffff) << 16) /* starting address */
2490                                 | ((ea & 0xffff) << 0)  /* ending address */
2491                                 );
2492                 } else {
2493                         /* setting bnds to 0xffffffff for inactive CS */
2494                         ddr->cs[i].bnds = 0xffffffff;
2495                 }
2496
2497                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2498                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2499                 set_csn_config_2(i, ddr);
2500         }
2501
2502         /*
2503          * In the case we only need to compute the ddr sdram size, we only need
2504          * to set csn registers, so return from here.
2505          */
2506         if (size_only)
2507                 return 0;
2508
2509         set_ddr_eor(ddr, popts);
2510
2511 #if !defined(CONFIG_SYS_FSL_DDR1)
2512         set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
2513 #endif
2514
2515         set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
2516                          additive_latency);
2517         set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2518         set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2519                          cas_latency, additive_latency);
2520
2521         set_ddr_cdr1(ddr, popts);
2522         set_ddr_cdr2(ddr, popts);
2523         set_ddr_sdram_cfg(ddr, popts, common_dimm);
2524         ip_rev = fsl_ddr_get_version(ctrl_num);
2525         if (ip_rev > 0x40400)
2526                 unq_mrs_en = 1;
2527
2528         if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2529                 ddr->debug[18] = popts->cswl_override;
2530
2531         set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2532         set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2533                            cas_latency, additive_latency, unq_mrs_en);
2534         set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2535 #ifdef CONFIG_SYS_FSL_DDR4
2536         set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2537         set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2538 #endif
2539         set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
2540         set_ddr_data_init(ddr);
2541         set_ddr_sdram_clk_cntl(ddr, popts);
2542         set_ddr_init_addr(ddr);
2543         set_ddr_init_ext_addr(ddr);
2544         set_timing_cfg_4(ddr, popts);
2545         set_timing_cfg_5(ddr, cas_latency);
2546 #ifdef CONFIG_SYS_FSL_DDR4
2547         set_ddr_sdram_cfg_3(ddr, popts);
2548         set_timing_cfg_6(ddr);
2549         set_timing_cfg_7(ctrl_num, ddr, popts, common_dimm);
2550         set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
2551         set_timing_cfg_9(ddr);
2552         set_ddr_dq_mapping(ddr, dimm_params);
2553 #endif
2554
2555         set_ddr_zq_cntl(ddr, zq_en);
2556         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2557
2558         set_ddr_sr_cntr(ddr, sr_it);
2559
2560         set_ddr_sdram_rcw(ddr, popts, common_dimm);
2561
2562 #ifdef CONFIG_SYS_FSL_DDR_EMU
2563         /* disble DDR training for emulator */
2564         ddr->debug[2] = 0x00000400;
2565         ddr->debug[4] = 0xff800800;
2566         ddr->debug[5] = 0x08000800;
2567         ddr->debug[6] = 0x08000800;
2568         ddr->debug[7] = 0x08000800;
2569         ddr->debug[8] = 0x08000800;
2570 #endif
2571 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2572         if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2573                 ddr->debug[2] |= 0x00000200;    /* set bit 22 */
2574 #endif
2575
2576 #if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
2577         /* Erratum applies when accumulated ECC is used, or DBI is enabled */
2578 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
2579 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
2580         if (has_erratum_a008378()) {
2581                 if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) ||
2582                     IS_DBI(ddr->ddr_sdram_cfg_3)) {
2583                         ddr->debug[28] = ddr_in32(&ddrc->debug[28]);
2584                         ddr->debug[28] |= (0x9 << 20);
2585                 }
2586         }
2587 #endif
2588
2589 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2590         ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
2591         ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);
2592         ddr->debug[28] &= 0xff0fff00;
2593         if (ddr_freq <= 1333)
2594                 ddr->debug[28] |= 0x0080006a;
2595         else if (ddr_freq <= 1600)
2596                 ddr->debug[28] |= 0x0070006f;
2597         else if (ddr_freq <= 1867)
2598                 ddr->debug[28] |= 0x00700076;
2599         else if (ddr_freq <= 2133)
2600                 ddr->debug[28] |= 0x0060007b;
2601         if (popts->cpo_sample)
2602                 ddr->debug[28] = (ddr->debug[28] & 0xffffff00) |
2603                                   popts->cpo_sample;
2604 #endif
2605
2606         return check_fsl_memctl_config_regs(ddr);
2607 }
2608
2609 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2610 /*
2611  * This additional workaround of A009942 checks the condition to determine if
2612  * the CPO value set by the existing A009942 workaround needs to be updated.
2613  * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with
2614  * expected optimal value, the optimal value is highly board dependent.
2615  */
2616 void erratum_a009942_check_cpo(void)
2617 {
2618         struct ccsr_ddr __iomem *ddr =
2619                 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
2620         u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
2621         u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
2622         u32 cpo_max = cpo_min;
2623         u32 sdram_cfg, i, tmp, lanes, ddr_type;
2624         bool update_cpo = false, has_ecc = false;
2625
2626         sdram_cfg = ddr_in32(&ddr->sdram_cfg);
2627         if (sdram_cfg & SDRAM_CFG_32_BE)
2628                 lanes = 4;
2629         else if (sdram_cfg & SDRAM_CFG_16_BE)
2630                 lanes = 2;
2631         else
2632                 lanes = 8;
2633
2634         if (sdram_cfg & SDRAM_CFG_ECC_EN)
2635                 has_ecc = true;
2636
2637         /* determine the maximum and minimum CPO values */
2638         for (i = 9; i < 9 + lanes / 2; i++) {
2639                 cpo = ddr_in32(&ddr->debug[i]);
2640                 cpo_e = cpo >> 24;
2641                 cpo_o = (cpo >> 8) & 0xff;
2642                 tmp = min(cpo_e, cpo_o);
2643                 if (tmp < cpo_min)
2644                         cpo_min = tmp;
2645                 tmp = max(cpo_e, cpo_o);
2646                 if (tmp > cpo_max)
2647                         cpo_max = tmp;
2648         }
2649
2650         if (has_ecc) {
2651                 cpo = ddr_in32(&ddr->debug[13]);
2652                 cpo = cpo >> 24;
2653                 if (cpo < cpo_min)
2654                         cpo_min = cpo;
2655                 if (cpo > cpo_max)
2656                         cpo_max = cpo;
2657         }
2658
2659         cpo_target = ddr_in32(&ddr->debug[28]) & 0xff;
2660         cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27;
2661         debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal,
2662               cpo_target);
2663         debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min);
2664
2665         ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
2666                     SDRAM_CFG_SDRAM_TYPE_SHIFT;
2667         if (ddr_type == SDRAM_TYPE_DDR4)
2668                 update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false;
2669         else if (ddr_type == SDRAM_TYPE_DDR3)
2670                 update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false;
2671
2672         if (update_cpo) {
2673                 printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal);
2674                 printf("in <board>/ddr.c to optimize cpo\n");
2675         }
2676 }
2677 #endif