git.sur5r.net Git - u-boot/blob - drivers/ddr/fsl/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  */
  12
  13 #include <common.h>
  14 #include <fsl_ddr_sdram.h>
  15
  16 #include <fsl_ddr.h>
  17 #include <fsl_immap.h>
  18 #include <asm/io.h>
  19
  20 #define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
  21
  22 static u32 fsl_ddr_get_version(void)
  23 {
  24         struct ccsr_ddr __iomem *ddr;
  25         u32 ver_major_minor_errata;
  26
  27         ddr = (void *)_DDR_ADDR;
  28         ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
  29         ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
  30
  31         return ver_major_minor_errata;
  32 }
  33
  34 unsigned int picos_to_mclk(unsigned int picos);
  35
  36 /*
  37  * Determine Rtt value.
  38  *
  39  * This should likely be either board or controller specific.
  40  *
  41  * Rtt(nominal) - DDR2:
  42  *      0 = Rtt disabled
  43  *      1 = 75 ohm
  44  *      2 = 150 ohm
  45  *      3 = 50 ohm
  46  * Rtt(nominal) - DDR3:
  47  *      0 = Rtt disabled
  48  *      1 = 60 ohm
  49  *      2 = 120 ohm
  50  *      3 = 40 ohm
  51  *      4 = 20 ohm
  52  *      5 = 30 ohm
  53  *
  54  * FIXME: Apparently 8641 needs a value of 2
  55  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  56  *
  57  * FIXME: There was some effort down this line earlier:
  58  *
  59  *      unsigned int i;
  60  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  61  *              if (popts->dimmslot[i].num_valid_cs
  62  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  63  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  64  *                      rtt = 2;
  65  *                      break;
  66  *              }
  67  *      }
  68  */
  69 static inline int fsl_ddr_get_rtt(void)
  70 {
  71         int rtt;
  72
  73 #if defined(CONFIG_SYS_FSL_DDR1)
  74         rtt = 0;
  75 #elif defined(CONFIG_SYS_FSL_DDR2)
  76         rtt = 3;
  77 #else
  78         rtt = 0;
  79 #endif
  80
  81         return rtt;
  82 }
  83
  84 /*
  85  * compute the CAS write latency according to DDR3 spec
  86  * CWL = 5 if tCK >= 2.5ns
  87  *       6 if 2.5ns > tCK >= 1.875ns
  88  *       7 if 1.875ns > tCK >= 1.5ns
  89  *       8 if 1.5ns > tCK >= 1.25ns
  90  *       9 if 1.25ns > tCK >= 1.07ns
  91  *       10 if 1.07ns > tCK >= 0.935ns
  92  *       11 if 0.935ns > tCK >= 0.833ns
  93  *       12 if 0.833ns > tCK >= 0.75ns
  94  */
  95 static inline unsigned int compute_cas_write_latency(void)
  96 {
  97         unsigned int cwl;
  98         const unsigned int mclk_ps = get_memory_clk_period_ps();
  99
 100         if (mclk_ps >= 2500)
 101                 cwl = 5;
 102         else if (mclk_ps >= 1875)
 103                 cwl = 6;
 104         else if (mclk_ps >= 1500)
 105                 cwl = 7;
 106         else if (mclk_ps >= 1250)
 107                 cwl = 8;
 108         else if (mclk_ps >= 1070)
 109                 cwl = 9;
 110         else if (mclk_ps >= 935)
 111                 cwl = 10;
 112         else if (mclk_ps >= 833)
 113                 cwl = 11;
 114         else if (mclk_ps >= 750)
 115                 cwl = 12;
 116         else {
 117                 cwl = 12;
 118                 printf("Warning: CWL is out of range\n");
 119         }
 120         return cwl;
 121 }
 122
 123 /* Chip Select Configuration (CSn_CONFIG) */
 124 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 125                                const memctl_options_t *popts,
 126                                const dimm_params_t *dimm_params)
 127 {
 128         unsigned int cs_n_en = 0; /* Chip Select enable */
 129         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 130         unsigned int intlv_ctl = 0; /* Interleaving control */
 131         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 132         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 133         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 134         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 135         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 136         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 137         int go_config = 0;
 138
 139         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 140         switch (i) {
 141         case 0:
 142                 if (dimm_params[dimm_number].n_ranks > 0) {
 143                         go_config = 1;
 144                         /* These fields only available in CS0_CONFIG */
 145                         if (!popts->memctl_interleaving)
 146                                 break;
 147                         switch (popts->memctl_interleaving_mode) {
 148                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 149                         case FSL_DDR_PAGE_INTERLEAVING:
 150                         case FSL_DDR_BANK_INTERLEAVING:
 151                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 152                                 intlv_en = popts->memctl_interleaving;
 153                                 intlv_ctl = popts->memctl_interleaving_mode;
 154                                 break;
 155                         default:
 156                                 break;
 157                         }
 158                 }
 159                 break;
 160         case 1:
 161                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 162                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 163                         go_config = 1;
 164                 break;
 165         case 2:
 166                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 167                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 168                         go_config = 1;
 169                 break;
 170         case 3:
 171                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 172                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 173                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 174                         go_config = 1;
 175                 break;
 176         default:
 177                 break;
 178         }
 179         if (go_config) {
 180                 unsigned int n_banks_per_sdram_device;
 181                 cs_n_en = 1;
 182                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 183                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 184                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 185                 n_banks_per_sdram_device
 186                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 187                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 188                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 189                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 190         }
 191         ddr->cs[i].config = (0
 192                 | ((cs_n_en & 0x1) << 31)
 193                 | ((intlv_en & 0x3) << 29)
 194                 | ((intlv_ctl & 0xf) << 24)
 195                 | ((ap_n_en & 0x1) << 23)
 196
 197                 /* XXX: some implementation only have 1 bit starting at left */
 198                 | ((odt_rd_cfg & 0x7) << 20)
 199
 200                 /* XXX: Some implementation only have 1 bit starting at left */
 201                 | ((odt_wr_cfg & 0x7) << 16)
 202
 203                 | ((ba_bits_cs_n & 0x3) << 14)
 204                 | ((row_bits_cs_n & 0x7) << 8)
 205                 | ((col_bits_cs_n & 0x7) << 0)
 206                 );
 207         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 208 }
 209
 210 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 211 /* FIXME: 8572 */
 212 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 213 {
 214         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 215
 216         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 217         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 218 }
 219
 220 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 221
 222 #if !defined(CONFIG_SYS_FSL_DDR1)
 223 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 224 {
 225 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 226         if (dimm_params[0].n_ranks == 4)
 227                 return 1;
 228 #endif
 229
 230 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 231         if ((dimm_params[0].n_ranks == 2) &&
 232                 (dimm_params[1].n_ranks == 2))
 233                 return 1;
 234
 235 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 236         if (dimm_params[0].n_ranks == 4)
 237                 return 1;
 238 #endif
 239 #endif
 240         return 0;
 241 }
 242
 243 /*
 244  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 245  *
 246  * Avoid writing for DDR I.  The new PQ38 DDR controller
 247  * dreams up non-zero default values to be backwards compatible.
 248  */
 249 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 250                                 const memctl_options_t *popts,
 251                                 const dimm_params_t *dimm_params)
 252 {
 253         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 254         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 255         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 256         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 257         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 258
 259         /* Active powerdown exit timing (tXARD and tXARDS). */
 260         unsigned char act_pd_exit_mclk;
 261         /* Precharge powerdown exit timing (tXP). */
 262         unsigned char pre_pd_exit_mclk;
 263         /* ODT powerdown exit timing (tAXPD). */
 264         unsigned char taxpd_mclk;
 265         /* Mode register set cycle time (tMRD). */
 266         unsigned char tmrd_mclk;
 267
 268 #ifdef CONFIG_SYS_FSL_DDR3
 269         /*
 270          * (tXARD and tXARDS). Empirical?
 271          * The DDR3 spec has not tXARD,
 272          * we use the tXP instead of it.
 273          * tXP=max(3nCK, 7.5ns) for DDR3.
 274          * spec has not the tAXPD, we use
 275          * tAXPD=1, need design to confirm.
 276          */
 277         int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
 278         unsigned int data_rate = get_ddr_freq(0);
 279         tmrd_mclk = 4;
 280         /* set the turnaround time */
 281
 282         /*
 283          * for single quad-rank DIMM and two dual-rank DIMMs
 284          * to avoid ODT overlap
 285          */
 286         if (avoid_odt_overlap(dimm_params)) {
 287                 twwt_mclk = 2;
 288                 trrt_mclk = 1;
 289         }
 290         /* for faster clock, need more time for data setup */
 291         trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 292
 293         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 294                 twrt_mclk = 1;
 295
 296         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 297                 act_pd_exit_mclk = 1;
 298                 pre_pd_exit_mclk = 1;
 299                 taxpd_mclk = 1;
 300         } else {
 301                 /* act_pd_exit_mclk = tXARD, see above */
 302                 act_pd_exit_mclk = picos_to_mclk(tXP);
 303                 /* Mode register MR0[A12] is '1' - fast exit */
 304                 pre_pd_exit_mclk = act_pd_exit_mclk;
 305                 taxpd_mclk = 1;
 306         }
 307 #else /* CONFIG_SYS_FSL_DDR2 */
 308         /*
 309          * (tXARD and tXARDS). Empirical?
 310          * tXARD = 2 for DDR2
 311          * tXP=2
 312          * tAXPD=8
 313          */
 314         act_pd_exit_mclk = 2;
 315         pre_pd_exit_mclk = 2;
 316         taxpd_mclk = 8;
 317         tmrd_mclk = 2;
 318 #endif
 319
 320         if (popts->trwt_override)
 321                 trwt_mclk = popts->trwt;
 322
 323         ddr->timing_cfg_0 = (0
 324                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 325                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 326                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 327                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 328                 | ((act_pd_exit_mclk & 0x7) << 20)  /* ACT_PD_EXIT */
 329                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 330                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 331                 | ((tmrd_mclk & 0xf) << 0)      /* MRS_CYC */
 332                 );
 333         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 334 }
 335 #endif  /* defined(CONFIG_SYS_FSL_DDR2) */
 336
 337 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 338 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 339                                const memctl_options_t *popts,
 340                                const common_timing_params_t *common_dimm,
 341                                unsigned int cas_latency)
 342 {
 343         /* Extended precharge to activate interval (tRP) */
 344         unsigned int ext_pretoact = 0;
 345         /* Extended Activate to precharge interval (tRAS) */
 346         unsigned int ext_acttopre = 0;
 347         /* Extended activate to read/write interval (tRCD) */
 348         unsigned int ext_acttorw = 0;
 349         /* Extended refresh recovery time (tRFC) */
 350         unsigned int ext_refrec;
 351         /* Extended MCAS latency from READ cmd */
 352         unsigned int ext_caslat = 0;
 353         /* Extended last data to precharge interval (tWR) */
 354         unsigned int ext_wrrec = 0;
 355         /* Control Adjust */
 356         unsigned int cntl_adj = 0;
 357
 358         ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
 359         ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
 360         ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
 361         ext_caslat = (2 * cas_latency - 1) >> 4;
 362         ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
 363         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 364         ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
 365                 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 366
 367         ddr->timing_cfg_3 = (0
 368                 | ((ext_pretoact & 0x1) << 28)
 369                 | ((ext_acttopre & 0x3) << 24)
 370                 | ((ext_acttorw & 0x1) << 22)
 371                 | ((ext_refrec & 0x1F) << 16)
 372                 | ((ext_caslat & 0x3) << 12)
 373                 | ((ext_wrrec & 0x1) << 8)
 374                 | ((cntl_adj & 0x7) << 0)
 375                 );
 376         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 377 }
 378
 379 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 380 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 381                                const memctl_options_t *popts,
 382                                const common_timing_params_t *common_dimm,
 383                                unsigned int cas_latency)
 384 {
 385         /* Precharge-to-activate interval (tRP) */
 386         unsigned char pretoact_mclk;
 387         /* Activate to precharge interval (tRAS) */
 388         unsigned char acttopre_mclk;
 389         /*  Activate to read/write interval (tRCD) */
 390         unsigned char acttorw_mclk;
 391         /* CASLAT */
 392         unsigned char caslat_ctrl;
 393         /*  Refresh recovery time (tRFC) ; trfc_low */
 394         unsigned char refrec_ctrl;
 395         /* Last data to precharge minimum interval (tWR) */
 396         unsigned char wrrec_mclk;
 397         /* Activate-to-activate interval (tRRD) */
 398         unsigned char acttoact_mclk;
 399         /* Last write data pair to read command issue interval (tWTR) */
 400         unsigned char wrtord_mclk;
 401         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 402         static const u8 wrrec_table[] = {
 403                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 404
 405         pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
 406         acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
 407         acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
 408
 409         /*
 410          * Translate CAS Latency to a DDR controller field value:
 411          *
 412          *      CAS Lat DDR I   DDR II  Ctrl
 413          *      Clocks  SPD Bit SPD Bit Value
 414          *      ------- ------- ------- -----
 415          *      1.0     0               0001
 416          *      1.5     1               0010
 417          *      2.0     2       2       0011
 418          *      2.5     3               0100
 419          *      3.0     4       3       0101
 420          *      3.5     5               0110
 421          *      4.0             4       0111
 422          *      4.5                     1000
 423          *      5.0             5       1001
 424          */
 425 #if defined(CONFIG_SYS_FSL_DDR1)
 426         caslat_ctrl = (cas_latency + 1) & 0x07;
 427 #elif defined(CONFIG_SYS_FSL_DDR2)
 428         caslat_ctrl = 2 * cas_latency - 1;
 429 #else
 430         /*
 431          * if the CAS latency more than 8 cycle,
 432          * we need set extend bit for it at
 433          * TIMING_CFG_3[EXT_CASLAT]
 434          */
 435         caslat_ctrl = 2 * cas_latency - 1;
 436 #endif
 437
 438         refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
 439         wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
 440
 441         if (wrrec_mclk > 16)
 442                 printf("Error: WRREC doesn't support more than 16 clocks\n");
 443         else
 444                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 445         if (popts->otf_burst_chop_en)
 446                 wrrec_mclk += 2;
 447
 448         acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
 449         /*
 450          * JEDEC has min requirement for tRRD
 451          */
 452 #if defined(CONFIG_SYS_FSL_DDR3)
 453         if (acttoact_mclk < 4)
 454                 acttoact_mclk = 4;
 455 #endif
 456         wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
 457         /*
 458          * JEDEC has some min requirements for tWTR
 459          */
 460 #if defined(CONFIG_SYS_FSL_DDR2)
 461         if (wrtord_mclk < 2)
 462                 wrtord_mclk = 2;
 463 #elif defined(CONFIG_SYS_FSL_DDR3)
 464         if (wrtord_mclk < 4)
 465                 wrtord_mclk = 4;
 466 #endif
 467         if (popts->otf_burst_chop_en)
 468                 wrtord_mclk += 2;
 469
 470         ddr->timing_cfg_1 = (0
 471                 | ((pretoact_mclk & 0x0F) << 28)
 472                 | ((acttopre_mclk & 0x0F) << 24)
 473                 | ((acttorw_mclk & 0xF) << 20)
 474                 | ((caslat_ctrl & 0xF) << 16)
 475                 | ((refrec_ctrl & 0xF) << 12)
 476                 | ((wrrec_mclk & 0x0F) << 8)
 477                 | ((acttoact_mclk & 0x0F) << 4)
 478                 | ((wrtord_mclk & 0x0F) << 0)
 479                 );
 480         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 481 }
 482
 483 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 484 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 485                                const memctl_options_t *popts,
 486                                const common_timing_params_t *common_dimm,
 487                                unsigned int cas_latency,
 488                                unsigned int additive_latency)
 489 {
 490         /* Additive latency */
 491         unsigned char add_lat_mclk;
 492         /* CAS-to-preamble override */
 493         unsigned short cpo;
 494         /* Write latency */
 495         unsigned char wr_lat;
 496         /*  Read to precharge (tRTP) */
 497         unsigned char rd_to_pre;
 498         /* Write command to write data strobe timing adjustment */
 499         unsigned char wr_data_delay;
 500         /* Minimum CKE pulse width (tCKE) */
 501         unsigned char cke_pls;
 502         /* Window for four activates (tFAW) */
 503         unsigned short four_act;
 504
 505         /* FIXME add check that this must be less than acttorw_mclk */
 506         add_lat_mclk = additive_latency;
 507         cpo = popts->cpo_override;
 508
 509 #if defined(CONFIG_SYS_FSL_DDR1)
 510         /*
 511          * This is a lie.  It should really be 1, but if it is
 512          * set to 1, bits overlap into the old controller's
 513          * otherwise unused ACSM field.  If we leave it 0, then
 514          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 515          */
 516         wr_lat = 0;
 517 #elif defined(CONFIG_SYS_FSL_DDR2)
 518         wr_lat = cas_latency - 1;
 519 #else
 520         wr_lat = compute_cas_write_latency();
 521 #endif
 522
 523         rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
 524         /*
 525          * JEDEC has some min requirements for tRTP
 526          */
 527 #if defined(CONFIG_SYS_FSL_DDR2)
 528         if (rd_to_pre  < 2)
 529                 rd_to_pre  = 2;
 530 #elif defined(CONFIG_SYS_FSL_DDR3)
 531         if (rd_to_pre < 4)
 532                 rd_to_pre = 4;
 533 #endif
 534         if (additive_latency)
 535                 rd_to_pre += additive_latency;
 536         if (popts->otf_burst_chop_en)
 537                 rd_to_pre += 2; /* according to UM */
 538
 539         wr_data_delay = popts->write_data_delay;
 540         cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
 541         four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
 542
 543         ddr->timing_cfg_2 = (0
 544                 | ((add_lat_mclk & 0xf) << 28)
 545                 | ((cpo & 0x1f) << 23)
 546                 | ((wr_lat & 0xf) << 19)
 547                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 548                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 549                 | ((cke_pls & 0x7) << 6)
 550                 | ((four_act & 0x3f) << 0)
 551                 );
 552         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 553 }
 554
 555 /* DDR SDRAM Register Control Word */
 556 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 557                                const memctl_options_t *popts,
 558                                const common_timing_params_t *common_dimm)
 559 {
 560         if (common_dimm->all_dimms_registered &&
 561             !common_dimm->all_dimms_unbuffered) {
 562                 if (popts->rcw_override) {
 563                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 564                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 565                 } else {
 566                         ddr->ddr_sdram_rcw_1 =
 567                                 common_dimm->rcw[0] << 28 | \
 568                                 common_dimm->rcw[1] << 24 | \
 569                                 common_dimm->rcw[2] << 20 | \
 570                                 common_dimm->rcw[3] << 16 | \
 571                                 common_dimm->rcw[4] << 12 | \
 572                                 common_dimm->rcw[5] << 8 | \
 573                                 common_dimm->rcw[6] << 4 | \
 574                                 common_dimm->rcw[7];
 575                         ddr->ddr_sdram_rcw_2 =
 576                                 common_dimm->rcw[8] << 28 | \
 577                                 common_dimm->rcw[9] << 24 | \
 578                                 common_dimm->rcw[10] << 20 | \
 579                                 common_dimm->rcw[11] << 16 | \
 580                                 common_dimm->rcw[12] << 12 | \
 581                                 common_dimm->rcw[13] << 8 | \
 582                                 common_dimm->rcw[14] << 4 | \
 583                                 common_dimm->rcw[15];
 584                 }
 585                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 586                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 587         }
 588 }
 589
 590 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 591 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 592                                const memctl_options_t *popts,
 593                                const common_timing_params_t *common_dimm)
 594 {
 595         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 596         unsigned int sren;              /* Self refresh enable (during sleep) */
 597         unsigned int ecc_en;            /* ECC enable. */
 598         unsigned int rd_en;             /* Registered DIMM enable */
 599         unsigned int sdram_type;        /* Type of SDRAM */
 600         unsigned int dyn_pwr;           /* Dynamic power management mode */
 601         unsigned int dbw;               /* DRAM dta bus width */
 602         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 603         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 604         unsigned int threet_en;         /* Enable 3T timing */
 605         unsigned int twot_en;           /* Enable 2T timing */
 606         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 607         unsigned int x32_en = 0;        /* x32 enable */
 608         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 609         unsigned int hse;               /* Global half strength override */
 610         unsigned int mem_halt = 0;      /* memory controller halt */
 611         unsigned int bi = 0;            /* Bypass initialization */
 612
 613         mem_en = 1;
 614         sren = popts->self_refresh_in_sleep;
 615         if (common_dimm->all_dimms_ecc_capable) {
 616                 /* Allow setting of ECC only if all DIMMs are ECC. */
 617                 ecc_en = popts->ecc_mode;
 618         } else {
 619                 ecc_en = 0;
 620         }
 621
 622         if (common_dimm->all_dimms_registered &&
 623             !common_dimm->all_dimms_unbuffered) {
 624                 rd_en = 1;
 625                 twot_en = 0;
 626         } else {
 627                 rd_en = 0;
 628                 twot_en = popts->twot_en;
 629         }
 630
 631         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 632
 633         dyn_pwr = popts->dynamic_power;
 634         dbw = popts->data_bus_width;
 635         /* 8-beat burst enable DDR-III case
 636          * we must clear it when use the on-the-fly mode,
 637          * must set it when use the 32-bits bus mode.
 638          */
 639         if (sdram_type == SDRAM_TYPE_DDR3) {
 640                 if (popts->burst_length == DDR_BL8)
 641                         eight_be = 1;
 642                 if (popts->burst_length == DDR_OTF)
 643                         eight_be = 0;
 644                 if (dbw == 0x1)
 645                         eight_be = 1;
 646         }
 647
 648         threet_en = popts->threet_en;
 649         ba_intlv_ctl = popts->ba_intlv_ctl;
 650         hse = popts->half_strength_driver_enable;
 651
 652         ddr->ddr_sdram_cfg = (0
 653                         | ((mem_en & 0x1) << 31)
 654                         | ((sren & 0x1) << 30)
 655                         | ((ecc_en & 0x1) << 29)
 656                         | ((rd_en & 0x1) << 28)
 657                         | ((sdram_type & 0x7) << 24)
 658                         | ((dyn_pwr & 0x1) << 21)
 659                         | ((dbw & 0x3) << 19)
 660                         | ((eight_be & 0x1) << 18)
 661                         | ((ncap & 0x1) << 17)
 662                         | ((threet_en & 0x1) << 16)
 663                         | ((twot_en & 0x1) << 15)
 664                         | ((ba_intlv_ctl & 0x7F) << 8)
 665                         | ((x32_en & 0x1) << 5)
 666                         | ((pchb8 & 0x1) << 4)
 667                         | ((hse & 0x1) << 3)
 668                         | ((mem_halt & 0x1) << 1)
 669                         | ((bi & 0x1) << 0)
 670                         );
 671         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 672 }
 673
 674 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 675 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 676                                const memctl_options_t *popts,
 677                                const unsigned int unq_mrs_en)
 678 {
 679         unsigned int frc_sr = 0;        /* Force self refresh */
 680         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 681         unsigned int dll_rst_dis;       /* DLL reset disable */
 682         unsigned int dqs_cfg;           /* DQS configuration */
 683         unsigned int odt_cfg = 0;       /* ODT configuration */
 684         unsigned int num_pr;            /* Number of posted refreshes */
 685         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 686         unsigned int x4_en = 0;         /* x4 DRAM enable */
 687         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 688         unsigned int ap_en;             /* Address Parity Enable */
 689         unsigned int d_init;            /* DRAM data initialization */
 690         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 691         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 692         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 693         int i;
 694
 695         dll_rst_dis = 1;        /* Make this configurable */
 696         dqs_cfg = popts->dqs_config;
 697         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 698                 if (popts->cs_local_opts[i].odt_rd_cfg
 699                         || popts->cs_local_opts[i].odt_wr_cfg) {
 700                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 701                         break;
 702                 }
 703         }
 704
 705         num_pr = 1;     /* Make this configurable */
 706
 707         /*
 708          * 8572 manual says
 709          *     {TIMING_CFG_1[PRETOACT]
 710          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 711          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 712          *      << DDR_SDRAM_INTERVAL[REFINT]
 713          */
 714 #if defined(CONFIG_SYS_FSL_DDR3)
 715         obc_cfg = popts->otf_burst_chop_en;
 716 #else
 717         obc_cfg = 0;
 718 #endif
 719
 720 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 721         slow = get_ddr_freq(0) < 1249000000;
 722 #endif
 723
 724         if (popts->registered_dimm_en) {
 725                 rcw_en = 1;
 726                 ap_en = popts->ap_en;
 727         } else {
 728                 ap_en = 0;
 729         }
 730
 731         x4_en = popts->x4_en ? 1 : 0;
 732
 733 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 734         /* Use the DDR controller to auto initialize memory. */
 735         d_init = popts->ecc_init_using_memctl;
 736         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 737         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 738 #else
 739         /* Memory will be initialized via DMA, or not at all. */
 740         d_init = 0;
 741 #endif
 742
 743 #if defined(CONFIG_SYS_FSL_DDR3)
 744         md_en = popts->mirrored_dimm;
 745 #endif
 746         qd_en = popts->quad_rank_present ? 1 : 0;
 747         ddr->ddr_sdram_cfg_2 = (0
 748                 | ((frc_sr & 0x1) << 31)
 749                 | ((sr_ie & 0x1) << 30)
 750                 | ((dll_rst_dis & 0x1) << 29)
 751                 | ((dqs_cfg & 0x3) << 26)
 752                 | ((odt_cfg & 0x3) << 21)
 753                 | ((num_pr & 0xf) << 12)
 754                 | ((slow & 1) << 11)
 755                 | (x4_en << 10)
 756                 | (qd_en << 9)
 757                 | (unq_mrs_en << 8)
 758                 | ((obc_cfg & 0x1) << 6)
 759                 | ((ap_en & 0x1) << 5)
 760                 | ((d_init & 0x1) << 4)
 761                 | ((rcw_en & 0x1) << 2)
 762                 | ((md_en & 0x1) << 0)
 763                 );
 764         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 765 }
 766
 767 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 768 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 769                                 const memctl_options_t *popts,
 770                                 const common_timing_params_t *common_dimm,
 771                                 const unsigned int unq_mrs_en)
 772 {
 773         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 774         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 775
 776 #if defined(CONFIG_SYS_FSL_DDR3)
 777         int i;
 778         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 779         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 780         unsigned int asr = 0;   /* auto self-refresh disable */
 781         unsigned int cwl = compute_cas_write_latency() - 5;
 782         unsigned int pasr = 0;  /* partial array self refresh disable */
 783
 784         if (popts->rtt_override)
 785                 rtt_wr = popts->rtt_wr_override_value;
 786         else
 787                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 788
 789         if (common_dimm->extended_op_srt)
 790                 srt = common_dimm->extended_op_srt;
 791
 792         esdmode2 = (0
 793                 | ((rtt_wr & 0x3) << 9)
 794                 | ((srt & 0x1) << 7)
 795                 | ((asr & 0x1) << 6)
 796                 | ((cwl & 0x7) << 3)
 797                 | ((pasr & 0x7) << 0));
 798 #endif
 799         ddr->ddr_sdram_mode_2 = (0
 800                                  | ((esdmode2 & 0xFFFF) << 16)
 801                                  | ((esdmode3 & 0xFFFF) << 0)
 802                                  );
 803         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 804
 805 #ifdef CONFIG_SYS_FSL_DDR3
 806         if (unq_mrs_en) {       /* unique mode registers are supported */
 807                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 808                         if (popts->rtt_override)
 809                                 rtt_wr = popts->rtt_wr_override_value;
 810                         else
 811                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 812
 813                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 814                         esdmode2 |= (rtt_wr & 0x3) << 9;
 815                         switch (i) {
 816                         case 1:
 817                                 ddr->ddr_sdram_mode_4 = (0
 818                                         | ((esdmode2 & 0xFFFF) << 16)
 819                                         | ((esdmode3 & 0xFFFF) << 0)
 820                                         );
 821                                 break;
 822                         case 2:
 823                                 ddr->ddr_sdram_mode_6 = (0
 824                                         | ((esdmode2 & 0xFFFF) << 16)
 825                                         | ((esdmode3 & 0xFFFF) << 0)
 826                                         );
 827                                 break;
 828                         case 3:
 829                                 ddr->ddr_sdram_mode_8 = (0
 830                                         | ((esdmode2 & 0xFFFF) << 16)
 831                                         | ((esdmode3 & 0xFFFF) << 0)
 832                                         );
 833                                 break;
 834                         }
 835                 }
 836                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
 837                         ddr->ddr_sdram_mode_4);
 838                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
 839                         ddr->ddr_sdram_mode_6);
 840                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
 841                         ddr->ddr_sdram_mode_8);
 842         }
 843 #endif
 844 }
 845
 846 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
 847 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 848                                const memctl_options_t *popts,
 849                                const common_timing_params_t *common_dimm)
 850 {
 851         unsigned int refint;    /* Refresh interval */
 852         unsigned int bstopre;   /* Precharge interval */
 853
 854         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
 855
 856         bstopre = popts->bstopre;
 857
 858         /* refint field used 0x3FFF in earlier controllers */
 859         ddr->ddr_sdram_interval = (0
 860                                    | ((refint & 0xFFFF) << 16)
 861                                    | ((bstopre & 0x3FFF) << 0)
 862                                    );
 863         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 864 }
 865
 866 #if defined(CONFIG_SYS_FSL_DDR3)
 867 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 868 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 869                                const memctl_options_t *popts,
 870                                const common_timing_params_t *common_dimm,
 871                                unsigned int cas_latency,
 872                                unsigned int additive_latency,
 873                                const unsigned int unq_mrs_en)
 874 {
 875         unsigned short esdmode;         /* Extended SDRAM mode */
 876         unsigned short sdmode;          /* SDRAM mode */
 877
 878         /* Mode Register - MR1 */
 879         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
 880         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
 881         unsigned int rtt;
 882         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
 883         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
 884         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
 885         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 886                                                        1=Disable (Test/Debug) */
 887
 888         /* Mode Register - MR0 */
 889         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
 890         unsigned int wr = 0;    /* Write Recovery */
 891         unsigned int dll_rst;   /* DLL Reset */
 892         unsigned int mode;      /* Normal=0 or Test=1 */
 893         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
 894         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
 895         unsigned int bt;
 896         unsigned int bl;        /* BL: Burst Length */
 897
 898         unsigned int wr_mclk;
 899         /*
 900          * DDR_SDRAM_MODE doesn't support 9,11,13,15
 901          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
 902          * for this table
 903          */
 904         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
 905
 906         const unsigned int mclk_ps = get_memory_clk_period_ps();
 907         int i;
 908
 909         if (popts->rtt_override)
 910                 rtt = popts->rtt_override_value;
 911         else
 912                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
 913
 914         if (additive_latency == (cas_latency - 1))
 915                 al = 1;
 916         if (additive_latency == (cas_latency - 2))
 917                 al = 2;
 918
 919         if (popts->quad_rank_present)
 920                 dic = 1;        /* output driver impedance 240/7 ohm */
 921
 922         /*
 923          * The esdmode value will also be used for writing
 924          * MR1 during write leveling for DDR3, although the
 925          * bits specifically related to the write leveling
 926          * scheme will be handled automatically by the DDR
 927          * controller. so we set the wrlvl_en = 0 here.
 928          */
 929         esdmode = (0
 930                 | ((qoff & 0x1) << 12)
 931                 | ((tdqs_en & 0x1) << 11)
 932                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 933                 | ((wrlvl_en & 0x1) << 7)
 934                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 935                 | ((dic & 0x2) << 4)   /* DIC field is split */
 936                 | ((al & 0x3) << 3)
 937                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 938                 | ((dic & 0x1) << 1)   /* DIC field is split */
 939                 | ((dll_en & 0x1) << 0)
 940                 );
 941
 942         /*
 943          * DLL control for precharge PD
 944          * 0=slow exit DLL off (tXPDLL)
 945          * 1=fast exit DLL on (tXP)
 946          */
 947         dll_on = 1;
 948
 949         wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps;
 950         if (wr_mclk <= 16) {
 951                 wr = wr_table[wr_mclk - 5];
 952         } else {
 953                 printf("Error: unsupported write recovery for mode register "
 954                        "wr_mclk = %d\n", wr_mclk);
 955         }
 956
 957         dll_rst = 0;    /* dll no reset */
 958         mode = 0;       /* normal mode */
 959
 960         /* look up table to get the cas latency bits */
 961         if (cas_latency >= 5 && cas_latency <= 16) {
 962                 unsigned char cas_latency_table[] = {
 963                         0x2,    /* 5 clocks */
 964                         0x4,    /* 6 clocks */
 965                         0x6,    /* 7 clocks */
 966                         0x8,    /* 8 clocks */
 967                         0xa,    /* 9 clocks */
 968                         0xc,    /* 10 clocks */
 969                         0xe,    /* 11 clocks */
 970                         0x1,    /* 12 clocks */
 971                         0x3,    /* 13 clocks */
 972                         0x5,    /* 14 clocks */
 973                         0x7,    /* 15 clocks */
 974                         0x9,    /* 16 clocks */
 975                 };
 976                 caslat = cas_latency_table[cas_latency - 5];
 977         } else {
 978                 printf("Error: unsupported cas latency for mode register\n");
 979         }
 980
 981         bt = 0; /* Nibble sequential */
 982
 983         switch (popts->burst_length) {
 984         case DDR_BL8:
 985                 bl = 0;
 986                 break;
 987         case DDR_OTF:
 988                 bl = 1;
 989                 break;
 990         case DDR_BC4:
 991                 bl = 2;
 992                 break;
 993         default:
 994                 printf("Error: invalid burst length of %u specified. "
 995                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
 996                         popts->burst_length);
 997                 bl = 1;
 998                 break;
 999         }
1000
1001         sdmode = (0
1002                   | ((dll_on & 0x1) << 12)
1003                   | ((wr & 0x7) << 9)
1004                   | ((dll_rst & 0x1) << 8)
1005                   | ((mode & 0x1) << 7)
1006                   | (((caslat >> 1) & 0x7) << 4)
1007                   | ((bt & 0x1) << 3)
1008                   | ((caslat & 1) << 2)
1009                   | ((bl & 0x3) << 0)
1010                   );
1011
1012         ddr->ddr_sdram_mode = (0
1013                                | ((esdmode & 0xFFFF) << 16)
1014                                | ((sdmode & 0xFFFF) << 0)
1015                                );
1016
1017         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1018
1019         if (unq_mrs_en) {       /* unique mode registers are supported */
1020                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1021                         if (popts->rtt_override)
1022                                 rtt = popts->rtt_override_value;
1023                         else
1024                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1025
1026                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1027                         esdmode |= (0
1028                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1029                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1030                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1031                                 );
1032                         switch (i) {
1033                         case 1:
1034                                 ddr->ddr_sdram_mode_3 = (0
1035                                        | ((esdmode & 0xFFFF) << 16)
1036                                        | ((sdmode & 0xFFFF) << 0)
1037                                        );
1038                                 break;
1039                         case 2:
1040                                 ddr->ddr_sdram_mode_5 = (0
1041                                        | ((esdmode & 0xFFFF) << 16)
1042                                        | ((sdmode & 0xFFFF) << 0)
1043                                        );
1044                                 break;
1045                         case 3:
1046                                 ddr->ddr_sdram_mode_7 = (0
1047                                        | ((esdmode & 0xFFFF) << 16)
1048                                        | ((sdmode & 0xFFFF) << 0)
1049                                        );
1050                                 break;
1051                         }
1052                 }
1053                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1054                         ddr->ddr_sdram_mode_3);
1055                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1056                         ddr->ddr_sdram_mode_5);
1057                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1058                         ddr->ddr_sdram_mode_5);
1059         }
1060 }
1061
1062 #else /* !CONFIG_SYS_FSL_DDR3 */
1063
1064 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1065 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1066                                const memctl_options_t *popts,
1067                                const common_timing_params_t *common_dimm,
1068                                unsigned int cas_latency,
1069                                unsigned int additive_latency,
1070                                const unsigned int unq_mrs_en)
1071 {
1072         unsigned short esdmode;         /* Extended SDRAM mode */
1073         unsigned short sdmode;          /* SDRAM mode */
1074
1075         /*
1076          * FIXME: This ought to be pre-calculated in a
1077          * technology-specific routine,
1078          * e.g. compute_DDR2_mode_register(), and then the
1079          * sdmode and esdmode passed in as part of common_dimm.
1080          */
1081
1082         /* Extended Mode Register */
1083         unsigned int mrs = 0;           /* Mode Register Set */
1084         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1085         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1086         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1087         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1088                                            0x7=OCD default state */
1089         unsigned int rtt;
1090         unsigned int al;                /* Posted CAS# additive latency (AL) */
1091         unsigned int ods = 0;           /* Output Drive Strength:
1092                                                 0 = Full strength (18ohm)
1093                                                 1 = Reduced strength (4ohm) */
1094         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1095                                                        1=Disable (Test/Debug) */
1096
1097         /* Mode Register (MR) */
1098         unsigned int mr;        /* Mode Register Definition */
1099         unsigned int pd;        /* Power-Down Mode */
1100         unsigned int wr;        /* Write Recovery */
1101         unsigned int dll_res;   /* DLL Reset */
1102         unsigned int mode;      /* Normal=0 or Test=1 */
1103         unsigned int caslat = 0;/* CAS# latency */
1104         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1105         unsigned int bt;
1106         unsigned int bl;        /* BL: Burst Length */
1107
1108 #if defined(CONFIG_SYS_FSL_DDR2)
1109         const unsigned int mclk_ps = get_memory_clk_period_ps();
1110 #endif
1111         dqs_en = !popts->dqs_config;
1112         rtt = fsl_ddr_get_rtt();
1113
1114         al = additive_latency;
1115
1116         esdmode = (0
1117                 | ((mrs & 0x3) << 14)
1118                 | ((outputs & 0x1) << 12)
1119                 | ((rdqs_en & 0x1) << 11)
1120                 | ((dqs_en & 0x1) << 10)
1121                 | ((ocd & 0x7) << 7)
1122                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1123                 | ((al & 0x7) << 3)
1124                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1125                 | ((ods & 0x1) << 1)
1126                 | ((dll_en & 0x1) << 0)
1127                 );
1128
1129         mr = 0;          /* FIXME: CHECKME */
1130
1131         /*
1132          * 0 = Fast Exit (Normal)
1133          * 1 = Slow Exit (Low Power)
1134          */
1135         pd = 0;
1136
1137 #if defined(CONFIG_SYS_FSL_DDR1)
1138         wr = 0;       /* Historical */
1139 #elif defined(CONFIG_SYS_FSL_DDR2)
1140         wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1;
1141 #endif
1142         dll_res = 0;
1143         mode = 0;
1144
1145 #if defined(CONFIG_SYS_FSL_DDR1)
1146         if (1 <= cas_latency && cas_latency <= 4) {
1147                 unsigned char mode_caslat_table[4] = {
1148                         0x5,    /* 1.5 clocks */
1149                         0x2,    /* 2.0 clocks */
1150                         0x6,    /* 2.5 clocks */
1151                         0x3     /* 3.0 clocks */
1152                 };
1153                 caslat = mode_caslat_table[cas_latency - 1];
1154         } else {
1155                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1156         }
1157 #elif defined(CONFIG_SYS_FSL_DDR2)
1158         caslat = cas_latency;
1159 #endif
1160         bt = 0;
1161
1162         switch (popts->burst_length) {
1163         case DDR_BL4:
1164                 bl = 2;
1165                 break;
1166         case DDR_BL8:
1167                 bl = 3;
1168                 break;
1169         default:
1170                 printf("Error: invalid burst length of %u specified. "
1171                         " Defaulting to 4 beats.\n",
1172                         popts->burst_length);
1173                 bl = 2;
1174                 break;
1175         }
1176
1177         sdmode = (0
1178                   | ((mr & 0x3) << 14)
1179                   | ((pd & 0x1) << 12)
1180                   | ((wr & 0x7) << 9)
1181                   | ((dll_res & 0x1) << 8)
1182                   | ((mode & 0x1) << 7)
1183                   | ((caslat & 0x7) << 4)
1184                   | ((bt & 0x1) << 3)
1185                   | ((bl & 0x7) << 0)
1186                   );
1187
1188         ddr->ddr_sdram_mode = (0
1189                                | ((esdmode & 0xFFFF) << 16)
1190                                | ((sdmode & 0xFFFF) << 0)
1191                                );
1192         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1193 }
1194 #endif
1195
1196 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1197 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1198 {
1199         unsigned int init_value;        /* Initialization value */
1200
1201 #ifdef CONFIG_MEM_INIT_VALUE
1202         init_value = CONFIG_MEM_INIT_VALUE;
1203 #else
1204         init_value = 0xDEADBEEF;
1205 #endif
1206         ddr->ddr_data_init = init_value;
1207 }
1208
1209 /*
1210  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1211  * The old controller on the 8540/60 doesn't have this register.
1212  * Hope it's OK to set it (to 0) anyway.
1213  */
1214 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1215                                          const memctl_options_t *popts)
1216 {
1217         unsigned int clk_adjust;        /* Clock adjust */
1218
1219         clk_adjust = popts->clk_adjust;
1220         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1221         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1222 }
1223
1224 /* DDR Initialization Address (DDR_INIT_ADDR) */
1225 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1226 {
1227         unsigned int init_addr = 0;     /* Initialization address */
1228
1229         ddr->ddr_init_addr = init_addr;
1230 }
1231
1232 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1233 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1234 {
1235         unsigned int uia = 0;   /* Use initialization address */
1236         unsigned int init_ext_addr = 0; /* Initialization address */
1237
1238         ddr->ddr_init_ext_addr = (0
1239                                   | ((uia & 0x1) << 31)
1240                                   | (init_ext_addr & 0xF)
1241                                   );
1242 }
1243
1244 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1245 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1246                                 const memctl_options_t *popts)
1247 {
1248         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1249         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1250         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1251         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1252         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1253
1254 #if defined(CONFIG_SYS_FSL_DDR3)
1255         if (popts->burst_length == DDR_BL8) {
1256                 /* We set BL/2 for fixed BL8 */
1257                 rrt = 0;        /* BL/2 clocks */
1258                 wwt = 0;        /* BL/2 clocks */
1259         } else {
1260                 /* We need to set BL/2 + 2 to BC4 and OTF */
1261                 rrt = 2;        /* BL/2 + 2 clocks */
1262                 wwt = 2;        /* BL/2 + 2 clocks */
1263         }
1264         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1265 #endif
1266         ddr->timing_cfg_4 = (0
1267                              | ((rwt & 0xf) << 28)
1268                              | ((wrt & 0xf) << 24)
1269                              | ((rrt & 0xf) << 20)
1270                              | ((wwt & 0xf) << 16)
1271                              | (dll_lock & 0x3)
1272                              );
1273         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1274 }
1275
1276 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1277 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1278 {
1279         unsigned int rodt_on = 0;       /* Read to ODT on */
1280         unsigned int rodt_off = 0;      /* Read to ODT off */
1281         unsigned int wodt_on = 0;       /* Write to ODT on */
1282         unsigned int wodt_off = 0;      /* Write to ODT off */
1283
1284 #if defined(CONFIG_SYS_FSL_DDR3)
1285         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1286         rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1287         rodt_off = 4;   /*  4 clocks */
1288         wodt_on = 1;    /*  1 clocks */
1289         wodt_off = 4;   /*  4 clocks */
1290 #endif
1291
1292         ddr->timing_cfg_5 = (0
1293                              | ((rodt_on & 0x1f) << 24)
1294                              | ((rodt_off & 0x7) << 20)
1295                              | ((wodt_on & 0x1f) << 12)
1296                              | ((wodt_off & 0x7) << 8)
1297                              );
1298         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1299 }
1300
1301 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1302 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1303 {
1304         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1305         /* Normal Operation Full Calibration Time (tZQoper) */
1306         unsigned int zqoper = 0;
1307         /* Normal Operation Short Calibration Time (tZQCS) */
1308         unsigned int zqcs = 0;
1309
1310         if (zq_en) {
1311                 zqinit = 9;     /* 512 clocks */
1312                 zqoper = 8;     /* 256 clocks */
1313                 zqcs = 6;       /* 64 clocks */
1314         }
1315
1316         ddr->ddr_zq_cntl = (0
1317                             | ((zq_en & 0x1) << 31)
1318                             | ((zqinit & 0xF) << 24)
1319                             | ((zqoper & 0xF) << 16)
1320                             | ((zqcs & 0xF) << 8)
1321                             );
1322         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1323 }
1324
1325 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1326 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1327                                 const memctl_options_t *popts)
1328 {
1329         /*
1330          * First DQS pulse rising edge after margining mode
1331          * is programmed (tWL_MRD)
1332          */
1333         unsigned int wrlvl_mrd = 0;
1334         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1335         unsigned int wrlvl_odten = 0;
1336         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1337         unsigned int wrlvl_dqsen = 0;
1338         /* WRLVL_SMPL: Write leveling sample time */
1339         unsigned int wrlvl_smpl = 0;
1340         /* WRLVL_WLR: Write leveling repeition time */
1341         unsigned int wrlvl_wlr = 0;
1342         /* WRLVL_START: Write leveling start time */
1343         unsigned int wrlvl_start = 0;
1344
1345         /* suggest enable write leveling for DDR3 due to fly-by topology */
1346         if (wrlvl_en) {
1347                 /* tWL_MRD min = 40 nCK, we set it 64 */
1348                 wrlvl_mrd = 0x6;
1349                 /* tWL_ODTEN 128 */
1350                 wrlvl_odten = 0x7;
1351                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1352                 wrlvl_dqsen = 0x5;
1353                 /*
1354                  * Write leveling sample time at least need 6 clocks
1355                  * higher than tWLO to allow enough time for progagation
1356                  * delay and sampling the prime data bits.
1357                  */
1358                 wrlvl_smpl = 0xf;
1359                 /*
1360                  * Write leveling repetition time
1361                  * at least tWLO + 6 clocks clocks
1362                  * we set it 64
1363                  */
1364                 wrlvl_wlr = 0x6;
1365                 /*
1366                  * Write leveling start time
1367                  * The value use for the DQS_ADJUST for the first sample
1368                  * when write leveling is enabled. It probably needs to be
1369                  * overriden per platform.
1370                  */
1371                 wrlvl_start = 0x8;
1372                 /*
1373                  * Override the write leveling sample and start time
1374                  * according to specific board
1375                  */
1376                 if (popts->wrlvl_override) {
1377                         wrlvl_smpl = popts->wrlvl_sample;
1378                         wrlvl_start = popts->wrlvl_start;
1379                 }
1380         }
1381
1382         ddr->ddr_wrlvl_cntl = (0
1383                                | ((wrlvl_en & 0x1) << 31)
1384                                | ((wrlvl_mrd & 0x7) << 24)
1385                                | ((wrlvl_odten & 0x7) << 20)
1386                                | ((wrlvl_dqsen & 0x7) << 16)
1387                                | ((wrlvl_smpl & 0xf) << 12)
1388                                | ((wrlvl_wlr & 0x7) << 8)
1389                                | ((wrlvl_start & 0x1F) << 0)
1390                                );
1391         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1392         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
1393         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
1394         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
1395         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
1396
1397 }
1398
1399 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1400 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1401 {
1402         /* Self Refresh Idle Threshold */
1403         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1404 }
1405
1406 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1407 {
1408         if (popts->addr_hash) {
1409                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
1410                 puts("Address hashing enabled.\n");
1411         }
1412 }
1413
1414 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1415 {
1416         ddr->ddr_cdr1 = popts->ddr_cdr1;
1417         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1418 }
1419
1420 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1421 {
1422         ddr->ddr_cdr2 = popts->ddr_cdr2;
1423         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
1424 }
1425
1426 unsigned int
1427 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1428 {
1429         unsigned int res = 0;
1430
1431         /*
1432          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1433          * not set at the same time.
1434          */
1435         if (ddr->ddr_sdram_cfg & 0x10000000
1436             && ddr->ddr_sdram_cfg & 0x00008000) {
1437                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1438                                 " should not be set at the same time.\n");
1439                 res++;
1440         }
1441
1442         return res;
1443 }
1444
1445 unsigned int
1446 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1447                                fsl_ddr_cfg_regs_t *ddr,
1448                                const common_timing_params_t *common_dimm,
1449                                const dimm_params_t *dimm_params,
1450                                unsigned int dbw_cap_adj,
1451                                unsigned int size_only)
1452 {
1453         unsigned int i;
1454         unsigned int cas_latency;
1455         unsigned int additive_latency;
1456         unsigned int sr_it;
1457         unsigned int zq_en;
1458         unsigned int wrlvl_en;
1459         unsigned int ip_rev = 0;
1460         unsigned int unq_mrs_en = 0;
1461         int cs_en = 1;
1462
1463         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1464
1465         if (common_dimm == NULL) {
1466                 printf("Error: subset DIMM params struct null pointer\n");
1467                 return 1;
1468         }
1469
1470         /*
1471          * Process overrides first.
1472          *
1473          * FIXME: somehow add dereated caslat to this
1474          */
1475         cas_latency = (popts->cas_latency_override)
1476                 ? popts->cas_latency_override_value
1477                 : common_dimm->lowest_common_SPD_caslat;
1478
1479         additive_latency = (popts->additive_latency_override)
1480                 ? popts->additive_latency_override_value
1481                 : common_dimm->additive_latency;
1482
1483         sr_it = (popts->auto_self_refresh_en)
1484                 ? popts->sr_it
1485                 : 0;
1486         /* ZQ calibration */
1487         zq_en = (popts->zq_en) ? 1 : 0;
1488         /* write leveling */
1489         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1490
1491         /* Chip Select Memory Bounds (CSn_BNDS) */
1492         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1493                 unsigned long long ea, sa;
1494                 unsigned int cs_per_dimm
1495                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1496                 unsigned int dimm_number
1497                         = i / cs_per_dimm;
1498                 unsigned long long rank_density
1499                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
1500
1501                 if (dimm_params[dimm_number].n_ranks == 0) {
1502                         debug("Skipping setup of CS%u "
1503                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1504                         continue;
1505                 }
1506                 if (popts->memctl_interleaving) {
1507                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1508                         case FSL_DDR_CS0_CS1_CS2_CS3:
1509                                 break;
1510                         case FSL_DDR_CS0_CS1:
1511                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1512                                 if (i > 1)
1513                                         cs_en = 0;
1514                                 break;
1515                         case FSL_DDR_CS2_CS3:
1516                         default:
1517                                 if (i > 0)
1518                                         cs_en = 0;
1519                                 break;
1520                         }
1521                         sa = common_dimm->base_address;
1522                         ea = sa + common_dimm->total_mem - 1;
1523                 } else if (!popts->memctl_interleaving) {
1524                         /*
1525                          * If memory interleaving between controllers is NOT
1526                          * enabled, the starting address for each memory
1527                          * controller is distinct.  However, because rank
1528                          * interleaving is enabled, the starting and ending
1529                          * addresses of the total memory on that memory
1530                          * controller needs to be programmed into its
1531                          * respective CS0_BNDS.
1532                          */
1533                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1534                         case FSL_DDR_CS0_CS1_CS2_CS3:
1535                                 sa = common_dimm->base_address;
1536                                 ea = sa + common_dimm->total_mem - 1;
1537                                 break;
1538                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1539                                 if ((i >= 2) && (dimm_number == 0)) {
1540                                         sa = dimm_params[dimm_number].base_address +
1541                                               2 * rank_density;
1542                                         ea = sa + 2 * rank_density - 1;
1543                                 } else {
1544                                         sa = dimm_params[dimm_number].base_address;
1545                                         ea = sa + 2 * rank_density - 1;
1546                                 }
1547                                 break;
1548                         case FSL_DDR_CS0_CS1:
1549                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1550                                         sa = dimm_params[dimm_number].base_address;
1551                                         ea = sa + rank_density - 1;
1552                                         if (i != 1)
1553                                                 sa += (i % cs_per_dimm) * rank_density;
1554                                         ea += (i % cs_per_dimm) * rank_density;
1555                                 } else {
1556                                         sa = 0;
1557                                         ea = 0;
1558                                 }
1559                                 if (i == 0)
1560                                         ea += rank_density;
1561                                 break;
1562                         case FSL_DDR_CS2_CS3:
1563                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1564                                         sa = dimm_params[dimm_number].base_address;
1565                                         ea = sa + rank_density - 1;
1566                                         if (i != 3)
1567                                                 sa += (i % cs_per_dimm) * rank_density;
1568                                         ea += (i % cs_per_dimm) * rank_density;
1569                                 } else {
1570                                         sa = 0;
1571                                         ea = 0;
1572                                 }
1573                                 if (i == 2)
1574                                         ea += (rank_density >> dbw_cap_adj);
1575                                 break;
1576                         default:  /* No bank(chip-select) interleaving */
1577                                 sa = dimm_params[dimm_number].base_address;
1578                                 ea = sa + rank_density - 1;
1579                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1580                                         sa += (i % cs_per_dimm) * rank_density;
1581                                         ea += (i % cs_per_dimm) * rank_density;
1582                                 } else {
1583                                         sa = 0;
1584                                         ea = 0;
1585                                 }
1586                                 break;
1587                         }
1588                 }
1589
1590                 sa >>= 24;
1591                 ea >>= 24;
1592
1593                 if (cs_en) {
1594                         ddr->cs[i].bnds = (0
1595                                 | ((sa & 0xFFF) << 16)/* starting address MSB */
1596                                 | ((ea & 0xFFF) << 0)   /* ending address MSB */
1597                                 );
1598                 } else {
1599                         /* setting bnds to 0xffffffff for inactive CS */
1600                         ddr->cs[i].bnds = 0xffffffff;
1601                 }
1602
1603                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1604                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1605                 set_csn_config_2(i, ddr);
1606         }
1607
1608         /*
1609          * In the case we only need to compute the ddr sdram size, we only need
1610          * to set csn registers, so return from here.
1611          */
1612         if (size_only)
1613                 return 0;
1614
1615         set_ddr_eor(ddr, popts);
1616
1617 #if !defined(CONFIG_SYS_FSL_DDR1)
1618         set_timing_cfg_0(ddr, popts, dimm_params);
1619 #endif
1620
1621         set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
1622         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1623         set_timing_cfg_2(ddr, popts, common_dimm,
1624                                 cas_latency, additive_latency);
1625
1626         set_ddr_cdr1(ddr, popts);
1627         set_ddr_cdr2(ddr, popts);
1628         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1629         ip_rev = fsl_ddr_get_version();
1630         if (ip_rev > 0x40400)
1631                 unq_mrs_en = 1;
1632
1633         set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1634         set_ddr_sdram_mode(ddr, popts, common_dimm,
1635                                 cas_latency, additive_latency, unq_mrs_en);
1636         set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
1637         set_ddr_sdram_interval(ddr, popts, common_dimm);
1638         set_ddr_data_init(ddr);
1639         set_ddr_sdram_clk_cntl(ddr, popts);
1640         set_ddr_init_addr(ddr);
1641         set_ddr_init_ext_addr(ddr);
1642         set_timing_cfg_4(ddr, popts);
1643         set_timing_cfg_5(ddr, cas_latency);
1644
1645         set_ddr_zq_cntl(ddr, zq_en);
1646         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1647
1648         set_ddr_sr_cntr(ddr, sr_it);
1649
1650         set_ddr_sdram_rcw(ddr, popts, common_dimm);
1651
1652 #ifdef CONFIG_SYS_FSL_DDR_EMU
1653         /* disble DDR training for emulator */
1654         ddr->debug[2] = 0x00000400;
1655         ddr->debug[4] = 0xff800000;
1656 #endif
1657         return check_fsl_memctl_config_regs(ddr);
1658 }