2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
14 #include <fsl_ddr_sdram.h>
19 #define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
21 static u32 fsl_ddr_get_version(void)
24 u32 ver_major_minor_errata;
26 ddr = (void *)_DDR_ADDR;
27 ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
28 ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
30 return ver_major_minor_errata;
33 unsigned int picos_to_mclk(unsigned int picos);
36 * Determine Rtt value.
38 * This should likely be either board or controller specific.
40 * Rtt(nominal) - DDR2:
45 * Rtt(nominal) - DDR3:
53 * FIXME: Apparently 8641 needs a value of 2
54 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
56 * FIXME: There was some effort down this line earlier:
59 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
60 * if (popts->dimmslot[i].num_valid_cs
61 * && (popts->cs_local_opts[2*i].odt_rd_cfg
62 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
68 static inline int fsl_ddr_get_rtt(void)
72 #if defined(CONFIG_SYS_FSL_DDR1)
74 #elif defined(CONFIG_SYS_FSL_DDR2)
84 * compute the CAS write latency according to DDR3 spec
85 * CWL = 5 if tCK >= 2.5ns
86 * 6 if 2.5ns > tCK >= 1.875ns
87 * 7 if 1.875ns > tCK >= 1.5ns
88 * 8 if 1.5ns > tCK >= 1.25ns
89 * 9 if 1.25ns > tCK >= 1.07ns
90 * 10 if 1.07ns > tCK >= 0.935ns
91 * 11 if 0.935ns > tCK >= 0.833ns
92 * 12 if 0.833ns > tCK >= 0.75ns
94 static inline unsigned int compute_cas_write_latency(void)
97 const unsigned int mclk_ps = get_memory_clk_period_ps();
101 else if (mclk_ps >= 1875)
103 else if (mclk_ps >= 1500)
105 else if (mclk_ps >= 1250)
107 else if (mclk_ps >= 1070)
109 else if (mclk_ps >= 935)
111 else if (mclk_ps >= 833)
113 else if (mclk_ps >= 750)
117 printf("Warning: CWL is out of range\n");
122 /* Chip Select Configuration (CSn_CONFIG) */
123 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
124 const memctl_options_t *popts,
125 const dimm_params_t *dimm_params)
127 unsigned int cs_n_en = 0; /* Chip Select enable */
128 unsigned int intlv_en = 0; /* Memory controller interleave enable */
129 unsigned int intlv_ctl = 0; /* Interleaving control */
130 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
131 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
132 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
133 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
134 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
135 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
138 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
141 if (dimm_params[dimm_number].n_ranks > 0) {
143 /* These fields only available in CS0_CONFIG */
144 if (!popts->memctl_interleaving)
146 switch (popts->memctl_interleaving_mode) {
147 case FSL_DDR_CACHE_LINE_INTERLEAVING:
148 case FSL_DDR_PAGE_INTERLEAVING:
149 case FSL_DDR_BANK_INTERLEAVING:
150 case FSL_DDR_SUPERBANK_INTERLEAVING:
151 intlv_en = popts->memctl_interleaving;
152 intlv_ctl = popts->memctl_interleaving_mode;
160 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
161 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
165 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
166 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
170 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
171 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
172 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
179 unsigned int n_banks_per_sdram_device;
181 ap_n_en = popts->cs_local_opts[i].auto_precharge;
182 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
183 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
184 n_banks_per_sdram_device
185 = dimm_params[dimm_number].n_banks_per_sdram_device;
186 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
187 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
188 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
190 ddr->cs[i].config = (0
191 | ((cs_n_en & 0x1) << 31)
192 | ((intlv_en & 0x3) << 29)
193 | ((intlv_ctl & 0xf) << 24)
194 | ((ap_n_en & 0x1) << 23)
196 /* XXX: some implementation only have 1 bit starting at left */
197 | ((odt_rd_cfg & 0x7) << 20)
199 /* XXX: Some implementation only have 1 bit starting at left */
200 | ((odt_wr_cfg & 0x7) << 16)
202 | ((ba_bits_cs_n & 0x3) << 14)
203 | ((row_bits_cs_n & 0x7) << 8)
204 | ((col_bits_cs_n & 0x7) << 0)
206 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
209 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
211 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
213 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
215 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
216 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
219 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
221 #if !defined(CONFIG_SYS_FSL_DDR1)
222 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
224 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
225 if (dimm_params[0].n_ranks == 4)
229 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
230 if ((dimm_params[0].n_ranks == 2) &&
231 (dimm_params[1].n_ranks == 2))
234 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
235 if (dimm_params[0].n_ranks == 4)
243 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
245 * Avoid writing for DDR I. The new PQ38 DDR controller
246 * dreams up non-zero default values to be backwards compatible.
248 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
249 const memctl_options_t *popts,
250 const dimm_params_t *dimm_params)
252 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
253 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
254 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
255 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
256 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
258 /* Active powerdown exit timing (tXARD and tXARDS). */
259 unsigned char act_pd_exit_mclk;
260 /* Precharge powerdown exit timing (tXP). */
261 unsigned char pre_pd_exit_mclk;
262 /* ODT powerdown exit timing (tAXPD). */
263 unsigned char taxpd_mclk;
264 /* Mode register set cycle time (tMRD). */
265 unsigned char tmrd_mclk;
267 #ifdef CONFIG_SYS_FSL_DDR3
269 * (tXARD and tXARDS). Empirical?
270 * The DDR3 spec has not tXARD,
271 * we use the tXP instead of it.
272 * tXP=max(3nCK, 7.5ns) for DDR3.
273 * spec has not the tAXPD, we use
274 * tAXPD=1, need design to confirm.
276 int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
277 unsigned int data_rate = get_ddr_freq(0);
279 /* set the turnaround time */
282 * for single quad-rank DIMM and two dual-rank DIMMs
283 * to avoid ODT overlap
285 if (avoid_odt_overlap(dimm_params)) {
289 /* for faster clock, need more time for data setup */
290 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
292 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
295 if (popts->dynamic_power == 0) { /* powerdown is not used */
296 act_pd_exit_mclk = 1;
297 pre_pd_exit_mclk = 1;
300 /* act_pd_exit_mclk = tXARD, see above */
301 act_pd_exit_mclk = picos_to_mclk(tXP);
302 /* Mode register MR0[A12] is '1' - fast exit */
303 pre_pd_exit_mclk = act_pd_exit_mclk;
306 #else /* CONFIG_SYS_FSL_DDR2 */
308 * (tXARD and tXARDS). Empirical?
313 act_pd_exit_mclk = 2;
314 pre_pd_exit_mclk = 2;
319 if (popts->trwt_override)
320 trwt_mclk = popts->trwt;
322 ddr->timing_cfg_0 = (0
323 | ((trwt_mclk & 0x3) << 30) /* RWT */
324 | ((twrt_mclk & 0x3) << 28) /* WRT */
325 | ((trrt_mclk & 0x3) << 26) /* RRT */
326 | ((twwt_mclk & 0x3) << 24) /* WWT */
327 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
328 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
329 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
330 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
332 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
334 #endif /* defined(CONFIG_SYS_FSL_DDR2) */
336 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
337 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
338 const memctl_options_t *popts,
339 const common_timing_params_t *common_dimm,
340 unsigned int cas_latency)
342 /* Extended precharge to activate interval (tRP) */
343 unsigned int ext_pretoact = 0;
344 /* Extended Activate to precharge interval (tRAS) */
345 unsigned int ext_acttopre = 0;
346 /* Extended activate to read/write interval (tRCD) */
347 unsigned int ext_acttorw = 0;
348 /* Extended refresh recovery time (tRFC) */
349 unsigned int ext_refrec;
350 /* Extended MCAS latency from READ cmd */
351 unsigned int ext_caslat = 0;
352 /* Extended last data to precharge interval (tWR) */
353 unsigned int ext_wrrec = 0;
355 unsigned int cntl_adj = 0;
357 ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
358 ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
359 ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
360 ext_caslat = (2 * cas_latency - 1) >> 4;
361 ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
362 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
363 ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
364 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
366 ddr->timing_cfg_3 = (0
367 | ((ext_pretoact & 0x1) << 28)
368 | ((ext_acttopre & 0x3) << 24)
369 | ((ext_acttorw & 0x1) << 22)
370 | ((ext_refrec & 0x1F) << 16)
371 | ((ext_caslat & 0x3) << 12)
372 | ((ext_wrrec & 0x1) << 8)
373 | ((cntl_adj & 0x7) << 0)
375 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
378 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
379 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
380 const memctl_options_t *popts,
381 const common_timing_params_t *common_dimm,
382 unsigned int cas_latency)
384 /* Precharge-to-activate interval (tRP) */
385 unsigned char pretoact_mclk;
386 /* Activate to precharge interval (tRAS) */
387 unsigned char acttopre_mclk;
388 /* Activate to read/write interval (tRCD) */
389 unsigned char acttorw_mclk;
391 unsigned char caslat_ctrl;
392 /* Refresh recovery time (tRFC) ; trfc_low */
393 unsigned char refrec_ctrl;
394 /* Last data to precharge minimum interval (tWR) */
395 unsigned char wrrec_mclk;
396 /* Activate-to-activate interval (tRRD) */
397 unsigned char acttoact_mclk;
398 /* Last write data pair to read command issue interval (tWTR) */
399 unsigned char wrtord_mclk;
400 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
401 static const u8 wrrec_table[] = {
402 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
404 pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
405 acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
406 acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
409 * Translate CAS Latency to a DDR controller field value:
411 * CAS Lat DDR I DDR II Ctrl
412 * Clocks SPD Bit SPD Bit Value
413 * ------- ------- ------- -----
424 #if defined(CONFIG_SYS_FSL_DDR1)
425 caslat_ctrl = (cas_latency + 1) & 0x07;
426 #elif defined(CONFIG_SYS_FSL_DDR2)
427 caslat_ctrl = 2 * cas_latency - 1;
430 * if the CAS latency more than 8 cycle,
431 * we need set extend bit for it at
432 * TIMING_CFG_3[EXT_CASLAT]
434 caslat_ctrl = 2 * cas_latency - 1;
437 refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
438 wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
441 printf("Error: WRREC doesn't support more than 16 clocks\n");
443 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
444 if (popts->otf_burst_chop_en)
447 acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
449 * JEDEC has min requirement for tRRD
451 #if defined(CONFIG_SYS_FSL_DDR3)
452 if (acttoact_mclk < 4)
455 wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
457 * JEDEC has some min requirements for tWTR
459 #if defined(CONFIG_SYS_FSL_DDR2)
462 #elif defined(CONFIG_SYS_FSL_DDR3)
466 if (popts->otf_burst_chop_en)
469 ddr->timing_cfg_1 = (0
470 | ((pretoact_mclk & 0x0F) << 28)
471 | ((acttopre_mclk & 0x0F) << 24)
472 | ((acttorw_mclk & 0xF) << 20)
473 | ((caslat_ctrl & 0xF) << 16)
474 | ((refrec_ctrl & 0xF) << 12)
475 | ((wrrec_mclk & 0x0F) << 8)
476 | ((acttoact_mclk & 0x0F) << 4)
477 | ((wrtord_mclk & 0x0F) << 0)
479 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
482 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
483 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
484 const memctl_options_t *popts,
485 const common_timing_params_t *common_dimm,
486 unsigned int cas_latency,
487 unsigned int additive_latency)
489 /* Additive latency */
490 unsigned char add_lat_mclk;
491 /* CAS-to-preamble override */
494 unsigned char wr_lat;
495 /* Read to precharge (tRTP) */
496 unsigned char rd_to_pre;
497 /* Write command to write data strobe timing adjustment */
498 unsigned char wr_data_delay;
499 /* Minimum CKE pulse width (tCKE) */
500 unsigned char cke_pls;
501 /* Window for four activates (tFAW) */
502 unsigned short four_act;
504 /* FIXME add check that this must be less than acttorw_mclk */
505 add_lat_mclk = additive_latency;
506 cpo = popts->cpo_override;
508 #if defined(CONFIG_SYS_FSL_DDR1)
510 * This is a lie. It should really be 1, but if it is
511 * set to 1, bits overlap into the old controller's
512 * otherwise unused ACSM field. If we leave it 0, then
513 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
516 #elif defined(CONFIG_SYS_FSL_DDR2)
517 wr_lat = cas_latency - 1;
519 wr_lat = compute_cas_write_latency();
522 rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
524 * JEDEC has some min requirements for tRTP
526 #if defined(CONFIG_SYS_FSL_DDR2)
529 #elif defined(CONFIG_SYS_FSL_DDR3)
533 if (additive_latency)
534 rd_to_pre += additive_latency;
535 if (popts->otf_burst_chop_en)
536 rd_to_pre += 2; /* according to UM */
538 wr_data_delay = popts->write_data_delay;
539 cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
540 four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
542 ddr->timing_cfg_2 = (0
543 | ((add_lat_mclk & 0xf) << 28)
544 | ((cpo & 0x1f) << 23)
545 | ((wr_lat & 0xf) << 19)
546 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
547 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
548 | ((cke_pls & 0x7) << 6)
549 | ((four_act & 0x3f) << 0)
551 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
554 /* DDR SDRAM Register Control Word */
555 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
556 const memctl_options_t *popts,
557 const common_timing_params_t *common_dimm)
559 if (common_dimm->all_dimms_registered &&
560 !common_dimm->all_dimms_unbuffered) {
561 if (popts->rcw_override) {
562 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
563 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
565 ddr->ddr_sdram_rcw_1 =
566 common_dimm->rcw[0] << 28 | \
567 common_dimm->rcw[1] << 24 | \
568 common_dimm->rcw[2] << 20 | \
569 common_dimm->rcw[3] << 16 | \
570 common_dimm->rcw[4] << 12 | \
571 common_dimm->rcw[5] << 8 | \
572 common_dimm->rcw[6] << 4 | \
574 ddr->ddr_sdram_rcw_2 =
575 common_dimm->rcw[8] << 28 | \
576 common_dimm->rcw[9] << 24 | \
577 common_dimm->rcw[10] << 20 | \
578 common_dimm->rcw[11] << 16 | \
579 common_dimm->rcw[12] << 12 | \
580 common_dimm->rcw[13] << 8 | \
581 common_dimm->rcw[14] << 4 | \
582 common_dimm->rcw[15];
584 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
585 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
589 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
590 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
591 const memctl_options_t *popts,
592 const common_timing_params_t *common_dimm)
594 unsigned int mem_en; /* DDR SDRAM interface logic enable */
595 unsigned int sren; /* Self refresh enable (during sleep) */
596 unsigned int ecc_en; /* ECC enable. */
597 unsigned int rd_en; /* Registered DIMM enable */
598 unsigned int sdram_type; /* Type of SDRAM */
599 unsigned int dyn_pwr; /* Dynamic power management mode */
600 unsigned int dbw; /* DRAM dta bus width */
601 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
602 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
603 unsigned int threet_en; /* Enable 3T timing */
604 unsigned int twot_en; /* Enable 2T timing */
605 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
606 unsigned int x32_en = 0; /* x32 enable */
607 unsigned int pchb8 = 0; /* precharge bit 8 enable */
608 unsigned int hse; /* Global half strength override */
609 unsigned int mem_halt = 0; /* memory controller halt */
610 unsigned int bi = 0; /* Bypass initialization */
613 sren = popts->self_refresh_in_sleep;
614 if (common_dimm->all_dimms_ecc_capable) {
615 /* Allow setting of ECC only if all DIMMs are ECC. */
616 ecc_en = popts->ecc_mode;
621 if (common_dimm->all_dimms_registered &&
622 !common_dimm->all_dimms_unbuffered) {
627 twot_en = popts->twot_en;
630 sdram_type = CONFIG_FSL_SDRAM_TYPE;
632 dyn_pwr = popts->dynamic_power;
633 dbw = popts->data_bus_width;
634 /* 8-beat burst enable DDR-III case
635 * we must clear it when use the on-the-fly mode,
636 * must set it when use the 32-bits bus mode.
638 if (sdram_type == SDRAM_TYPE_DDR3) {
639 if (popts->burst_length == DDR_BL8)
641 if (popts->burst_length == DDR_OTF)
647 threet_en = popts->threet_en;
648 ba_intlv_ctl = popts->ba_intlv_ctl;
649 hse = popts->half_strength_driver_enable;
651 ddr->ddr_sdram_cfg = (0
652 | ((mem_en & 0x1) << 31)
653 | ((sren & 0x1) << 30)
654 | ((ecc_en & 0x1) << 29)
655 | ((rd_en & 0x1) << 28)
656 | ((sdram_type & 0x7) << 24)
657 | ((dyn_pwr & 0x1) << 21)
658 | ((dbw & 0x3) << 19)
659 | ((eight_be & 0x1) << 18)
660 | ((ncap & 0x1) << 17)
661 | ((threet_en & 0x1) << 16)
662 | ((twot_en & 0x1) << 15)
663 | ((ba_intlv_ctl & 0x7F) << 8)
664 | ((x32_en & 0x1) << 5)
665 | ((pchb8 & 0x1) << 4)
667 | ((mem_halt & 0x1) << 1)
670 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
673 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
674 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
675 const memctl_options_t *popts,
676 const unsigned int unq_mrs_en)
678 unsigned int frc_sr = 0; /* Force self refresh */
679 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
680 unsigned int dll_rst_dis; /* DLL reset disable */
681 unsigned int dqs_cfg; /* DQS configuration */
682 unsigned int odt_cfg = 0; /* ODT configuration */
683 unsigned int num_pr; /* Number of posted refreshes */
684 unsigned int slow = 0; /* DDR will be run less than 1250 */
685 unsigned int x4_en = 0; /* x4 DRAM enable */
686 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
687 unsigned int ap_en; /* Address Parity Enable */
688 unsigned int d_init; /* DRAM data initialization */
689 unsigned int rcw_en = 0; /* Register Control Word Enable */
690 unsigned int md_en = 0; /* Mirrored DIMM Enable */
691 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
694 dll_rst_dis = 1; /* Make this configurable */
695 dqs_cfg = popts->dqs_config;
696 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
697 if (popts->cs_local_opts[i].odt_rd_cfg
698 || popts->cs_local_opts[i].odt_wr_cfg) {
699 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
704 num_pr = 1; /* Make this configurable */
708 * {TIMING_CFG_1[PRETOACT]
709 * + [DDR_SDRAM_CFG_2[NUM_PR]
710 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
711 * << DDR_SDRAM_INTERVAL[REFINT]
713 #if defined(CONFIG_SYS_FSL_DDR3)
714 obc_cfg = popts->otf_burst_chop_en;
719 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
720 slow = get_ddr_freq(0) < 1249000000;
723 if (popts->registered_dimm_en) {
725 ap_en = popts->ap_en;
730 x4_en = popts->x4_en ? 1 : 0;
732 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
733 /* Use the DDR controller to auto initialize memory. */
734 d_init = popts->ecc_init_using_memctl;
735 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
736 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
738 /* Memory will be initialized via DMA, or not at all. */
742 #if defined(CONFIG_SYS_FSL_DDR3)
743 md_en = popts->mirrored_dimm;
745 qd_en = popts->quad_rank_present ? 1 : 0;
746 ddr->ddr_sdram_cfg_2 = (0
747 | ((frc_sr & 0x1) << 31)
748 | ((sr_ie & 0x1) << 30)
749 | ((dll_rst_dis & 0x1) << 29)
750 | ((dqs_cfg & 0x3) << 26)
751 | ((odt_cfg & 0x3) << 21)
752 | ((num_pr & 0xf) << 12)
757 | ((obc_cfg & 0x1) << 6)
758 | ((ap_en & 0x1) << 5)
759 | ((d_init & 0x1) << 4)
760 | ((rcw_en & 0x1) << 2)
761 | ((md_en & 0x1) << 0)
763 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
766 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
767 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
768 const memctl_options_t *popts,
769 const common_timing_params_t *common_dimm,
770 const unsigned int unq_mrs_en)
772 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
773 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
775 #if defined(CONFIG_SYS_FSL_DDR3)
777 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
778 unsigned int srt = 0; /* self-refresh temerature, normal range */
779 unsigned int asr = 0; /* auto self-refresh disable */
780 unsigned int cwl = compute_cas_write_latency() - 5;
781 unsigned int pasr = 0; /* partial array self refresh disable */
783 if (popts->rtt_override)
784 rtt_wr = popts->rtt_wr_override_value;
786 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
788 if (common_dimm->extended_op_srt)
789 srt = common_dimm->extended_op_srt;
792 | ((rtt_wr & 0x3) << 9)
796 | ((pasr & 0x7) << 0));
798 ddr->ddr_sdram_mode_2 = (0
799 | ((esdmode2 & 0xFFFF) << 16)
800 | ((esdmode3 & 0xFFFF) << 0)
802 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
804 #ifdef CONFIG_SYS_FSL_DDR3
805 if (unq_mrs_en) { /* unique mode registers are supported */
806 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
807 if (popts->rtt_override)
808 rtt_wr = popts->rtt_wr_override_value;
810 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
812 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
813 esdmode2 |= (rtt_wr & 0x3) << 9;
816 ddr->ddr_sdram_mode_4 = (0
817 | ((esdmode2 & 0xFFFF) << 16)
818 | ((esdmode3 & 0xFFFF) << 0)
822 ddr->ddr_sdram_mode_6 = (0
823 | ((esdmode2 & 0xFFFF) << 16)
824 | ((esdmode3 & 0xFFFF) << 0)
828 ddr->ddr_sdram_mode_8 = (0
829 | ((esdmode2 & 0xFFFF) << 16)
830 | ((esdmode3 & 0xFFFF) << 0)
835 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
836 ddr->ddr_sdram_mode_4);
837 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
838 ddr->ddr_sdram_mode_6);
839 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
840 ddr->ddr_sdram_mode_8);
845 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
846 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
847 const memctl_options_t *popts,
848 const common_timing_params_t *common_dimm)
850 unsigned int refint; /* Refresh interval */
851 unsigned int bstopre; /* Precharge interval */
853 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
855 bstopre = popts->bstopre;
857 /* refint field used 0x3FFF in earlier controllers */
858 ddr->ddr_sdram_interval = (0
859 | ((refint & 0xFFFF) << 16)
860 | ((bstopre & 0x3FFF) << 0)
862 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
865 #if defined(CONFIG_SYS_FSL_DDR3)
866 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
867 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
868 const memctl_options_t *popts,
869 const common_timing_params_t *common_dimm,
870 unsigned int cas_latency,
871 unsigned int additive_latency,
872 const unsigned int unq_mrs_en)
874 unsigned short esdmode; /* Extended SDRAM mode */
875 unsigned short sdmode; /* SDRAM mode */
877 /* Mode Register - MR1 */
878 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
879 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
881 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
882 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
883 unsigned int dic = 0; /* Output driver impedance, 40ohm */
884 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
885 1=Disable (Test/Debug) */
887 /* Mode Register - MR0 */
888 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
889 unsigned int wr = 0; /* Write Recovery */
890 unsigned int dll_rst; /* DLL Reset */
891 unsigned int mode; /* Normal=0 or Test=1 */
892 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
893 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
895 unsigned int bl; /* BL: Burst Length */
897 unsigned int wr_mclk;
899 * DDR_SDRAM_MODE doesn't support 9,11,13,15
900 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
903 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
905 const unsigned int mclk_ps = get_memory_clk_period_ps();
908 if (popts->rtt_override)
909 rtt = popts->rtt_override_value;
911 rtt = popts->cs_local_opts[0].odt_rtt_norm;
913 if (additive_latency == (cas_latency - 1))
915 if (additive_latency == (cas_latency - 2))
918 if (popts->quad_rank_present)
919 dic = 1; /* output driver impedance 240/7 ohm */
922 * The esdmode value will also be used for writing
923 * MR1 during write leveling for DDR3, although the
924 * bits specifically related to the write leveling
925 * scheme will be handled automatically by the DDR
926 * controller. so we set the wrlvl_en = 0 here.
929 | ((qoff & 0x1) << 12)
930 | ((tdqs_en & 0x1) << 11)
931 | ((rtt & 0x4) << 7) /* rtt field is split */
932 | ((wrlvl_en & 0x1) << 7)
933 | ((rtt & 0x2) << 5) /* rtt field is split */
934 | ((dic & 0x2) << 4) /* DIC field is split */
936 | ((rtt & 0x1) << 2) /* rtt field is split */
937 | ((dic & 0x1) << 1) /* DIC field is split */
938 | ((dll_en & 0x1) << 0)
942 * DLL control for precharge PD
943 * 0=slow exit DLL off (tXPDLL)
944 * 1=fast exit DLL on (tXP)
948 wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps;
950 wr = wr_table[wr_mclk - 5];
952 printf("Error: unsupported write recovery for mode register "
953 "wr_mclk = %d\n", wr_mclk);
956 dll_rst = 0; /* dll no reset */
957 mode = 0; /* normal mode */
959 /* look up table to get the cas latency bits */
960 if (cas_latency >= 5 && cas_latency <= 16) {
961 unsigned char cas_latency_table[] = {
975 caslat = cas_latency_table[cas_latency - 5];
977 printf("Error: unsupported cas latency for mode register\n");
980 bt = 0; /* Nibble sequential */
982 switch (popts->burst_length) {
993 printf("Error: invalid burst length of %u specified. "
994 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
995 popts->burst_length);
1001 | ((dll_on & 0x1) << 12)
1003 | ((dll_rst & 0x1) << 8)
1004 | ((mode & 0x1) << 7)
1005 | (((caslat >> 1) & 0x7) << 4)
1007 | ((caslat & 1) << 2)
1011 ddr->ddr_sdram_mode = (0
1012 | ((esdmode & 0xFFFF) << 16)
1013 | ((sdmode & 0xFFFF) << 0)
1016 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1018 if (unq_mrs_en) { /* unique mode registers are supported */
1019 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1020 if (popts->rtt_override)
1021 rtt = popts->rtt_override_value;
1023 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1025 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1027 | ((rtt & 0x4) << 7) /* rtt field is split */
1028 | ((rtt & 0x2) << 5) /* rtt field is split */
1029 | ((rtt & 0x1) << 2) /* rtt field is split */
1033 ddr->ddr_sdram_mode_3 = (0
1034 | ((esdmode & 0xFFFF) << 16)
1035 | ((sdmode & 0xFFFF) << 0)
1039 ddr->ddr_sdram_mode_5 = (0
1040 | ((esdmode & 0xFFFF) << 16)
1041 | ((sdmode & 0xFFFF) << 0)
1045 ddr->ddr_sdram_mode_7 = (0
1046 | ((esdmode & 0xFFFF) << 16)
1047 | ((sdmode & 0xFFFF) << 0)
1052 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1053 ddr->ddr_sdram_mode_3);
1054 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1055 ddr->ddr_sdram_mode_5);
1056 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1057 ddr->ddr_sdram_mode_5);
1061 #else /* !CONFIG_SYS_FSL_DDR3 */
1063 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1064 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1065 const memctl_options_t *popts,
1066 const common_timing_params_t *common_dimm,
1067 unsigned int cas_latency,
1068 unsigned int additive_latency,
1069 const unsigned int unq_mrs_en)
1071 unsigned short esdmode; /* Extended SDRAM mode */
1072 unsigned short sdmode; /* SDRAM mode */
1075 * FIXME: This ought to be pre-calculated in a
1076 * technology-specific routine,
1077 * e.g. compute_DDR2_mode_register(), and then the
1078 * sdmode and esdmode passed in as part of common_dimm.
1081 /* Extended Mode Register */
1082 unsigned int mrs = 0; /* Mode Register Set */
1083 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1084 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1085 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1086 unsigned int ocd = 0; /* 0x0=OCD not supported,
1087 0x7=OCD default state */
1089 unsigned int al; /* Posted CAS# additive latency (AL) */
1090 unsigned int ods = 0; /* Output Drive Strength:
1091 0 = Full strength (18ohm)
1092 1 = Reduced strength (4ohm) */
1093 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1094 1=Disable (Test/Debug) */
1096 /* Mode Register (MR) */
1097 unsigned int mr; /* Mode Register Definition */
1098 unsigned int pd; /* Power-Down Mode */
1099 unsigned int wr; /* Write Recovery */
1100 unsigned int dll_res; /* DLL Reset */
1101 unsigned int mode; /* Normal=0 or Test=1 */
1102 unsigned int caslat = 0;/* CAS# latency */
1103 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1105 unsigned int bl; /* BL: Burst Length */
1107 #if defined(CONFIG_SYS_FSL_DDR2)
1108 const unsigned int mclk_ps = get_memory_clk_period_ps();
1110 dqs_en = !popts->dqs_config;
1111 rtt = fsl_ddr_get_rtt();
1113 al = additive_latency;
1116 | ((mrs & 0x3) << 14)
1117 | ((outputs & 0x1) << 12)
1118 | ((rdqs_en & 0x1) << 11)
1119 | ((dqs_en & 0x1) << 10)
1120 | ((ocd & 0x7) << 7)
1121 | ((rtt & 0x2) << 5) /* rtt field is split */
1123 | ((rtt & 0x1) << 2) /* rtt field is split */
1124 | ((ods & 0x1) << 1)
1125 | ((dll_en & 0x1) << 0)
1128 mr = 0; /* FIXME: CHECKME */
1131 * 0 = Fast Exit (Normal)
1132 * 1 = Slow Exit (Low Power)
1136 #if defined(CONFIG_SYS_FSL_DDR1)
1137 wr = 0; /* Historical */
1138 #elif defined(CONFIG_SYS_FSL_DDR2)
1139 wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1;
1144 #if defined(CONFIG_SYS_FSL_DDR1)
1145 if (1 <= cas_latency && cas_latency <= 4) {
1146 unsigned char mode_caslat_table[4] = {
1147 0x5, /* 1.5 clocks */
1148 0x2, /* 2.0 clocks */
1149 0x6, /* 2.5 clocks */
1150 0x3 /* 3.0 clocks */
1152 caslat = mode_caslat_table[cas_latency - 1];
1154 printf("Warning: unknown cas_latency %d\n", cas_latency);
1156 #elif defined(CONFIG_SYS_FSL_DDR2)
1157 caslat = cas_latency;
1161 switch (popts->burst_length) {
1169 printf("Error: invalid burst length of %u specified. "
1170 " Defaulting to 4 beats.\n",
1171 popts->burst_length);
1177 | ((mr & 0x3) << 14)
1178 | ((pd & 0x1) << 12)
1180 | ((dll_res & 0x1) << 8)
1181 | ((mode & 0x1) << 7)
1182 | ((caslat & 0x7) << 4)
1187 ddr->ddr_sdram_mode = (0
1188 | ((esdmode & 0xFFFF) << 16)
1189 | ((sdmode & 0xFFFF) << 0)
1191 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1195 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1196 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1198 unsigned int init_value; /* Initialization value */
1200 #ifdef CONFIG_MEM_INIT_VALUE
1201 init_value = CONFIG_MEM_INIT_VALUE;
1203 init_value = 0xDEADBEEF;
1205 ddr->ddr_data_init = init_value;
1209 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1210 * The old controller on the 8540/60 doesn't have this register.
1211 * Hope it's OK to set it (to 0) anyway.
1213 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1214 const memctl_options_t *popts)
1216 unsigned int clk_adjust; /* Clock adjust */
1218 clk_adjust = popts->clk_adjust;
1219 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1220 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1223 /* DDR Initialization Address (DDR_INIT_ADDR) */
1224 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1226 unsigned int init_addr = 0; /* Initialization address */
1228 ddr->ddr_init_addr = init_addr;
1231 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1232 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1234 unsigned int uia = 0; /* Use initialization address */
1235 unsigned int init_ext_addr = 0; /* Initialization address */
1237 ddr->ddr_init_ext_addr = (0
1238 | ((uia & 0x1) << 31)
1239 | (init_ext_addr & 0xF)
1243 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1244 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1245 const memctl_options_t *popts)
1247 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1248 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1249 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1250 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1251 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1253 #if defined(CONFIG_SYS_FSL_DDR3)
1254 if (popts->burst_length == DDR_BL8) {
1255 /* We set BL/2 for fixed BL8 */
1256 rrt = 0; /* BL/2 clocks */
1257 wwt = 0; /* BL/2 clocks */
1259 /* We need to set BL/2 + 2 to BC4 and OTF */
1260 rrt = 2; /* BL/2 + 2 clocks */
1261 wwt = 2; /* BL/2 + 2 clocks */
1263 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1265 ddr->timing_cfg_4 = (0
1266 | ((rwt & 0xf) << 28)
1267 | ((wrt & 0xf) << 24)
1268 | ((rrt & 0xf) << 20)
1269 | ((wwt & 0xf) << 16)
1272 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1275 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1276 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1278 unsigned int rodt_on = 0; /* Read to ODT on */
1279 unsigned int rodt_off = 0; /* Read to ODT off */
1280 unsigned int wodt_on = 0; /* Write to ODT on */
1281 unsigned int wodt_off = 0; /* Write to ODT off */
1283 #if defined(CONFIG_SYS_FSL_DDR3)
1284 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1285 rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1286 rodt_off = 4; /* 4 clocks */
1287 wodt_on = 1; /* 1 clocks */
1288 wodt_off = 4; /* 4 clocks */
1291 ddr->timing_cfg_5 = (0
1292 | ((rodt_on & 0x1f) << 24)
1293 | ((rodt_off & 0x7) << 20)
1294 | ((wodt_on & 0x1f) << 12)
1295 | ((wodt_off & 0x7) << 8)
1297 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1300 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1301 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1303 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1304 /* Normal Operation Full Calibration Time (tZQoper) */
1305 unsigned int zqoper = 0;
1306 /* Normal Operation Short Calibration Time (tZQCS) */
1307 unsigned int zqcs = 0;
1310 zqinit = 9; /* 512 clocks */
1311 zqoper = 8; /* 256 clocks */
1312 zqcs = 6; /* 64 clocks */
1315 ddr->ddr_zq_cntl = (0
1316 | ((zq_en & 0x1) << 31)
1317 | ((zqinit & 0xF) << 24)
1318 | ((zqoper & 0xF) << 16)
1319 | ((zqcs & 0xF) << 8)
1321 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1324 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1325 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1326 const memctl_options_t *popts)
1329 * First DQS pulse rising edge after margining mode
1330 * is programmed (tWL_MRD)
1332 unsigned int wrlvl_mrd = 0;
1333 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1334 unsigned int wrlvl_odten = 0;
1335 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1336 unsigned int wrlvl_dqsen = 0;
1337 /* WRLVL_SMPL: Write leveling sample time */
1338 unsigned int wrlvl_smpl = 0;
1339 /* WRLVL_WLR: Write leveling repeition time */
1340 unsigned int wrlvl_wlr = 0;
1341 /* WRLVL_START: Write leveling start time */
1342 unsigned int wrlvl_start = 0;
1344 /* suggest enable write leveling for DDR3 due to fly-by topology */
1346 /* tWL_MRD min = 40 nCK, we set it 64 */
1350 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1353 * Write leveling sample time at least need 6 clocks
1354 * higher than tWLO to allow enough time for progagation
1355 * delay and sampling the prime data bits.
1359 * Write leveling repetition time
1360 * at least tWLO + 6 clocks clocks
1365 * Write leveling start time
1366 * The value use for the DQS_ADJUST for the first sample
1367 * when write leveling is enabled. It probably needs to be
1368 * overriden per platform.
1372 * Override the write leveling sample and start time
1373 * according to specific board
1375 if (popts->wrlvl_override) {
1376 wrlvl_smpl = popts->wrlvl_sample;
1377 wrlvl_start = popts->wrlvl_start;
1381 ddr->ddr_wrlvl_cntl = (0
1382 | ((wrlvl_en & 0x1) << 31)
1383 | ((wrlvl_mrd & 0x7) << 24)
1384 | ((wrlvl_odten & 0x7) << 20)
1385 | ((wrlvl_dqsen & 0x7) << 16)
1386 | ((wrlvl_smpl & 0xf) << 12)
1387 | ((wrlvl_wlr & 0x7) << 8)
1388 | ((wrlvl_start & 0x1F) << 0)
1390 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1391 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
1392 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
1393 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
1394 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
1398 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1399 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1401 /* Self Refresh Idle Threshold */
1402 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1405 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1407 if (popts->addr_hash) {
1408 ddr->ddr_eor = 0x40000000; /* address hash enable */
1409 puts("Address hashing enabled.\n");
1413 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1415 ddr->ddr_cdr1 = popts->ddr_cdr1;
1416 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1419 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1421 ddr->ddr_cdr2 = popts->ddr_cdr2;
1422 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
1426 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1428 unsigned int res = 0;
1431 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1432 * not set at the same time.
1434 if (ddr->ddr_sdram_cfg & 0x10000000
1435 && ddr->ddr_sdram_cfg & 0x00008000) {
1436 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1437 " should not be set at the same time.\n");
1445 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1446 fsl_ddr_cfg_regs_t *ddr,
1447 const common_timing_params_t *common_dimm,
1448 const dimm_params_t *dimm_params,
1449 unsigned int dbw_cap_adj,
1450 unsigned int size_only)
1453 unsigned int cas_latency;
1454 unsigned int additive_latency;
1457 unsigned int wrlvl_en;
1458 unsigned int ip_rev = 0;
1459 unsigned int unq_mrs_en = 0;
1462 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1464 if (common_dimm == NULL) {
1465 printf("Error: subset DIMM params struct null pointer\n");
1470 * Process overrides first.
1472 * FIXME: somehow add dereated caslat to this
1474 cas_latency = (popts->cas_latency_override)
1475 ? popts->cas_latency_override_value
1476 : common_dimm->lowest_common_SPD_caslat;
1478 additive_latency = (popts->additive_latency_override)
1479 ? popts->additive_latency_override_value
1480 : common_dimm->additive_latency;
1482 sr_it = (popts->auto_self_refresh_en)
1485 /* ZQ calibration */
1486 zq_en = (popts->zq_en) ? 1 : 0;
1487 /* write leveling */
1488 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1490 /* Chip Select Memory Bounds (CSn_BNDS) */
1491 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1492 unsigned long long ea, sa;
1493 unsigned int cs_per_dimm
1494 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1495 unsigned int dimm_number
1497 unsigned long long rank_density
1498 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
1500 if (dimm_params[dimm_number].n_ranks == 0) {
1501 debug("Skipping setup of CS%u "
1502 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1505 if (popts->memctl_interleaving) {
1506 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1507 case FSL_DDR_CS0_CS1_CS2_CS3:
1509 case FSL_DDR_CS0_CS1:
1510 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1514 case FSL_DDR_CS2_CS3:
1520 sa = common_dimm->base_address;
1521 ea = sa + common_dimm->total_mem - 1;
1522 } else if (!popts->memctl_interleaving) {
1524 * If memory interleaving between controllers is NOT
1525 * enabled, the starting address for each memory
1526 * controller is distinct. However, because rank
1527 * interleaving is enabled, the starting and ending
1528 * addresses of the total memory on that memory
1529 * controller needs to be programmed into its
1530 * respective CS0_BNDS.
1532 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1533 case FSL_DDR_CS0_CS1_CS2_CS3:
1534 sa = common_dimm->base_address;
1535 ea = sa + common_dimm->total_mem - 1;
1537 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1538 if ((i >= 2) && (dimm_number == 0)) {
1539 sa = dimm_params[dimm_number].base_address +
1541 ea = sa + 2 * rank_density - 1;
1543 sa = dimm_params[dimm_number].base_address;
1544 ea = sa + 2 * rank_density - 1;
1547 case FSL_DDR_CS0_CS1:
1548 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1549 sa = dimm_params[dimm_number].base_address;
1550 ea = sa + rank_density - 1;
1552 sa += (i % cs_per_dimm) * rank_density;
1553 ea += (i % cs_per_dimm) * rank_density;
1561 case FSL_DDR_CS2_CS3:
1562 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1563 sa = dimm_params[dimm_number].base_address;
1564 ea = sa + rank_density - 1;
1566 sa += (i % cs_per_dimm) * rank_density;
1567 ea += (i % cs_per_dimm) * rank_density;
1573 ea += (rank_density >> dbw_cap_adj);
1575 default: /* No bank(chip-select) interleaving */
1576 sa = dimm_params[dimm_number].base_address;
1577 ea = sa + rank_density - 1;
1578 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1579 sa += (i % cs_per_dimm) * rank_density;
1580 ea += (i % cs_per_dimm) * rank_density;
1593 ddr->cs[i].bnds = (0
1594 | ((sa & 0xFFF) << 16)/* starting address MSB */
1595 | ((ea & 0xFFF) << 0) /* ending address MSB */
1598 /* setting bnds to 0xffffffff for inactive CS */
1599 ddr->cs[i].bnds = 0xffffffff;
1602 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1603 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1604 set_csn_config_2(i, ddr);
1608 * In the case we only need to compute the ddr sdram size, we only need
1609 * to set csn registers, so return from here.
1614 set_ddr_eor(ddr, popts);
1616 #if !defined(CONFIG_SYS_FSL_DDR1)
1617 set_timing_cfg_0(ddr, popts, dimm_params);
1620 set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
1621 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1622 set_timing_cfg_2(ddr, popts, common_dimm,
1623 cas_latency, additive_latency);
1625 set_ddr_cdr1(ddr, popts);
1626 set_ddr_cdr2(ddr, popts);
1627 set_ddr_sdram_cfg(ddr, popts, common_dimm);
1628 ip_rev = fsl_ddr_get_version();
1629 if (ip_rev > 0x40400)
1632 set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1633 set_ddr_sdram_mode(ddr, popts, common_dimm,
1634 cas_latency, additive_latency, unq_mrs_en);
1635 set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
1636 set_ddr_sdram_interval(ddr, popts, common_dimm);
1637 set_ddr_data_init(ddr);
1638 set_ddr_sdram_clk_cntl(ddr, popts);
1639 set_ddr_init_addr(ddr);
1640 set_ddr_init_ext_addr(ddr);
1641 set_timing_cfg_4(ddr, popts);
1642 set_timing_cfg_5(ddr, cas_latency);
1644 set_ddr_zq_cntl(ddr, zq_en);
1645 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1647 set_ddr_sr_cntr(ddr, sr_it);
1649 set_ddr_sdram_rcw(ddr, popts, common_dimm);
1651 #ifdef CONFIG_SYS_FSL_DDR_EMU
1652 /* disble DDR training for emulator */
1653 ddr->debug[2] = 0x00000400;
1654 ddr->debug[4] = 0xff800000;
1656 return check_fsl_memctl_config_regs(ddr);